From: Andreas Hansson Date: Tue, 23 Dec 2014 14:31:20 +0000 (-0500) Subject: stats: Bump stats for decoder, TLB, prefetcher and DRAM changes X-Git-Tag: stable_2015_04_15~39 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df8df4fd0a95763cb0658cbe77615e7deac391d3;p=gem5.git stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. --- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index d1ad31617..4fcd96b8e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.884241 # Number of seconds simulated -sim_ticks 1884241273000 # Number of ticks simulated -final_tick 1884241273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.884236 # Number of seconds simulated +sim_ticks 1884235597000 # Number of ticks simulated +final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193195 # Simulator instruction rate (inst/s) -host_op_rate 193195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6486085343 # Simulator tick rate (ticks/s) -host_mem_usage 317148 # Number of bytes of host memory used -host_seconds 290.51 # Real time elapsed on the host -sim_insts 56124126 # Number of instructions simulated -sim_ops 56124126 # Number of ops (including micro ops) simulated +host_inst_rate 284222 # Simulator instruction rate (inst/s) +host_op_rate 284222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9542341098 # Simulator tick rate (ticks/s) +host_mem_usage 373416 # Number of bytes of host memory used +host_seconds 197.46 # Real time elapsed on the host +sim_insts 56122640 # Number of instructions simulated +sim_ops 56122640 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25914944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 25914816 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25915904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7561408 # Number of bytes written to this memory -system.physmem.bytes_written::total 7561408 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 404921 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 404919 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404936 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118147 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118147 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13753517 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13753490 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13754026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4012972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4012972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4012972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13753517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 558945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13753490 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17766999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404936 # Number of read requests accepted -system.physmem.writeReqs 159699 # Number of write requests accepted -system.physmem.readBursts 404936 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159699 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25909568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue -system.physmem.bytesWritten 10083392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25915904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10220736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2126 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 153 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25482 # Per bank write bursts +system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404934 # Number of read requests accepted +system.physmem.writeReqs 159706 # Number of write requests accepted +system.physmem.readBursts 404934 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159706 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25910208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5568 # Total number of bytes read from write queue +system.physmem.bytesWritten 10081344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25915776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10221184 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 87 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2165 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25481 # Per bank write bursts system.physmem.perBankRdBursts::1 25742 # Per bank write bursts -system.physmem.perBankRdBursts::2 25842 # Per bank write bursts -system.physmem.perBankRdBursts::3 25776 # Per bank write bursts -system.physmem.perBankRdBursts::4 25226 # Per bank write bursts +system.physmem.perBankRdBursts::2 25839 # Per bank write bursts +system.physmem.perBankRdBursts::3 25784 # Per bank write bursts +system.physmem.perBankRdBursts::4 25228 # Per bank write bursts system.physmem.perBankRdBursts::5 24953 # Per bank write bursts -system.physmem.perBankRdBursts::6 24814 # Per bank write bursts -system.physmem.perBankRdBursts::7 24563 # Per bank write bursts +system.physmem.perBankRdBursts::6 24817 # Per bank write bursts +system.physmem.perBankRdBursts::7 24560 # Per bank write bursts system.physmem.perBankRdBursts::8 25102 # Per bank write bursts -system.physmem.perBankRdBursts::9 25273 # Per bank write bursts -system.physmem.perBankRdBursts::10 25528 # Per bank write bursts -system.physmem.perBankRdBursts::11 24851 # Per bank write bursts -system.physmem.perBankRdBursts::12 24526 # Per bank write bursts +system.physmem.perBankRdBursts::9 25274 # Per bank write bursts +system.physmem.perBankRdBursts::10 25530 # Per bank write bursts +system.physmem.perBankRdBursts::11 24856 # Per bank write bursts +system.physmem.perBankRdBursts::12 24523 # Per bank write bursts system.physmem.perBankRdBursts::13 25574 # Per bank write bursts -system.physmem.perBankRdBursts::14 25842 # Per bank write bursts -system.physmem.perBankRdBursts::15 25743 # Per bank write bursts -system.physmem.perBankWrBursts::0 10288 # Per bank write bursts -system.physmem.perBankWrBursts::1 10037 # Per bank write bursts -system.physmem.perBankWrBursts::2 10678 # Per bank write bursts -system.physmem.perBankWrBursts::3 10053 # Per bank write bursts -system.physmem.perBankWrBursts::4 9806 # Per bank write bursts -system.physmem.perBankWrBursts::5 9437 # Per bank write bursts -system.physmem.perBankWrBursts::6 9137 # Per bank write bursts -system.physmem.perBankWrBursts::7 8750 # Per bank write bursts -system.physmem.perBankWrBursts::8 9885 # Per bank write bursts -system.physmem.perBankWrBursts::9 8937 # Per bank write bursts -system.physmem.perBankWrBursts::10 9881 # Per bank write bursts -system.physmem.perBankWrBursts::11 9301 # Per bank write bursts -system.physmem.perBankWrBursts::12 9770 # Per bank write bursts -system.physmem.perBankWrBursts::13 10691 # Per bank write bursts -system.physmem.perBankWrBursts::14 10395 # Per bank write bursts -system.physmem.perBankWrBursts::15 10507 # Per bank write bursts +system.physmem.perBankRdBursts::14 25845 # Per bank write bursts +system.physmem.perBankRdBursts::15 25739 # Per bank write bursts +system.physmem.perBankWrBursts::0 10323 # Per bank write bursts +system.physmem.perBankWrBursts::1 10094 # Per bank write bursts +system.physmem.perBankWrBursts::2 10597 # Per bank write bursts +system.physmem.perBankWrBursts::3 9998 # Per bank write bursts +system.physmem.perBankWrBursts::4 9794 # Per bank write bursts +system.physmem.perBankWrBursts::5 9430 # Per bank write bursts +system.physmem.perBankWrBursts::6 9122 # Per bank write bursts +system.physmem.perBankWrBursts::7 8746 # Per bank write bursts +system.physmem.perBankWrBursts::8 9866 # Per bank write bursts +system.physmem.perBankWrBursts::9 8965 # Per bank write bursts +system.physmem.perBankWrBursts::10 9841 # Per bank write bursts +system.physmem.perBankWrBursts::11 9391 # Per bank write bursts +system.physmem.perBankWrBursts::12 9895 # Per bank write bursts +system.physmem.perBankWrBursts::13 10602 # Per bank write bursts +system.physmem.perBankWrBursts::14 10396 # Per bank write bursts +system.physmem.perBankWrBursts::15 10461 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1884232486500 # Total gap between requests +system.physmem.totGap 1884226862500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404936 # Read request sizes (log2) +system.physmem.readPktSize::6 404934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159699 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159706 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -144,119 +144,119 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 547.429771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 335.789885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 418.130322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14719 22.39% 22.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10714 16.30% 38.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4807 7.31% 45.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3176 4.83% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2550 3.88% 54.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1953 2.97% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1437 2.19% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1697 2.58% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24696 37.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65749 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5738 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.553154 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2788.767091 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5735 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 547.425008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 336.336786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.790126 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14590 22.19% 22.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10813 16.45% 38.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4856 7.39% 46.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3188 4.85% 50.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2531 3.85% 54.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1959 2.98% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1455 2.21% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1675 2.55% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24680 37.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65747 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5741 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.518028 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2788.038880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5738 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5738 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5738 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.457825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.746842 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.017596 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4693 81.79% 81.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 187 3.26% 85.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 275 4.79% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 67 1.17% 91.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 92 1.60% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 47 0.82% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 24 0.42% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.19% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.33% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.12% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.24% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.10% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.07% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 17 0.30% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 47 0.82% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.30% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 17 0.30% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 79 1.38% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 32 0.56% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 20 0.35% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 19 0.33% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 15 0.26% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 7 0.12% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5738 # Writes before turning the bus around for reads -system.physmem.totQLat 2167079250 # Total ticks spent queuing -system.physmem.totMemAccLat 9757773000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024185000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5352.97 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5741 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.437903 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.774518 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.753883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4686 81.62% 81.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 175 3.05% 84.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 305 5.31% 89.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 60 1.05% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 91 1.59% 92.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 55 0.96% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 13 0.23% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 10 0.17% 93.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 19 0.33% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 16 0.28% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 10 0.17% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 11 0.19% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 17 0.30% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 40 0.70% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 20 0.35% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 16 0.28% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 94 1.64% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 33 0.57% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 16 0.28% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 17 0.30% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.16% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.09% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5741 # Writes before turning the bus around for reads +system.physmem.totQLat 2143675250 # Total ticks spent queuing +system.physmem.totMemAccLat 9734556500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5295.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24102.97 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24045.03 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s @@ -266,66 +266,71 @@ system.physmem.busUtil 0.15 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 364185 # Number of row buffer hits during reads -system.physmem.writeRowHits 132456 # Number of row buffer hits during writes +system.physmem.avgWrQLen 25.52 # Average write queue length when enqueuing +system.physmem.readRowHits 364210 # Number of row buffer hits during reads +system.physmem.writeRowHits 132411 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.06 # Row buffer hit rate for writes -system.physmem.avgGap 3337080.57 # Average gap between requests +system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes +system.physmem.avgGap 3337041.06 # Average gap between requests system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1774592996500 # Time in different power states -system.physmem.memoryStateTime::REF 62918700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 46722146000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 242668440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 254394000 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 132408375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 138806250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1578704400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1579024200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 506645280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 514298160 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 59931006120 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 60719870160 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1077969239250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1077277253250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1263429649065 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1263552623220 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.526996 # Core power per rank (mW) -system.physmem.averagePower::1 670.592261 # Core power per rank (mW) -system.cpu.branchPred.lookups 15011318 # Number of BP lookups -system.cpu.branchPred.condPredicted 13019220 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 376037 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9980368 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5204970 # Number of BTB hits +system.physmem_0.actEnergy 243152280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132672375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578751200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 506113920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 59789504475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1078093355250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1263412526700 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.517914 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1793297401750 # Time in different power states +system.physmem_0.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28017727000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 253895040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138534000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579055400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 514622160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60612218820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1077371684250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1263538986870 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.585024 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1792097761500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29217381000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 15006303 # Number of BP lookups +system.cpu.branchPred.condPredicted 13014667 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 375459 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9787101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5202858 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.152085 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808971 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32603 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.160359 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 808926 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32598 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9241438 # DTB read hits -system.cpu.dtb.read_misses 17791 # DTB read misses +system.cpu.dtb.read_hits 9241313 # DTB read hits +system.cpu.dtb.read_misses 17796 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766265 # DTB read accesses -system.cpu.dtb.write_hits 6385998 # DTB write hits -system.cpu.dtb.write_misses 2317 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298404 # DTB write accesses -system.cpu.dtb.data_hits 15627436 # DTB hits -system.cpu.dtb.data_misses 20108 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064669 # DTB accesses -system.cpu.itb.fetch_hits 4019003 # ITB hits -system.cpu.itb.fetch_misses 6884 # ITB misses -system.cpu.itb.fetch_acv 661 # ITB acv -system.cpu.itb.fetch_accesses 4025887 # ITB accesses +system.cpu.dtb.read_accesses 766310 # DTB read accesses +system.cpu.dtb.write_hits 6385986 # DTB write hits +system.cpu.dtb.write_misses 2327 # DTB write misses +system.cpu.dtb.write_acv 160 # DTB write access violations +system.cpu.dtb.write_accesses 298447 # DTB write accesses +system.cpu.dtb.data_hits 15627299 # DTB hits +system.cpu.dtb.data_misses 20123 # DTB misses +system.cpu.dtb.data_acv 371 # DTB access violations +system.cpu.dtb.data_accesses 1064757 # DTB accesses +system.cpu.itb.fetch_hits 4016976 # ITB hits +system.cpu.itb.fetch_misses 6883 # ITB misses +system.cpu.itb.fetch_acv 674 # ITB acv +system.cpu.itb.fetch_accesses 4023859 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,39 +343,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 175285694 # number of cpu cycles simulated +system.cpu.numCycles 175257245 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56124126 # Number of instructions committed -system.cpu.committedOps 56124126 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2495853 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5575 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593196852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.123179 # CPI: cycles per instruction -system.cpu.ipc 0.320187 # IPC: instructions per cycle +system.cpu.committedInsts 56122640 # Number of instructions committed +system.cpu.committedOps 56122640 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2496382 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5595 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593213949 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.122755 # CPI: cycles per instruction +system.cpu.ipc 0.320230 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211480 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74791 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211475 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105868 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182691 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73424 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73424 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148880 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833816082000 97.32% 97.32% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80474500 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 673053000 0.04% 97.36% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49670669500 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1884240279000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1833807390500 97.32% 97.32% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80545000 0.00% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 673176000 0.04% 97.36% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 49673506000 2.64% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1884234617500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693543 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814928 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693560 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814939 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -409,7 +414,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175532 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175527 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -418,28 +423,28 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192418 # number of callpals executed +system.cpu.kern.callpal::total 192413 # number of callpals executed system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325383 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393986 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36270859500 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4083023000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843886386500 97.86% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.393490 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36258202500 1.92% 1.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4079939000 0.22% 2.14% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1843896466000 97.86% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.tickCycles 84485847 # Number of cycles that the object actually ticked -system.cpu.idleCycles 90799847 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395229 # number of replacements +system.cpu.tickCycles 84474734 # Number of cycles that the object actually ticked +system.cpu.idleCycles 90782511 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395383 # number of replacements system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13773041 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395741 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.867906 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13772439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982334 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy @@ -449,72 +454,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63657366 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63657366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 7814636 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814636 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 5576637 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576637 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182736 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182736 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 7814297 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 5576378 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182732 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 13391273 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13391273 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 13391273 # number of overall hits -system.cpu.dcache.overall_hits::total 13391273 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1201532 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201532 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 573582 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573582 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17284 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17284 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 1775114 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775114 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1775114 # number of overall misses -system.cpu.dcache.overall_misses::total 1775114 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31036730750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31036730750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20700048539 # number of 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-system.cpu.dcache.WriteReq_accesses::total 6150219 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 13390675 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13390675 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 13390675 # number of overall hits +system.cpu.dcache.overall_hits::total 13390675 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1201640 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201640 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 573763 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573763 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17288 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17288 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.inst 1775403 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1775403 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1775403 # number of overall misses +system.cpu.dcache.overall_misses::total 1775403 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31034654250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20679395543 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231275750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 51714049793 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 51714049793 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 9015937 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9015937 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 6150141 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150141 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200020 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198999 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 15166387 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15166387 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 15166387 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15166387 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133264 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133264 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093262 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093262 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086411 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086411 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.117043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.117043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25830.964760 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25830.964760 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36089.083233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36089.083233 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13366.118954 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.118954 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29145.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29145.609403 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 15166078 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15166078 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 15166078 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15166078 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133280 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133280 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093293 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093293 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086431 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086431 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.117064 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117064 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.117064 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117064 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25826.915091 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36041.702834 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13377.819875 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29128.062639 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29128.062639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29128.062639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,64 +528,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838115 # number of writebacks -system.cpu.dcache.writebacks::total 838115 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127210 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127210 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269406 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269406 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838265 # number of writebacks +system.cpu.dcache.writebacks::total 838265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127268 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127268 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269487 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269487 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 396616 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396616 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 396616 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396616 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074322 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074322 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304176 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304176 # number of WriteReq MSHR misses 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-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196291500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196291500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179428847 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37179428847 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179428847 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37179428847 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423887000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423887000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002910000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002910000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426797000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426797000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086396 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086396 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090892 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090892 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25057.317313 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25057.317313 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33729.819568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33729.819568 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11358.804467 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 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WriteReq mshr uncacheable latency @@ -588,58 +593,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1458001 # number of replacements -system.cpu.icache.tags.tagsinuse 509.626489 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18970775 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1458512 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.006938 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31607473250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.626489 # Average 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latency +system.cpu.icache.demand_avg_miss_latency::total 13723.661864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13723.661864 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -648,115 +653,115 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458688 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1458688 # 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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69119.344261 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.344261 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66572.913111 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66572.913111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66572.913111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66572.913111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -765,54 +770,54 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each 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# number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405347 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 405347 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405347 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15311644500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15311644500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 271014 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271014 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6608324888 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6608324888 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21931621388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21931621388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21931621388 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21931621388 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333779000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333779000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887481500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887481500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221260500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221260500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6596786889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6596786889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21908431389 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21908431389 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21908431389 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21908431389 # number of overall MSHR miss cycles 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accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383500 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383500 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.142009 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.142009 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53078.171275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53078.171275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383443 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383443 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141928 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141928 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53041.852143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15942 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency 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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2557364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558856 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838265 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304285 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917316 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662927 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6580243 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143021148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236373340 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41941 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3734307 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011173 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105112 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920255 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663385 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6583640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93446144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143040604 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236486748 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41944 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3736082 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3692582 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3694357 98.88% 98.88% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3734307 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2697490998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3736082 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698528498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191666369 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2193867384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194528153 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194759654 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -928,7 +933,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406196790 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406197789 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -937,14 +942,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.296059 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.296028 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728026020000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.296059 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081004 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081004 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1728025570000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.296028 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081002 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081002 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -960,8 +965,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635314907 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635314907 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635920906 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13635920906 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles @@ -984,17 +989,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328150.628297 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328150.628297 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206297 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206267 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23564 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23556 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.754753 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.756453 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1010,8 +1015,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474610907 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474610907 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11475216906 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11475216906 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles @@ -1026,57 +1031,57 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276150.628297 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276150.628297 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295796 # Transaction distribution -system.membus.trans_dist::ReadResp 295780 # Transaction distribution +system.membus.trans_dist::ReadReq 295774 # Transaction distribution +system.membus.trans_dist::ReadResp 295758 # Transaction distribution system.membus.trans_dist::WriteReq 9619 # Transaction distribution system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118147 # Transaction distribution +system.membus.trans_dist::Writeback 118154 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 155 # Transaction distribution -system.membus.trans_dist::UpgradeResp 155 # Transaction distribution -system.membus.trans_dist::ReadExReq 116517 # Transaction distribution -system.membus.trans_dist::ReadExResp 116517 # Transaction distribution +system.membus.trans_dist::UpgradeReq 156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 156 # Transaction distribution +system.membus.trans_dist::ReadExReq 116537 # Transaction distribution +system.membus.trans_dist::ReadExResp 116537 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887063 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920193 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044997 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30863900 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30864220 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36180956 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36181276 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 565237 # Request fanout histogram +system.membus.snoop_fanout::samples 565243 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 565237 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 565243 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 565237 # Request fanout histogram -system.membus.reqLayer0.occupancy 30298500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 565243 # Request fanout histogram +system.membus.reqLayer0.occupancy 30308000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1878232500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1878196000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3792450097 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3792332596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 092a1319f..38c6e11f9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901187 # Number of seconds simulated -sim_ticks 1901187238000 # Number of ticks simulated -final_tick 1901187238000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.901175 # Number of seconds simulated +sim_ticks 1901175003500 # Number of ticks simulated +final_tick 1901175003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164685 # Simulator instruction rate (inst/s) -host_op_rate 164685 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5473626023 # Simulator tick rate (ticks/s) -host_mem_usage 324480 # Number of bytes of host memory used -host_seconds 347.34 # Real time elapsed on the host -sim_insts 57201060 # Number of instructions simulated -sim_ops 57201060 # Number of ops (including micro ops) simulated +host_inst_rate 154934 # Simulator instruction rate (inst/s) +host_op_rate 154934 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5197600055 # Simulator tick rate (ticks/s) +host_mem_usage 378544 # Number of bytes of host memory used +host_seconds 365.78 # Real time elapsed on the host +sim_insts 56671579 # Number of instructions simulated +sim_ops 56671579 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 886592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24764800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 96384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 525056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 885824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24795264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 95808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 496320 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26273792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 886592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 96384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7873024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7873024 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13853 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386950 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8204 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26274176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 885824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 95808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7885056 # Number of bytes written to this memory +system.physmem.bytes_written::total 7885056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7755 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410528 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 466336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13025966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 276173 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 410534 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123204 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123204 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 465935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13042073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 261060 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13819676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 466336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50697 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4141109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4141109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4141109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 466336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13025966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 276173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13819967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 465935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50394 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4147465 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4147465 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4147465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 465935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13042073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 261060 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17960785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410528 # Number of read requests accepted -system.physmem.writeReqs 164568 # Number of write requests accepted -system.physmem.readBursts 410528 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 164568 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26267072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 10385920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26273792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10532352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6311 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25881 # Per bank write bursts -system.physmem.perBankRdBursts::1 25672 # Per bank write bursts -system.physmem.perBankRdBursts::2 26260 # Per bank write bursts -system.physmem.perBankRdBursts::3 25757 # Per bank write bursts -system.physmem.perBankRdBursts::4 25283 # Per bank write bursts -system.physmem.perBankRdBursts::5 25202 # Per bank write bursts -system.physmem.perBankRdBursts::6 25755 # Per bank write bursts -system.physmem.perBankRdBursts::7 25257 # Per bank write bursts -system.physmem.perBankRdBursts::8 25550 # Per bank write bursts -system.physmem.perBankRdBursts::9 25721 # Per bank write bursts -system.physmem.perBankRdBursts::10 25770 # Per bank write bursts -system.physmem.perBankRdBursts::11 25804 # Per bank write bursts -system.physmem.perBankRdBursts::12 25810 # Per bank write bursts -system.physmem.perBankRdBursts::13 25881 # Per bank write bursts -system.physmem.perBankRdBursts::14 25644 # Per bank write bursts -system.physmem.perBankRdBursts::15 25176 # Per bank write bursts -system.physmem.perBankWrBursts::0 10943 # Per bank write bursts -system.physmem.perBankWrBursts::1 9789 # Per bank write bursts -system.physmem.perBankWrBursts::2 10222 # Per bank write bursts -system.physmem.perBankWrBursts::3 9625 # Per bank write bursts -system.physmem.perBankWrBursts::4 9290 # Per bank write bursts -system.physmem.perBankWrBursts::5 9560 # Per bank write bursts -system.physmem.perBankWrBursts::6 10277 # Per bank write bursts -system.physmem.perBankWrBursts::7 9346 # Per bank write bursts -system.physmem.perBankWrBursts::8 9649 # Per bank write bursts -system.physmem.perBankWrBursts::9 9784 # Per bank write bursts -system.physmem.perBankWrBursts::10 9978 # Per bank write bursts -system.physmem.perBankWrBursts::11 10113 # Per bank write bursts -system.physmem.perBankWrBursts::12 11182 # Per bank write bursts -system.physmem.perBankWrBursts::13 11629 # Per bank write bursts -system.physmem.perBankWrBursts::14 10712 # Per bank write bursts -system.physmem.perBankWrBursts::15 10181 # Per bank write bursts +system.physmem.bw_total::total 17967432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410534 # Number of read requests accepted +system.physmem.writeReqs 164756 # Number of write requests accepted +system.physmem.readBursts 410534 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 164756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26267904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue +system.physmem.bytesWritten 10393408 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26274176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10544384 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2335 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4921 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25742 # Per bank write bursts +system.physmem.perBankRdBursts::1 25822 # Per bank write bursts +system.physmem.perBankRdBursts::2 25939 # Per bank write bursts +system.physmem.perBankRdBursts::3 25643 # Per bank write bursts +system.physmem.perBankRdBursts::4 25873 # Per bank write bursts +system.physmem.perBankRdBursts::5 25657 # Per bank write bursts +system.physmem.perBankRdBursts::6 25709 # Per bank write bursts +system.physmem.perBankRdBursts::7 25201 # Per bank write bursts +system.physmem.perBankRdBursts::8 25222 # Per bank write bursts +system.physmem.perBankRdBursts::9 26115 # Per bank write bursts +system.physmem.perBankRdBursts::10 25677 # Per bank write bursts +system.physmem.perBankRdBursts::11 25575 # Per bank write bursts +system.physmem.perBankRdBursts::12 25800 # Per bank write bursts +system.physmem.perBankRdBursts::13 26085 # Per bank write bursts +system.physmem.perBankRdBursts::14 25301 # Per bank write bursts +system.physmem.perBankRdBursts::15 25075 # Per bank write bursts +system.physmem.perBankWrBursts::0 10194 # Per bank write bursts +system.physmem.perBankWrBursts::1 10103 # Per bank write bursts +system.physmem.perBankWrBursts::2 10030 # Per bank write bursts +system.physmem.perBankWrBursts::3 9736 # Per bank write bursts +system.physmem.perBankWrBursts::4 9490 # Per bank write bursts +system.physmem.perBankWrBursts::5 10167 # Per bank write bursts +system.physmem.perBankWrBursts::6 10200 # Per bank write bursts +system.physmem.perBankWrBursts::7 9338 # Per bank write bursts +system.physmem.perBankWrBursts::8 9741 # Per bank write bursts +system.physmem.perBankWrBursts::9 10459 # Per bank write bursts +system.physmem.perBankWrBursts::10 10157 # Per bank write bursts +system.physmem.perBankWrBursts::11 10688 # Per bank write bursts +system.physmem.perBankWrBursts::12 11170 # Per bank write bursts +system.physmem.perBankWrBursts::13 11200 # Per bank write bursts +system.physmem.perBankWrBursts::14 10147 # Per bank write bursts +system.physmem.perBankWrBursts::15 9577 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1901182789000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 1901170614000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410528 # Read request sizes (log2) +system.physmem.readPktSize::6 410534 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 164568 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 164756 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,187 +158,193 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 546.521218 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 334.319778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.846112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14858 22.15% 22.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11363 16.94% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5157 7.69% 46.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2935 4.38% 51.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2350 3.50% 54.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 2.54% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1587 2.37% 59.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1704 2.54% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25411 37.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67066 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.402667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2725.840527 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5997 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 545.527075 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 333.566914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.530844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14928 22.21% 22.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11337 16.87% 39.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5205 7.75% 46.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2937 4.37% 51.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2377 3.54% 54.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1798 2.68% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1602 2.38% 59.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1684 2.51% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25335 37.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67203 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6020 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.178073 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2721.311016 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6017 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6000 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.046667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.651184 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.190276 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4953 82.55% 82.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 193 3.22% 85.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 289 4.82% 90.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.83% 91.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 96 1.60% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 44 0.73% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 19 0.32% 94.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 8 0.13% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 23 0.38% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 10 0.17% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 13 0.22% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.10% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 95.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.08% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 20 0.33% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 38 0.63% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.28% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 12 0.20% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 91 1.52% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 43 0.72% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 17 0.28% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 19 0.32% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 8 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6000 # Writes before turning the bus around for reads -system.physmem.totQLat 3893190750 # Total ticks spent queuing -system.physmem.totMemAccLat 11588622000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9485.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6020 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6020 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.976246 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.646869 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.117275 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4955 82.31% 82.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 186 3.09% 85.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 316 5.25% 90.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 58 0.96% 91.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 93 1.54% 93.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 41 0.68% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 21 0.35% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.18% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 26 0.43% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.28% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 7 0.12% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.03% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 20 0.33% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 42 0.70% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 17 0.28% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 7 0.12% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 80 1.33% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 45 0.75% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 12 0.20% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 27 0.45% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 6 0.10% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.08% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.07% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 4 0.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6020 # Writes before turning the bus around for reads +system.physmem.totQLat 3885054500 # Total ticks spent queuing +system.physmem.totMemAccLat 11580729500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9465.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28235.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28215.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 5.47 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.54 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing -system.physmem.readRowHits 370176 # Number of row buffer hits during reads -system.physmem.writeRowHits 135461 # Number of row buffer hits during writes +system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing +system.physmem.readRowHits 370181 # Number of row buffer hits during reads +system.physmem.writeRowHits 135448 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.46 # Row buffer hit rate for writes -system.physmem.avgGap 3305852.92 # Average gap between requests -system.physmem.pageHitRate 88.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800384684500 # Time in different power states -system.physmem.memoryStateTime::REF 63484720000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37315104250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 252216720 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 254802240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 137618250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 139029000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1599522600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1601776800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 512256960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 539317440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 124176112320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 124176112320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 57055460715 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 57001965930 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1090662047250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1090708972500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1274395234815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1274421976230 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.316446 # Core power per rank (mW) -system.physmem.averagePower::1 670.330512 # Core power per rank (mW) -system.cpu0.branchPred.lookups 15024669 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13090822 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 302150 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9266199 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5129053 # Number of BTB hits +system.physmem.writeRowHitRate 83.39 # Row buffer hit rate for writes +system.physmem.avgGap 3304716.95 # Average gap between requests +system.physmem.pageHitRate 88.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 253260000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138187500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1603570800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 513591840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57090888495 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1090621618500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1274396212335 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.322456 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1814181645000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23503077500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 254688840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138967125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597455600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 538429680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57028143465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1090676670000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1274409449910 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.329412 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1814277217000 # Time in different power states +system.physmem_1.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23408681000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu0.branchPred.lookups 16131633 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14074847 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 326763 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9526803 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5411642 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 55.352286 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 762066 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 14857 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 56.804387 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 814199 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17678 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8699665 # DTB read hits -system.cpu0.dtb.read_misses 31652 # DTB read misses -system.cpu0.dtb.read_acv 518 # DTB read access violations -system.cpu0.dtb.read_accesses 684964 # DTB read accesses -system.cpu0.dtb.write_hits 5527628 # DTB write hits -system.cpu0.dtb.write_misses 7312 # DTB write misses -system.cpu0.dtb.write_acv 384 # DTB write access violations -system.cpu0.dtb.write_accesses 236678 # DTB write accesses -system.cpu0.dtb.data_hits 14227293 # DTB hits -system.cpu0.dtb.data_misses 38964 # DTB misses -system.cpu0.dtb.data_acv 902 # DTB access violations -system.cpu0.dtb.data_accesses 921642 # DTB accesses -system.cpu0.itb.fetch_hits 1360805 # ITB hits -system.cpu0.itb.fetch_misses 29325 # ITB misses -system.cpu0.itb.fetch_acv 623 # ITB acv -system.cpu0.itb.fetch_accesses 1390130 # ITB accesses +system.cpu0.dtb.read_hits 9231009 # DTB read hits +system.cpu0.dtb.read_misses 34580 # DTB read misses +system.cpu0.dtb.read_acv 535 # DTB read access violations +system.cpu0.dtb.read_accesses 687791 # DTB read accesses +system.cpu0.dtb.write_hits 5940395 # DTB write hits +system.cpu0.dtb.write_misses 7538 # DTB write misses +system.cpu0.dtb.write_acv 382 # DTB write access violations +system.cpu0.dtb.write_accesses 237219 # DTB write accesses +system.cpu0.dtb.data_hits 15171404 # DTB hits +system.cpu0.dtb.data_misses 42118 # DTB misses +system.cpu0.dtb.data_acv 917 # DTB access violations +system.cpu0.dtb.data_accesses 925010 # DTB accesses +system.cpu0.itb.fetch_hits 1435355 # ITB hits +system.cpu0.itb.fetch_misses 29386 # ITB misses +system.cpu0.itb.fetch_acv 625 # ITB acv +system.cpu0.itb.fetch_accesses 1464741 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,467 +357,466 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 108792579 # number of cpu cycles simulated +system.cpu0.numCycles 112944275 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24480610 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 66921510 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 15024669 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5891119 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 76960209 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1006918 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 587 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 30320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1459024 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 459440 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7808182 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 214478 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103893877 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.944480 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26734623 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70871158 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16131633 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6225841 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 78572167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1087344 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 938 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1452901 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 461019 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8195583 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 233790 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 107793734 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.657470 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.965319 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 91308838 87.89% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 814381 0.78% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1763801 1.70% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 741690 0.71% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2523255 2.43% 93.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 561128 0.54% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 635570 0.61% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 719335 0.69% 95.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4825879 4.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 94531257 87.70% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 858509 0.80% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1823492 1.69% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 785861 0.73% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2602190 2.41% 93.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 590625 0.55% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 664328 0.62% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 839547 0.78% 95.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5097925 4.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103893877 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.138104 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.615129 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19900832 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 73745257 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8046257 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1730950 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 470580 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 495026 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 33344 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 58913691 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 103815 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 470580 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20722206 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 48316669 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17970373 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8856068 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7557979 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 56901533 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 202703 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2015999 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 141191 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3736855 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 38160864 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 69501237 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69376844 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 115358 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33567232 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4593624 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1365129 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 198221 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12480015 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8824182 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5791367 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1299957 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 953544 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50831435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1735186 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49951846 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52661 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5989483 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2856975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1193961 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103893877 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.480797 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.214404 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 107793734 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.142828 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.627488 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21731474 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 75223274 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8544304 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1787077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 507604 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 524648 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36495 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62167212 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 115754 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 507604 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22589385 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48401768 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19164228 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9376952 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7753795 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 60013920 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 204923 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2024034 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 144343 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3822558 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 40119139 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72975711 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72834321 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 131688 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35221894 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4897237 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1480119 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 216056 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12920416 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9368350 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6206352 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1340557 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 962340 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53512619 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1895957 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52599778 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52230 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6392747 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3006442 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1305426 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 107793734 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.487967 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.221871 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 83240383 80.12% 80.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8994841 8.66% 88.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3729897 3.59% 92.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2662216 2.56% 94.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2692674 2.59% 97.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1272103 1.22% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 842802 0.81% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 349148 0.34% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109813 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 86044446 79.82% 79.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9475309 8.79% 88.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3928815 3.64% 92.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2790586 2.59% 94.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2836372 2.63% 97.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1349941 1.25% 98.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 893970 0.83% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 358292 0.33% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 116003 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103893877 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 107793734 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 174329 19.02% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 437335 47.71% 66.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 305033 33.28% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 177733 18.25% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 467063 47.95% 66.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 329340 33.81% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34481483 69.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54630 0.11% 69.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 27712 0.06% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9019851 18.06% 87.26% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5598402 11.21% 98.47% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 764115 1.53% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36087462 68.61% 68.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57222 0.11% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28709 0.05% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9582527 18.22% 87.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6011046 11.43% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 827159 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49951846 # Type of FU issued -system.cpu0.iq.rate 0.459148 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 916697 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018352 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 204260867 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 58336070 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48679612 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 506059 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 237571 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 232415 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 50592327 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 272446 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 560089 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52599778 # Type of FU issued +system.cpu0.iq.rate 0.465714 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 974136 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018520 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 213441030 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61548330 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51220095 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 578625 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 270952 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 265721 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53258517 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 311627 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 583786 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1038811 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4304 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17864 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 487331 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1112279 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5019 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18330 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 503254 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18869 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 349661 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 369989 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 470580 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 44276704 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1577501 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 55768983 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 120052 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8824182 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5791367 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1533608 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 47079 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1307470 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17864 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 152204 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 328517 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 480721 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49479281 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8753036 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 472564 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 507604 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 44339596 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1604348 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58817574 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 124782 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9368350 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6206352 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1675353 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 48473 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1332642 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18330 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164161 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 356822 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 520983 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52091421 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9288991 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 508356 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3202362 # number of nop insts executed -system.cpu0.iew.exec_refs 14301032 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7879408 # Number of branches executed -system.cpu0.iew.exec_stores 5547996 # Number of stores executed -system.cpu0.iew.exec_rate 0.454804 # Inst execution rate -system.cpu0.iew.wb_sent 49022541 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48912027 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25297454 # num instructions producing a value -system.cpu0.iew.wb_consumers 34938196 # num instructions consuming a value +system.cpu0.iew.exec_nop 3408998 # number of nop insts executed +system.cpu0.iew.exec_refs 15250639 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8273174 # Number of branches executed +system.cpu0.iew.exec_stores 5961648 # Number of stores executed +system.cpu0.iew.exec_rate 0.461213 # Inst execution rate +system.cpu0.iew.wb_sent 51600991 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51485816 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26436063 # num instructions producing a value +system.cpu0.iew.wb_consumers 36546981 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.724063 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.455851 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723345 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6548409 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 541225 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 440159 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102738863 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.478033 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.411836 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7016261 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 590531 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 476969 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 106554717 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.485172 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.424408 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 85310078 83.04% 83.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6928869 6.74% 89.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3804927 3.70% 93.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2004533 1.95% 95.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1514323 1.47% 96.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 555844 0.54% 97.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 414883 0.40% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 408778 0.40% 98.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1796628 1.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 88252662 82.82% 82.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7298996 6.85% 89.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3974083 3.73% 93.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2090799 1.96% 95.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1561874 1.47% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 585444 0.55% 97.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 439090 0.41% 97.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 445608 0.42% 98.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1906161 1.79% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102738863 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49112602 # Number of instructions committed -system.cpu0.commit.committedOps 49112602 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 106554717 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51697359 # Number of instructions committed +system.cpu0.commit.committedOps 51697359 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13089407 # Number of memory references committed -system.cpu0.commit.loads 7785371 # Number of loads committed -system.cpu0.commit.membars 183023 # Number of memory barriers committed -system.cpu0.commit.branches 7443994 # Number of branches committed -system.cpu0.commit.fp_insts 229281 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45524861 # Number of committed integer instructions. -system.cpu0.commit.function_calls 617737 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2801788 5.70% 5.70% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32185758 65.53% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 53394 0.11% 71.35% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.35% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 27239 0.06% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7968394 16.22% 87.63% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5310031 10.81% 98.44% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 764115 1.56% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13959169 # Number of memory references committed +system.cpu0.commit.loads 8256071 # Number of loads committed +system.cpu0.commit.membars 200989 # Number of memory barriers committed +system.cpu0.commit.branches 7816314 # Number of branches committed +system.cpu0.commit.fp_insts 262681 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47879291 # Number of committed integer instructions. +system.cpu0.commit.function_calls 663768 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2971590 5.75% 5.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33646334 65.08% 70.83% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55999 0.11% 70.94% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28236 0.05% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8457060 16.36% 87.36% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5709098 11.04% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 827159 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49112602 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1796628 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 51697359 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1906161 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 156399894 # The number of ROB reads -system.cpu0.rob.rob_writes 112470885 # The number of ROB writes -system.cpu0.timesIdled 448982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4898702 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693581898 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46314581 # Number of Instructions Simulated -system.cpu0.committedOps 46314581 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.348992 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.348992 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.425715 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.425715 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65241971 # number of integer regfile reads -system.cpu0.int_regfile_writes 35484902 # number of integer regfile writes -system.cpu0.fp_regfile_reads 114300 # number of floating regfile reads -system.cpu0.fp_regfile_writes 114851 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1680980 # number of misc regfile reads -system.cpu0.misc_regfile_writes 762179 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1226061 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.967877 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9972327 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1226573 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.130235 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 163161097 # The number of ROB reads +system.cpu0.rob.rob_writes 118660594 # The number of ROB writes +system.cpu0.timesIdled 501791 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5150541 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3689405733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48729536 # Number of Instructions Simulated +system.cpu0.committedOps 48729536 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.317779 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.317779 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.431448 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.431448 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68466406 # number of integer regfile reads +system.cpu0.int_regfile_writes 37249066 # number of integer regfile writes +system.cpu0.fp_regfile_reads 130692 # number of floating regfile reads +system.cpu0.fp_regfile_writes 131766 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1811017 # number of misc regfile reads +system.cpu0.misc_regfile_writes 827352 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1291740 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.889209 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10636670 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1292252 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.231111 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.967877 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988219 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988219 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.889209 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988065 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988065 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 53849509 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 53849509 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6192446 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6192446 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3442531 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3442531 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150135 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 150135 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172107 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 172107 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9634977 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9634977 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9634977 # number of overall hits -system.cpu0.dcache.overall_hits::total 9634977 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1501821 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1501821 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1669841 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1669841 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19141 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19141 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4636 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4636 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3171662 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3171662 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3171662 # number of overall misses -system.cpu0.dcache.overall_misses::total 3171662 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39101656628 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39101656628 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78115764371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 78115764371 # number of WriteReq miss cycles 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accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5112372 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5112372 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169276 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 169276 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176743 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 176743 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12806639 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12806639 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12806639 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12806639 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195187 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.195187 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.326627 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.326627 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113076 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113076 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026230 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026230 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247658 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247658 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247658 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247658 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26036.163183 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26036.163183 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46780.360748 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46780.360748 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15156.104018 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15156.104018 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7586.870147 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7586.870147 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36957.727841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36957.727841 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3837622 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 160954 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.842974 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 37.561798 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 57483025 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 57483025 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6556019 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6556019 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3715997 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3715997 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164872 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 164872 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189733 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189733 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10272016 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10272016 # number of demand (read+write) hits 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misses +system.cpu0.dcache.overall_misses::cpu0.data 3395313 # number of overall misses +system.cpu0.dcache.overall_misses::total 3395313 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40801843239 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40801843239 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80191363617 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 80191363617 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336613990 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336613990 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 19436381 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 19436381 # number of StoreCondReq miss cycles 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accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192360 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192360 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13667329 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13667329 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13667329 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13667329 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197682 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197682 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323870 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323870 # miss rate for WriteReq accesses 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average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3895440 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3799 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 167914 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.199019 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 40.414894 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 711843 # number of writebacks -system.cpu0.dcache.writebacks::total 711843 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 520027 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 520027 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1419840 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1419840 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4544 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4544 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1939867 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1939867 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1939867 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1939867 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 981794 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 981794 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 250001 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250001 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14597 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14597 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4636 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4636 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1231795 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1231795 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1231795 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1231795 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27071690424 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27071690424 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11368022018 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11368022018 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148174261 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148174261 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25899270 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25899270 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38439712442 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38439712442 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38439712442 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38439712442 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458085000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458085000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2211101998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2211101998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3669186998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3669186998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127601 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127601 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048901 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048901 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086232 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086232 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026230 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026230 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096184 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096184 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27573.697154 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27573.697154 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45471.906184 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45471.906184 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10151.007810 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10151.007810 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5586.555220 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5586.555220 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 762456 # number of writebacks +system.cpu0.dcache.writebacks::total 762456 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 593909 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 593909 # number of ReadReq MSHR hits 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(read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12338398473 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12338398473 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12338398473 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808179 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7808179 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7808179 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7808179 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7808179 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7808179 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110405 # miss rate for ReadReq accesses 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accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8195582 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8195582 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8195582 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8195582 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117038 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117038 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117038 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117038 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117038 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117038 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14177.227819 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14177.227819 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14177.227819 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14177.227819 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4960 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 185 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.367568 # average 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miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10177943027 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105317 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105317 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105317 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12376.851616 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43965 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43965 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43965 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43965 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43965 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43965 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915228 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915228 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915228 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915228 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915228 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915228 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11221708315 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11221708315 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11221708315 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11221708315 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11221708315 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11221708315 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111673 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111673 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111673 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12261.106866 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4575539 # Number of BP lookups -system.cpu1.branchPred.condPredicted 4011453 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 80159 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2846769 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1118608 # Number of BTB hits +system.cpu1.branchPred.lookups 3410499 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2981782 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 63006 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1861186 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 813170 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 39.293950 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 219011 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6943 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 43.690958 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 161954 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4822 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2376918 # DTB read hits -system.cpu1.dtb.read_misses 9978 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 290947 # DTB read accesses -system.cpu1.dtb.write_hits 1576285 # DTB write hits -system.cpu1.dtb.write_misses 2026 # DTB write misses -system.cpu1.dtb.write_acv 38 # DTB write access violations -system.cpu1.dtb.write_accesses 109535 # DTB write accesses -system.cpu1.dtb.data_hits 3953203 # DTB hits -system.cpu1.dtb.data_misses 12004 # DTB misses -system.cpu1.dtb.data_acv 43 # DTB access violations -system.cpu1.dtb.data_accesses 400482 # DTB accesses -system.cpu1.itb.fetch_hits 602928 # ITB hits -system.cpu1.itb.fetch_misses 5576 # ITB misses -system.cpu1.itb.fetch_acv 51 # ITB acv -system.cpu1.itb.fetch_accesses 608504 # ITB accesses +system.cpu1.dtb.read_hits 1800297 # DTB read hits +system.cpu1.dtb.read_misses 9623 # DTB read misses +system.cpu1.dtb.read_acv 4 # DTB read access violations +system.cpu1.dtb.read_accesses 290908 # DTB read accesses +system.cpu1.dtb.write_hits 1120103 # DTB write hits +system.cpu1.dtb.write_misses 2035 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 109629 # DTB write accesses +system.cpu1.dtb.data_hits 2920400 # DTB hits +system.cpu1.dtb.data_misses 11658 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 400537 # DTB accesses +system.cpu1.itb.fetch_hits 513208 # ITB hits +system.cpu1.itb.fetch_misses 5417 # ITB misses +system.cpu1.itb.fetch_acv 59 # ITB acv +system.cpu1.itb.fetch_accesses 518625 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -951,463 +956,463 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 18735029 # number of cpu cycles simulated +system.cpu1.numCycles 13834996 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8327481 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17619609 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4575539 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1337619 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9079051 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 321428 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 222369 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 65129 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1934705 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 65647 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 17881393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.985360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.396691 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5742756 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13201278 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3410499 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 975124 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7052078 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 251690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 24829 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 212437 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 51117 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1482208 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50416 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 13209086 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.999409 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.408470 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 14806869 82.81% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 203122 1.14% 83.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 303524 1.70% 85.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 223355 1.25% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 384843 2.15% 89.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149669 0.84% 89.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 166893 0.93% 90.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 294645 1.65% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1348473 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 10898169 82.51% 82.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 144102 1.09% 83.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 239022 1.81% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 173764 1.32% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 293834 2.22% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 119928 0.91% 89.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 132080 1.00% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 175112 1.33% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1033075 7.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 17881393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.244224 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.940463 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6834927 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8400269 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2240291 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 252863 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 153042 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 134285 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7749 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14408505 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 25621 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 153042 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7012697 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 586426 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6840794 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2316099 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 972333 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13683407 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 9781 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 69005 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 16467 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 367791 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 8910587 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16181694 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16097130 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 77675 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7724005 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1186582 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 556647 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 57942 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2323703 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2456737 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1657029 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 275399 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 155321 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12021391 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 653222 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11806375 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22216 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1705669 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 770229 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 468205 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 17881393 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.660260 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.377042 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13209086 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.246512 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.954195 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 4781490 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6446001 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1665086 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 196515 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 119993 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 102189 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5928 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10739248 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 19374 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 119993 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 4918512 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 544557 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5139003 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1724887 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 762132 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10178184 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4877 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 68265 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 13199 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 289695 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6692544 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12133960 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12078154 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 50250 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5671659 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1020885 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 419664 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 38232 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1772644 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1865226 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1191683 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 210655 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 119712 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8963290 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 478811 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8726606 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20522 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1437541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 698510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 352654 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13209086 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.660652 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.378469 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 12935770 72.34% 72.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2198264 12.29% 84.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 914656 5.12% 89.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 630896 3.53% 93.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 572849 3.20% 96.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 314457 1.76% 98.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 208202 1.16% 99.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 77174 0.43% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 29125 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9547804 72.28% 72.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1625741 12.31% 84.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 686242 5.20% 89.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 474957 3.60% 93.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 417301 3.16% 96.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 221804 1.68% 98.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 145793 1.10% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 65024 0.49% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 24420 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 17881393 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13209086 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 23808 8.12% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 159009 54.21% 62.33% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 110483 37.67% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22353 9.61% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 126163 54.23% 63.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 84116 36.16% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7355530 62.30% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 19854 0.17% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12327 0.10% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2486397 21.06% 83.68% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1602376 13.57% 97.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 324614 2.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5425627 62.17% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 15090 0.17% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10661 0.12% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1878240 21.52% 84.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1141614 13.08% 97.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 250097 2.87% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11806375 # Type of FU issued -system.cpu1.iq.rate 0.630176 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 293300 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.024843 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 41494201 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 14236824 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 11389686 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 315458 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 147457 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 145351 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11926347 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 169810 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 115792 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8726606 # Type of FU issued +system.cpu1.iq.rate 0.630763 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 232632 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.026658 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 30722514 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10791679 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8409842 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 192938 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 91772 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 89511 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8852667 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 103053 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 90033 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 308768 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1081 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4102 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 143102 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 271460 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 498 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 125337 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 395 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 55406 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 380 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 50736 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 153042 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 303896 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 248843 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13398271 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 36703 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2456737 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1657029 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 586577 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4501 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 243181 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4102 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 36741 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 118067 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 154808 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11654930 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2396476 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 151445 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 119993 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 268498 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 245239 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9936241 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 29107 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1865226 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1191683 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 435120 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4465 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 239666 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3940 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28286 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 93108 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 121394 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8606074 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1816179 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 120532 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 723658 # number of nop insts executed -system.cpu1.iew.exec_refs 3982565 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1739472 # Number of branches executed -system.cpu1.iew.exec_stores 1586089 # Number of stores executed -system.cpu1.iew.exec_rate 0.622093 # Inst execution rate -system.cpu1.iew.wb_sent 11565622 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11535037 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5422471 # num instructions producing a value -system.cpu1.iew.wb_consumers 7736628 # num instructions consuming a value +system.cpu1.iew.exec_nop 494140 # number of nop insts executed +system.cpu1.iew.exec_refs 2943760 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1279494 # Number of branches executed +system.cpu1.iew.exec_stores 1127581 # Number of stores executed +system.cpu1.iew.exec_rate 0.622051 # Inst execution rate +system.cpu1.iew.wb_sent 8526125 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8499353 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4051784 # num instructions producing a value +system.cpu1.iew.wb_consumers 5752933 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.615694 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.700883 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614337 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.704299 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1839025 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 185017 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142916 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 17538839 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.655077 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.643008 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1506985 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126157 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 110245 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 12932417 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.645119 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.622232 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 13431880 76.58% 76.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1875136 10.69% 87.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 688221 3.92% 91.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 418119 2.38% 93.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 312509 1.78% 95.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 131127 0.75% 96.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 110360 0.63% 96.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 156367 0.89% 97.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 415120 2.37% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 9905025 76.59% 76.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1407731 10.89% 87.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 501740 3.88% 91.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 308618 2.39% 93.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 224670 1.74% 95.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 96970 0.75% 96.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 89070 0.69% 96.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 100805 0.78% 97.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 297788 2.30% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 17538839 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 11489295 # Number of instructions committed -system.cpu1.commit.committedOps 11489295 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 12932417 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8342954 # Number of instructions committed +system.cpu1.commit.committedOps 8342954 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3661896 # Number of memory references committed -system.cpu1.commit.loads 2147969 # Number of loads committed -system.cpu1.commit.membars 61867 # Number of memory barriers committed -system.cpu1.commit.branches 1640602 # Number of branches committed -system.cpu1.commit.fp_insts 143665 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 10598150 # Number of committed integer instructions. -system.cpu1.commit.function_calls 183822 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 606334 5.28% 5.28% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6800030 59.19% 64.46% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 19654 0.17% 64.63% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.63% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 12323 0.11% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 2209836 19.23% 83.99% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1514745 13.18% 97.17% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 324614 2.83% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2660112 # Number of memory references committed +system.cpu1.commit.loads 1593766 # Number of loads committed +system.cpu1.commit.membars 39768 # Number of memory barriers committed +system.cpu1.commit.branches 1189273 # Number of branches committed +system.cpu1.commit.fp_insts 87820 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7729091 # Number of committed integer instructions. +system.cpu1.commit.function_calls 132492 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 404429 4.85% 4.85% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 4960733 59.46% 64.31% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 14917 0.18% 64.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10656 0.13% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1633534 19.58% 84.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1066829 12.79% 97.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 250097 3.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 11489295 # Class of committed instruction -system.cpu1.commit.bw_lim_events 415120 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 8342954 # Class of committed instruction +system.cpu1.commit.bw_lim_events 297788 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 30366198 # The number of ROB reads -system.cpu1.rob.rob_writes 26995045 # The number of ROB writes -system.cpu1.timesIdled 163095 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 853636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3782985916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 10886479 # Number of Instructions Simulated -system.cpu1.committedOps 10886479 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.720945 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.720945 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.581076 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.581076 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14951888 # number of integer regfile reads -system.cpu1.int_regfile_writes 8155185 # number of integer regfile writes -system.cpu1.fp_regfile_reads 77020 # number of floating regfile reads -system.cpu1.fp_regfile_writes 77068 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1117526 # number of misc regfile reads -system.cpu1.misc_regfile_writes 276759 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 138501 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.617684 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3193598 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 138812 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.006642 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 39570817000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.617684 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962144 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.962144 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15087685 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15087685 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1906947 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1906947 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1195571 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1195571 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 44901 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 44901 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 43886 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 43886 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3102518 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3102518 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3102518 # number of overall hits -system.cpu1.dcache.overall_hits::total 3102518 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 266692 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 266692 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 262982 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 262982 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8052 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8052 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4916 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 4916 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 529674 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 529674 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 529674 # number of overall misses -system.cpu1.dcache.overall_misses::total 529674 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4020623652 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4020623652 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8531401983 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8531401983 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 76759992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 76759992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 36344731 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 36344731 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12552025635 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12552025635 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12552025635 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12552025635 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2173639 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2173639 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1458553 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1458553 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 52953 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 52953 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 48802 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 48802 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3632192 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3632192 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3632192 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3632192 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.122694 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.122694 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.180303 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.180303 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152059 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152059 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100734 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100734 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.145828 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.145828 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.145828 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.145828 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15075.906484 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15075.906484 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32441.011107 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32441.011107 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9533.034277 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9533.034277 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7393.151139 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7393.151139 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23697.643522 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23697.643522 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 379144 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 215 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 18342 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.670810 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 23.888889 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 22401053 # The number of ROB reads +system.cpu1.rob.rob_writes 19972727 # The number of ROB writes +system.cpu1.timesIdled 110858 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 625910 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3787862669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 7942043 # Number of Instructions Simulated +system.cpu1.committedOps 7942043 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.741995 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.741995 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.574055 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.574055 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11080172 # number of integer regfile reads +system.cpu1.int_regfile_writes 6056867 # number of integer regfile writes +system.cpu1.fp_regfile_reads 49492 # number of floating regfile reads +system.cpu1.fp_regfile_writes 48750 # number of floating regfile writes +system.cpu1.misc_regfile_reads 911686 # number of misc regfile reads +system.cpu1.misc_regfile_writes 198554 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 93396 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.127271 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2362095 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 93708 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 25.206973 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1032235519500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.127271 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959233 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.959233 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.609375 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11044469 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11044469 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1462423 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1462423 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 846221 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 846221 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29364 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 29364 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27945 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 27945 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2308644 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2308644 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2308644 # number of overall hits +system.cpu1.dcache.overall_hits::total 2308644 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 178507 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 178507 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 183677 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 183677 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4603 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4603 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2762 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2762 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 362184 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 362184 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 362184 # number of overall misses +system.cpu1.dcache.overall_misses::total 362184 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2741731463 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2741731463 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7132330313 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7132330313 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 45481992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 45481992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20461911 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 20461911 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9874061776 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9874061776 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9874061776 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9874061776 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1640930 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1640930 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1029898 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1029898 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33967 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 33967 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 30707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2670828 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2670828 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2670828 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2670828 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108784 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.108784 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178345 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.178345 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.089947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.089947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135607 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135607 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135607 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135607 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9880.945470 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9880.945470 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7408.367487 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7408.367487 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 351094 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 268 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 15302 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.944321 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 17.866667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 93139 # number of writebacks -system.cpu1.dcache.writebacks::total 93139 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 164682 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 164682 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 213530 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 213530 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 378212 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 378212 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 378212 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 378212 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 102010 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 102010 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 49452 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 49452 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7397 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7397 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4916 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 4916 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 151462 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 151462 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 151462 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 151462 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1194457513 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1194457513 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1312928589 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1312928589 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54001007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54001007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26510269 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26510269 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2507386102 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2507386102 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2507386102 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2507386102 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24847500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24847500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 692513000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 692513000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717360500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717360500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046931 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046931 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033905 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033905 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.139690 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.139690 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100734 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100734 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041700 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.041700 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041700 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.041700 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11709.219812 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11709.219812 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26549.554902 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26549.554902 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7300.392997 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7300.392997 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5392.650325 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5392.650325 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16554.555611 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 60059 # number of writebacks +system.cpu1.dcache.writebacks::total 60059 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 108966 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 108966 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 150714 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 150714 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 427 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 259680 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 259680 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 259680 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 259680 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69541 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 69541 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32963 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 32963 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4176 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4176 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2762 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2762 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 102504 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 102504 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 102504 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 102504 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 829052502 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 829052502 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081287205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081287205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31817008 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31817008 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14937089 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14937089 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1910339707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1910339707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1910339707 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1910339707 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24846500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24846500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 618764500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 618764500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643611000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643611000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042379 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042379 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032006 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.122943 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.122943 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.089947 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.089947 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038379 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038379 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7619.015326 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7619.015326 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5408.069877 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5408.069877 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1415,95 +1420,95 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 306147 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.962529 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1618659 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 306656 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.278419 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878409820250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.962529 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919849 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919849 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id +system.cpu1.icache.tags.replacements 205003 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.613699 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1269898 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 205514 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.179131 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1878408675250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.613699 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919167 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919167 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2241410 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2241410 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1618659 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1618659 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1618659 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1618659 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1618659 # number of overall hits -system.cpu1.icache.overall_hits::total 1618659 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316046 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316046 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316046 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316046 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316046 # number of overall misses -system.cpu1.icache.overall_misses::total 316046 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4251188208 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4251188208 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4251188208 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4251188208 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4251188208 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4251188208 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1934705 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1934705 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1934705 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1934705 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1934705 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1934705 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.163356 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.163356 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.163356 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.163356 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.163356 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.163356 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13451.169159 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13451.169159 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13451.169159 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13451.169159 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1687783 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1687783 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1269898 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1269898 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1269898 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1269898 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1269898 # number of overall hits +system.cpu1.icache.overall_hits::total 1269898 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 212310 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 212310 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 212310 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 212310 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 212310 # number of overall misses +system.cpu1.icache.overall_misses::total 212310 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2888653039 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2888653039 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2888653039 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2888653039 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2888653039 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2888653039 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1482208 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1482208 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1482208 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1482208 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1482208 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1482208 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.143239 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.143239 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.143239 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.143239 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.143239 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.143239 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13605.826570 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13605.826570 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 412 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.307692 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.846154 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9341 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 9341 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 9341 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 9341 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 9341 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 9341 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 306705 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 306705 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 306705 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 306705 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 306705 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 306705 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3543296218 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3543296218 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3543296218 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3543296218 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3543296218 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3543296218 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158528 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.158528 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.158528 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11552.782700 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6735 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6735 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6735 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6735 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6735 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6735 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 205575 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 205575 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 205575 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 205575 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 205575 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 205575 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2403236890 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2403236890 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2403236890 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2403236890 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2403236890 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2403236890 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.138695 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.138695 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.138695 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1517,13 +1522,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7368 # Transaction distribution -system.iobus.trans_dist::ReadResp 7368 # Transaction distribution -system.iobus.trans_dist::WriteReq 55198 # Transaction distribution -system.iobus.trans_dist::WriteResp 13646 # Transaction distribution +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 54536 # Transaction distribution +system.iobus.trans_dist::WriteResp 12984 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13082 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1534,12 +1539,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 41682 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123826 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1550,13 +1555,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 78554 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2740162 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12437000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73266 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2734938 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1576,52 +1581,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406224779 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406222784 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28036000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27376000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010550 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42026793 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41693 # number of replacements -system.iocache.tags.tagsinuse 0.465320 # Cycle average of tags in use +system.iocache.tags.replacements 41701 # number of replacements +system.iocache.tags.tagsinuse 0.465228 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710336865000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.465320 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029083 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029083 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710337218000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.465228 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.029077 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.tags.tag_accesses 375597 # Number of tag accesses +system.iocache.tags.data_accesses 375597 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 181 # number of ReadReq misses +system.iocache.ReadReq_misses::total 181 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13658910846 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13658910846 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21134383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21134383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21134383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21134383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 181 # number of demand (read+write) misses +system.iocache.demand_misses::total 181 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 181 # number of overall misses +system.iocache.overall_misses::total 181 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22038383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22038383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13652440608 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13652440608 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22038383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22038383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22038383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22038383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 181 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 181 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 181 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 181 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 181 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 181 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1630,40 +1635,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328718.493598 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328718.493598 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122164.063584 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122164.063584 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 207096 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121759.022099 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121759.022099 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121759.022099 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206720 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23572 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23552 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.785678 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.777174 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 181 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11498106946 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11498106946 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12137383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12137383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12137383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12137383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 181 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 181 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 181 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 181 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12625383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12625383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11491649194 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11491649194 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12625383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12625383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12625383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12625383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1672,189 +1677,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276716.089382 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276716.089382 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345011 # number of replacements -system.l2c.tags.tagsinuse 65255.839207 # Cycle average of tags in use -system.l2c.tags.total_refs 2587062 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410177 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.307184 # Average number of references to valid blocks. +system.l2c.tags.replacements 345072 # number of replacements +system.l2c.tags.tagsinuse 65237.196274 # Cycle average of tags in use +system.l2c.tags.total_refs 2611817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410198 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.367210 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53401.606938 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5320.695867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6228.167915 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 214.693065 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 90.675422 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.814844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081187 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.095034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001384 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995725 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2663 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5629 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5286 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51350 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27100727 # Number of tag accesses -system.l2c.tags.data_accesses 27100727 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 808308 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 697381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 305176 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 93224 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1904089 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 804982 # number of Writeback hits -system.l2c.Writeback_hits::total 804982 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 430 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 602 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 137834 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 34568 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172402 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 808308 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 835215 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 305176 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 127792 # number of demand (read+write) hits -system.l2c.demand_hits::total 2076491 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 808308 # number of overall hits -system.l2c.overall_hits::cpu0.data 835215 # number of overall hits -system.l2c.overall_hits::cpu1.inst 305176 # number of overall hits -system.l2c.overall_hits::cpu1.data 127792 # number of overall hits -system.l2c.overall_hits::total 2076491 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13868 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273214 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1510 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 835 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289427 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2863 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1520 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4383 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 730 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 742 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1472 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114473 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121925 # number of ReadExReq misses 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ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 74847500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19201570000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1318455 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 8321116 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9639571 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1217948 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209991 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1427939 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9484677078 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 797025966 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10281703044 # number of ReadExReq miss cycles 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overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164384 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53167.825985 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76666.454082 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53787.048176 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.083673 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.050744 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.503902 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10061.356955 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.805288 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.493099 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70998.038549 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94425.922444 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72353.628002 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1992,101 +1997,101 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296777 # Transaction distribution -system.membus.trans_dist::ReadResp 296698 # Transaction distribution -system.membus.trans_dist::WriteReq 13646 # Transaction distribution -system.membus.trans_dist::WriteResp 13646 # Transaction distribution -system.membus.trans_dist::Writeback 123016 # Transaction distribution +system.membus.trans_dist::ReadReq 296649 # Transaction distribution +system.membus.trans_dist::ReadResp 296568 # Transaction distribution +system.membus.trans_dist::WriteReq 12984 # Transaction distribution +system.membus.trans_dist::WriteResp 12984 # Transaction distribution +system.membus.trans_dist::Writeback 123204 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14268 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9480 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6314 # Transaction distribution -system.membus.trans_dist::ReadExReq 122151 # Transaction distribution -system.membus.trans_dist::ReadExResp 121466 # Transaction distribution -system.membus.trans_dist::BadAddressError 79 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41682 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 933549 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 975389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1100201 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78554 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31488576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31567130 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 9668 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5310 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4924 # Transaction distribution +system.membus.trans_dist::ReadExReq 121989 # Transaction distribution +system.membus.trans_dist::ReadExResp 121610 # Transaction distribution +system.membus.trans_dist::BadAddressError 81 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 923282 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 963804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1088624 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73266 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31500992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31574258 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36884698 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 18563 # Total snoops (count) -system.membus.snoop_fanout::samples 600049 # Request fanout histogram +system.membus.pkt_size::total 36891826 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 10884 # Total snoops (count) +system.membus.snoop_fanout::samples 591178 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600049 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 591178 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600049 # Request fanout histogram -system.membus.reqLayer0.occupancy 40411498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 591178 # Request fanout histogram +system.membus.reqLayer0.occupancy 38973998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1927899500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1927807998 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 99500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3832783452 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3829664091 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43159450 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43225207 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2231232 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2231137 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13646 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13646 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 804982 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 14411 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 23963 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296031 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296031 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1644513 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3224840 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 613391 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 402307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5885051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52619264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123882452 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19627904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14694726 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 210824346 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 91368 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3390565 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012306 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110249 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2228449 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2228352 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12984 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12984 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822515 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9795 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5388 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15183 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301926 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301926 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1830333 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3396960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 411121 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 269188 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5907602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58566720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131328844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13154944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9749222 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 212799730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 73699 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3402430 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012266 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110070 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3348840 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41725 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3360696 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41734 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3390565 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4912159072 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3402430 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4987291538 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3705712969 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4124247177 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5664612723 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5936070669 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1381251781 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 692182943 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 925874109 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 467054772 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2120,32 +2125,32 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6735 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 170888 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 59399 40.36% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1921 1.31% 41.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 339 0.23% 41.99% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 85372 58.01% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 147162 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 58699 49.14% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1921 1.61% 50.86% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 339 0.28% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 58360 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 119450 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1860822176500 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61176000 0.00% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 541931500 0.03% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 152116500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39608995500 2.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901186396000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988215 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6564 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 186274 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65832 40.54% 40.54% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1922 1.18% 41.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 173 0.11% 41.91% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94323 58.09% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162381 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64799 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1922 1.46% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 173 0.13% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64626 49.09% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131651 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1859979639500 97.83% 97.83% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61305500 0.00% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 538798500 0.03% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 78674500 0.00% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40515747500 2.13% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1901174165500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984309 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683596 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811691 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685156 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810754 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed @@ -2177,60 +2182,60 @@ system.cpu0.kern.syscall::144 2 0.86% 99.14% # nu system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 232 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 432 0.28% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3241 2.09% 2.37% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed -system.cpu0.kern.callpal::swpipl 140334 90.29% 92.69% # number of callpals executed -system.cpu0.kern.callpal::rdps 6381 4.11% 96.80% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::rti 4436 2.85% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 155429 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7000 # number of protection mode switches +system.cpu0.kern.callpal::wripir 266 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3573 2.09% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155550 90.98% 93.26% # number of callpals executed +system.cpu0.kern.callpal::rdps 6382 3.73% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4604 2.69% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 391 0.23% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 170980 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7167 # number of protection mode switches system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1354 system.cpu0.kern.mode_good::user 1355 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.193429 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188921 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.324237 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899184407000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2001981000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.317883 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1899194834000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1979323500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3242 # number of times the context was actually changed +system.cpu0.kern.swap_context 3574 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2589 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 70429 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 23508 38.03% 38.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 3.11% 41.14% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 432 0.70% 41.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 35949 58.16% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 61809 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 22831 47.98% 47.98% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 4.04% 52.02% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 432 0.91% 52.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 22399 47.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 47582 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869145937500 98.33% 98.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 530408500 0.03% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 194479500 0.01% 98.37% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30989632500 1.63% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900860458000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.971201 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2428 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 53091 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16423 36.25% 36.25% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 4.24% 40.49% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 266 0.59% 41.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26695 58.92% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45304 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16079 47.18% 47.18% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 5.63% 52.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 266 0.78% 53.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15813 46.40% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34078 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870417466500 98.40% 98.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 530332500 0.03% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 120265000 0.01% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29780754000 1.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900848818000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979054 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.623077 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769823 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.592358 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.752207 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed @@ -2246,35 +2251,35 @@ system.cpu1.kern.syscall::74 9 9.57% 96.81% # nu system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 94 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 339 0.53% 0.53% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1656 2.59% 3.12% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.13% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 56045 87.56% 90.70% # number of callpals executed -system.cpu1.kern.callpal::rdps 2366 3.70% 94.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.40% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.41% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.41% # number of callpals executed -system.cpu1.kern.callpal::rti 3411 5.33% 99.74% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.19% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 173 0.37% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 989 2.11% 2.49% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.49% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40205 85.85% 88.36% # number of callpals executed +system.cpu1.kern.callpal::rdps 2366 5.05% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed +system.cpu1.kern.callpal::rti 2912 6.22% 99.64% # number of callpals executed +system.cpu1.kern.callpal::callsys 124 0.26% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 64005 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1702 # number of protection mode switches +system.cpu1.kern.callpal::total 46833 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1197 # number of protection mode switches system.cpu1.kern.mode_switch::user 384 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2700 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 740 +system.cpu1.kern.mode_switch::idle 2372 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 574 system.cpu1.kern.mode_good::user 384 -system.cpu1.kern.mode_good::idle 356 -system.cpu1.kern.mode_switch_good::kernel 0.434783 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 190 +system.cpu1.kern.mode_switch_good::kernel 0.479532 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.131852 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309235 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6130779500 0.32% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 692688500 0.04% 0.36% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893719133000 99.64% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1657 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.080101 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.290412 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3852720500 0.20% 0.20% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 690217500 0.04% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1895996394000 99.76% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 990 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 44e9b2e2b..aba3b9944 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859049 # Number of seconds simulated -sim_ticks 1859049148500 # Number of ticks simulated -final_tick 1859049148500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859045 # Number of seconds simulated +sim_ticks 1859045389000 # Number of ticks simulated +final_tick 1859045389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168870 # Simulator instruction rate (inst/s) -host_op_rate 168870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5931192571 # Simulator tick rate (ticks/s) -host_mem_usage 320216 # Number of bytes of host memory used -host_seconds 313.44 # Real time elapsed on the host -sim_insts 52930035 # Number of instructions simulated -sim_ops 52930035 # Number of ops (including micro ops) simulated +host_inst_rate 155751 # Simulator instruction rate (inst/s) +host_op_rate 155751 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5470499619 # Simulator tick rate (ticks/s) +host_mem_usage 374716 # Number of bytes of host memory used +host_seconds 339.83 # Real time elapsed on the host +sim_insts 52929026 # Number of instructions simulated +sim_ops 52929026 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 968128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24876416 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388684 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25845504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15127 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388694 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13380914 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117450 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117450 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13381285 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13901679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13380914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13902567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043366 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043366 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13381285 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17944726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403811 # Number of read requests accepted -system.physmem.writeReqs 158993 # Number of write requests accepted -system.physmem.readBursts 403811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158993 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25836928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 10037376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10175552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2130 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write +system.physmem.bw_total::total 17945933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403836 # Number of read requests accepted +system.physmem.writeReqs 159002 # Number of write requests accepted +system.physmem.readBursts 403836 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159002 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25838848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 10042304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25845504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10176128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2068 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 208 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25744 # Per bank write bursts -system.physmem.perBankRdBursts::1 25560 # Per bank write bursts -system.physmem.perBankRdBursts::2 25512 # Per bank write bursts -system.physmem.perBankRdBursts::3 25342 # Per bank write bursts -system.physmem.perBankRdBursts::4 25388 # Per bank write bursts -system.physmem.perBankRdBursts::5 24802 # Per bank write bursts -system.physmem.perBankRdBursts::6 25022 # Per bank write bursts -system.physmem.perBankRdBursts::7 25128 # Per bank write bursts -system.physmem.perBankRdBursts::8 24929 # Per bank write bursts -system.physmem.perBankRdBursts::9 25033 # Per bank write bursts -system.physmem.perBankRdBursts::10 25435 # Per bank write bursts -system.physmem.perBankRdBursts::11 24778 # Per bank write bursts -system.physmem.perBankRdBursts::12 24542 # Per bank write bursts -system.physmem.perBankRdBursts::13 25239 # Per bank write bursts -system.physmem.perBankRdBursts::14 25649 # Per bank write bursts -system.physmem.perBankRdBursts::15 25599 # Per bank write bursts -system.physmem.perBankWrBursts::0 10531 # Per bank write bursts -system.physmem.perBankWrBursts::1 10049 # Per bank write bursts -system.physmem.perBankWrBursts::2 10576 # Per bank write bursts -system.physmem.perBankWrBursts::3 9740 # Per bank write bursts -system.physmem.perBankWrBursts::4 9614 # Per bank write bursts -system.physmem.perBankWrBursts::5 9115 # Per bank write bursts -system.physmem.perBankWrBursts::6 9087 # Per bank write bursts -system.physmem.perBankWrBursts::7 8933 # Per bank write bursts -system.physmem.perBankWrBursts::8 9694 # Per bank write bursts -system.physmem.perBankWrBursts::9 8895 # Per bank write bursts -system.physmem.perBankWrBursts::10 9699 # Per bank write bursts -system.physmem.perBankWrBursts::11 9449 # Per bank write bursts -system.physmem.perBankWrBursts::12 10004 # Per bank write bursts +system.physmem.perBankRdBursts::1 25557 # Per bank write bursts +system.physmem.perBankRdBursts::2 25510 # Per bank write bursts +system.physmem.perBankRdBursts::3 25348 # Per bank write bursts +system.physmem.perBankRdBursts::4 25387 # Per bank write bursts +system.physmem.perBankRdBursts::5 24799 # Per bank write bursts +system.physmem.perBankRdBursts::6 25027 # Per bank write bursts +system.physmem.perBankRdBursts::7 25129 # Per bank write bursts +system.physmem.perBankRdBursts::8 24928 # Per bank write bursts +system.physmem.perBankRdBursts::9 25032 # Per bank write bursts +system.physmem.perBankRdBursts::10 25436 # Per bank write bursts +system.physmem.perBankRdBursts::11 24784 # Per bank write bursts +system.physmem.perBankRdBursts::12 24551 # Per bank write bursts +system.physmem.perBankRdBursts::13 25235 # Per bank write bursts +system.physmem.perBankRdBursts::14 25659 # Per bank write bursts +system.physmem.perBankRdBursts::15 25606 # Per bank write bursts +system.physmem.perBankWrBursts::0 10485 # Per bank write bursts +system.physmem.perBankWrBursts::1 10108 # Per bank write bursts +system.physmem.perBankWrBursts::2 10574 # Per bank write bursts +system.physmem.perBankWrBursts::3 9632 # Per bank write bursts +system.physmem.perBankWrBursts::4 9668 # Per bank write bursts +system.physmem.perBankWrBursts::5 9137 # Per bank write bursts +system.physmem.perBankWrBursts::6 9064 # Per bank write bursts +system.physmem.perBankWrBursts::7 8900 # Per bank write bursts +system.physmem.perBankWrBursts::8 9821 # Per bank write bursts +system.physmem.perBankWrBursts::9 8750 # Per bank write bursts +system.physmem.perBankWrBursts::10 9677 # Per bank write bursts +system.physmem.perBankWrBursts::11 9460 # Per bank write bursts +system.physmem.perBankWrBursts::12 10019 # Per bank write bursts system.physmem.perBankWrBursts::13 10709 # Per bank write bursts -system.physmem.perBankWrBursts::14 10413 # Per bank write bursts -system.physmem.perBankWrBursts::15 10326 # Per bank write bursts +system.physmem.perBankWrBursts::14 10502 # Per bank write bursts +system.physmem.perBankWrBursts::15 10405 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 1859043836000 # Total gap between requests +system.physmem.totGap 1859040142000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403811 # Read request sizes (log2) +system.physmem.readPktSize::6 403836 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 158993 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314947 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159002 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314988 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -148,120 +148,119 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 562.390130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 348.747922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.715872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13502 21.17% 21.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10319 16.18% 37.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4795 7.52% 44.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2857 4.48% 49.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2332 3.66% 53.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1655 2.59% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1501 2.35% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1587 2.49% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25241 39.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63789 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5661 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.309309 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2806.420357 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5658 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63696 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 563.318764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 349.809758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.596932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13378 21.00% 21.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10306 16.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4860 7.63% 44.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2855 4.48% 49.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2272 3.57% 52.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1671 2.62% 55.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1518 2.38% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1616 2.54% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25220 39.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63696 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.190619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2803.945627 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5668 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5661 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5661 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.704293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.909682 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.456612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4621 81.63% 81.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 191 3.37% 85.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 281 4.96% 89.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 54 0.95% 90.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 96 1.70% 92.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 48 0.85% 93.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.30% 93.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 14 0.25% 94.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.34% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 15 0.26% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 5 0.09% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 19 0.34% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 42 0.74% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 21 0.37% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 11 0.19% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 96 1.70% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 35 0.62% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 14 0.25% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 13 0.23% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.18% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 6 0.11% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5661 # Writes before turning the bus around for reads -system.physmem.totQLat 3666880250 # Total ticks spent queuing -system.physmem.totMemAccLat 11236292750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9083.14 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5671 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5671 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.669018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.928355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.069194 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4623 81.52% 81.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 171 3.02% 84.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 302 5.33% 89.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 63 1.11% 90.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 97 1.71% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 43 0.76% 93.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 19 0.34% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 6 0.11% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 22 0.39% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.30% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 6 0.11% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 18 0.32% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 43 0.76% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 8 0.14% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 17 0.30% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 89 1.57% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 36 0.63% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 17 0.30% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 22 0.39% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 13 0.23% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 5 0.09% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5671 # Writes before turning the bus around for reads +system.physmem.totQLat 3621320000 # Total ticks spent queuing +system.physmem.totMemAccLat 11191295000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8969.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27833.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27719.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s @@ -270,67 +269,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing -system.physmem.readRowHits 364667 # Number of row buffer hits during reads -system.physmem.writeRowHits 132080 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.20 # Row buffer hit rate for writes -system.physmem.avgGap 3303181.63 # Average gap between requests -system.physmem.pageHitRate 88.62 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1760890123500 # Time in different power states -system.physmem.memoryStateTime::REF 62077600000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 36077600250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 239795640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 242449200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 130840875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132288750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1579484400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1569391200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 503139600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 513144720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 55719498420 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 55486362150 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1066550433000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1066754938500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1246146977535 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1246122360120 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.315549 # Core power per rank (mW) -system.physmem.averagePower::1 670.302307 # Core power per rank (mW) -system.cpu.branchPred.lookups 17761302 # Number of BP lookups -system.cpu.branchPred.condPredicted 15456576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379954 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12009119 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5937139 # Number of BTB hits +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.54 # Average write queue length when enqueuing +system.physmem.readRowHits 364717 # Number of row buffer hits during reads +system.physmem.writeRowHits 132230 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes +system.physmem.avgGap 3302975.53 # Average gap between requests +system.physmem.pageHitRate 88.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239009400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130411875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579507800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 502640640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 55671864660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1066592208750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1246139428725 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.311493 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1774205493250 # Time in different power states +system.physmem_0.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22762216750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 242532360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 132334125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1569601800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 514142640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 55569327930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1066682161500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1246133885955 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.308507 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1774360012750 # Time in different power states +system.physmem_1.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22607711000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 17755011 # Number of BP lookups +system.cpu.branchPred.condPredicted 15447257 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 380557 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11928628 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5915753 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.438589 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 914399 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21305 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 49.592904 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 917507 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21428 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10308188 # DTB read hits -system.cpu.dtb.read_misses 41379 # DTB read misses -system.cpu.dtb.read_acv 521 # DTB read access violations -system.cpu.dtb.read_accesses 967155 # DTB read accesses -system.cpu.dtb.write_hits 6646702 # DTB write hits -system.cpu.dtb.write_misses 9325 # DTB write misses -system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 342603 # DTB write accesses -system.cpu.dtb.data_hits 16954890 # DTB hits -system.cpu.dtb.data_misses 50704 # DTB misses -system.cpu.dtb.data_acv 931 # DTB access violations -system.cpu.dtb.data_accesses 1309758 # DTB accesses -system.cpu.itb.fetch_hits 1770443 # ITB hits -system.cpu.itb.fetch_misses 36092 # ITB misses -system.cpu.itb.fetch_acv 664 # ITB acv -system.cpu.itb.fetch_accesses 1806535 # ITB accesses +system.cpu.dtb.read_hits 10297861 # DTB read hits +system.cpu.dtb.read_misses 41459 # DTB read misses +system.cpu.dtb.read_acv 502 # DTB read access violations +system.cpu.dtb.read_accesses 968382 # DTB read accesses +system.cpu.dtb.write_hits 6648165 # DTB write hits +system.cpu.dtb.write_misses 9537 # DTB write misses +system.cpu.dtb.write_acv 407 # DTB write access violations +system.cpu.dtb.write_accesses 342637 # DTB write accesses +system.cpu.dtb.data_hits 16946026 # DTB hits +system.cpu.dtb.data_misses 50996 # DTB misses +system.cpu.dtb.data_acv 909 # DTB access violations +system.cpu.dtb.data_accesses 1311019 # DTB accesses +system.cpu.itb.fetch_hits 1769037 # ITB hits +system.cpu.itb.fetch_misses 35976 # ITB misses +system.cpu.itb.fetch_acv 675 # ITB acv +system.cpu.itb.fetch_accesses 1805013 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -343,256 +347,256 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118298016 # number of cpu cycles simulated +system.cpu.numCycles 118253854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29541198 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78055768 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17761302 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6851538 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80476428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1253224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1384 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1737629 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 451562 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9019799 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273133 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 29528041 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78024704 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17755011 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6833260 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80443267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1255548 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1917 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1737879 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 457742 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9020958 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 272859 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112863592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.691594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.010851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 112824612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.691557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.011053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98289284 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 935566 0.83% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1976201 1.75% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 911928 0.81% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2795335 2.48% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 642698 0.57% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 727750 0.64% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007954 0.89% 95.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5576876 4.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98261708 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 933543 0.83% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1973411 1.75% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 908515 0.81% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2794922 2.48% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 638903 0.57% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 728605 0.65% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007079 0.89% 95.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5577926 4.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112863592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150140 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.659823 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24058379 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76821722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9496623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1902660 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 584207 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 588094 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68303161 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 133250 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 584207 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24982800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47259981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20734687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10387203 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8914712 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65869472 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 202922 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2041149 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 141248 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4766165 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43946104 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79818079 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79637315 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168311 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38139253 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5806843 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1691151 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241440 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13536828 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10424364 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6928356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1483959 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1059889 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58630025 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2138995 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57603342 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50950 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7503583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3485287 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1477804 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112863592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.510380 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.252962 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 112824612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150143 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.659807 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24062318 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76790103 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9490656 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1896068 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 585466 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586954 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42767 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68209057 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130935 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 585466 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24987088 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 47248716 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20734654 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10372019 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8896667 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65782894 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 200446 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2040001 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 143212 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4746299 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43863584 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79748694 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79567373 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168869 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38138490 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5725086 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1691130 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13583154 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10423192 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6953251 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1496634 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1073096 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58558441 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2136854 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57535876 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 59225 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7428094 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503981 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1475675 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 112824612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.509959 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.252016 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89383207 79.20% 79.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10013548 8.87% 88.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4301377 3.81% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2962557 2.62% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3086274 2.73% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1586017 1.41% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1012124 0.90% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 396460 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 122028 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89346173 79.19% 79.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10029271 8.89% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4305402 3.82% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2956038 2.62% 94.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3073019 2.72% 97.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1592834 1.41% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1003723 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 396113 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 122039 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112863592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 112824612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 213045 18.77% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547519 48.24% 67.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 374446 32.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206156 18.23% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547934 48.46% 66.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 376604 33.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39102059 67.88% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61815 0.11% 68.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38377 0.07% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10718615 18.61% 86.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722522 11.67% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949032 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39037949 67.85% 67.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61847 0.11% 67.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38375 0.07% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10709010 18.61% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6728743 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949030 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57603342 # Type of FU issued -system.cpu.iq.rate 0.486934 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1135010 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019704 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228544022 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67957775 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55921178 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712213 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 334464 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328973 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58348779 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382287 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 639736 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57535876 # Type of FU issued +system.cpu.iq.rate 0.486545 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1130694 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019652 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228371695 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67806986 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55854530 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 714587 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336328 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329574 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58275622 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 383662 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 641458 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1339690 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4038 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 554552 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1338736 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3932 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20392 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 579549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18285 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 544771 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18260 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537508 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 584207 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44318330 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 613096 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64473181 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145267 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10424364 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6928356 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890724 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42751 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 366947 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 190952 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410451 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 601403 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57018878 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10377294 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 584463 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 585466 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44292826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 620223 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64391845 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145304 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10423192 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6953251 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1888969 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42563 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 374293 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20392 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 192990 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410068 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 603058 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56949005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10367007 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586870 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3704161 # number of nop insts executed -system.cpu.iew.exec_refs 17048455 # number of memory reference insts executed -system.cpu.iew.exec_branches 8982580 # Number of branches executed -system.cpu.iew.exec_stores 6671161 # Number of stores executed -system.cpu.iew.exec_rate 0.481994 # Inst execution rate -system.cpu.iew.wb_sent 56384919 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56250151 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28947314 # num instructions producing a value -system.cpu.iew.wb_consumers 40326252 # num instructions consuming a value +system.cpu.iew.exec_nop 3696550 # number of nop insts executed +system.cpu.iew.exec_refs 17039818 # number of memory reference insts executed +system.cpu.iew.exec_branches 8972525 # Number of branches executed +system.cpu.iew.exec_stores 6672811 # Number of stores executed +system.cpu.iew.exec_rate 0.481583 # Inst execution rate +system.cpu.iew.wb_sent 56323297 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56184104 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28889312 # num instructions producing a value +system.cpu.iew.wb_consumers 40263081 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475495 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717828 # average fanout of values written-back +system.cpu.iew.wb_rate 0.475114 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717514 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8239076 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661191 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 548552 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111427799 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503633 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.455266 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8158001 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661179 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 549251 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111396128 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.503767 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.456242 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91796177 82.38% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7808087 7.01% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4129534 3.71% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2155296 1.93% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1855711 1.67% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615462 0.55% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 470761 0.42% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 513166 0.46% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2083605 1.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91779533 82.39% 82.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7802293 7.00% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4122327 3.70% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2151634 1.93% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1854051 1.66% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 612708 0.55% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 470628 0.42% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 511278 0.46% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2091676 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111427799 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56118765 # Number of instructions committed -system.cpu.commit.committedOps 56118765 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111396128 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56117715 # Number of instructions committed +system.cpu.commit.committedOps 56117715 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15458478 # Number of memory references committed -system.cpu.commit.loads 9084674 # Number of loads committed -system.cpu.commit.membars 226351 # Number of memory barriers committed -system.cpu.commit.branches 8434924 # Number of branches committed -system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51970227 # Number of committed integer instructions. -system.cpu.commit.function_calls 739937 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3196003 5.70% 5.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36180557 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60666 0.11% 70.27% # Class of committed instruction +system.cpu.commit.refs 15458158 # Number of memory references committed +system.cpu.commit.loads 9084456 # Number of loads committed +system.cpu.commit.membars 226347 # Number of memory barriers committed +system.cpu.commit.branches 8434758 # Number of branches committed +system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.int_insts 51969244 # Number of committed integer instructions. +system.cpu.commit.function_calls 739915 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3195962 5.70% 5.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36179881 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60661 0.11% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction @@ -618,192 +622,192 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9311025 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6379757 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949032 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9310803 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6379655 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949030 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56118765 # Class of committed instruction -system.cpu.commit.bw_lim_events 2083605 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56117715 # Class of committed instruction +system.cpu.commit.bw_lim_events 2091676 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173452486 # The number of ROB reads -system.cpu.rob.rob_writes 130147702 # The number of ROB writes -system.cpu.timesIdled 575947 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5434424 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599800282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52930035 # Number of Instructions Simulated -system.cpu.committedOps 52930035 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.234988 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.234988 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447430 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447430 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74659793 # number of integer regfile reads -system.cpu.int_regfile_writes 40587610 # number of integer regfile writes -system.cpu.fp_regfile_reads 166949 # number of floating regfile reads -system.cpu.fp_regfile_writes 167607 # number of floating regfile writes -system.cpu.misc_regfile_reads 2029497 # number of misc regfile reads -system.cpu.misc_regfile_writes 939434 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1404580 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994645 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11874772 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1405092 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.451242 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 173330307 # The number of ROB reads +system.cpu.rob.rob_writes 129976168 # The number of ROB writes +system.cpu.timesIdled 574999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5429242 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599836925 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52929026 # Number of Instructions Simulated +system.cpu.committedOps 52929026 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.234197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.234197 # CPI: Total CPI of All Threads +system.cpu.ipc 0.447588 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.447588 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74582639 # number of integer regfile reads +system.cpu.int_regfile_writes 40531859 # number of integer regfile writes +system.cpu.fp_regfile_reads 167323 # number of floating regfile reads +system.cpu.fp_regfile_writes 167888 # number of floating regfile writes +system.cpu.misc_regfile_reads 2030592 # number of misc regfile reads +system.cpu.misc_regfile_writes 939419 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1404198 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994647 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11876238 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404710 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.454584 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994645 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994647 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63937777 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63937777 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7284414 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7284414 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4188003 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4188003 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186359 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186359 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215726 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215726 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11472417 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11472417 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11472417 # number of overall hits -system.cpu.dcache.overall_hits::total 11472417 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1780024 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1780024 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1955346 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1955346 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23271 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23271 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 63918355 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63918355 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7286393 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7286393 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4187319 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4187319 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186500 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186500 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215720 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215720 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11473712 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11473712 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11473712 # number of overall hits +system.cpu.dcache.overall_hits::total 11473712 # number of overall hits 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-system.cpu.dcache.ReadReq_miss_latency::cpu.data 39520730746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39520730746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 78084026192 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 78084026192 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364876749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 364876749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 441006 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 441006 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117604756938 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117604756938 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117604756938 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117604756938 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9064438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9064438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6143349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6143349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209630 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209630 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15207787 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15207787 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15207787 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15207787 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196374 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.196374 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111010 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3729145 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3729145 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3729145 # number of overall misses +system.cpu.dcache.overall_misses::total 3729145 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39410540501 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39410540501 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77932908678 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77932908678 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 363692999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 363692999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 466008 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 466008 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117343449179 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117343449179 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117343449179 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117343449179 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9059604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9059604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6143253 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6143253 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209806 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209806 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215748 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215748 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15202857 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15202857 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15202857 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15202857 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195727 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.195727 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318387 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318387 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111084 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111084 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245622 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245622 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245622 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245622 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22202.358365 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22202.358365 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39933.610825 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39933.610825 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15679.461519 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15679.461519 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15750.214286 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15750.214286 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31484.098480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31484.098480 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3992388 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1705 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 180260 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.147942 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.041667 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.245292 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245292 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245292 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245292 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31466.582602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31466.582602 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3975824 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1887 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 179816 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.110513 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82.043478 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842675 # number of writebacks -system.cpu.dcache.writebacks::total 842675 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683874 # 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-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291118 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291118 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17995 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17995 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 842396 # number of writebacks +system.cpu.dcache.writebacks::total 842396 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 677447 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 677447 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664842 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664842 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5278 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5278 # 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number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1387268 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1387268 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1387268 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1387268 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27519652282 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27519652282 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11779193020 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11779193020 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204738251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204738251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 384994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 384994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39298845302 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39298845302 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39298845302 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39298845302 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423580000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423580000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999637498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999637498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423217498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423217498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085842 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085842 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27504145773 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27504145773 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11747551273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11747551273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205106501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205106501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 409992 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 409992 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39251697046 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39251697046 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39251697046 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39251697046 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423712500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423712500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999632498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999632498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423344998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423344998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047384 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047384 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085927 # mshr miss rate for LoadLockedReq accesses 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40461.919290 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.507697 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.507697 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13749.785714 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13749.785714 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091223 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091223 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25100.428352 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25100.428352 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40356.833142 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40356.833142 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.107888 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.107888 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14642.571429 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14642.571429 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -811,213 +815,213 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1035530 # number of replacements -system.cpu.icache.tags.tagsinuse 509.402349 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7932375 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1036038 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.656452 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup 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9019797 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13915.467449 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13915.467449 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13915.467449 # average overall miss latency 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mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53221.601180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53773.718554 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 12641.298246 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 12641.298246 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71707.813759 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71707.813759 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71432.829575 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71432.829575 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1107,43 +1111,43 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2146647 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2146537 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2145159 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2145056 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 842675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 842396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 88 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 93 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2072410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686471 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5758881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66311616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143911276 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210222892 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42053 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3325984 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111300 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 86 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2070119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3685432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5755551 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66237760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143868972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210106732 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42071 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3324189 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012552 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111331 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3284259 98.75% 98.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3282463 98.74% 98.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 1.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3325984 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2497867498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3324189 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2496690997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1558461609 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1556745400 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189866891 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2189304171 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1216,23 +1220,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406221775 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406216778 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010536 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42011283 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260575 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.260535 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709355371000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260575 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078786 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078786 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1709356303000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260535 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078783 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078783 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1248,8 +1252,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13648838856 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13648838856 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13645647112 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13645647112 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles @@ -1272,17 +1276,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328476.098768 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328476.098768 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206574 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206436 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23538 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23523 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.776192 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.775921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1298,8 +1302,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11488062928 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11488062928 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11484876678 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11484876678 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles @@ -1314,60 +1318,60 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276474.367732 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276474.367732 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296033 # Transaction distribution -system.membus.trans_dist::ReadResp 295940 # Transaction distribution +system.membus.trans_dist::ReadReq 296054 # Transaction distribution +system.membus.trans_dist::ReadResp 295968 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117441 # Transaction distribution +system.membus.trans_dist::Writeback 117450 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 186 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 192 # Transaction distribution -system.membus.trans_dist::ReadExReq 115233 # Transaction distribution -system.membus.trans_dist::ReadExResp 115233 # Transaction distribution -system.membus.trans_dist::BadAddressError 93 # Transaction distribution +system.membus.trans_dist::UpgradeReq 203 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.membus.trans_dist::UpgradeResp 211 # Transaction distribution +system.membus.trans_dist::ReadExReq 115230 # Transaction distribution +system.membus.trans_dist::ReadExResp 115230 # Transaction distribution +system.membus.trans_dist::BadAddressError 86 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 186 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917499 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042303 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30748716 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36063596 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36065772 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 563522 # Request fanout histogram +system.membus.snoop_fanout::samples 563568 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 563522 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 563568 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 563522 # Request fanout histogram -system.membus.reqLayer0.occupancy 31470000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 563568 # Request fanout histogram +system.membus.reqLayer0.occupancy 31570500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1857946999 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1858044250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 115000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 107000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3754266813 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3754720043 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43145464 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43142717 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1401,28 +1405,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211002 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105561 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105562 57.93% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817339213500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61863500 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 521835500 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41125418500 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859048331000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817332157500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 61952500 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 528077500 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41122369500 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859044557000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694338 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815440 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815429 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1458,10 +1462,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175118 91.22% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175118 91.23% 93.44% # number of callpals executed system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1470,20 +1474,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191963 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.callpal::total 191962 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::user 1743 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1743 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326499 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326953 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394468 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29096339500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2660038000 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827291945500 98.29% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394840 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29081819500 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2655993500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827306736000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 3aeb0bbf5..b0cdac391 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.842592 # Number of seconds simulated -sim_ticks 1842592129000 # Number of ticks simulated -final_tick 1842592129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1842591955000 # Number of ticks simulated +final_tick 1842591955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226605 # Simulator instruction rate (inst/s) -host_op_rate 226605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6393875150 # Simulator tick rate (ticks/s) -host_mem_usage 320256 # Number of bytes of host memory used -host_seconds 288.18 # Real time elapsed on the host -sim_insts 65303087 # Number of instructions simulated -sim_ops 65303087 # Number of ops (including micro ops) simulated +host_inst_rate 212167 # Simulator instruction rate (inst/s) +host_op_rate 212167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5858461865 # Simulator tick rate (ticks/s) +host_mem_usage 373744 # Number of bytes of host memory used +host_seconds 314.52 # Real time elapsed on the host +sim_insts 66730424 # Number of instructions simulated +sim_ops 66730424 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20073664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2246336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 292800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2554880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 480192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20072256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 146880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2246976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2555648 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25796096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 292800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 920256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481536 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481536 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2294 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35099 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4575 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39920 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25796928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 480192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 146880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 921088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7481920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7481920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313629 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39932 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116899 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116899 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10894253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1219117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 158907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1386568 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403077 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116905 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116905 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 260607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10893489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1219465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1386985 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13999895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 158907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4060332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4060332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4060332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10894253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1219117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 158907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1386568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14000348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4060541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4060541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4060541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10893489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1219465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1386985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18060227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81903 # Number of read requests accepted -system.physmem.writeReqs 62699 # Number of write requests accepted -system.physmem.readBursts 81903 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 62699 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5240384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue -system.physmem.bytesWritten 3952512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5241792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4012736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 916 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5341 # Per bank write bursts -system.physmem.perBankRdBursts::1 4966 # Per bank write bursts -system.physmem.perBankRdBursts::2 4940 # Per bank write bursts -system.physmem.perBankRdBursts::3 5071 # Per bank write bursts -system.physmem.perBankRdBursts::4 5028 # Per bank write bursts -system.physmem.perBankRdBursts::5 5062 # Per bank write bursts -system.physmem.perBankRdBursts::6 5140 # Per bank write bursts -system.physmem.perBankRdBursts::7 5148 # Per bank write bursts -system.physmem.perBankRdBursts::8 5331 # Per bank write bursts +system.physmem.bw_total::total 18060889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81945 # Number of read requests accepted +system.physmem.writeReqs 62218 # Number of write requests accepted +system.physmem.readBursts 81945 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 62218 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5243136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue +system.physmem.bytesWritten 3931008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5244480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3981952 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 773 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 65 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5216 # Per bank write bursts +system.physmem.perBankRdBursts::1 4952 # Per bank write bursts +system.physmem.perBankRdBursts::2 4966 # Per bank write bursts +system.physmem.perBankRdBursts::3 5032 # Per bank write bursts +system.physmem.perBankRdBursts::4 5011 # Per bank write bursts +system.physmem.perBankRdBursts::5 5077 # Per bank write bursts +system.physmem.perBankRdBursts::6 5139 # Per bank write bursts +system.physmem.perBankRdBursts::7 5153 # Per bank write bursts +system.physmem.perBankRdBursts::8 5336 # Per bank write bursts system.physmem.perBankRdBursts::9 5012 # Per bank write bursts -system.physmem.perBankRdBursts::10 5278 # Per bank write bursts -system.physmem.perBankRdBursts::11 5132 # Per bank write bursts -system.physmem.perBankRdBursts::12 4684 # Per bank write bursts -system.physmem.perBankRdBursts::13 5065 # Per bank write bursts -system.physmem.perBankRdBursts::14 5602 # Per bank write bursts -system.physmem.perBankRdBursts::15 5081 # Per bank write bursts -system.physmem.perBankWrBursts::0 3943 # Per bank write bursts -system.physmem.perBankWrBursts::1 3578 # Per bank write bursts -system.physmem.perBankWrBursts::2 3780 # Per bank write bursts -system.physmem.perBankWrBursts::3 4114 # Per bank write bursts -system.physmem.perBankWrBursts::4 3703 # Per bank write bursts -system.physmem.perBankWrBursts::5 3530 # Per bank write bursts -system.physmem.perBankWrBursts::6 4127 # Per bank write bursts -system.physmem.perBankWrBursts::7 3704 # Per bank write bursts -system.physmem.perBankWrBursts::8 4410 # Per bank write bursts -system.physmem.perBankWrBursts::9 3736 # Per bank write bursts -system.physmem.perBankWrBursts::10 4083 # Per bank write bursts -system.physmem.perBankWrBursts::11 3942 # Per bank write bursts -system.physmem.perBankWrBursts::12 3446 # Per bank write bursts -system.physmem.perBankWrBursts::13 3846 # Per bank write bursts -system.physmem.perBankWrBursts::14 4153 # Per bank write bursts -system.physmem.perBankWrBursts::15 3663 # Per bank write bursts +system.physmem.perBankRdBursts::10 5284 # Per bank write bursts +system.physmem.perBankRdBursts::11 5137 # Per bank write bursts +system.physmem.perBankRdBursts::12 4814 # Per bank write bursts +system.physmem.perBankRdBursts::13 5083 # Per bank write bursts +system.physmem.perBankRdBursts::14 5582 # Per bank write bursts +system.physmem.perBankRdBursts::15 5130 # Per bank write bursts +system.physmem.perBankWrBursts::0 3820 # Per bank write bursts +system.physmem.perBankWrBursts::1 3672 # Per bank write bursts +system.physmem.perBankWrBursts::2 3762 # Per bank write bursts +system.physmem.perBankWrBursts::3 4075 # Per bank write bursts +system.physmem.perBankWrBursts::4 3759 # Per bank write bursts +system.physmem.perBankWrBursts::5 3520 # Per bank write bursts +system.physmem.perBankWrBursts::6 4123 # Per bank write bursts +system.physmem.perBankWrBursts::7 3706 # Per bank write bursts +system.physmem.perBankWrBursts::8 4379 # Per bank write bursts +system.physmem.perBankWrBursts::9 3471 # Per bank write bursts +system.physmem.perBankWrBursts::10 3889 # Per bank write bursts +system.physmem.perBankWrBursts::11 3981 # Per bank write bursts +system.physmem.perBankWrBursts::12 3541 # Per bank write bursts +system.physmem.perBankWrBursts::13 3879 # Per bank write bursts +system.physmem.perBankWrBursts::14 4169 # Per bank write bursts +system.physmem.perBankWrBursts::15 3676 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1841579852500 # Total gap between requests +system.physmem.totGap 1841579678500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81903 # Read request sizes (log2) +system.physmem.readPktSize::6 81945 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 62699 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 62218 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,193 +153,216 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see 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see -system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4782 # What write queue length does an incoming req see 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length does an incoming req see -system.physmem.wrQLenPdf::35 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 414.094414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 234.871610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 395.166984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6979 31.44% 31.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4758 21.43% 52.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1802 8.12% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1018 4.59% 65.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 909 4.09% 69.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 488 2.20% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 377 1.70% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 379 1.71% 75.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5490 24.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22200 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.346604 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1004.576162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2133 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 22279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 411.784371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 233.119875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 394.569349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7102 31.88% 31.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4721 21.19% 53.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1798 8.07% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1010 4.53% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 955 4.29% 69.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 478 2.15% 72.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 370 1.66% 73.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 364 1.63% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5481 24.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22279 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2129 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 38.475810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1006.180082 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2127 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.926464 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.717874 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 36.556650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 42 1.97% 1.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 3 0.14% 2.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 1647 77.14% 79.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 96 4.50% 83.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 109 5.11% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 21 0.98% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 47 2.20% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.66% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 5 0.23% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.19% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 8 0.37% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 8 0.37% 93.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 2 0.09% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.09% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.05% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 13 0.61% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.70% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 12 0.56% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 7 0.33% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 36 1.69% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 13 0.61% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.33% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 7 0.33% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 5 0.23% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.14% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.14% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::296-303 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2135 # Writes before turning the bus around for reads -system.physmem.totQLat 816878250 # Total ticks spent queuing -system.physmem.totMemAccLat 2352147000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9976.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2129 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2129 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 28.850164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.675931 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 36.499081 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.60% 1.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.33% 1.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 1.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 1 0.05% 2.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1615 75.86% 77.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 35 1.64% 79.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10 0.47% 79.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 84 3.95% 83.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 64 3.01% 86.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 45 2.11% 89.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.42% 89.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.52% 90.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 35 1.64% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.23% 91.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 21 0.99% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.09% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.14% 93.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.09% 93.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.23% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.05% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.19% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.05% 93.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.14% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.19% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.05% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.05% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.28% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.09% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.05% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 15 0.70% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.14% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.09% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.05% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.19% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 43 2.02% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.05% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 11 0.52% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.14% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.14% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.09% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 6 0.28% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.19% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.23% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 3 0.14% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.14% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.14% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2129 # Writes before turning the bus around for reads +system.physmem.totQLat 814366500 # Total ticks spent queuing +system.physmem.totMemAccLat 2350441500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 409620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9940.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28726.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28690.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 70255 # Number of row buffer hits during reads -system.physmem.writeRowHits 51184 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.84 # Row buffer hit rate for writes -system.physmem.avgGap 12735507.48 # Average gap between requests -system.physmem.pageHitRate 84.53 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1767479155500 # Time in different power states -system.physmem.memoryStateTime::REF 61527960000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13578075750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 83696760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 84135240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 45667875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 45907125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 317428800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 321243000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 197503920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 202687920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 120348689760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 120348689760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 46124478945 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 45810126225 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1065091037250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1065366785250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1232208503310 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1232179574520 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.738964 # Core power per rank (mW) -system.physmem.averagePower::1 668.723264 # Core power per rank (mW) +system.physmem.readRowHits 70260 # Number of row buffer hits during reads +system.physmem.writeRowHits 50807 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.69 # Row buffer hit rate for writes +system.physmem.avgGap 12774287.98 # Average gap between requests +system.physmem.pageHitRate 84.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 83779920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45618375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 316258800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 197231760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35724246975 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 802806617250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 928299910200 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.726630 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309959191250 # Time in different power states +system.physmem_0.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9222216250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 84649320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 46030875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 322748400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 200782800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35431940430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799831550250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 925043859195 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.972279 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1310405285500 # Time in different power states +system.physmem_1.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8771812500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4840766 # DTB read hits +system.cpu0.dtb.read_hits 4841130 # DTB read hits system.cpu0.dtb.read_misses 6162 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 429577 # DTB read accesses -system.cpu0.dtb.write_hits 3449248 # DTB write hits +system.cpu0.dtb.write_hits 3448228 # DTB write hits system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 85 # DTB write access violations system.cpu0.dtb.write_accesses 165228 # DTB write accesses -system.cpu0.dtb.data_hits 8290014 # DTB hits +system.cpu0.dtb.data_hits 8289358 # DTB hits system.cpu0.dtb.data_misses 6850 # DTB misses system.cpu0.dtb.data_acv 211 # DTB access violations system.cpu0.dtb.data_accesses 594805 # DTB accesses -system.cpu0.itb.fetch_hits 2745005 # ITB hits +system.cpu0.itb.fetch_hits 2744473 # ITB hits system.cpu0.itb.fetch_misses 3071 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2748076 # ITB accesses +system.cpu0.itb.fetch_accesses 2747544 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -352,87 +375,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 930170502 # number of cpu cycles simulated +system.cpu0.numCycles 929111283 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31084978 # Number of instructions committed -system.cpu0.committedOps 31084978 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28990115 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165280 # Number of float alu accesses -system.cpu0.num_func_calls 801354 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3884267 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28990115 # number of integer instructions -system.cpu0.num_fp_insts 165280 # number of float instructions -system.cpu0.num_int_register_reads 40144651 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21293303 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85481 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86924 # number of times the floating registers were written -system.cpu0.num_mem_refs 8319976 # number of memory refs -system.cpu0.num_load_insts 4862063 # Number of load instructions -system.cpu0.num_store_insts 3457913 # Number of store instructions -system.cpu0.num_idle_cycles 907838728.357051 # Number of idle cycles -system.cpu0.num_busy_cycles 22331773.642949 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024008 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975992 # Percentage of idle cycles -system.cpu0.Branches 4943919 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1583961 5.09% 5.09% # Class of executed instruction -system.cpu0.op_class::IntAlu 20486094 65.89% 70.98% # Class of executed instruction -system.cpu0.op_class::IntMult 31888 0.10% 71.09% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.09% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12950 0.04% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.01% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::MemRead 4993462 16.06% 87.19% # Class of executed instruction -system.cpu0.op_class::MemWrite 3461022 11.13% 98.32% # Class of executed instruction -system.cpu0.op_class::IprAccess 521056 1.68% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30392058 # Number of instructions committed +system.cpu0.committedOps 30392058 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28296981 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 165313 # Number of float alu accesses +system.cpu0.num_func_calls 800920 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3653475 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28296981 # number of integer instructions +system.cpu0.num_fp_insts 165313 # number of float instructions +system.cpu0.num_int_register_reads 38988704 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20831324 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85482 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86956 # number of times the floating registers were written +system.cpu0.num_mem_refs 8319320 # number of memory refs +system.cpu0.num_load_insts 4862427 # Number of load instructions +system.cpu0.num_store_insts 3456893 # Number of store instructions +system.cpu0.num_idle_cycles 905971177.002448 # Number of idle cycles +system.cpu0.num_busy_cycles 23140105.997552 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024906 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975094 # Percentage of idle cycles +system.cpu0.Branches 4712544 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1584509 5.21% 5.21% # Class of executed instruction +system.cpu0.op_class::IntAlu 19793641 65.11% 70.32% # Class of executed instruction +system.cpu0.op_class::IntMult 31883 0.10% 70.43% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.43% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12951 0.04% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1606 0.01% 70.48% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::MemRead 4993701 16.43% 86.90% # Class of executed instruction +system.cpu0.op_class::MemWrite 3459999 11.38% 98.29% # Class of executed instruction +system.cpu0.op_class::IprAccess 520829 1.71% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31092039 # Class of executed instruction +system.cpu0.op_class::total 30399119 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211371 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6424 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211373 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182570 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105693 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819773509500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38545500 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357643000 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22421661500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842591359500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1819763275500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38885000 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357575500 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22431449500 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842591185500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694761 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815808 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815799 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -471,7 +494,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175311 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -480,266 +503,266 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192226 # number of callpals executed +system.cpu0.kern.callpal::total 192228 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1740 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::kernel 1910 +system.cpu0.kern.mode_good::user 1740 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322526 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29639680500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2561811500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810389863000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.391474 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29641344500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2562591500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810387245000 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4177 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393201 # number of replacements +system.cpu0.dcache.tags.replacements 1393017 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13277254 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393713 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.526534 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13281490 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393529 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.530831 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 261.608452 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.750107 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 175.639259 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.510954 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.145996 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.343045 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.752731 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 75.043138 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.201949 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509283 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146569 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.344144 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63354718 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63354718 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4014926 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1052133 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2504051 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7571110 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157714 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 807247 # number of WriteReq hits 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(read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3861372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12893392 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7172640 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1859380 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3861372 # number of overall hits -system.cpu0.dcache.overall_hits::total 12893392 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 712217 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 95395 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 559235 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1366847 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 166399 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43585 # number of WriteReq misses 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(read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3853314760 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 29104949733 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32958264493 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4727143 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1147528 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3063286 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8937957 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3324113 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 850832 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1974450 # number of WriteReq accesses(hits+misses) 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# number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8050821 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 1999779 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5039743 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15090343 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8050821 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 1999779 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5039743 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15090343 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150839 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082364 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182112 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152767 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050059 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051180 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.312423 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.134469 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075725 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100694 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.129452 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093694 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000016 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000146 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109128 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069547 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233510 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.145417 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109128 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069547 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233510 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.145417 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23097.526076 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17314.698767 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8696.199403 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37855.369049 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31471.481924 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25476.434814 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13187.052933 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16697.452751 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8083.729846 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000128 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109239 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069081 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233179 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.145310 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109239 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069081 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233179 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.145310 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23197.259180 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17316.005182 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8682.077472 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37914.772566 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31426.740507 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25446.962075 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.420152 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16607.100185 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8033.386588 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10400 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27725.678227 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24741.448848 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15022.272281 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27725.678227 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24741.448848 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15022.272281 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 825872 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 866 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 61038 # number of cycles access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10111.111111 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15004.795330 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15004.795330 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 825255 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1343 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 61465 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.530456 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 96.222222 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.426422 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 149.222222 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835902 # number of writebacks -system.cpu0.dcache.writebacks::total 835902 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 293112 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 293112 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 524642 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 524642 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1568 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1568 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 817754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 817754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 817754 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 817754 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 95395 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 266123 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 361518 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43585 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92487 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 136072 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2097 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6030 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8127 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 138980 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 358610 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 497590 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 138980 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 358610 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 497590 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2005063500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4453995148 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6459058648 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1554433740 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2785719201 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4340152941 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23457750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72881252 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96339002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3559497240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7239714349 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10799211589 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3559497240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7239714349 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10799211589 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248461000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342715000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591176000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 319650500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 420043000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 739693500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 568111500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762758000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1330869500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083131 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086875 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040447 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051226 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046842 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022128 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100929 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103287 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.039924 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000146 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069547 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071185 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032981 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069547 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071185 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032981 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21018.538707 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.603555 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17866.492534 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35664.419869 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30120.116351 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31896.003153 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11186.337625 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12086.443118 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.189984 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835667 # number of writebacks +system.cpu0.dcache.writebacks::total 835667 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292188 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 292188 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 524505 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 524505 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 816693 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 816693 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 816693 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 816693 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 94552 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 265940 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 360492 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43595 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92528 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 136123 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2104 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5986 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8090 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 138147 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 358468 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 496615 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 138147 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 358468 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 496615 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1996702750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4449426882 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6446129632 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1557368490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2781486410 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4338854900 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23520500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72740751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96261251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3554071240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7230913292 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10784984532 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3554071240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7230913292 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10784984532 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249355000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342279000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591634000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320316500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419818000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740134500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569671500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762097000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1331768500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082364 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086774 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040322 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051180 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046850 # mshr miss rate for WriteReq accesses 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0.069081 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032909 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21117.509413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16730.942626 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17881.477625 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35723.557518 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30061.023798 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31874.517165 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.944867 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12151.812730 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.794932 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25611.578932 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20188.266777 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21703.031791 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25611.578932 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20188.266777 # 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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.892216 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.705882 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16187 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16187 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16187 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16187 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16187 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16187 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 123865 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326745 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 450610 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 123865 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 326745 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 450610 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 123865 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 326745 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 450610 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1517675250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982959026 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5500634276 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1517675250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982959026 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5500634276 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1517675250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982959026 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5500634276 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010898 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010898 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010898 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12207.084343 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12207.084343 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12207.084343 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16232 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16232 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16232 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16232 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16232 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16232 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124188 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326610 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 450798 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 124188 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 326610 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 450798 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 124188 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 326610 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 450798 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1522394000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982795175 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5505189175 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1522394000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982795175 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5505189175 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1522394000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982795175 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5505189175 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011087 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011087 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011087 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1166206 # DTB read hits +system.cpu1.dtb.read_hits 1166781 # DTB read hits system.cpu1.dtb.read_misses 1314 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations system.cpu1.dtb.read_accesses 141633 # DTB read accesses -system.cpu1.dtb.write_hits 871808 # DTB write hits +system.cpu1.dtb.write_hits 872888 # DTB write hits system.cpu1.dtb.write_misses 168 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations system.cpu1.dtb.write_accesses 57088 # DTB write accesses -system.cpu1.dtb.data_hits 2038014 # DTB hits +system.cpu1.dtb.data_hits 2039669 # DTB hits system.cpu1.dtb.data_misses 1482 # DTB misses system.cpu1.dtb.data_acv 56 # DTB access violations system.cpu1.dtb.data_accesses 198721 # DTB accesses -system.cpu1.itb.fetch_hits 847614 # ITB hits +system.cpu1.itb.fetch_hits 848090 # ITB hits system.cpu1.itb.fetch_misses 662 # ITB misses system.cpu1.itb.fetch_acv 32 # ITB acv -system.cpu1.itb.fetch_accesses 848276 # ITB accesses +system.cpu1.itb.fetch_accesses 848752 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -919,64 +942,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953409628 # number of cpu cycles simulated +system.cpu1.numCycles 953408444 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7451589 # Number of instructions committed -system.cpu1.committedOps 7451589 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6926409 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43920 # Number of float alu accesses -system.cpu1.num_func_calls 202937 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 904115 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6926409 # number of integer instructions -system.cpu1.num_fp_insts 43920 # number of float instructions -system.cpu1.num_int_register_reads 9636713 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5051586 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23745 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24097 # number of times the floating registers were written -system.cpu1.num_mem_refs 2044932 # number of memory refs -system.cpu1.num_load_insts 1170872 # Number of load instructions -system.cpu1.num_store_insts 874060 # Number of store instructions -system.cpu1.num_idle_cycles 925046236.205368 # Number of idle cycles -system.cpu1.num_busy_cycles 28363391.794632 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029749 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970251 # Percentage of idle cycles -system.cpu1.Branches 1171500 # Number of branches fetched -system.cpu1.op_class::No_OpClass 399169 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 4836084 64.89% 70.24% # Class of executed instruction -system.cpu1.op_class::IntMult 8208 0.11% 70.35% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5096 0.07% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::MemRead 1198833 16.08% 86.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 875271 11.74% 98.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 129656 1.74% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7454598 # Number of instructions committed +system.cpu1.committedOps 7454598 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6929268 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 43953 # Number of float alu accesses +system.cpu1.num_func_calls 203515 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 903765 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6929268 # number of integer instructions +system.cpu1.num_fp_insts 43953 # number of float instructions +system.cpu1.num_int_register_reads 9641119 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5054145 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 23746 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written +system.cpu1.num_mem_refs 2046592 # number of memory refs +system.cpu1.num_load_insts 1171450 # Number of load instructions +system.cpu1.num_store_insts 875142 # Number of store instructions +system.cpu1.num_idle_cycles 924951081.946169 # Number of idle cycles +system.cpu1.num_busy_cycles 28457362.053831 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029848 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970152 # Percentage of idle cycles +system.cpu1.Branches 1171881 # Number of branches fetched +system.cpu1.op_class::No_OpClass 398972 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 4837309 64.88% 70.23% # Class of executed instruction +system.cpu1.op_class::IntMult 8193 0.11% 70.34% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5097 0.07% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::MemRead 1199545 16.09% 86.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 876356 11.75% 98.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 129854 1.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7453127 # Class of executed instruction +system.cpu1.op_class::total 7456136 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -994,35 +1017,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8975833 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8240091 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125146 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6986744 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 4884457 # Number of BTB hits +system.cpu2.branchPred.lookups 9673449 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8936896 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 125098 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7569787 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5584968 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 69.910347 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 298693 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7800 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 73.779725 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 299823 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7809 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3460113 # DTB read hits -system.cpu2.dtb.read_misses 12059 # DTB read misses -system.cpu2.dtb.read_acv 120 # DTB read access violations -system.cpu2.dtb.read_accesses 225843 # DTB read accesses -system.cpu2.dtb.write_hits 2120785 # DTB write hits -system.cpu2.dtb.write_misses 2578 # DTB write misses -system.cpu2.dtb.write_acv 111 # DTB write access violations -system.cpu2.dtb.write_accesses 84303 # DTB write accesses -system.cpu2.dtb.data_hits 5580898 # DTB hits -system.cpu2.dtb.data_misses 14637 # DTB misses -system.cpu2.dtb.data_acv 231 # DTB access violations -system.cpu2.dtb.data_accesses 310146 # DTB accesses -system.cpu2.itb.fetch_hits 534656 # ITB hits -system.cpu2.itb.fetch_misses 5715 # ITB misses -system.cpu2.itb.fetch_acv 156 # ITB acv -system.cpu2.itb.fetch_accesses 540371 # ITB accesses +system.cpu2.dtb.read_hits 3461968 # DTB read hits +system.cpu2.dtb.read_misses 12174 # DTB read misses +system.cpu2.dtb.read_acv 114 # DTB read access violations +system.cpu2.dtb.read_accesses 224881 # DTB read accesses +system.cpu2.dtb.write_hits 2122047 # DTB write hits +system.cpu2.dtb.write_misses 2563 # DTB write misses +system.cpu2.dtb.write_acv 106 # DTB write access violations +system.cpu2.dtb.write_accesses 83942 # DTB write accesses +system.cpu2.dtb.data_hits 5584015 # DTB hits +system.cpu2.dtb.data_misses 14737 # DTB misses +system.cpu2.dtb.data_acv 220 # DTB access violations +system.cpu2.dtb.data_accesses 308823 # DTB accesses +system.cpu2.itb.fetch_hits 534012 # ITB hits +system.cpu2.itb.fetch_misses 5788 # ITB misses +system.cpu2.itb.fetch_acv 158 # ITB acv +system.cpu2.itb.fetch_accesses 539800 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1035,305 +1058,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 29309170 # number of cpu cycles simulated +system.cpu2.numCycles 30013580 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9355872 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 35312418 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8975833 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5183150 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 17863271 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 408038 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 9363383 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37425902 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9673449 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5884791 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18558568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 408186 # Number of cycles fetch has spent squashing system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1926 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 226509 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 98836 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2801357 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 93254 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27760138 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.272055 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.388957 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.MiscStallCycles 10133 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 231517 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 99918 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 308 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2804138 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 92736 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 28469903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.314578 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.374234 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20067804 72.29% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312324 1.13% 73.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 471431 1.70% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3277065 11.80% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 832356 3.00% 89.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194310 0.70% 90.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 239050 0.86% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 435621 1.57% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1930177 6.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20072313 70.50% 70.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 312422 1.10% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 471724 1.66% 73.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3982470 13.99% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 833365 2.93% 90.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 193345 0.68% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 238464 0.84% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 434747 1.53% 93.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1931053 6.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27760138 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.306247 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.204825 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7663207 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13056286 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6071971 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 531660 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 191161 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 175121 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13218 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 31964587 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42189 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 191161 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7944282 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4747926 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6306317 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6292094 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2032514 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 31148031 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68690 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 405455 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57635 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 961672 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 20857546 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 38489272 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 38429323 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56078 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 18957389 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1900157 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 527032 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63032 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3906781 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3488819 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2211142 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 463556 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329659 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 28630875 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 676639 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 28279580 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16369 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2426454 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1141058 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 483735 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27760138 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.018712 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.595651 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 28469903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.322302 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.246966 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7673000 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13050358 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6778876 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 530616 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 191226 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 175016 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13225 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34075356 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 43360 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 191226 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7953535 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4758129 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6310003 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6998808 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2012380 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33260601 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 68695 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 404029 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57097 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 943831 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 22264761 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41311324 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41251440 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56013 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20369021 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1895740 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 527174 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63098 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3903100 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3489643 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2214871 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 462169 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 329723 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30742037 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 676819 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30393110 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 17376 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2421658 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1144384 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 483915 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 28469903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.067552 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.605150 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17419876 62.75% 62.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2765921 9.96% 72.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1372782 4.95% 77.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4034544 14.53% 92.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1009748 3.64% 95.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 570537 2.06% 97.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 383332 1.38% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154390 0.56% 99.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 49008 0.18% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17422923 61.20% 61.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2767864 9.72% 70.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1373994 4.83% 75.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4735624 16.63% 92.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1013556 3.56% 95.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 570411 2.00% 97.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 382804 1.34% 99.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 154533 0.54% 99.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 48194 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27760138 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 28469903 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 83197 21.73% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 176333 46.06% 67.80% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 123266 32.20% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 82144 21.47% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 176872 46.24% 67.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 123495 32.29% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 22202311 78.51% 78.52% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21087 0.07% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20489 0.07% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3587142 12.68% 91.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2144327 7.58% 98.94% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 300564 1.06% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24311305 79.99% 80.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21079 0.07% 80.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 80.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20485 0.07% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3589842 11.81% 91.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2146129 7.06% 99.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 300610 0.99% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 28279580 # Type of FU issued -system.cpu2.iq.rate 0.964871 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 382796 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013536 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 84465202 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 31620396 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27707676 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 253261 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119445 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 116967 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 28524107 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 135829 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206522 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30393110 # Type of FU issued +system.cpu2.iq.rate 1.012645 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 382511 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.012585 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 89403074 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33727235 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29817840 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 252936 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119279 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 116815 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30637549 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 135632 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205530 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 435956 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1412 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6012 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178431 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 436638 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1484 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6154 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 181627 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5029 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 168380 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4994 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 170094 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 191161 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3997544 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 279888 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 30686163 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51755 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3488819 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2211142 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 602233 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15645 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 216255 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6012 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63410 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 133827 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197237 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 28083451 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3480678 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 196129 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 191226 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3996466 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 295299 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32798710 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 54858 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3489643 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2214871 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 602209 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15595 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 231865 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6154 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 62873 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134195 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197068 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30195469 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3482644 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 197641 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1378649 # number of nop insts executed -system.cpu2.iew.exec_refs 5608668 # number of memory reference insts executed -system.cpu2.iew.exec_branches 5940571 # Number of branches executed -system.cpu2.iew.exec_stores 2127990 # Number of stores executed -system.cpu2.iew.exec_rate 0.958180 # Inst execution rate -system.cpu2.iew.wb_sent 27865492 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27824643 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15848860 # num instructions producing a value -system.cpu2.iew.wb_consumers 19489990 # num instructions consuming a value +system.cpu2.iew.exec_nop 1379854 # number of nop insts executed +system.cpu2.iew.exec_refs 5611883 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6643679 # Number of branches executed +system.cpu2.iew.exec_stores 2129239 # Number of stores executed +system.cpu2.iew.exec_rate 1.006060 # Inst execution rate +system.cpu2.iew.wb_sent 29976342 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29934655 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17254819 # num instructions producing a value +system.cpu2.iew.wb_consumers 20895222 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.949349 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.813179 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.997370 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.825778 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2662629 # The number of squashed insts skipped by commit +system.cpu2.commit.commitSquashedInsts 2658447 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180156 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27293607 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.025131 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.859726 # Number of insts commited each cycle +system.cpu2.commit.branchMispredicts 180111 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28004103 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.074728 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.862098 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18211809 66.73% 66.73% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2232896 8.18% 74.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1177901 4.32% 79.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 3741262 13.71% 92.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 541174 1.98% 94.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200137 0.73% 95.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164418 0.60% 96.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 176928 0.65% 96.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 847082 3.10% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18216020 65.05% 65.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2235913 7.98% 73.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1176646 4.20% 77.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4445185 15.87% 93.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 540129 1.93% 95.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 200547 0.72% 95.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 166033 0.59% 96.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 176455 0.63% 96.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 847175 3.03% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27293607 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 27979525 # Number of instructions committed -system.cpu2.commit.committedOps 27979525 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28004103 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30096794 # Number of instructions committed +system.cpu2.commit.committedOps 30096794 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5085574 # Number of memory references committed -system.cpu2.commit.loads 3052863 # Number of loads committed -system.cpu2.commit.membars 67982 # Number of memory barriers committed -system.cpu2.commit.branches 5768887 # Number of branches committed -system.cpu2.commit.fp_insts 115191 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 26471742 # Number of committed integer instructions. -system.cpu2.commit.function_calls 239400 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1215445 4.34% 4.34% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 21266434 76.01% 80.35% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20635 0.07% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20039 0.07% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3120845 11.15% 91.65% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2034343 7.27% 98.93% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 300564 1.07% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5086249 # Number of memory references committed +system.cpu2.commit.loads 3053005 # Number of loads committed +system.cpu2.commit.membars 67981 # Number of memory barriers committed +system.cpu2.commit.branches 6474041 # Number of branches committed +system.cpu2.commit.fp_insts 115125 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28589001 # Number of committed integer instructions. +system.cpu2.commit.function_calls 239427 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1215466 4.04% 4.04% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 23382957 77.69% 81.73% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20643 0.07% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20037 0.07% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3120986 10.37% 92.24% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2034876 6.76% 99.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 300609 1.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 27979525 # Class of committed instruction -system.cpu2.commit.bw_lim_events 847082 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 30096794 # Class of committed instruction +system.cpu2.commit.bw_lim_events 847175 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 57015033 # The number of ROB reads -system.cpu2.rob.rob_writes 61749251 # The number of ROB writes -system.cpu2.timesIdled 174924 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1549032 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1748451761 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 26766520 # Number of Instructions Simulated -system.cpu2.committedOps 26766520 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.094994 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.094994 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.913247 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.913247 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 36812900 # number of integer regfile reads -system.cpu2.int_regfile_writes 19756149 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70792 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70904 # number of floating regfile writes -system.cpu2.misc_regfile_reads 3635366 # number of misc regfile reads -system.cpu2.misc_regfile_writes 270473 # number of misc regfile writes +system.cpu2.rob.rob_reads 59838509 # The number of ROB reads +system.cpu2.rob.rob_writes 65974697 # The number of ROB writes +system.cpu2.timesIdled 175016 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1543677 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747747743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 28883768 # Number of Instructions Simulated +system.cpu2.committedOps 28883768 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.039116 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.039116 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.962357 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.962357 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39632695 # number of integer regfile reads +system.cpu2.int_regfile_writes 21162382 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70702 # number of floating regfile reads +system.cpu2.fp_regfile_writes 70843 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4340126 # number of misc regfile reads +system.cpu2.misc_regfile_writes 270474 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1389,25 +1412,25 @@ system.iobus.reqLayer1.occupancy 102000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5523000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5529000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 169052512 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 166547212 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9350000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9356000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17532500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17276500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262652 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.262651 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693890023000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262652 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1693890143000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.262651 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1425,8 +1448,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5715176550 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5715176550 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5628764250 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 5628764250 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles @@ -1449,17 +1472,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 137542.754861 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 137542.754861 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 87544 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 86158 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9998 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9840 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756151 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.755894 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1467,234 +1490,234 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17024 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4816616550 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4816616550 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4743516250 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4743516250 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.409704 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.409704 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278739.383681 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278739.383681 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278636.997768 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278636.997768 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337552 # number of replacements -system.l2c.tags.tagsinuse 65418.667862 # Cycle average of tags in use -system.l2c.tags.total_refs 2487006 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402715 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.175598 # Average number of references to valid blocks. +system.l2c.tags.replacements 337565 # number of replacements +system.l2c.tags.tagsinuse 65420.967844 # Cycle average of tags in use +system.l2c.tags.total_refs 2486640 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402728 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.174490 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54698.574366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2340.440822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2723.231256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 572.328176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 607.228358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2274.234670 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2202.630214 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.834634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041553 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008733 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034702 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033609 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54725.451973 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2331.479005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2701.186077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 572.371097 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 609.192683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2285.385373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2195.901635 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.035576 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041217 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008734 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009296 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034872 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.033507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998245 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1015 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5951 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2685 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55344 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5954 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2697 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55331 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26261755 # Number of tag accesses -system.l2c.tags.data_accesses 26261755 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 506757 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 483132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 121571 # 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+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173792 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.066007 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020243 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.805556 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.604167 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421159 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.237872 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.133576 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.250681 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109791 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034792 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.250681 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109791 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034792 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54265.105965 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54258.911637 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 55683.866820 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 15483.655172 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 15483.655172 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56107.979847 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69958.127106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63670.699955 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1804,91 +1827,91 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 294926 # Transaction distribution -system.membus.trans_dist::ReadResp 294920 # Transaction distribution +system.membus.trans_dist::ReadReq 294932 # Transaction distribution +system.membus.trans_dist::ReadResp 294926 # Transaction distribution system.membus.trans_dist::WriteReq 9811 # Transaction distribution system.membus.trans_dist::WriteResp 9811 # Transaction distribution -system.membus.trans_dist::Writeback 116899 # Transaction distribution +system.membus.trans_dist::Writeback 116905 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 147 # Transaction distribution +system.membus.trans_dist::UpgradeReq 163 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 149 # Transaction distribution -system.membus.trans_dist::ReadExReq 115717 # Transaction distribution -system.membus.trans_dist::ReadExResp 115717 # Transaction distribution +system.membus.trans_dist::UpgradeResp 165 # Transaction distribution +system.membus.trans_dist::ReadExReq 115724 # Transaction distribution +system.membus.trans_dist::ReadExResp 115724 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882304 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916226 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1041133 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30677576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30678792 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36001224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36002440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 140 # Total snoops (count) -system.membus.snoop_fanout::samples 562099 # Request fanout histogram +system.membus.snoop_fanout::samples 562134 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562099 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 562134 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562099 # Request fanout histogram -system.membus.reqLayer0.occupancy 11803000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 562134 # Request fanout histogram +system.membus.reqLayer0.occupancy 11832500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 659094000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 654960000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 769927201 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 770434435 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17910500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17654500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063113 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2063092 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2063004 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2062983 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835902 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302718 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302718 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835667 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17024 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 48 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 57 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302779 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302779 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1929756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5587153 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61750976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142744520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204495496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41919 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3236289 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012893 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112812 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930013 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3656818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5586831 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61758720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142717704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204476424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41934 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3236018 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012894 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112817 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3194564 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3194293 98.71% 98.71% # Request fanout histogram system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3236289 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2206148499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3236018 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2201638999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2029921963 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2030846564 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2294082992 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2289452792 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 9cf124dc2..16f8b652d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.844427 # Number of seconds simulated -sim_ticks 2844427140500 # Number of ticks simulated -final_tick 2844427140500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.845843 # Number of seconds simulated +sim_ticks 2845842660500 # Number of ticks simulated +final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 150296 # Simulator instruction rate (inst/s) -host_op_rate 181972 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3416553864 # Simulator tick rate (ticks/s) -host_mem_usage 612172 # Number of bytes of host memory used -host_seconds 832.54 # Real time elapsed on the host -sim_insts 125127935 # Number of instructions simulated -sim_ops 151499394 # Number of ops (including micro ops) simulated +host_inst_rate 164712 # Simulator instruction rate (inst/s) +host_op_rate 199442 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3743328799 # Simulator tick rate (ticks/s) +host_mem_usage 646452 # Number of bytes of host memory used +host_seconds 760.24 # Real time elapsed on the host +sim_insts 125221621 # Number of instructions simulated +sim_ops 151624712 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 10304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1349820 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10836800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 503456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1120064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3007420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 774240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 13821980 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 416640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 27264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 443904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9404288 # Number of bytes written to this memory +system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1722304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9422032 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 161 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 21616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 169325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7890 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 17501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 47516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 12121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216517 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 146942 # Number of write requests responded to by this memory +system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 151378 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 474549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3809836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 176997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 393775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4859319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 146476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 9585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3306215 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 6224 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 1056777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 272060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 605200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 6221 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3312453 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3306215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 480773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3809836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 177011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 393775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8171773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 216517 # Number of read requests accepted -system.physmem.writeReqs 187602 # Number of write requests accepted -system.physmem.readBursts 216517 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 187602 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13846784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.physmem.bytesWritten 11642944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13821980 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11740368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5664 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13644 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13513 # Per bank write bursts -system.physmem.perBankRdBursts::1 13311 # Per bank write bursts -system.physmem.perBankRdBursts::2 14548 # Per bank write bursts -system.physmem.perBankRdBursts::3 14027 # Per bank write bursts -system.physmem.perBankRdBursts::4 15548 # Per bank write bursts -system.physmem.perBankRdBursts::5 13123 # Per bank write bursts -system.physmem.perBankRdBursts::6 13508 # Per bank write bursts -system.physmem.perBankRdBursts::7 14039 # Per bank write bursts -system.physmem.perBankRdBursts::8 13183 # Per bank write bursts -system.physmem.perBankRdBursts::9 13181 # Per bank write bursts -system.physmem.perBankRdBursts::10 13142 # Per bank write bursts -system.physmem.perBankRdBursts::11 11743 # Per bank write bursts -system.physmem.perBankRdBursts::12 13238 # Per bank write bursts -system.physmem.perBankRdBursts::13 14181 # Per bank write bursts -system.physmem.perBankRdBursts::14 13272 # Per bank write bursts -system.physmem.perBankRdBursts::15 12799 # Per bank write bursts -system.physmem.perBankWrBursts::0 11429 # Per bank write bursts -system.physmem.perBankWrBursts::1 11725 # Per bank write bursts -system.physmem.perBankWrBursts::2 12190 # Per bank write bursts -system.physmem.perBankWrBursts::3 11854 # Per bank write bursts -system.physmem.perBankWrBursts::4 10909 # Per bank write bursts -system.physmem.perBankWrBursts::5 11199 # Per bank write bursts -system.physmem.perBankWrBursts::6 11528 # Per bank write bursts -system.physmem.perBankWrBursts::7 11643 # Per bank write bursts -system.physmem.perBankWrBursts::8 11026 # Per bank write bursts -system.physmem.perBankWrBursts::9 11436 # Per bank write bursts -system.physmem.perBankWrBursts::10 11468 # Per bank write bursts -system.physmem.perBankWrBursts::11 11022 # Per bank write bursts -system.physmem.perBankWrBursts::12 11525 # Per bank write bursts -system.physmem.perBankWrBursts::13 11398 # Per bank write bursts -system.physmem.perBankWrBursts::14 10974 # Per bank write bursts -system.physmem.perBankWrBursts::15 10595 # Per bank write bursts +system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 1062998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 272074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 202521 # Number of read requests accepted +system.physmem.writeReqs 180931 # Number of write requests accepted +system.physmem.readBursts 202521 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 180931 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12951936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue +system.physmem.bytesWritten 11206784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12926236 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11313424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5797 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13571 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12806 # Per bank write bursts +system.physmem.perBankRdBursts::1 12696 # Per bank write bursts +system.physmem.perBankRdBursts::2 13455 # Per bank write bursts +system.physmem.perBankRdBursts::3 13223 # Per bank write bursts +system.physmem.perBankRdBursts::4 15141 # Per bank write bursts +system.physmem.perBankRdBursts::5 12251 # Per bank write bursts +system.physmem.perBankRdBursts::6 12720 # Per bank write bursts +system.physmem.perBankRdBursts::7 12666 # Per bank write bursts +system.physmem.perBankRdBursts::8 12396 # Per bank write bursts +system.physmem.perBankRdBursts::9 12410 # Per bank write bursts +system.physmem.perBankRdBursts::10 12030 # Per bank write bursts +system.physmem.perBankRdBursts::11 11077 # Per bank write bursts +system.physmem.perBankRdBursts::12 12224 # Per bank write bursts +system.physmem.perBankRdBursts::13 12978 # Per bank write bursts +system.physmem.perBankRdBursts::14 12239 # Per bank write bursts +system.physmem.perBankRdBursts::15 12062 # Per bank write bursts +system.physmem.perBankWrBursts::0 11243 # Per bank write bursts +system.physmem.perBankWrBursts::1 11520 # Per bank write bursts +system.physmem.perBankWrBursts::2 11868 # Per bank write bursts +system.physmem.perBankWrBursts::3 11342 # Per bank write bursts +system.physmem.perBankWrBursts::4 10753 # Per bank write bursts +system.physmem.perBankWrBursts::5 10659 # Per bank write bursts +system.physmem.perBankWrBursts::6 11197 # Per bank write bursts +system.physmem.perBankWrBursts::7 10854 # Per bank write bursts +system.physmem.perBankWrBursts::8 10720 # Per bank write bursts +system.physmem.perBankWrBursts::9 10780 # Per bank write bursts +system.physmem.perBankWrBursts::10 10917 # Per bank write bursts +system.physmem.perBankWrBursts::11 10553 # Per bank write bursts +system.physmem.perBankWrBursts::12 10892 # Per bank write bursts +system.physmem.perBankWrBursts::13 10850 # Per bank write bursts +system.physmem.perBankWrBursts::14 10512 # Per bank write bursts +system.physmem.perBankWrBursts::15 10446 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2844424796500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 2845842079500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 215930 # Read request sizes (log2) +system.physmem.readPktSize::6 201934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 183166 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 79055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 92 # What read queue length does an incoming req see +system.physmem.writePktSize::6 176495 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9843 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -176,173 +176,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 13080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 93322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 273.137395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.655882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.256113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45588 48.85% 48.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18736 20.08% 68.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6915 7.41% 76.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3558 3.81% 80.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3108 3.33% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2062 2.21% 85.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1352 1.45% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1057 1.13% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10946 11.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 93322 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7762 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.873744 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 521.384620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7761 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7762 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7762 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.437387 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.920909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.626862 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6141 79.12% 79.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 490 6.31% 85.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 77 0.99% 86.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 208 2.68% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 144 1.86% 90.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 0.70% 91.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 53 0.68% 92.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 34 0.44% 92.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 115 1.48% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.19% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 16 0.21% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.18% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 31 0.40% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.22% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.12% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.31% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 61 0.79% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.12% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.05% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 7 0.09% 96.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 74 0.95% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.15% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.10% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 21 0.27% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 7 0.09% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 12 0.15% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 7 0.09% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.36% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.12% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.12% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 8 0.10% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.09% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 3 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7762 # Writes before turning the bus around for reads -system.physmem.totQLat 7644398000 # Total ticks spent queuing -system.physmem.totMemAccLat 11701073000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1081780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35332.50 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 94139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 256.627498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.457232 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.924062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48795 51.83% 51.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18347 19.49% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6488 6.89% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3770 4.00% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2738 2.91% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1619 1.72% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 964 1.02% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1076 1.14% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10342 10.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94139 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7479 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.058430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 520.327968 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7478 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7479 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.413023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.870843 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.578889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 6390 85.44% 85.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 248 3.32% 88.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 198 2.65% 91.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 77 1.03% 92.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 144 1.93% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 30 0.40% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 35 0.47% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 33 0.44% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 72 0.96% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 21 0.28% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 96 1.28% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 18 0.24% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 22 0.29% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 12 0.16% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 35 0.47% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 12 0.16% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 4 0.05% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 8 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7479 # Writes before turning the bus around for reads +system.physmem.totQLat 5783977250 # Total ticks spent queuing +system.physmem.totMemAccLat 9578489750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1011870000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28580.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54082.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.86 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.13 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47330.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.94 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.48 # Average write queue length when enqueuing -system.physmem.readRowHits 183280 # Number of row buffer hits during reads -system.physmem.writeRowHits 121675 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.88 # Row buffer hit rate for writes -system.physmem.avgGap 7038582.19 # Average gap between requests -system.physmem.pageHitRate 76.57 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2710525028500 # Time in different power states -system.physmem.memoryStateTime::REF 94981640000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 38919724000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 365533560 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 339980760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 199447875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 185505375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 870612600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 816964200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 599250960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 579597120 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 185784087840 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 185784087840 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82151193285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81119552850 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1634593377000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1635498324750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1904563503120 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1904324012895 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.577359 # Core power per rank (mW) -system.physmem.averagePower::1 669.493163 # Core power per rank (mW) +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 168404 # Number of row buffer hits during reads +system.physmem.writeRowHits 114936 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.63 # Row buffer hit rate for writes +system.physmem.avgGap 7421638.38 # Average gap between requests +system.physmem.pageHitRate 75.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 372813840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 203420250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 818672400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 579545280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83421293220 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634324841000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905596723190 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.608836 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2718714861000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95028700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32092142750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 338877000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 184903125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 759837000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 555141600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82372109895 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635245177250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905332183070 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.515879 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720254769500 # Time in different power states +system.physmem_1.memoryStateTime::REF 95028700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30559102000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory @@ -352,31 +338,39 @@ system.realview.nvmem.bytes_inst_read::total 1216 system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 157 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 427 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 157 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 427 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 157 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 35736686 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17706973 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1707657 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20554340 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14845557 # Number of BTB hits +system.cpu0.branchPred.lookups 35059389 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17250705 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1579435 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20094508 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14609065 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.225900 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10924417 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 815226 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.701780 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10810171 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 733013 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -398,27 +392,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 67889 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67889 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44852 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23037 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 67889 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 67889 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 67889 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6673 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 8598.195564 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7320.525431 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6106.619536 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6491 97.27% 97.27% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 168 2.52% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6673 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 287368000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 287368000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 287368000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5164 77.39% 77.39% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1509 22.61% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6673 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67889 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67889 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6673 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6673 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 74562 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24607000 # DTB read hits -system.cpu0.dtb.read_misses 66402 # DTB read misses -system.cpu0.dtb.write_hits 18455953 # DTB write hits -system.cpu0.dtb.write_misses 6655 # DTB write misses +system.cpu0.dtb.read_hits 23969568 # DTB read hits +system.cpu0.dtb.read_misses 61820 # DTB read misses +system.cpu0.dtb.write_hits 17946825 # DTB write hits +system.cpu0.dtb.write_misses 6069 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3808 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1234 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2108 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1251 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2004 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 615 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24673402 # DTB read accesses -system.cpu0.dtb.write_accesses 18462608 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24031388 # DTB read accesses +system.cpu0.dtb.write_accesses 17952894 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43062953 # DTB hits -system.cpu0.dtb.misses 73057 # DTB misses -system.cpu0.dtb.accesses 43136010 # DTB accesses +system.cpu0.dtb.hits 41916393 # DTB hits +system.cpu0.dtb.misses 67889 # DTB misses +system.cpu0.dtb.accesses 41984282 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -440,8 +473,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 71661808 # ITB inst hits -system.cpu0.itb.inst_misses 4142 # ITB inst misses +system.cpu0.itb.walker.walks 3825 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3825 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3518 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3825 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3825 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3825 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 8874.535345 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 7628.532351 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4888.994435 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1491 61.64% 61.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 888 36.71% 98.35% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.51% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 286941000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 286941000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 286941000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3825 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3825 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 70462798 # ITB inst hits +system.cpu0.itb.inst_misses 3825 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -450,123 +513,123 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2456 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 8241 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7291 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 71665950 # ITB inst accesses -system.cpu0.itb.hits 71661808 # DTB hits -system.cpu0.itb.misses 4142 # DTB misses -system.cpu0.itb.accesses 71665950 # DTB accesses -system.cpu0.numCycles 235973632 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70466623 # ITB inst accesses +system.cpu0.itb.hits 70462798 # DTB hits +system.cpu0.itb.misses 3825 # DTB misses +system.cpu0.itb.accesses 70466623 # DTB accesses +system.cpu0.numCycles 234985394 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 111703770 # Number of instructions committed -system.cpu0.committedOps 135097839 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8562554 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1855 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5452894525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.112495 # CPI: cycles per instruction -system.cpu0.ipc 0.473374 # IPC: instructions per cycle +system.cpu0.committedInsts 109265327 # Number of instructions committed +system.cpu0.committedOps 132114239 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8364757 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1821 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5456715361 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.150594 # CPI: cycles per instruction +system.cpu0.ipc 0.464988 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1855 # number of quiesce instructions executed -system.cpu0.tickCycles 199544848 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 36428784 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 751860 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.262864 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41566353 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 752372 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.247076 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 306713000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.262864 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965357 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965357 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1824 # number of quiesce instructions executed +system.cpu0.tickCycles 195318282 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 39667112 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 718541 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.305697 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40476936 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.305697 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 86104149 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 86104149 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 23403701 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23403701 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 17336391 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17336391 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 390425 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 390425 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 371566 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 371566 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 40740092 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40740092 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 40740092 # number of overall hits -system.cpu0.dcache.overall_hits::total 40740092 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 564897 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 564897 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 554409 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 554409 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6644 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6644 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20340 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20340 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1119306 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1119306 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1119306 # number of overall misses -system.cpu0.dcache.overall_misses::total 1119306 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6887885459 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6887885459 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8219762503 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8219762503 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 108110000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 108110000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 440070983 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 440070983 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 121000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 15107647962 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15107647962 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 15107647962 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15107647962 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23968598 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23968598 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17890800 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17890800 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 397069 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 397069 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 391906 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391906 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 41859398 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41859398 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 41859398 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 41859398 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023568 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.023568 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030988 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030988 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016733 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051900 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051900 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026740 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026740 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026740 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026740 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12193.170541 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12193.170541 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 14826.170757 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14826.170757 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16271.824202 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.824202 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21635.741544 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21635.741544 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 83802985 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83802985 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 22808347 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22808347 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 16863099 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16863099 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381264 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 381264 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362825 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362825 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 39671446 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 39671446 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 39671446 # number of overall hits +system.cpu0.dcache.overall_hits::total 39671446 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 540080 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 540080 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 532227 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 532227 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6489 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6489 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 19898 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19898 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 1072307 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1072307 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 1072307 # number of overall misses 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accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387753 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382723 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382723 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 40743753 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40743753 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 40743753 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40743753 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023131 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.023131 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030596 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030596 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016735 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016735 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051991 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051991 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026318 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026318 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026318 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026318 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12310.092429 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15632.187388 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16169.479119 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 22019.443411 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13497.334922 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13497.334922 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13497.334922 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,74 +638,74 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 541643 # number of writebacks -system.cpu0.dcache.writebacks::total 541643 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 45094 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 45094 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 240822 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 240822 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 285916 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 285916 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 285916 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 285916 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 519803 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 519803 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 313587 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 313587 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6644 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6644 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20340 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20340 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 833390 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 833390 # number of demand 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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 398879017 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 115000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 115000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9690655600 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9690655600 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9690655600 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9690655600 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6196262496 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6196262496 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4811489492 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4811489492 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11007751988 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11007751988 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021687 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021687 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017528 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017528 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051900 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051900 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.019909 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019909 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019909 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10241.794353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10241.794353 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13925.769149 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13925.769149 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14269.416014 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14269.416014 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19610.571141 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19610.571141 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 523102 # number of writebacks +system.cpu0.dcache.writebacks::total 523102 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42658 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 42658 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230433 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 230433 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273091 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 273091 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273091 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 273091 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 497422 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 497422 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 301794 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 301794 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6489 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6489 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 19898 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19898 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 799216 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 799216 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 799216 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 799216 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5149793898 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149793898 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4423706193 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4423706193 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 91926250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91926250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397751115 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397751115 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 291000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 291000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9573500091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9573500091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9573500091 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9573500091 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6190990749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6190990749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4804555500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4804555500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995546249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995546249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016735 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016735 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051991 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051991 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019616 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.019616 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019616 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019616 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10352.967697 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14658.032277 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14166.474033 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19989.502211 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11627.996016 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11627.996016 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency 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number of replacements -system.cpu0.icache.tags.tagsinuse 511.797171 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 69582233 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 2070954 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.599121 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6297775000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.797171 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999604 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1982441 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.792915 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 68472197 # Total number of references to valid blocks. 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accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 71653203 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 71653203 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 71653203 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 71653203 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 71653203 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028903 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028903 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028903 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028903 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028903 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028903 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8333.299362 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8333.299362 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8333.299362 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8333.299362 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8333.299362 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 142893294 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 142893294 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 68472197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 68472197 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 68472197 # number of demand (read+write) hits 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demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18641895952 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18641895952 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18641895952 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70455164 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70455164 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70455164 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70455164 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70455164 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70455164 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028145 # miss rate for ReadReq accesses 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overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,313 +773,323 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2070970 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 2070970 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 2070970 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 2070970 # number of demand (read+write) MSHR misses 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6832.401976 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6832.401976 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6832.401976 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6832.401976 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1982967 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1982967 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1982967 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1982967 # number of demand (read+write) MSHR misses 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7895.848517 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7895.848517 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 18115074 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 431506 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 17132776 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9283 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6596 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 534910 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1383846 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 428439 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16212.256950 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3152645 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 444682 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.089662 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2824980212500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4226.197620 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.775812 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065487 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2187.555983 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.662049 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.257947 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003099 # Average percentage of cache occupancy +system.cpu0.l2cache.prefetcher.num_hwpf_issued 2292717 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 2293221 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 436 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 284211 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 303376 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16141.726832 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2969035 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 319611 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.289527 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2825848630000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6310.295058 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.412646 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.063392 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 7791.524761 # Average occupied blocks per requestor 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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.057106 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055577 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856775 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856775 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.881465 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.881465 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.154795 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154795 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.044889 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.846699 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.846699 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.905006 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905006 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.150831 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225125 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30134.034017 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17026.462281 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13360.510885 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 109500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35947.135948 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1024,67 +1097,75 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2861093 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2792980 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28855 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28855 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 541643 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 731101 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2669763 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 523100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 388140 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 68486 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42622 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 93982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 302729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 293421 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 4148051 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2491359 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12339 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 183942 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6835691 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 132737600 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90757533 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17524 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 340220 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 223852877 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1093341 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4548807 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.213001 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.409428 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeReq 64720 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42432 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 88655 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299964 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 286773 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3972081 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2399294 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11788 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172273 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6555436 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127106560 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 87442327 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17780 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325388 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 214892055 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 732010 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4046250 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.152317 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.359328 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 3579907 78.70% 78.70% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 968900 21.30% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 3429939 84.77% 84.77% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 616311 15.23% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4548807 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2378574445 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4046250 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2284841999 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 119537998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 117254000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 3112636730 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2984852953 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1291088389 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1241569539 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7963988 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7347491 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 98908477 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 90940738 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3448752 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1941981 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 196391 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2221819 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1396869 # Number of BTB hits +system.cpu1.branchPred.lookups 4088735 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2366310 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 253216 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2663045 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1651600 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 62.870513 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 715789 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 52420 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 62.019230 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 809555 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 58673 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1106,27 +1187,66 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 25571 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 25571 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18521 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7050 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 25571 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 25571 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 25571 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 8701.256278 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7631.681902 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5745.938863 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2093 77.29% 77.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 481 17.76% 95.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 9 0.33% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 4 0.15% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1108722264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1108722264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1108722264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.74% 73.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 711 26.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 25571 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 25571 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28279 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3432223 # DTB read hits -system.cpu1.dtb.read_misses 19764 # DTB read misses -system.cpu1.dtb.write_hits 2826731 # DTB write hits -system.cpu1.dtb.write_misses 1392 # DTB write misses +system.cpu1.dtb.read_hits 4075725 # DTB read hits +system.cpu1.dtb.read_misses 23546 # DTB read misses +system.cpu1.dtb.write_hits 3346999 # DTB write hits +system.cpu1.dtb.write_misses 2025 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1674 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2069 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 121 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 325 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3451987 # DTB read accesses -system.cpu1.dtb.write_accesses 2828123 # DTB write accesses +system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4099271 # DTB read accesses +system.cpu1.dtb.write_accesses 3349024 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6258954 # DTB hits -system.cpu1.dtb.misses 21156 # DTB misses -system.cpu1.dtb.accesses 6280110 # DTB accesses +system.cpu1.dtb.hits 7422724 # DTB hits +system.cpu1.dtb.misses 25571 # DTB misses +system.cpu1.dtb.accesses 7448295 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1148,8 +1268,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 6653879 # ITB inst hits -system.cpu1.itb.inst_misses 1856 # ITB inst misses +system.cpu1.itb.walker.walks 2243 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2243 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2062 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2243 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2243 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2243 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 8831.106061 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 7825.020839 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4777.823788 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 160 14.26% 14.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 676 60.25% 74.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 3 0.27% 74.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 248 22.10% 96.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 98.13% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.69% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1108154264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1108154264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1108154264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 954 85.03% 85.03% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 14.97% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2243 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2243 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3365 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 7772051 # ITB inst hits +system.cpu1.itb.inst_misses 2243 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1158,122 +1312,122 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 882 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1128 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1845 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6655735 # ITB inst accesses -system.cpu1.itb.hits 6653879 # DTB hits -system.cpu1.itb.misses 1856 # DTB misses -system.cpu1.itb.accesses 6655735 # DTB accesses -system.cpu1.numCycles 36145472 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7774294 # ITB inst accesses +system.cpu1.itb.hits 7772051 # DTB hits +system.cpu1.itb.misses 2243 # DTB misses +system.cpu1.itb.accesses 7774294 # DTB accesses +system.cpu1.numCycles 42246986 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13424165 # Number of instructions committed -system.cpu1.committedOps 16401555 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1287407 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5652095397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.692568 # CPI: cycles per instruction -system.cpu1.ipc 0.371393 # IPC: instructions per cycle +system.cpu1.committedInsts 15956294 # Number of instructions committed +system.cpu1.committedOps 19510473 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1491389 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2792 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5648821854 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.647669 # CPI: cycles per instruction +system.cpu1.ipc 0.377691 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed -system.cpu1.tickCycles 26236459 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 9909013 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 149765 # number of replacements -system.cpu1.dcache.tags.tagsinuse 476.829408 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5935391 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 150124 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.536590 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 107725830000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 476.829408 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.931307 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.931307 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12574886 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12574886 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3167382 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3167382 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 2587127 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2587127 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 79870 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79870 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 60510 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 60510 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 5754509 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5754509 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 5754509 # number of overall hits -system.cpu1.dcache.overall_hits::total 5754509 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 151161 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 151161 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 116953 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 116953 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5079 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5079 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 22818 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22818 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 268114 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 268114 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 268114 # number of overall misses -system.cpu1.dcache.overall_misses::total 268114 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2359046468 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2359046468 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3063915205 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3063915205 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93260000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 93260000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 534664798 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 534664798 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 106500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 106500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 5422961673 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5422961673 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 5422961673 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5422961673 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3318543 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3318543 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 2704080 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2704080 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 84949 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 84949 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 83328 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83328 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 6022623 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6022623 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 6022623 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6022623 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.045550 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045550 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043251 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043251 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.059789 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.059789 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.273834 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273834 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044518 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044518 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044518 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044518 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15606.184585 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.184585 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26197.833360 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26197.833360 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18361.882260 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18361.882260 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23431.711719 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.711719 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2795 # number of quiesce instructions executed +system.cpu1.tickCycles 30354295 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 11892691 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 187758 # number of replacements +system.cpu1.dcache.tags.tagsinuse 478.493571 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7034054 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 188124 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.390519 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 108317904000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 478.493571 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.934558 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.934558 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14914460 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14914460 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 3762812 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3762812 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 3070723 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3070723 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 89288 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 89288 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69262 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 69262 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 6833535 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6833535 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 6833535 # number of overall hits +system.cpu1.dcache.overall_hits::total 6833535 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 181434 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 181434 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 139542 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 139542 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5058 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5058 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23425 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23425 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 320976 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320976 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 320976 # number of overall misses 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+system.cpu1.dcache.WriteReq_miss_rate::total 0.043467 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.053611 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.053611 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.252732 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.252732 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044863 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044863 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044863 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044863 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.161695 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26324.772233 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18120.650652 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23092.073127 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20226.327879 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 20226.327879 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20226.327879 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1282,74 +1436,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 93707 # number of writebacks -system.cpu1.dcache.writebacks::total 93707 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 11593 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 11593 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 39187 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 39187 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 50780 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 50780 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 50780 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 50780 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 139568 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 139568 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 77766 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 77766 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5079 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5079 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 22818 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 22818 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 217334 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 217334 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 217334 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 217334 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 1914681986 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914681986 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1867013423 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1867013423 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83091000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83091000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 487833202 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 487833202 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 100500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 100500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 3781695409 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3781695409 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 3781695409 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3781695409 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 327471996 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 327471996 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 198424999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 198424999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 525896995 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 525896995 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042057 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042057 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028759 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028759 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.059789 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059789 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.273834 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273834 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.036086 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036086 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036086 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13718.631678 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13718.631678 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24008.093807 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24008.093807 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16359.716480 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16359.716480 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21379.314664 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21379.314664 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks +system.cpu1.dcache.writebacks::total 113901 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15137 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49794 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 49794 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64931 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 64931 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64931 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 64931 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166297 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166297 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89748 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 89748 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5058 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5058 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23425 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23425 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256045 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 256045 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256045 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 256045 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2162409829 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2162409829 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2163633710 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2163633710 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 81526749 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81526749 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492905187 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492905187 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 177500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 177500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4326043539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4326043539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4326043539 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4326043539 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 330271000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 330271000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 203208500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 203208500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 533479500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 533479500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042162 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042162 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027957 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027957 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.053611 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053611 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.252732 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.252732 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.035788 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035788 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13003.300294 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24107.876610 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16118.376631 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21041.843629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 17400.385623 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17400.385623 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1357,58 +1511,57 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 827152 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.447245 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 5824947 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 827664 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.037816 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 71343314500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.447245 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975483 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975483 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 908016 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.415703 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6861520 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 908528 # Sample count of references to valid blocks. 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system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14132886 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14132886 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 5824947 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5824947 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5824947 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5824947 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5824947 # number of overall hits -system.cpu1.icache.overall_hits::total 5824947 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 827664 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 827664 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 827664 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 827664 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 827664 # number of overall misses -system.cpu1.icache.overall_misses::total 827664 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6712177482 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6712177482 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6712177482 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6712177482 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6712177482 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6712177482 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 6652611 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 6652611 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 6652611 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 6652611 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 6652611 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 6652611 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124412 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.124412 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124412 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.124412 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124412 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.124412 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8109.785471 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8109.785471 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8109.785471 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8109.785471 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8109.785471 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 16448624 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16448624 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6861520 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6861520 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6861520 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6861520 # number of demand (read+write) hits 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of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7748571238 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7748571238 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7770048 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7770048 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7770048 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7770048 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7770048 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7770048 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116927 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.116927 # miss rate for ReadReq accesses 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access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1417,310 +1570,307 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 827664 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 827664 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 827664 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 827664 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 827664 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 827664 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5467532518 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5467532518 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5467532518 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5467532518 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5467532518 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5467532518 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10038000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10038000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10038000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10038000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124412 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.124412 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.124412 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6605.980830 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 908528 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 908528 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 908528 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 908528 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 908528 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 908528 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6381932762 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6381932762 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6381932762 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6381932762 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6381932762 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6381932762 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10331250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10331250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10331250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10331250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116927 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.116927 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.116927 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7024.475593 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6453687 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 29592 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6340817 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 898 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2376 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 80004 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 668025 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 52740 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15520.178150 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1029232 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 68128 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 15.107327 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.num_hwpf_issued 255012 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 255045 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 26 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 67427 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 54264 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15327.785502 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1131516 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 69292 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.329677 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6901.586978 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.255538 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.084140 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2337.993929 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6253.257565 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.421239 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142700 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.381669 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.947276 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8859 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 87 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6442 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 153 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1624 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 7082 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5323.780218 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy 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0.962220 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.579041 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.579041 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103663 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168476 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 16584.286753 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14215.662923 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13602.785492 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413 # average overall mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30008.051108 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1728,64 +1878,64 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1502965 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1041469 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2098 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2098 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 93707 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 114724 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1157222 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2126 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2126 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 113900 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 36842 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 83933 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40744 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 65298 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 52790 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1655558 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 667978 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6105 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48641 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2378282 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 52977856 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21039827 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10136 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93092 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 74120911 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 816365 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1934720 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.382054 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.485890 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74786 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41424 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85596 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 82199 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 64364 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1817284 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 767101 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7150 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 61380 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2652915 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58153088 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24793955 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11380 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115036 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 83073459 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 610470 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1874725 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.283158 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.450533 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1195552 61.79% 61.79% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 739168 38.21% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1343882 71.68% 71.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 530843 28.32% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1934720 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 695166718 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1874725 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 789561722 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78719500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79017500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1243267482 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1364909988 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 322631890 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 381206023 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3571998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4307495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 25370995 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 32623745 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31020 # Transaction distribution -system.iobus.trans_dist::ReadResp 31020 # Transaction distribution -system.iobus.trans_dist::WriteReq 59447 # Transaction distribution -system.iobus.trans_dist::WriteResp 23223 # Transaction distribution +system.iobus.trans_dist::ReadReq 31012 # Transaction distribution +system.iobus.trans_dist::ReadResp 31012 # Transaction distribution +system.iobus.trans_dist::WriteReq 59440 # Transaction distribution +system.iobus.trans_dist::WriteResp 23216 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56686 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1806,11 +1956,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 108000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71630 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1831,11 +1981,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40158000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1875,23 +2025,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347075142 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347036169 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84777000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36822606 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36822569 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 0.995239 # Cycle average of tags in use +system.iocache.tags.replacements 36417 # number of replacements +system.iocache.tags.tagsinuse 0.997930 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 269184120000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.995239 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062202 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062202 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 269849823000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.997930 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062371 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062371 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1905,14 +2055,14 @@ system.iocache.demand_misses::realview.ide 243 # system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30315377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30315377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9644186159 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9644186159 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30315377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30315377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30315377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30315377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30354377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30354377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9625347223 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9625347223 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30354377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30354377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30354377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30354377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1929,24 +2079,24 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124754.637860 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124754.637860 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124754.637860 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 57278 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124915.131687 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124915.131687 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265717.403462 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265717.403462 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124915.131687 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124915.131687 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56938 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7269 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7266 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.879763 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.836224 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.writebacks::writebacks 36174 # number of writebacks +system.iocache.writebacks::total 36174 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses @@ -1955,14 +2105,14 @@ system.iocache.demand_mshr_misses::realview.ide 243 system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17678377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17678377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7760326371 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7760326371 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17678377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17678377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17678377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17678377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17717377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17717377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7741561361 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7741561361 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17717377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17717377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17717377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17717377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1971,264 +2121,264 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72911.016461 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72911.016461 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213713.597642 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213713.597642 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 150396 # number of replacements -system.l2c.tags.tagsinuse 64479.883220 # Cycle average of tags in use -system.l2c.tags.total_refs 522727 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 215317 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.427709 # Average number of references to valid blocks. +system.l2c.tags.replacements 139153 # number of replacements +system.l2c.tags.tagsinuse 64176.379405 # Cycle average of tags in use +system.l2c.tags.total_refs 380612 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 203608 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.869337 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12469.492368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 93.733463 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3818.005633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.718540 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 732.215158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4549.115372 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.190269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001430 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.058258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.653238 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.069414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983885 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 47457 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 17396 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 475 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6086 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 40896 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 11502.485032 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 90.401142 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 12425.194881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36413.661117 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.683124 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1856.879628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1880.036266 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.175514 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001379 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 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25972 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 67 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 270 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2310 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 14797 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.724136 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.265442 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6561930 # Number of tag accesses -system.l2c.tags.data_accesses 6561930 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 576 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 131 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 39519 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 221242 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 94 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 19 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 25945 # number of ReadReq hits -system.l2c.ReadReq_hits::total 294426 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 250431 # number of Writeback hits -system.l2c.Writeback_hits::total 250431 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 11782 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 481 # number of UpgradeReq hits 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+system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3295 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28977 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.485153 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.497330 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5313847 # Number of tag accesses +system.l2c.tags.data_accesses 5313847 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 426 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 70654 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 75814 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 118 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 24007 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7439 # number of ReadReq hits +system.l2c.ReadReq_hits::total 178553 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 234152 # number of Writeback hits +system.l2c.Writeback_hits::total 234152 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 2938 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 658 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3596 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 142 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 176 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 3842 # number 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accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.448460 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.823292 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.490824 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.741210 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.863442 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.822390 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.656524 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.876244 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.746324 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.218453 # mshr miss rate for demand accesses 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cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16730077755 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5519244498 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263262750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5782507248 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096891000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150604000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4247495000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9616135498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413866750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10030002248 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.315304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.121800 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.500587 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.753275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.806014 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.871062 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850353 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.750795 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.866906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.796500 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.520232 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.520232 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62521.611524 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64927.927628 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10229.922408 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.488296 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.542071 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10022.864592 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69789.055983 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61107.769940 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2396,57 +2549,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 238185 # Transaction distribution -system.membus.trans_dist::ReadResp 238185 # Transaction distribution -system.membus.trans_dist::WriteReq 30953 # Transaction distribution -system.membus.trans_dist::WriteResp 30953 # Transaction distribution -system.membus.trans_dist::Writeback 146942 # Transaction distribution +system.membus.trans_dist::ReadReq 217279 # Transaction distribution +system.membus.trans_dist::ReadResp 217279 # Transaction distribution +system.membus.trans_dist::WriteReq 30939 # Transaction distribution +system.membus.trans_dist::WriteResp 30939 # Transaction distribution +system.membus.trans_dist::Writeback 140271 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78292 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39832 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13662 # Transaction distribution -system.membus.trans_dist::ReadExReq 30241 # Transaction distribution -system.membus.trans_dist::ReadExResp 13298 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 108000 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 75080 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40217 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13603 # Transaction distribution +system.membus.trans_dist::ReadExReq 40948 # Transaction distribution +system.membus.trans_dist::ReadExResp 20159 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13634 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 701758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 823430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 932326 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 668031 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 789629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 898509 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27268 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 20926892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21118256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25753712 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122070 # Total snoops (count) -system.membus.snoop_fanout::samples 531658 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27180 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19605228 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19796474 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24430906 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123136 # Total snoops (count) +system.membus.snoop_fanout::samples 511969 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 531658 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 511969 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 531658 # Request fanout histogram -system.membus.reqLayer0.occupancy 88755994 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 511969 # Request fanout histogram +system.membus.reqLayer0.occupancy 88887000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11894500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11855500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1935574499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1869891749 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2123782192 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2005520473 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38517394 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38480431 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2479,44 +2632,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 658320 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 658305 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30953 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30953 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 250431 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 516876 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 516861 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30939 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30939 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 234152 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 90455 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 130663 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 38633 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 38633 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1411505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 304961 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1716466 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 43486557 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5753747 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49240304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 287552 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1076220 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033884 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.180932 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeReq 78584 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40535 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 119119 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51536 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51536 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1131248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290761 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1422009 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34509719 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5415139 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39924858 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 285546 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 919868 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039644 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195121 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1039753 96.61% 96.61% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36467 3.39% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 883401 96.04% 96.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36467 3.96% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1076220 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1573537018 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 919868 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1489301846 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2438104006 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1891845782 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 680349684 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 645358377 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 1c98029fc..8068ce076 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,116 +1,116 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852850 # Number of seconds simulated -sim_ticks 2852849954000 # Number of ticks simulated -final_tick 2852849954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852858 # Number of seconds simulated +sim_ticks 2852857543000 # Number of ticks simulated +final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160685 # Simulator instruction rate (inst/s) -host_op_rate 194286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4092855045 # Simulator tick rate (ticks/s) -host_mem_usage 562916 # Number of bytes of host memory used -host_seconds 697.03 # Real time elapsed on the host -sim_insts 112002684 # Number of instructions simulated -sim_ops 135423332 # Number of ops (including micro ops) simulated +host_inst_rate 169259 # Simulator instruction rate (inst/s) +host_op_rate 204656 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4303403710 # Simulator tick rate (ticks/s) +host_mem_usage 619600 # Number of bytes of host memory used +host_seconds 662.93 # Real time elapsed on the host +sim_insts 112207125 # Number of instructions simulated +sim_ops 135672670 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10823844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10837924 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1658560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1658560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7967296 # Number of bytes written to this memory +system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7984820 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 169642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 169862 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169781 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124489 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128870 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2759 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3794046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3798971 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3797164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 581370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 581370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2792750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.inst 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2798892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2792750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3800189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3805114 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6596057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 169781 # Number of read requests accepted -system.physmem.writeReqs 165094 # Number of write requests accepted -system.physmem.readBursts 169781 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165094 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10858880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10194112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10832740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10303156 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5787 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4592 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10675 # Per bank write bursts -system.physmem.perBankRdBursts::1 10570 # Per bank write bursts -system.physmem.perBankRdBursts::2 10940 # Per bank write bursts -system.physmem.perBankRdBursts::3 10884 # Per bank write bursts -system.physmem.perBankRdBursts::4 12996 # Per bank write bursts +system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170006 # Number of read requests accepted +system.physmem.writeReqs 165023 # Number of write requests accepted +system.physmem.readBursts 170006 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165023 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10873728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 10175104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10847140 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10298612 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6006 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10656 # Per bank write bursts +system.physmem.perBankRdBursts::1 10651 # Per bank write bursts +system.physmem.perBankRdBursts::2 10704 # Per bank write bursts +system.physmem.perBankRdBursts::3 10614 # Per bank write bursts +system.physmem.perBankRdBursts::4 13356 # Per bank write bursts system.physmem.perBankRdBursts::5 10666 # Per bank write bursts -system.physmem.perBankRdBursts::6 11098 # Per bank write bursts -system.physmem.perBankRdBursts::7 10877 # Per bank write bursts -system.physmem.perBankRdBursts::8 10287 # Per bank write bursts -system.physmem.perBankRdBursts::9 10457 # Per bank write bursts -system.physmem.perBankRdBursts::10 10268 # Per bank write bursts -system.physmem.perBankRdBursts::11 9318 # Per bank write bursts -system.physmem.perBankRdBursts::12 10425 # Per bank write bursts -system.physmem.perBankRdBursts::13 10908 # Per bank write bursts -system.physmem.perBankRdBursts::14 9678 # Per bank write bursts -system.physmem.perBankRdBursts::15 9623 # Per bank write bursts -system.physmem.perBankWrBursts::0 10097 # Per bank write bursts -system.physmem.perBankWrBursts::1 10006 # Per bank write bursts -system.physmem.perBankWrBursts::2 10747 # Per bank write bursts -system.physmem.perBankWrBursts::3 10511 # Per bank write bursts -system.physmem.perBankWrBursts::4 9282 # Per bank write bursts -system.physmem.perBankWrBursts::5 9914 # Per bank write bursts -system.physmem.perBankWrBursts::6 10247 # Per bank write bursts -system.physmem.perBankWrBursts::7 10166 # Per bank write bursts -system.physmem.perBankWrBursts::8 10178 # Per bank write bursts -system.physmem.perBankWrBursts::9 10302 # Per bank write bursts -system.physmem.perBankWrBursts::10 10037 # Per bank write bursts -system.physmem.perBankWrBursts::11 9553 # Per bank write bursts -system.physmem.perBankWrBursts::12 10068 # Per bank write bursts -system.physmem.perBankWrBursts::13 10279 # Per bank write bursts -system.physmem.perBankWrBursts::14 8984 # Per bank write bursts -system.physmem.perBankWrBursts::15 8912 # Per bank write bursts +system.physmem.perBankRdBursts::6 11042 # Per bank write bursts +system.physmem.perBankRdBursts::7 10972 # Per bank write bursts +system.physmem.perBankRdBursts::8 10208 # Per bank write bursts +system.physmem.perBankRdBursts::9 10672 # Per bank write bursts +system.physmem.perBankRdBursts::10 10509 # Per bank write bursts +system.physmem.perBankRdBursts::11 9657 # Per bank write bursts +system.physmem.perBankRdBursts::12 10109 # Per bank write bursts +system.physmem.perBankRdBursts::13 10747 # Per bank write bursts +system.physmem.perBankRdBursts::14 9757 # Per bank write bursts +system.physmem.perBankRdBursts::15 9582 # Per bank write bursts +system.physmem.perBankWrBursts::0 10072 # Per bank write bursts +system.physmem.perBankWrBursts::1 10092 # Per bank write bursts +system.physmem.perBankWrBursts::2 10491 # Per bank write bursts +system.physmem.perBankWrBursts::3 10304 # Per bank write bursts +system.physmem.perBankWrBursts::4 9538 # Per bank write bursts +system.physmem.perBankWrBursts::5 9899 # Per bank write bursts +system.physmem.perBankWrBursts::6 10133 # Per bank write bursts +system.physmem.perBankWrBursts::7 10134 # Per bank write bursts +system.physmem.perBankWrBursts::8 10091 # Per bank write bursts +system.physmem.perBankWrBursts::9 10380 # Per bank write bursts +system.physmem.perBankWrBursts::10 10169 # Per bank write bursts +system.physmem.perBankWrBursts::11 9697 # Per bank write bursts +system.physmem.perBankWrBursts::12 9799 # Per bank write bursts +system.physmem.perBankWrBursts::13 10201 # Per bank write bursts +system.physmem.perBankWrBursts::14 9040 # Per bank write bursts +system.physmem.perBankWrBursts::15 8946 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2852849531000 # Total gap between requests +system.physmem.totGap 2852857119000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169226 # Read request sizes (log2) +system.physmem.readPktSize::6 169451 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160713 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 162999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160642 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -155,134 +155,134 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11206 # What write queue length does an incoming req see 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queue length does an incoming req see +system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see 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req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.747313 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.220308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.895470 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22415 35.64% 35.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14531 23.10% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6612 10.51% 69.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3482 5.54% 74.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2506 3.98% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1581 2.51% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1054 1.68% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1133 1.80% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9578 15.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62892 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6668 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.444061 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 561.318574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6666 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6668 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6668 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.887672 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.937507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.272912 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5557 83.34% 83.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 39 0.58% 83.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.36% 84.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 223 3.34% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 119 1.78% 89.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 51 0.76% 90.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 29 0.43% 90.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 45 0.67% 91.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 120 1.80% 93.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.18% 93.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 15 0.22% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.21% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 30 0.45% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.28% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.12% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.52% 95.08% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 62962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.308059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.690406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.894179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22562 35.83% 35.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14454 22.96% 58.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6551 10.40% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3518 5.59% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2542 4.04% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1533 2.43% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1128 1.79% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1127 1.79% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9547 15.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.554603 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.154464 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.914862 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.938842 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.611148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5537 83.29% 83.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 45 0.68% 83.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 19 0.29% 84.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 242 3.64% 87.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 123 1.85% 89.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 53 0.80% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 26 0.39% 90.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 33 0.50% 91.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 114 1.71% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.29% 93.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.21% 93.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.17% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 33 0.50% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 20 0.30% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.15% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 22 0.33% 95.08% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.13% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.09% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.21% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 100 1.50% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 13 0.19% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.12% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 22 0.33% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 10 0.15% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.40% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.13% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.12% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6668 # Writes before turning the bus around for reads -system.physmem.totQLat 1702635750 # Total ticks spent queuing -system.physmem.totMemAccLat 4883948250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 848350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10034.98 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::84-87 16 0.24% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.11% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 13 0.20% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 84 1.26% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.08% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 9 0.14% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.14% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.23% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.05% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 10 0.15% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 37 0.56% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 8 0.12% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.14% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 5 0.08% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 4 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads +system.physmem.totQLat 1659710000 # Total ticks spent queuing +system.physmem.totMemAccLat 4845372500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849510000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9768.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28784.98 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28518.63 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s @@ -291,37 +291,42 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing -system.physmem.readRowHits 139924 # Number of row buffer hits during reads -system.physmem.writeRowHits 126136 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.18 # Row buffer hit rate for writes -system.physmem.avgGap 8519147.54 # Average gap between requests -system.physmem.pageHitRate 80.87 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2713515031250 # Time in different power states -system.physmem.memoryStateTime::REF 95262700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 44072132750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 246765960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 228697560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134644125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 124785375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 691906800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 631511400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 524685600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 507468240 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 186333841200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 186333841200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 83199782385 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 82045768365 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1638723732000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1639736025000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1909855358070 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1909608097140 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.456797 # Core power per rank (mW) -system.physmem.averagePower::1 669.370126 # Core power per rank (mW) +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.33 # Average write queue length when enqueuing +system.physmem.readRowHits 140084 # Number of row buffer hits during reads +system.physmem.writeRowHits 125841 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes +system.physmem.avgGap 8515254.26 # Average gap between requests +system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 246909600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134722500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 691555800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 522696240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83503223595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638462219000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909895676495 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.469106 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725585905000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32002250000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 229083120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124995750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 633664200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 507533040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82044200295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639742072250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909615898415 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.371033 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727729306000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29860939000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory @@ -340,16 +345,24 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31051775 # Number of BP lookups -system.cpu.branchPred.condPredicted 16857996 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2519060 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18534749 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13337392 # Number of BTB hits +system.cpu.branchPred.lookups 31058702 # Number of BP lookups +system.cpu.branchPred.condPredicted 16880390 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2530392 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18557624 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13376459 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.958849 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7856975 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1512712 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.080666 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7810096 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1523796 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -371,27 +384,65 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 66845 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66845 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43967 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22878 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66845 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66845 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66845 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7791 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10107.303299 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7513.505454 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7923.201613 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7786 99.94% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7791 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 234495500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 234495500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 234495500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6429 82.52% 82.52% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1362 17.48% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7791 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66845 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66845 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7791 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7791 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74636 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24746159 # DTB read hits -system.cpu.dtb.read_misses 60199 # DTB read misses -system.cpu.dtb.write_hits 19443156 # DTB write hits -system.cpu.dtb.write_misses 6950 # DTB write misses +system.cpu.dtb.read_hits 24793006 # DTB read hits +system.cpu.dtb.read_misses 59858 # DTB read misses +system.cpu.dtb.write_hits 19468400 # DTB write hits +system.cpu.dtb.write_misses 6987 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4352 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1783 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 751 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24806358 # DTB read accesses -system.cpu.dtb.write_accesses 19450106 # DTB write accesses +system.cpu.dtb.perms_faults 757 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24852864 # DTB read accesses +system.cpu.dtb.write_accesses 19475387 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44189315 # DTB hits -system.cpu.dtb.misses 67149 # DTB misses -system.cpu.dtb.accesses 44256464 # DTB accesses +system.cpu.dtb.hits 44261406 # DTB hits +system.cpu.dtb.misses 66845 # DTB misses +system.cpu.dtb.accesses 44328251 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -413,8 +464,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 57672689 # ITB inst hits -system.cpu.itb.inst_misses 5411 # ITB inst misses +system.cpu.itb.walker.walks 5440 # Table walker walks requested +system.cpu.itb.walker.walksShort 5440 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 316 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5124 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5440 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5440 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5440 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3188 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10236.198243 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7641.069075 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7067.497935 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1310 41.09% 41.09% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1157 36.29% 77.38% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 720 22.58% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3188 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 234126500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 234126500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 234126500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2879 90.31% 90.31% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.69% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3188 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5440 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5440 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3188 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3188 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8628 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57692911 # ITB inst hits +system.cpu.itb.inst_misses 5440 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -423,119 +503,119 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2970 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2976 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8383 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57678100 # ITB inst accesses -system.cpu.itb.hits 57672689 # DTB hits -system.cpu.itb.misses 5411 # DTB misses -system.cpu.itb.accesses 57678100 # DTB accesses -system.cpu.numCycles 314966932 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57698351 # ITB inst accesses +system.cpu.itb.hits 57692911 # DTB hits +system.cpu.itb.misses 5440 # DTB misses +system.cpu.itb.accesses 57698351 # DTB accesses +system.cpu.numCycles 314937774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112002684 # Number of instructions committed -system.cpu.committedOps 135423332 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7762811 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3036 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390780993 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.812137 # CPI: cycles per instruction -system.cpu.ipc 0.355601 # IPC: instructions per cycle +system.cpu.committedInsts 112207125 # Number of instructions committed +system.cpu.committedOps 135672670 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7783589 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5390825701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.806754 # CPI: cycles per instruction +system.cpu.ipc 0.356283 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3036 # number of quiesce instructions executed -system.cpu.tickCycles 228185661 # Number of cycles that the object actually ticked -system.cpu.idleCycles 86781271 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 843230 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.953176 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42691062 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 843742 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.597294 # Average number of references to valid blocks. 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overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21572.997924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -615,58 +695,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 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ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11499.062297 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11499.062297 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11499.062297 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11499.062297 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050285 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050285 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050285 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11500.373956 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11500.373956 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 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access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -853,92 +933,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88299 # number of writebacks -system.cpu.l2cache.writebacks::total 88299 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 156 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 156 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 156 # number of demand (read+write) MSHR hits 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cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9828833572 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9836898572 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545306500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545306500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4107046000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107046000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652352500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652352500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010758 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010560 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.982612 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982612 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9796383317 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9805087067 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545301250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545301250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4107025000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107025000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652326250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652326250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010806 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010611 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.981285 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981285 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.443071 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443071 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044077 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044077 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.443005 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443005 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044136 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044993 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044136 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61532.254585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61543.946887 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10066.727700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10066.727700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 61000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 61000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57558.304584 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57558.304584 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61636.248926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10068.290392 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57182.821397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58434.353561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58439.219923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58167.770978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58434.353561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58439.219923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58167.770978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -946,54 +1026,54 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3581708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3581608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3581627 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 699279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 698310 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2832 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2510082 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14997 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8490744 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185730048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98946845 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 286516 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284981381 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 60946 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4581834 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.007957 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088847 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296087 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5807240 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506645 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160889 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8489768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185830784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98804957 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284938125 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61311 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4581044 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.007958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088854 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4545376 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 4544586 99.20% 99.20% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4581834 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3016682672 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4581044 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3015323412 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4358543218 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4360848041 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1342977701 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1341145704 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10504000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10564000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89938750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89727250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution @@ -1090,23 +1170,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347024164 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347055145 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804504 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.033420 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.033413 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270180945000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.033420 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064589 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064589 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270192614000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.033413 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064588 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064588 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1122,8 +1202,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9603131283 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9603131283 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9592588263 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9592588263 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles @@ -1146,17 +1226,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265104.110065 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265104.110065 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264813.059381 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264813.059381 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56022 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55542 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7210 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7161 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.770042 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.756179 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1172,8 +1252,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7719475291 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7719475291 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7708930273 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7708930273 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles @@ -1188,64 +1268,64 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213103.889438 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213103.889438 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212812.783597 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212812.783597 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71576 # Transaction distribution -system.membus.trans_dist::ReadResp 71576 # Transaction distribution +system.membus.trans_dist::ReadReq 71749 # Transaction distribution +system.membus.trans_dist::ReadResp 71749 # Transaction distribution system.membus.trans_dist::WriteReq 27607 # Transaction distribution system.membus.trans_dist::WriteResp 27607 # Transaction distribution -system.membus.trans_dist::Writeback 124489 # Transaction distribution +system.membus.trans_dist::Writeback 124418 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4592 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4594 # Transaction distribution -system.membus.trans_dist::ReadExReq 129300 # Transaction distribution -system.membus.trans_dist::ReadExResp 129300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution +system.membus.trans_dist::ReadExReq 129351 # Transaction distribution +system.membus.trans_dist::ReadExResp 129351 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446065 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446451 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554083 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662584 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 662970 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16500440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16664221 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16510296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16674077 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21299677 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 507 # Total snoops (count) -system.membus.snoop_fanout::samples 332045 # Request fanout histogram +system.membus.pkt_size::total 21309533 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 506 # Total snoops (count) +system.membus.snoop_fanout::samples 332202 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332045 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332202 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332045 # Request fanout histogram -system.membus.reqLayer0.occupancy 87455500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332202 # Request fanout histogram +system.membus.reqLayer0.occupancy 87413000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1699000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1675329000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1674431500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1688631909 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1690391904 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38334496 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index d32247ca8..c276b537b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827042 # Number of seconds simulated -sim_ticks 2827042159500 # Number of ticks simulated -final_tick 2827042159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827025 # Number of seconds simulated +sim_ticks 2827025397500 # Number of ticks simulated +final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73670 # Simulator instruction rate (inst/s) -host_op_rate 89358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1840258315 # Simulator tick rate (ticks/s) -host_mem_usage 564112 # Number of bytes of host memory used -host_seconds 1536.22 # Real time elapsed on the host -sim_insts 113173742 # Number of instructions simulated -sim_ops 137273263 # Number of ops (including micro ops) simulated +host_inst_rate 71679 # Simulator instruction rate (inst/s) +host_op_rate 86943 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1789973688 # Simulator tick rate (ticks/s) +host_mem_usage 620632 # Number of bytes of host memory used +host_seconds 1579.37 # Real time elapsed on the host +sim_insts 113206948 # Number of instructions simulated +sim_ops 137314363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9496932 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10823604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8116352 # Number of bytes written to this memory +system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8133876 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171883 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126818 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131199 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3359317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3828597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2870970 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2877168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2870970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3365516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6705765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171884 # Number of read requests accepted -system.physmem.writeReqs 167423 # Number of write requests accepted -system.physmem.readBursts 171884 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167423 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10992576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.physmem.bytesWritten 10315392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10823668 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10452212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6228 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4543 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10965 # Per bank write bursts -system.physmem.perBankRdBursts::1 10116 # Per bank write bursts -system.physmem.perBankRdBursts::2 11197 # Per bank write bursts -system.physmem.perBankRdBursts::3 11389 # Per bank write bursts -system.physmem.perBankRdBursts::4 13120 # Per bank write bursts -system.physmem.perBankRdBursts::5 10535 # Per bank write bursts -system.physmem.perBankRdBursts::6 11120 # Per bank write bursts -system.physmem.perBankRdBursts::7 11540 # Per bank write bursts -system.physmem.perBankRdBursts::8 10348 # Per bank write bursts -system.physmem.perBankRdBursts::9 11053 # Per bank write bursts -system.physmem.perBankRdBursts::10 10478 # Per bank write bursts -system.physmem.perBankRdBursts::11 9244 # Per bank write bursts -system.physmem.perBankRdBursts::12 10124 # Per bank write bursts -system.physmem.perBankRdBursts::13 10758 # Per bank write bursts -system.physmem.perBankRdBursts::14 10029 # Per bank write bursts -system.physmem.perBankRdBursts::15 9743 # Per bank write bursts -system.physmem.perBankWrBursts::0 10407 # Per bank write bursts -system.physmem.perBankWrBursts::1 9909 # Per bank write bursts -system.physmem.perBankWrBursts::2 10642 # Per bank write bursts -system.physmem.perBankWrBursts::3 10446 # Per bank write bursts -system.physmem.perBankWrBursts::4 9703 # Per bank write bursts -system.physmem.perBankWrBursts::5 10218 # Per bank write bursts -system.physmem.perBankWrBursts::6 10399 # Per bank write bursts -system.physmem.perBankWrBursts::7 10626 # Per bank write bursts -system.physmem.perBankWrBursts::8 10202 # Per bank write bursts -system.physmem.perBankWrBursts::9 10761 # Per bank write bursts -system.physmem.perBankWrBursts::10 9802 # Per bank write bursts -system.physmem.perBankWrBursts::11 9030 # Per bank write bursts -system.physmem.perBankWrBursts::12 9755 # Per bank write bursts -system.physmem.perBankWrBursts::13 10443 # Per bank write bursts -system.physmem.perBankWrBursts::14 9720 # Per bank write bursts -system.physmem.perBankWrBursts::15 9115 # Per bank write bursts +system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171932 # Number of read requests accepted +system.physmem.writeReqs 167449 # Number of write requests accepted +system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11320 # Per bank write bursts +system.physmem.perBankRdBursts::1 10283 # Per bank write bursts +system.physmem.perBankRdBursts::2 11137 # Per bank write bursts +system.physmem.perBankRdBursts::3 11363 # Per bank write bursts +system.physmem.perBankRdBursts::4 13028 # Per bank write bursts +system.physmem.perBankRdBursts::5 10237 # Per bank write bursts +system.physmem.perBankRdBursts::6 10954 # Per bank write bursts +system.physmem.perBankRdBursts::7 11381 # Per bank write bursts +system.physmem.perBankRdBursts::8 10407 # Per bank write bursts +system.physmem.perBankRdBursts::9 11232 # Per bank write bursts +system.physmem.perBankRdBursts::10 10729 # Per bank write bursts +system.physmem.perBankRdBursts::11 9386 # Per bank write bursts +system.physmem.perBankRdBursts::12 9853 # Per bank write bursts +system.physmem.perBankRdBursts::13 10909 # Per bank write bursts +system.physmem.perBankRdBursts::14 9951 # Per bank write bursts +system.physmem.perBankRdBursts::15 9636 # Per bank write bursts +system.physmem.perBankWrBursts::0 10810 # Per bank write bursts +system.physmem.perBankWrBursts::1 10132 # Per bank write bursts +system.physmem.perBankWrBursts::2 10502 # Per bank write bursts +system.physmem.perBankWrBursts::3 10558 # Per bank write bursts +system.physmem.perBankWrBursts::4 9654 # Per bank write bursts +system.physmem.perBankWrBursts::5 9978 # Per bank write bursts +system.physmem.perBankWrBursts::6 10358 # Per bank write bursts +system.physmem.perBankWrBursts::7 10535 # Per bank write bursts +system.physmem.perBankWrBursts::8 10309 # Per bank write bursts +system.physmem.perBankWrBursts::9 10935 # Per bank write bursts +system.physmem.perBankWrBursts::10 10009 # Per bank write bursts +system.physmem.perBankWrBursts::11 9154 # Per bank write bursts +system.physmem.perBankWrBursts::12 9556 # Per bank write bursts +system.physmem.perBankWrBursts::13 10555 # Per bank write bursts +system.physmem.perBankWrBursts::14 9521 # Per bank write bursts +system.physmem.perBankWrBursts::15 9009 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2827041948500 # Total gap between requests +system.physmem.totGap 2827025186500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168336 # Read request sizes (log2) +system.physmem.readPktSize::6 168384 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 163042 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163068 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,137 +159,134 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64399 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.873212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.977516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.816153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23539 36.55% 36.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14785 22.96% 59.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6319 9.81% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3687 5.73% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2636 4.09% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1562 2.43% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1140 1.77% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1107 1.72% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9624 14.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64399 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.206340 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.339482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6812 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6814 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6814 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.653948 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.805353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.459775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5702 83.68% 83.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 39 0.57% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.38% 84.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 231 3.39% 88.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 131 1.92% 89.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 61 0.90% 90.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 35 0.51% 91.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 27 0.40% 91.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 123 1.81% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.19% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 19 0.28% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.16% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 31 0.45% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 13 0.19% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 13 0.19% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.38% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 61 0.90% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 10 0.15% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 9 0.13% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 11 0.16% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 89 1.31% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 18 0.26% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 5 0.07% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.38% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.06% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.16% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 11 0.16% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6814 # Writes before turning the bus around for reads -system.physmem.totQLat 2084525750 # Total ticks spent queuing -system.physmem.totMemAccLat 5305007000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 858795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12136.34 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads +system.physmem.totQLat 2011805750 # Total ticks spent queuing +system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30886.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -297,36 +294,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.50 # Average write queue length when enqueuing -system.physmem.readRowHits 141721 # Number of row buffer hits during reads -system.physmem.writeRowHits 126816 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.67 # Row buffer hit rate for writes -system.physmem.avgGap 8331811.45 # Average gap between requests -system.physmem.pageHitRate 80.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694668588500 # Time in different power states -system.physmem.memoryStateTime::REF 94401060000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37972497000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 254499840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 232356600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 138864000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 126781875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 701859600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 637852800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 533628000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 510805440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184648473360 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184648473360 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80377758270 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79142156730 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625717004000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626800865000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892372087070 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1892099291805 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.382923 # Core power per rank (mW) -system.physmem.averagePower::1 669.286428 # Core power per rank (mW) +system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing +system.physmem.readRowHits 141825 # Number of row buffer hits during reads +system.physmem.writeRowHits 127038 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes +system.physmem.avgGap 8329945.36 # Average gap between requests +system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.379373 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states +system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.289511 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states +system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory @@ -345,16 +347,24 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46933448 # Number of BP lookups -system.cpu.branchPred.condPredicted 24039449 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232882 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29542848 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21360620 # Number of BTB hits +system.cpu.branchPred.lookups 46965884 # Number of BP lookups +system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.303862 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754095 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33720 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -376,27 +386,53 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 9687 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9687 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9687 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9687 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9687 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 207947000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 207947000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 207947000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 6190 82.28% 82.28% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1333 17.72% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7523 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9687 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9687 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7523 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7523 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17210 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24594187 # DTB read hits -system.cpu.checker.dtb.read_misses 8246 # DTB read misses -system.cpu.checker.dtb.write_hits 19641862 # DTB write hits -system.cpu.checker.dtb.write_misses 1441 # DTB write misses +system.cpu.checker.dtb.read_hits 24601959 # DTB read hits +system.cpu.checker.dtb.read_misses 8249 # DTB read misses +system.cpu.checker.dtb.write_hits 19645805 # DTB write hits +system.cpu.checker.dtb.write_misses 1438 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4296 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 4297 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24602433 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19643303 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24610208 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19647243 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44236049 # DTB hits +system.cpu.checker.dtb.hits 44247764 # DTB hits system.cpu.checker.dtb.misses 9687 # DTB misses -system.cpu.checker.dtb.accesses 44245736 # DTB accesses +system.cpu.checker.dtb.accesses 44257451 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -418,7 +454,25 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 115876249 # ITB inst hits +system.cpu.checker.itb.walker.walks 4826 # Table walker walks requested +system.cpu.checker.itb.walker.walksShort 4826 # Table walker walks initiated with short descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples 207571000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 207571000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 207571000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4826 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4826 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 115911347 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -435,13 +489,21 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115881075 # ITB inst accesses -system.cpu.checker.itb.hits 115876249 # DTB hits +system.cpu.checker.itb.inst_accesses 115916173 # ITB inst accesses +system.cpu.checker.itb.hits 115911347 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115881075 # DTB accesses -system.cpu.checker.numCycles 139127814 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115916173 # DTB accesses +system.cpu.checker.numCycles 139170806 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -463,27 +525,89 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 69937 # Table walker walks requested +system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25465003 # DTB read hits -system.cpu.dtb.read_misses 60438 # DTB read misses -system.cpu.dtb.write_hits 19916425 # DTB write hits -system.cpu.dtb.write_misses 9382 # DTB write misses +system.cpu.dtb.read_hits 25472400 # DTB read hits +system.cpu.dtb.read_misses 60528 # DTB read misses +system.cpu.dtb.write_hits 19920178 # DTB write hits +system.cpu.dtb.write_misses 9409 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 344 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2309 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25525441 # DTB read accesses -system.cpu.dtb.write_accesses 19925807 # DTB write accesses +system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25532928 # DTB read accesses +system.cpu.dtb.write_accesses 19929587 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45381428 # DTB hits -system.cpu.dtb.misses 69820 # DTB misses -system.cpu.dtb.accesses 45451248 # DTB accesses +system.cpu.dtb.hits 45392578 # DTB hits +system.cpu.dtb.misses 69937 # DTB misses +system.cpu.dtb.accesses 45462515 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -505,8 +629,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66294026 # ITB inst hits -system.cpu.itb.inst_misses 11939 # ITB inst misses +system.cpu.itb.walker.walks 11957 # Table walker walks requested +system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66242388 # ITB inst hits +system.cpu.itb.inst_misses 11957 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -522,91 +693,91 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66305965 # ITB inst accesses -system.cpu.itb.hits 66294026 # DTB hits -system.cpu.itb.misses 11939 # DTB misses -system.cpu.itb.accesses 66305965 # DTB accesses -system.cpu.numCycles 260580731 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66254345 # ITB inst accesses +system.cpu.itb.hits 66242388 # DTB hits +system.cpu.itb.misses 11957 # DTB misses +system.cpu.itb.accesses 66254345 # DTB accesses +system.cpu.numCycles 260505842 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104873538 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184739295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46933448 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33114715 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145635789 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6158762 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 168952 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8750 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338958 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 503648 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66294321 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1128854 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4994 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254609122 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155317216 61.00% 61.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29235163 11.48% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14076452 5.53% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55980291 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254609122 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180111 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78085586 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105431733 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64660886 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829260 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2601657 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422216 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485978 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157447803 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691485 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2601657 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83925210 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10033565 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74541150 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62655394 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20852146 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146807646 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950357 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437123 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62766 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16447 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18089237 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150492315 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678770164 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164434086 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141835122 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8657190 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2845976 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2649716 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13845319 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26411369 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21300781 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686386 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2189128 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143541895 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120957 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143337283 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269192 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6251828 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14653372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125306 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254609122 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.562970 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882443 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166344309 65.33% 65.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45117660 17.72% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32035421 12.58% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10298180 4.04% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813519 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -614,9 +785,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254609122 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7370311 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -645,13 +816,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632420 24.93% 57.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9586874 42.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96009315 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113982 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -679,96 +850,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26194290 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21008765 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143337283 # Type of FU issued -system.cpu.iq.rate 0.550069 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22589637 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157598 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564106761 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151919680 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140223084 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35756 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued +system.cpu.iq.rate 0.550386 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165901147 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23436 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324147 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1490308 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18251 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701176 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88081 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6304 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2601657 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 950737 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 291154 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145863821 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26411369 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21300781 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096076 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17895 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 256263 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18251 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317548 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471732 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789280 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142394540 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25793108 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 873030 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200969 # number of nop insts executed -system.cpu.iew.exec_refs 46672402 # number of memory reference insts executed -system.cpu.iew.exec_branches 26533167 # Number of branches executed -system.cpu.iew.exec_stores 20879294 # Number of stores executed -system.cpu.iew.exec_rate 0.546451 # Inst execution rate -system.cpu.iew.wb_sent 142007306 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140234515 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63283849 # num instructions producing a value -system.cpu.iew.wb_consumers 95860591 # num instructions consuming a value +system.cpu.iew.exec_nop 200965 # number of nop insts executed +system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed +system.cpu.iew.exec_branches 26544582 # Number of branches executed +system.cpu.iew.exec_stores 20883032 # Number of stores executed +system.cpu.iew.exec_rate 0.546767 # Inst execution rate +system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63301991 # num instructions producing a value +system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538161 # insts written-back per cycle +system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591533 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995651 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755158 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251674404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546055 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.146686 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178222235 70.81% 70.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43294364 17.20% 88.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15476639 6.15% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357303 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6369018 2.53% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1679088 0.67% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777340 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414271 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1084146 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251674404 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113328647 # Number of instructions committed -system.cpu.commit.committedOps 137428168 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113361853 # Number of instructions committed +system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45520666 # Number of memory references committed -system.cpu.commit.loads 24921061 # Number of loads committed -system.cpu.commit.membars 814701 # Number of memory barriers committed -system.cpu.commit.branches 26049415 # Number of branches committed +system.cpu.commit.refs 45532382 # Number of memory references committed +system.cpu.commit.loads 24928817 # Number of loads committed +system.cpu.commit.membars 814713 # Number of memory barriers committed +system.cpu.commit.branches 26060941 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120247607 # Number of committed integer instructions. -system.cpu.commit.function_calls 4892692 # Number of function calls committed. +system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. +system.cpu.commit.function_calls 4896517 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91785919 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction @@ -797,210 +968,210 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24921061 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20599605 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137428168 # Class of committed instruction -system.cpu.commit.bw_lim_events 1084146 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction +system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373381031 # The number of ROB reads -system.cpu.rob.rob_writes 292971684 # The number of ROB writes -system.cpu.timesIdled 892930 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5971609 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393503589 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113173742 # Number of Instructions Simulated -system.cpu.committedOps 137273263 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.302484 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302484 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155831391 # number of integer regfile reads -system.cpu.int_regfile_writes 88636025 # number of integer regfile writes +system.cpu.rob.rob_reads 373323554 # The number of ROB reads +system.cpu.rob.rob_writes 293054802 # The number of ROB writes +system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113206948 # Number of Instructions Simulated +system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155872747 # number of integer regfile reads +system.cpu.int_regfile_writes 88664447 # number of integer regfile writes system.cpu.fp_regfile_reads 9607 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503020698 # number of cc regfile reads -system.cpu.cc_regfile_writes 53185327 # number of cc regfile writes -system.cpu.misc_regfile_reads 444130548 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521619 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837995 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958491 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40159583 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838507 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.894154 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 503168369 # number of cc regfile reads +system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes +system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes +system.cpu.dcache.tags.replacements 837844 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958491 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179379502 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179379502 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23322864 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23322864 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15584894 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15584894 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346636 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346636 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 442009 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 442009 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460310 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460310 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38907758 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38907758 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39254394 # number of overall hits -system.cpu.dcache.overall_hits::total 39254394 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700618 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700618 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3574058 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3574058 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177109 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177109 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26740 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26740 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4274676 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4274676 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4451785 # number of overall misses -system.cpu.dcache.overall_misses::total 4451785 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9939142148 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9939142148 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 135148977049 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356483749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 356483749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 189500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 189500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145088119197 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145088119197 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145088119197 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145088119197 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24023482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24023482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19158952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19158952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523745 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523745 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468749 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468749 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460315 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460315 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43182434 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43182434 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43706179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43706179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029164 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029164 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186548 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186548 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338159 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338159 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.098991 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.098991 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 37900 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 37900 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33941.313727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32590.998711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 505021 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits +system.cpu.dcache.overall_hits::total 39264228 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177079 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177079 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26763 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26763 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 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+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029155 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029155 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186604 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186604 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338096 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338096 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057096 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057096 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.916691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.370238 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695574 # number of writebacks -system.cpu.dcache.writebacks::total 695574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286297 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286297 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274736 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3274736 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18417 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3561033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3561033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3561033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3561033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414321 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414321 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299322 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299322 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119334 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119334 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8323 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8323 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713643 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713643 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832977 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832977 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5358688665 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5358688665 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11888843709 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11888843709 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1476460251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1476460251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110246000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110246000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 179500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 179500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17247532374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17247532374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18723992625 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18723992625 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792718250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792718250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233175703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233175703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017247 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017247 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017756 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017756 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019059 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019059 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 35900 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 35900 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 695426 # number of writebacks +system.cpu.dcache.writebacks::total 695426 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286545 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286545 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3276416 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3276416 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18452 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18452 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3562961 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3562961 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3562961 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3562961 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414078 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414078 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299459 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299459 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119308 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119308 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8311 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8311 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713537 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713537 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832845 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832845 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5351526415 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5351526415 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11825722463 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11825722463 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1475435001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1475435001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109426500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109426500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17177248878 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17177248878 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18652683879 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019050 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42125 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1008,265 +1179,265 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1894210 # number of replacements -system.cpu.icache.tags.tagsinuse 511.373832 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64309690 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894722 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.941491 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1894041 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373863 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64258114 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894553 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.917296 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.373832 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373863 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id 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MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1251787750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9128456559 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10381932809 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157877000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387474750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545351750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107339500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107339500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494814250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652691250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000352 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000598 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024922 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013377 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987004 # mshr miss rate for UpgradeReq accesses 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0.000372 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013376 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988468 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988468 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461519 # mshr miss rate for ReadExReq accesses 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overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060908 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62718.026171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64612.832850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10097.791834 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1387,31 +1558,31 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2565344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2565278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296684 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495832 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128794 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6451318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121309456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98375777 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219947773 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65392 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3562462 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.010230 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100625 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65703 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.010231 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram @@ -1422,23 +1593,23 @@ system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 3526018 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 3525674 98.98% 98.98% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::10 36444 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3562462 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503396529 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849706150 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334755109 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19527240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74897454 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution @@ -1535,23 +1706,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347066130 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776516 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.000725 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251942535000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000725 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062545 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062545 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1565,14 +1736,14 @@ system.iocache.demand_misses::realview.ide 220 # system.iocache.demand_misses::total 220 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 220 # number of overall misses system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26411377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26411377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9622478237 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9622478237 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26411377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26411377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26411377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26411377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1589,19 +1760,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120051.713636 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120051.713636 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120051.713636 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56749 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7275 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.800550 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1615,14 +1786,14 @@ system.iocache.demand_mshr_misses::realview.ide 220 system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14970377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14970377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7738798269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7738798269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14970377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14970377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14970377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14970377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1631,66 +1802,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67832 # Transaction distribution -system.membus.trans_dist::ReadResp 67831 # Transaction distribution +system.membus.trans_dist::ReadReq 67820 # Transaction distribution +system.membus.trans_dist::ReadResp 67819 # Transaction distribution system.membus.trans_dist::WriteReq 27608 # Transaction distribution system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 126818 # Transaction distribution +system.membus.trans_dist::Writeback 126844 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135125 # Transaction distribution -system.membus.trans_dist::ReadExResp 135125 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution +system.membus.trans_dist::ReadExReq 135185 # Transaction distribution +system.membus.trans_dist::ReadExResp 135185 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452492 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 669001 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16640360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16803825 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21439281 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 484 # Total snoops (count) -system.membus.snoop_fanout::samples 336405 # Request fanout histogram +system.membus.snoop_fanout::samples 336478 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 336405 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 336405 # Request fanout histogram -system.membus.reqLayer0.occupancy 94190000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 336478 # Request fanout histogram +system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1683660499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1677935457 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38220484 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 8bea05f5e..f860bb1f1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,165 +1,165 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824570 # Number of seconds simulated -sim_ticks 2824570221000 # Number of ticks simulated -final_tick 2824570221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.825254 # Number of seconds simulated +sim_ticks 2825254262000 # Number of ticks simulated +final_tick 2825254262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42227 # Simulator instruction rate (inst/s) -host_op_rate 51230 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 992732164 # Simulator tick rate (ticks/s) -host_mem_usage 776620 # Number of bytes of host memory used -host_seconds 2845.25 # Real time elapsed on the host -sim_insts 120145307 # Number of instructions simulated -sim_ops 145762315 # Number of ops (including micro ops) simulated +host_inst_rate 94727 # Simulator instruction rate (inst/s) +host_op_rate 114921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2228089891 # Simulator tick rate (ticks/s) +host_mem_usage 647304 # Number of bytes of host memory used +host_seconds 1268.02 # Real time elapsed on the host +sim_insts 120114928 # Number of instructions simulated +sim_ops 145721614 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 286752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1037180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10498560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1295328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1287356 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8203456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 549024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1342912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 192592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 613216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 685312 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 13750604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 286752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 318704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9574272 # Number of bytes written to this memory +system.physmem.bytes_read::total 12280396 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1295328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 192592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1487920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8689216 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9592016 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6726 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 16731 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 164040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8706960 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22485 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20640 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 128179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8602 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 20983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3076 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 10708 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217714 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149598 # Number of write requests responded to by this memory +system.physmem.num_reads::total 194742 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135769 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 154034 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 101521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 367199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3716870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 140205 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 458482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 455660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2903617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 194374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 475439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 68168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 217048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 242566 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4868211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 101521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 112833 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3389639 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4346652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 458482 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 68168 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 526650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3075552 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6266 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3395921 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3389639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 101521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 373467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3716870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3081832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3075552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 458482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 461927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2903617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 194389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 475439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 68168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 217062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 242566 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8264132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 217714 # Number of read requests accepted -system.physmem.writeReqs 190258 # Number of write requests accepted -system.physmem.readBursts 217714 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 190258 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13924352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 11782272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13750604 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11910352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6131 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13778 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13720 # Per bank write bursts -system.physmem.perBankRdBursts::1 13621 # Per bank write bursts -system.physmem.perBankRdBursts::2 14360 # Per bank write bursts -system.physmem.perBankRdBursts::3 14230 # Per bank write bursts -system.physmem.perBankRdBursts::4 15917 # Per bank write bursts -system.physmem.perBankRdBursts::5 12969 # Per bank write bursts -system.physmem.perBankRdBursts::6 13917 # Per bank write bursts -system.physmem.perBankRdBursts::7 13922 # Per bank write bursts -system.physmem.perBankRdBursts::8 13602 # Per bank write bursts -system.physmem.perBankRdBursts::9 13356 # Per bank write bursts -system.physmem.perBankRdBursts::10 12792 # Per bank write bursts -system.physmem.perBankRdBursts::11 11688 # Per bank write bursts -system.physmem.perBankRdBursts::12 13275 # Per bank write bursts -system.physmem.perBankRdBursts::13 14168 # Per bank write bursts -system.physmem.perBankRdBursts::14 13342 # Per bank write bursts -system.physmem.perBankRdBursts::15 12689 # Per bank write bursts -system.physmem.perBankWrBursts::0 11837 # Per bank write bursts -system.physmem.perBankWrBursts::1 11937 # Per bank write bursts -system.physmem.perBankWrBursts::2 12245 # Per bank write bursts -system.physmem.perBankWrBursts::3 12130 # Per bank write bursts -system.physmem.perBankWrBursts::4 11220 # Per bank write bursts -system.physmem.perBankWrBursts::5 11075 # Per bank write bursts -system.physmem.perBankWrBursts::6 11642 # Per bank write bursts -system.physmem.perBankWrBursts::7 11554 # Per bank write bursts -system.physmem.perBankWrBursts::8 11490 # Per bank write bursts -system.physmem.perBankWrBursts::9 11375 # Per bank write bursts -system.physmem.perBankWrBursts::10 11404 # Per bank write bursts -system.physmem.perBankWrBursts::11 11050 # Per bank write bursts -system.physmem.perBankWrBursts::12 11716 # Per bank write bursts -system.physmem.perBankWrBursts::13 11527 # Per bank write bursts -system.physmem.perBankWrBursts::14 11100 # Per bank write bursts -system.physmem.perBankWrBursts::15 10796 # Per bank write bursts +system.physmem.bw_total::total 7428484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 194742 # Number of read requests accepted +system.physmem.writeReqs 176429 # Number of write requests accepted +system.physmem.readBursts 194742 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 176429 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12454272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesWritten 10909824 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12280396 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11025296 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5937 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13544 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12112 # Per bank write bursts +system.physmem.perBankRdBursts::1 11748 # Per bank write bursts +system.physmem.perBankRdBursts::2 12331 # Per bank write bursts +system.physmem.perBankRdBursts::3 12396 # Per bank write bursts +system.physmem.perBankRdBursts::4 14329 # Per bank write bursts +system.physmem.perBankRdBursts::5 12174 # Per bank write bursts +system.physmem.perBankRdBursts::6 12464 # Per bank write bursts +system.physmem.perBankRdBursts::7 12653 # Per bank write bursts +system.physmem.perBankRdBursts::8 12280 # Per bank write bursts +system.physmem.perBankRdBursts::9 12648 # Per bank write bursts +system.physmem.perBankRdBursts::10 12320 # Per bank write bursts +system.physmem.perBankRdBursts::11 11195 # Per bank write bursts +system.physmem.perBankRdBursts::12 11560 # Per bank write bursts +system.physmem.perBankRdBursts::13 11958 # Per bank write bursts +system.physmem.perBankRdBursts::14 11562 # Per bank write bursts +system.physmem.perBankRdBursts::15 10868 # Per bank write bursts +system.physmem.perBankWrBursts::0 10717 # Per bank write bursts +system.physmem.perBankWrBursts::1 10772 # Per bank write bursts +system.physmem.perBankWrBursts::2 11107 # Per bank write bursts +system.physmem.perBankWrBursts::3 11182 # Per bank write bursts +system.physmem.perBankWrBursts::4 10467 # Per bank write bursts +system.physmem.perBankWrBursts::5 10805 # Per bank write bursts +system.physmem.perBankWrBursts::6 10968 # Per bank write bursts +system.physmem.perBankWrBursts::7 10867 # Per bank write bursts +system.physmem.perBankWrBursts::8 10652 # Per bank write bursts +system.physmem.perBankWrBursts::9 11077 # Per bank write bursts +system.physmem.perBankWrBursts::10 11118 # Per bank write bursts +system.physmem.perBankWrBursts::11 10634 # Per bank write bursts +system.physmem.perBankWrBursts::12 10720 # Per bank write bursts +system.physmem.perBankWrBursts::13 10162 # Per bank write bursts +system.physmem.perBankWrBursts::14 9784 # Per bank write bursts +system.physmem.perBankWrBursts::15 9434 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2824568625000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2825253981000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3083 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 214044 # Read request sizes (log2) +system.physmem.readPktSize::6 191072 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 185822 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 53286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 171993 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4663 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -188,172 +188,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 13286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 12445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 9379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 351 # What write queue length does an incoming req see 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# What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.047419 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.647814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.885603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47290 49.68% 49.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18811 19.76% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6810 7.15% 76.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3608 3.79% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3189 3.35% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2125 2.23% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1286 1.35% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1091 1.15% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10983 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95193 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7956 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.345777 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 514.192665 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7955 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7956 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7956 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.139517 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.869319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.452539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6216 78.13% 78.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 561 7.05% 85.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 92 1.16% 86.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 246 3.09% 89.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 152 1.91% 91.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 55 0.69% 92.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 34 0.43% 92.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.47% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 126 1.58% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.23% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 19 0.24% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.11% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 35 0.44% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 15 0.19% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.11% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.44% 96.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 47 0.59% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.14% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 5 0.06% 97.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.11% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.11% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 8 0.10% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 17 0.21% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 6 0.08% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 8 0.10% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 29 0.36% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 10 0.13% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.05% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.09% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 7 0.09% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 5 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7956 # Writes before turning the bus around for reads -system.physmem.totQLat 8935367250 # Total ticks spent queuing -system.physmem.totMemAccLat 13014767250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1087840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 41069.31 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 261.529865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.433799 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.548299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46507 52.06% 52.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17145 19.19% 71.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5910 6.62% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3229 3.61% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2663 2.98% 84.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1401 1.57% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 977 1.09% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1056 1.18% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10448 11.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89336 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7194 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.049903 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 528.366464 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7192 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7194 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7194 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.695580 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.063476 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.872294 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 6078 84.49% 84.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 276 3.84% 88.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 196 2.72% 91.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 78 1.08% 92.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 140 1.95% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 36 0.50% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 37 0.51% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 44 0.61% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 68 0.95% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 17 0.24% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 97 1.35% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.19% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 17 0.24% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 12 0.17% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 42 0.58% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 10 0.14% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.04% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 8 0.11% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.06% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.01% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-343 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7194 # Writes before turning the bus around for reads +system.physmem.totQLat 6681295250 # Total ticks spent queuing +system.physmem.totMemAccLat 10330007750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 972990000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34333.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 59819.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.93 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.22 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53083.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.29 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing -system.physmem.readRowHits 184937 # Number of row buffer hits during reads -system.physmem.writeRowHits 121536 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.01 # Row buffer hit rate for writes -system.physmem.avgGap 6923437.45 # Average gap between requests -system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2697464747500 # Time in different power states -system.physmem.memoryStateTime::REF 94318380000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32780541250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 374477040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 345182040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 204327750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 188343375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 878716800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 818313600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 606787200 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 586167840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184486751280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184486751280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 79037968995 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 78368155155 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625406641250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1625994197250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1890995670315 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1890787110540 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.482406 # Core power per rank (mW) -system.physmem.averagePower::1 669.408568 # Core power per rank (mW) +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing +system.physmem.readRowHits 162654 # Number of row buffer hits during reads +system.physmem.writeRowHits 113073 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.32 # Row buffer hit rate for writes +system.physmem.avgGap 7611731.47 # Average gap between requests +system.physmem.pageHitRate 75.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 347571000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 189646875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 781614600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 563014800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79272493785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625612031750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1891297877370 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.427007 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704246406250 # Time in different power states +system.physmem_0.memoryStateTime::REF 94341260000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26661192500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 327809160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178864125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 736242000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 541604880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 78684430770 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626127876500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1891128331995 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.366996 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705112983500 # Time in different power states +system.physmem_1.memoryStateTime::REF 94341260000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 25799982000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory @@ -378,16 +367,24 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 24032454 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15719473 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 977282 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14661590 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10774814 # Number of BTB hits +system.cpu0.branchPred.lookups 23750953 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15527618 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 965372 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14472059 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10661692 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.490078 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3879582 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32449 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.670872 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3843618 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32002 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -409,27 +406,95 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 61986 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 61986 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26264 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18370 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 17352 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 336.413945 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2220.174334 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43963 98.50% 98.50% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 507 1.14% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 73 0.16% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 64 0.14% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 44634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 13427 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 7972.648842 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 6416.497879 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8239.915942 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 13383 99.67% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 25 0.19% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.07% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 13427 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 89356407948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.591290 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.497127 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 36606156956 40.97% 40.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 52714291992 58.99% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2 18812000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::3 8121500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4 2346000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::5 1919500 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6 1535000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::7 979500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8 384000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::9 515500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10 241000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::11 224500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12 422000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::13 109500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14 86500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::15 262500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 89356407948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4894 78.56% 78.56% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1336 21.44% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6230 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61986 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61986 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6230 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6230 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 68216 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17723797 # DTB read hits -system.cpu0.dtb.read_misses 56461 # DTB read misses -system.cpu0.dtb.write_hits 14648555 # DTB write hits -system.cpu0.dtb.write_misses 8741 # DTB write misses +system.cpu0.dtb.read_hits 17554590 # DTB read hits +system.cpu0.dtb.read_misses 54209 # DTB read misses +system.cpu0.dtb.write_hits 14392399 # DTB write hits +system.cpu0.dtb.write_misses 7777 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3527 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2355 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 317 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2330 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 868 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17780258 # DTB read accesses -system.cpu0.dtb.write_accesses 14657296 # DTB write accesses +system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17608799 # DTB read accesses +system.cpu0.dtb.write_accesses 14400176 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32372352 # DTB hits -system.cpu0.dtb.misses 65202 # DTB misses -system.cpu0.dtb.accesses 32437554 # DTB accesses +system.cpu0.dtb.hits 31946989 # DTB hits +system.cpu0.dtb.misses 61986 # DTB misses +system.cpu0.dtb.accesses 32008975 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -451,8 +516,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 37754755 # ITB inst hits -system.cpu0.itb.inst_misses 10287 # ITB inst misses +system.cpu0.itb.walker.walks 10002 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10002 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3947 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 65 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9937 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 314.380598 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 1718.762352 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-2047 9514 95.74% 95.74% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::2048-4095 89 0.90% 96.64% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-6143 92 0.93% 97.56% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::6144-8191 156 1.57% 99.13% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-10239 23 0.23% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::10240-12287 21 0.21% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-14335 10 0.10% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::14336-16383 9 0.09% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-18431 7 0.07% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::18432-20479 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-22527 2 0.02% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::22528-24575 4 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-26623 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::26624-28671 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9937 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2600 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9117.887308 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 7551.234816 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5655.414847 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1525 58.65% 58.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 976 37.54% 96.19% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 32 1.23% 97.42% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 60 2.31% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2600 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 20627596212 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.981751 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.134001 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 376836000 1.83% 1.83% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 20250383712 98.17% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 360000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 20627596212 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2218 87.50% 87.50% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 317 12.50% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2535 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10002 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10002 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2535 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2535 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 12537 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 37321844 # ITB inst hits +system.cpu0.itb.inst_misses 10002 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -461,500 +580,500 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2369 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2308 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1949 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37765042 # ITB inst accesses -system.cpu0.itb.hits 37754755 # DTB hits -system.cpu0.itb.misses 10287 # DTB misses -system.cpu0.itb.accesses 37765042 # DTB accesses -system.cpu0.numCycles 126967483 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37331846 # ITB inst accesses +system.cpu0.itb.hits 37321844 # DTB hits +system.cpu0.itb.misses 10002 # DTB misses +system.cpu0.itb.accesses 37331846 # DTB accesses +system.cpu0.numCycles 127490392 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18140354 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 112726031 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 24032454 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14654396 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 104803073 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2823208 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 134368 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 38414 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 364228 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 430065 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 37874 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37755386 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 265155 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3922 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 125359980 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.084816 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.263057 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18416586 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 111347815 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 23750953 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14505310 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 103542853 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2791794 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 127823 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 53549 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 359263 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 418714 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 68477 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37322509 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 269100 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3836 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 124383162 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.079346 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.261981 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62797458 50.09% 50.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21463892 17.12% 67.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8767294 6.99% 74.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 32331336 25.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 62596919 50.33% 50.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21226112 17.07% 67.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8654044 6.96% 74.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 31906087 25.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 125359980 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.189280 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.887834 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19213877 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58702572 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 41417912 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4958150 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1067469 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3055480 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 348347 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 110732586 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3998245 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1067469 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24964892 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12028946 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 36555738 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40486723 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10256212 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 105650222 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1060720 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1433198 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 161272 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 61252 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6057790 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 109732658 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 482396625 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 120923658 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 98143798 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11588857 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1229050 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1087734 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12319550 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18736791 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 16202841 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1700720 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2277601 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 102690318 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1694621 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 100676052 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 483863 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9017764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22481770 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 122874 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 125359980 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.803096 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.034807 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 124383162 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.186296 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.873382 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19346102 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58140113 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 40971754 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4869688 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1055505 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3027271 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 344448 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 109400605 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3934770 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1055505 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25005985 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11977086 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 36202111 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40046327 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10096148 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 104386948 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1045357 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1411792 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 159433 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 59086 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5966912 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 108436619 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 476371377 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 119317721 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9226 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 97033193 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11403415 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1211111 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1071444 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12097609 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18549268 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 15931724 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1681801 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2123013 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 101474466 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1673346 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 99505309 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 475979 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8870309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22101778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 120255 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 124383162 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.799990 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.034146 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 69212985 55.21% 55.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 23181797 18.49% 73.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22515986 17.96% 91.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9334603 7.45% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1114571 0.89% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 38 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 68905319 55.40% 55.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 22874220 18.39% 73.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22288669 17.92% 91.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9206102 7.40% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1108815 0.89% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 125359980 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 124383162 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9379077 40.75% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 80 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5582793 24.26% 65.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8054863 35.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9283826 40.69% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 70 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5520798 24.20% 64.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8011764 35.11% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 66413118 65.97% 65.97% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 93141 0.09% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8113 0.01% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18432239 18.31% 84.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15727166 15.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2266 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 65682798 66.01% 66.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 92825 0.09% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8012 0.01% 66.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18253823 18.34% 84.46% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15465584 15.54% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 100676052 # Type of FU issued -system.cpu0.iq.rate 0.792928 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 23016813 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228623 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 350180984 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 113410550 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 98587478 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 31776 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9721 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 123670062 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 20530 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365459 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 99505309 # Type of FU issued +system.cpu0.iq.rate 0.780493 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 22816458 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229299 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 346654844 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 112025701 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 97442801 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 31372 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11049 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9514 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 122299120 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 20381 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 360751 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2006136 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2602 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19208 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1021760 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1973339 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2498 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18704 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1001610 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 106419 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 336961 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 104951 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 329906 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1067469 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1620814 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 189225 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 104559654 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1055505 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1579113 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 185823 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 103314574 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18736791 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 16202841 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876235 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27148 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 138418 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19208 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 291783 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 400552 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 692335 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 99578675 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17975392 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1032310 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18549268 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 15931724 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 862014 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 26297 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 136520 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18704 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 287591 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 395520 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 683111 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 98423737 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17803606 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1019712 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 174715 # number of nop insts executed -system.cpu0.iew.exec_refs 33511345 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16844732 # Number of branches executed -system.cpu0.iew.exec_stores 15535953 # Number of stores executed -system.cpu0.iew.exec_rate 0.784285 # Inst execution rate -system.cpu0.iew.wb_sent 99047596 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 98597199 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 51323656 # num instructions producing a value -system.cpu0.iew.wb_consumers 84802398 # num instructions consuming a value +system.cpu0.iew.exec_nop 166762 # number of nop insts executed +system.cpu0.iew.exec_refs 33081779 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16674739 # Number of branches executed +system.cpu0.iew.exec_stores 15278173 # Number of stores executed +system.cpu0.iew.exec_rate 0.772009 # Inst execution rate +system.cpu0.iew.wb_sent 97898733 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 97452315 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 50771632 # num instructions producing a value +system.cpu0.iew.wb_consumers 83764488 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.776555 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.605215 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.764389 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.606124 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8524425 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1571747 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 633147 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 123606126 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.768066 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.480848 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 8390139 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1553091 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 624980 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 122653513 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.765118 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.477688 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 79269760 64.13% 64.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24721020 20.00% 84.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8248963 6.67% 90.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3214548 2.60% 93.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3440916 2.78% 96.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1523839 1.23% 97.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1135185 0.92% 98.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 534039 0.43% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1517856 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 78804860 64.25% 64.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24438835 19.93% 84.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8183554 6.67% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3164514 2.58% 93.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3412948 2.78% 96.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1509244 1.23% 97.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1121963 0.91% 98.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 525683 0.43% 98.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1491912 1.22% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 123606126 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 78906627 # Number of instructions committed -system.cpu0.commit.committedOps 94937680 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 122653513 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78072085 # Number of instructions committed +system.cpu0.commit.committedOps 93844352 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31911736 # Number of memory references committed -system.cpu0.commit.loads 16730655 # Number of loads committed -system.cpu0.commit.membars 647181 # Number of memory barriers committed -system.cpu0.commit.branches 16206992 # Number of branches committed -system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 81886422 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1929931 # Number of function calls committed. +system.cpu0.commit.refs 31506042 # Number of memory references committed +system.cpu0.commit.loads 16575928 # Number of loads committed +system.cpu0.commit.membars 642248 # Number of memory barriers committed +system.cpu0.commit.branches 16047033 # Number of branches committed +system.cpu0.commit.fp_insts 9500 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 80932371 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1914804 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 62927104 66.28% 66.28% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 90727 0.10% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8113 0.01% 66.39% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16730655 17.62% 84.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 15181081 15.99% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62239958 66.32% 66.32% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 90340 0.10% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8012 0.01% 66.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16575928 17.66% 84.09% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 14930114 15.91% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 94937680 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1517856 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 93844352 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1491912 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 221365586 # The number of ROB reads -system.cpu0.rob.rob_writes 208677314 # The number of ROB writes -system.cpu0.timesIdled 109557 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1607503 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5522172985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 78784576 # Number of Instructions Simulated -system.cpu0.committedOps 94815629 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.611578 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.611578 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.620510 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.620510 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 110621221 # number of integer regfile reads -system.cpu0.int_regfile_writes 59741549 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8143 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 350793071 # number of cc regfile reads -system.cpu0.cc_regfile_writes 41074475 # number of cc regfile writes -system.cpu0.misc_regfile_reads 246484638 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1224545 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 712867 # number of replacements -system.cpu0.dcache.tags.tagsinuse 493.083932 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28844186 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 713379 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.433186 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.083932 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963055 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.963055 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 219244998 # The number of ROB reads +system.cpu0.rob.rob_writes 206197797 # The number of ROB writes +system.cpu0.timesIdled 126478 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3107230 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5523018391 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 77956509 # Number of Instructions Simulated +system.cpu0.committedOps 93728776 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.635404 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.635404 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.611470 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.611470 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 109237443 # number of integer regfile reads +system.cpu0.int_regfile_writes 59093647 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8049 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2136 # number of floating regfile writes +system.cpu0.cc_regfile_reads 346833598 # number of cc regfile reads +system.cpu0.cc_regfile_writes 40564465 # number of cc regfile writes +system.cpu0.misc_regfile_reads 243214174 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1207250 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 702516 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.143728 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28480758 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 703028 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.511556 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 256726000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.143728 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970984 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.970984 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63487140 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63487140 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15590249 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15590249 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12072536 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12072536 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311110 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 311110 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363193 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363193 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360660 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 360660 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27662785 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27662785 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27973895 # number of overall hits -system.cpu0.dcache.overall_hits::total 27973895 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 638253 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 638253 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1832121 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1832121 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146008 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 146008 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25001 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25001 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20609 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20609 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2470374 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2470374 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2616382 # number of overall misses -system.cpu0.dcache.overall_misses::total 2616382 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8112547038 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8112547038 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24972133492 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24972133492 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394969003 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 394969003 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454279790 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 454279790 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 381000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 381000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 33084680530 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 33084680530 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 33084680530 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 33084680530 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16228502 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16228502 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904657 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13904657 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457118 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 457118 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388194 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388194 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381269 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381269 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30133159 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30133159 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30590277 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30590277 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039329 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039329 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131763 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131763 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319410 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319410 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064403 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064403 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054054 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054054 # miss rate for StoreCondReq accesses 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number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 33712125591 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16070881 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16070881 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13657618 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13657618 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 454600 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 454600 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385257 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 385257 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 378390 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 378390 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 29728499 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 29728499 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30183099 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30183099 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039242 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039242 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.133778 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.133778 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325414 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325414 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065837 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065837 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053011 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053011 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082673 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.082673 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086329 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086329 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13117.642329 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13117.642329 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13923.523338 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 13923.523338 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15355.336027 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15355.336027 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22165.129568 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22165.129568 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13392.579638 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13392.579638 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12645.202623 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12645.202623 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1345 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3372122 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 71 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 191319 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.943662 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 17.625651 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13716.734374 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13716.734374 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12937.987386 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12937.987386 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 953 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3495034 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 184351 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.017857 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18.958584 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 512814 # number of writebacks -system.cpu0.dcache.writebacks::total 512814 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248043 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 248043 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519569 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1519569 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18426 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18426 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767612 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1767612 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767612 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1767612 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390210 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 390210 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312552 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312552 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101508 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101508 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6575 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6575 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20609 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20609 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 702762 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 702762 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 804270 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 804270 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4184101504 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4184101504 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5001279356 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5001279356 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1410085492 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1410085492 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97668747 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97668747 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 412365210 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 412365210 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 359000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 359000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9185380860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9185380860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10595466352 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10595466352 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4216928747 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4216928747 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3186876498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3186876498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7403805245 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7403805245 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022478 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022478 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222061 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222061 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016937 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016937 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023322 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023322 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026292 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026292 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10722.691638 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10722.691638 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16001.431301 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16001.431301 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13891.373015 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13891.373015 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.562281 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.562281 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20008.986850 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20008.986850 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 508420 # number of writebacks +system.cpu0.dcache.writebacks::total 508420 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 245938 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 245938 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1508738 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1508738 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18883 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18883 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1754676 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1754676 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1754676 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1754676 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 384717 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 384717 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 318344 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 318344 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102343 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102343 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6481 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6481 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20059 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20059 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 703061 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 703061 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 805404 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 805404 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4089649462 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4089649462 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4952590494 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4952590494 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1562592504 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1562592504 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94643501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94643501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403849666 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403849666 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 399500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 399500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9042239956 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9042239956 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10604832460 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10604832460 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4215061000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4215061000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3183836000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3183836000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7398897000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7398897000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023939 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023939 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023309 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023309 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225128 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225128 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016823 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016823 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053011 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053011 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026684 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026684 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10630.280081 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10630.280081 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15557.354604 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15557.354604 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15268.191317 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15268.191317 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14603.224965 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14603.224965 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20133.090682 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20133.090682 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13070.400591 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13070.400591 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13174.016626 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13174.016626 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12861.245263 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12861.245263 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13167.096836 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13167.096836 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -962,420 +1081,429 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1263628 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.774293 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36451354 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1264140 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.834903 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774293 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1252930 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.771234 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36023030 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1253442 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.739287 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6360261750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.771234 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999553 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id 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accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37752197 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37752197 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37752197 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37752197 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37752197 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034457 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034457 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034457 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034457 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034457 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034457 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8468.530066 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8468.530066 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8468.530066 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8468.530066 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8468.530066 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8468.530066 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 721640 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 96102 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.509105 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 75891509 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 75891509 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36023030 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36023030 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36023030 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36023030 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36023030 # number of overall hits +system.cpu0.icache.overall_hits::total 36023030 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1295987 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1295987 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1295987 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1295987 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1295987 # number of overall misses +system.cpu0.icache.overall_misses::total 1295987 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12767063333 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12767063333 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12767063333 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12767063333 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12767063333 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12767063333 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37319017 # number of ReadReq accesses(hits+misses) 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accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.227931 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.227931 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9851.227931 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9851.227931 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1314207 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 320 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 107284 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.249795 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36666 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 36666 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 36666 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 36666 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 36666 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 36666 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264177 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1264177 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264177 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1264177 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264177 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1264177 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8917861032 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8917861032 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8917861032 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8917861032 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8917861032 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8917861032 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033486 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033486 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033486 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033486 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.281981 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.281981 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.281981 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.281981 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42511 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 42511 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 42511 # number of demand (read+write) MSHR hits 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ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10355026178 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10355026178 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10355026178 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10355026178 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243898498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243898498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243898498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 243898498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033588 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033588 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033588 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8261.048618 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8261.048618 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8261.048618 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11568415 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525589 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10417206 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118474 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25510 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 481631 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881553 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 396536 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16205.751344 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2245612 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 412784 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.440162 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2809249850500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4624.087674 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 10.817381 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.808377 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 942.420690 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1398.445665 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9228.171558 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.282232 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000660 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000110 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057521 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.085354 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.563243 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989121 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8089 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8146 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 44 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 199 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3272 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4134 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 440 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 478 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3751 # Occupied blocks per task id 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MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2127750 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2131132759 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3628232864 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5769080873 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2127750 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2131132759 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3628232864 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14990297637 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 20759378510 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218480000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4052038481 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4270518481 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3037285940 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3037285940 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218480000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7089324421 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7307804421 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.194809 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.082897 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.645932 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.645932 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.897521 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.897521 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163160 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163160 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009922 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015945 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171294 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009922 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015945 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012843 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171294 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478276 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478276 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.912753 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.912753 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157375 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157375 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181760 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.092372 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181760 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.300100 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23035.645199 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25055.367788 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45584.105017 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.482661 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.482661 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13495.796237 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13495.796237 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 30024.896989 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 30024.896989 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25372.553683 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26526.881263 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36232.893385 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25372.553683 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41093.419955 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207616 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22013.107099 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28351.226403 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62677.901511 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17152.067442 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17152.067442 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13390.146166 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13390.146166 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36393.851676 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36393.851676 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30094.475574 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48180.926443 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1385,67 +1513,76 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2021847 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1920670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 512814 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 646384 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1959682 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1897898 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19079 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19079 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 508419 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 329547 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 131 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43154 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 104914 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 291875 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 281146 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2534329 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360353 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29069 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120916 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5044667 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80953504 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86188042 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50924 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 220524 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 167412994 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1039110 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3610193 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.254626 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.435651 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88597 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42717 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112274 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 292255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 279169 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2512932 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2353027 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27983 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 115316 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5009258 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80268960 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 85221321 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 209248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 165747753 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 677561 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3234113 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.173543 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.378716 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2690945 74.54% 74.54% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 919248 25.46% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2672856 82.65% 82.65% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 561257 17.35% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3610193 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1889992000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3234113 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1876283497 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 117303500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114853000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1901297082 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1888093495 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1220075844 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1210751284 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16351973 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15934735 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 65816442 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63036190 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 33910806 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11562772 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 305112 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18755942 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 14959399 # Number of BTB hits +system.cpu1.branchPred.lookups 34134097 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11727075 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 316019 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18898892 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 15069568 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.758185 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12490105 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7221 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.737839 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12517859 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7561 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1467,27 +1604,99 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 23600 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 23600 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8914 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6871 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7815 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 15785 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 672.093760 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3265.172364 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 14984 94.93% 94.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 394 2.50% 97.42% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 71 0.45% 97.87% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 205 1.30% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 14 0.09% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.19% 99.45% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 46 0.29% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 19 0.12% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.10% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-53247 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 15785 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5984 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 7948.780916 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 6651.023666 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5565.886785 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 4665 77.96% 77.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 897 14.99% 92.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 299 5.00% 97.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 93 1.55% 99.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 7 0.12% 99.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 21 0.35% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 2 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5984 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 71907287764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.149161 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.363512 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 61231753172 85.15% 85.15% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 10656881592 14.82% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 10600500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3048000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1243000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 909500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 707500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 390500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 165000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 220500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 87000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 114500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 127500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 62500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 410000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 567000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 71907287764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2101 76.21% 76.21% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 656 23.79% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2757 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23600 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23600 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2757 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2757 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 26357 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10163643 # DTB read hits -system.cpu1.dtb.read_misses 18794 # DTB read misses -system.cpu1.dtb.write_hits 6541990 # DTB write hits -system.cpu1.dtb.write_misses 2867 # DTB write misses +system.cpu1.dtb.read_hits 10322903 # DTB read hits +system.cpu1.dtb.read_misses 19223 # DTB read misses +system.cpu1.dtb.write_hits 6788033 # DTB write hits +system.cpu1.dtb.write_misses 4377 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 58 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2089 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 54 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 409 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10182437 # DTB read accesses -system.cpu1.dtb.write_accesses 6544857 # DTB write accesses +system.cpu1.dtb.perms_faults 398 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10342126 # DTB read accesses +system.cpu1.dtb.write_accesses 6792410 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16705633 # DTB hits -system.cpu1.dtb.misses 21661 # DTB misses -system.cpu1.dtb.accesses 16727294 # DTB accesses +system.cpu1.dtb.hits 17110936 # DTB hits +system.cpu1.dtb.misses 23600 # DTB misses +system.cpu1.dtb.accesses 17134536 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1509,8 +1718,65 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 43641889 # ITB inst hits -system.cpu1.itb.inst_misses 7003 # ITB inst misses +system.cpu1.itb.walker.walks 7135 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7135 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4170 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2894 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 71 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 7064 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 161.877123 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1382.094776 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 6918 97.93% 97.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 45 0.64% 98.57% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 37 0.52% 99.09% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 22 0.31% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 14 0.20% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 9 0.13% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 3 0.04% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.03% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 1 0.01% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 7064 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1280 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9064.455469 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 7676.805908 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5570.114480 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 198 15.47% 15.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 721 56.33% 71.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 25 1.95% 73.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 272 21.25% 95.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 5 0.39% 95.39% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 10 0.78% 96.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.64% 97.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.48% 99.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.08% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.47% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1280 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 16042620916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.990716 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.095951 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 149006264 0.93% 0.93% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 15893540152 99.07% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 74500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 16042620916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1033 85.44% 85.44% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 176 14.56% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1209 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1209 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1209 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 8344 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 43998995 # ITB inst hits +system.cpu1.itb.inst_misses 7135 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1519,98 +1785,98 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1205 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1239 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 544 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 569 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43648892 # ITB inst accesses -system.cpu1.itb.hits 43641889 # DTB hits -system.cpu1.itb.misses 7003 # DTB misses -system.cpu1.itb.accesses 43648892 # DTB accesses -system.cpu1.numCycles 104622935 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 44006130 # ITB inst accesses +system.cpu1.itb.hits 43998995 # DTB hits +system.cpu1.itb.misses 7135 # DTB misses +system.cpu1.itb.accesses 44006130 # DTB accesses +system.cpu1.numCycles 106356723 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9986788 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 109166158 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 33910806 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27449504 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 91794015 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3775656 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78908 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 31556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 200392 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 294710 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 7499 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43641278 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 116202 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2270 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104281696 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.296833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339781 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 10248604 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 110247468 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 34134097 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27587427 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 92894950 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3804096 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79886 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 35043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 199386 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 306315 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 18555 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43998345 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 120822 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2367 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 105684787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.292794 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339203 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 47334317 45.39% 45.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 14034977 13.46% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7536210 7.23% 66.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35376192 33.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 48118877 45.53% 45.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 14213464 13.45% 58.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7642144 7.23% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35710302 33.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104281696 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.324124 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.043425 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13018026 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 61674095 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 26725105 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1111367 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1753103 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 754241 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 137598 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 68060945 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1169140 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1753103 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17450583 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2252903 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 56981552 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23380155 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2463400 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 55156301 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 230486 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 263427 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 35391 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18241 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1436172 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 55002320 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 260520543 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 58679791 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1657 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 52223668 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2778652 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1878098 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1805410 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13101415 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10456972 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6914054 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 629493 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 831483 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 54264321 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 589116 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 53908666 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 111755 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2291961 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5808692 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 48780 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104281696 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.516952 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.852554 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 105684787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.320940 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.036582 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13299736 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 62299682 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 27136759 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1184524 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1764086 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 778297 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 140897 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69265057 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1207807 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1764086 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17799261 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2243721 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 57294733 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23798018 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2784968 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 56317455 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 239325 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 267963 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 37417 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15706 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1709289 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 56195584 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 266063253 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 60158486 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1810 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 53296548 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2899036 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1893782 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1819648 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13269922 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10622155 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7171113 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 643276 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 895479 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 55388735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 607798 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 55019063 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 118019 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2383882 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 6031867 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 50125 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 105684787 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.520596 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.855641 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71029795 68.11% 68.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16529290 15.85% 83.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13075763 12.54% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3359554 3.22% 99.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 287282 0.28% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 71804994 67.94% 67.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16804413 15.90% 83.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13307202 12.59% 96.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3472478 3.29% 99.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 295688 0.28% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -1618,400 +1884,400 @@ system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104281696 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 105684787 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2925282 45.12% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 677 0.01% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1673331 25.81% 70.93% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1884639 29.07% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3013223 44.49% 44.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 670 0.01% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1729221 25.53% 70.03% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 2029703 29.97% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36727327 68.13% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46544 0.09% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10380092 19.25% 87.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6751298 12.52% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 73 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37421348 68.02% 68.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46238 0.08% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3333 0.01% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10544210 19.16% 87.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7003861 12.73% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 53908666 # Type of FU issued -system.cpu1.iq.rate 0.515266 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6483929 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.120276 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 218688932 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57153517 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 51920276 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 60388837 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 91402 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 55019063 # Type of FU issued +system.cpu1.iq.rate 0.517307 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6772817 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.123099 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 222607082 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58388753 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53008185 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6667 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2258 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1929 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 61787450 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4357 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94839 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 490292 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 689 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10197 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 355874 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 509093 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10627 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 368944 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 52006 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 70534 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 52621 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 79740 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1753103 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 547921 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 114364 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 54905583 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1764086 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 541667 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 103172 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 56056220 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10456972 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6914054 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 301613 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9861 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 97001 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10197 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 54939 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 127326 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 182265 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 53638641 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10278143 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 248381 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10622155 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7171113 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 314475 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9900 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 85548 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10627 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 58910 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 131027 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 189937 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 54736921 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10438101 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 258564 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 52146 # number of nop insts executed -system.cpu1.iew.exec_refs 16965109 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11808008 # Number of branches executed -system.cpu1.iew.exec_stores 6686966 # Number of stores executed -system.cpu1.iew.exec_rate 0.512685 # Inst execution rate -system.cpu1.iew.wb_sent 53497702 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 51922060 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25229975 # num instructions producing a value -system.cpu1.iew.wb_consumers 38490431 # num instructions consuming a value +system.cpu1.iew.exec_nop 59687 # number of nop insts executed +system.cpu1.iew.exec_refs 17373742 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11974777 # Number of branches executed +system.cpu1.iew.exec_stores 6935641 # Number of stores executed +system.cpu1.iew.exec_rate 0.514654 # Inst execution rate +system.cpu1.iew.wb_sent 54589285 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53010114 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25746768 # num instructions producing a value +system.cpu1.iew.wb_consumers 39490922 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.496278 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.655487 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.498418 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.651967 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3657476 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 540336 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 170387 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102349842 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.498091 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.159102 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3744166 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 557673 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 178057 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103735818 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.501583 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.163784 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 76769313 75.01% 75.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14290135 13.96% 88.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6080073 5.94% 94.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 704006 0.69% 95.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1980080 1.93% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1566587 1.53% 99.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 444714 0.43% 99.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 123770 0.12% 99.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 391164 0.38% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77652029 74.86% 74.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14577800 14.05% 88.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6160967 5.94% 94.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 757264 0.73% 95.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 2015553 1.94% 97.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1576437 1.52% 99.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 460071 0.44% 99.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 129756 0.13% 99.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 405941 0.39% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102349842 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41393585 # Number of instructions committed -system.cpu1.commit.committedOps 50979540 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103735818 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 42197750 # Number of instructions committed +system.cpu1.commit.committedOps 52032169 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16524860 # Number of memory references committed -system.cpu1.commit.loads 9966680 # Number of loads committed -system.cpu1.commit.membars 209721 # Number of memory barriers committed -system.cpu1.commit.branches 11640060 # Number of branches committed -system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 45829312 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3366651 # Number of function calls committed. +system.cpu1.commit.refs 16915231 # Number of memory references committed +system.cpu1.commit.loads 10113062 # Number of loads committed +system.cpu1.commit.membars 214317 # Number of memory barriers committed +system.cpu1.commit.branches 11798243 # Number of branches committed +system.cpu1.commit.fp_insts 1928 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 46741115 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3380053 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 34405704 67.49% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.58% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9966680 19.55% 87.14% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6558180 12.86% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 35068266 67.40% 67.40% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 45339 0.09% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3333 0.01% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 10113062 19.44% 86.93% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6802169 13.07% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 50979540 # Class of committed instruction -system.cpu1.commit.bw_lim_events 391164 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 52032169 # Class of committed instruction +system.cpu1.commit.bw_lim_events 405941 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 136558924 # The number of ROB reads -system.cpu1.rob.rob_writes 111202252 # The number of ROB writes -system.cpu1.timesIdled 53311 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 341239 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5543976372 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41360731 # Number of Instructions Simulated -system.cpu1.committedOps 50946686 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.529523 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.529523 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.395331 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.395331 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 56284724 # number of integer regfile reads -system.cpu1.int_regfile_writes 35740870 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads -system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 191161936 # number of cc regfile reads -system.cpu1.cc_regfile_writes 15560884 # number of cc regfile writes -system.cpu1.misc_regfile_reads 205876605 # number of misc regfile reads -system.cpu1.misc_regfile_writes 388900 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 191071 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.564441 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 15741519 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 82.246239 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.564441 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922977 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922977 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32983738 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32983738 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9574548 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9574548 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5910552 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5910552 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49554 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49554 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79147 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79147 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71001 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71001 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15485100 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15485100 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15534654 # number of overall hits -system.cpu1.dcache.overall_hits::total 15534654 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 219354 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 219354 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 398461 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 398461 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30111 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30111 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18127 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18127 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23403 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23403 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 617815 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 617815 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 647926 # number of overall misses -system.cpu1.dcache.overall_misses::total 647926 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453063988 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3453063988 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8746670918 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8746670918 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363087750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 363087750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542334299 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 542334299 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 511000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 511000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12199734906 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12199734906 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12199734906 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12199734906 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793902 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9793902 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6309013 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6309013 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79665 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79665 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97274 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97274 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94404 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94404 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16102915 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16102915 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16182580 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16182580 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022397 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022397 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063157 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.063157 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377970 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377970 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186350 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186350 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247903 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247903 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038367 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038367 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040038 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040038 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15741.969547 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15741.969547 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21951.134284 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21951.134284 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.217355 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.217355 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.708456 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.708456 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 139039973 # The number of ROB reads +system.cpu1.rob.rob_writes 113498046 # The number of ROB writes +system.cpu1.timesIdled 59982 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 671936 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5543606797 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 42158419 # Number of Instructions Simulated +system.cpu1.committedOps 51992838 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.522787 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.522787 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.396387 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.396387 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 57596911 # number of integer regfile reads +system.cpu1.int_regfile_writes 36337307 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1495 # number of floating regfile reads +system.cpu1.fp_regfile_writes 580 # number of floating regfile writes +system.cpu1.cc_regfile_reads 194912842 # number of cc regfile reads +system.cpu1.cc_regfile_writes 16071052 # number of cc regfile writes +system.cpu1.misc_regfile_reads 208513912 # number of misc regfile reads +system.cpu1.misc_regfile_writes 404751 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 201045 # number of replacements +system.cpu1.dcache.tags.tagsinuse 470.607708 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16083620 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 201364 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 79.873364 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 93308892000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.607708 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.919156 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.919156 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 33778764 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 33778764 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9715738 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9715738 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6106545 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6106545 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50809 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50809 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81509 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81509 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73252 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73252 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15822283 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15822283 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15873092 # number of overall hits +system.cpu1.dcache.overall_hits::total 15873092 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 224637 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 224637 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 441375 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 441375 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31038 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 31038 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18294 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18294 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 666012 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 666012 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 697050 # number of overall misses +system.cpu1.dcache.overall_misses::total 697050 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3524459329 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3524459329 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10055246312 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10055246312 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 359810249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 359810249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545166265 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 545166265 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 431000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 431000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13579705641 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13579705641 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13579705641 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13579705641 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9940375 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9940375 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6547920 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6547920 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81847 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 81847 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 99803 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 99803 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 96921 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 96921 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16488295 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16488295 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16570142 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16570142 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022598 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022598 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067407 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.067407 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379220 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379220 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.183301 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.183301 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.244209 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.244209 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040393 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.040393 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042067 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.042067 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15689.576201 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15689.576201 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22781.639903 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22781.639903 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19668.210834 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19668.210834 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23032.923444 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23032.923444 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19746.582563 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19746.582563 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18828.901612 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18828.901612 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1116392 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39638 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 28.164690 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20389.581030 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20389.581030 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19481.680856 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19481.680856 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1443381 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 46 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 45166 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.391304 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 31.957247 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 117580 # number of writebacks -system.cpu1.dcache.writebacks::total 117580 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79511 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79511 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306644 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306644 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13188 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13188 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 386155 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 386155 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 386155 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 386155 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139843 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 139843 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91817 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91817 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28628 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28628 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4939 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4939 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23403 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23403 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 231660 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 231660 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 260288 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 260288 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827288064 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827288064 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2196971984 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2196971984 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494563997 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494563997 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87258999 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87258999 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494349701 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494349701 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 489000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 489000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4024260048 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4024260048 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4518824045 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4518824045 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298813494 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298813494 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826635494 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826635494 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125448988 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125448988 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014553 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014553 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359355 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359355 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050774 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050774 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247903 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247903 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014386 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014386 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016084 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016084 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13066.710983 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13066.710983 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23927.725628 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23927.725628 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17275.534337 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17275.534337 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17667.341365 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17667.341365 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21123.347477 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21123.347477 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 125175 # number of writebacks +system.cpu1.dcache.writebacks::total 125175 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 81304 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 81304 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 345063 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 345063 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13214 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13214 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 426367 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 426367 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 426367 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 426367 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143333 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 143333 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 96312 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 96312 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29478 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29478 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5080 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5080 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 239645 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 239645 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 269123 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 269123 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1836231651 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1836231651 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2306828153 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2306828153 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 473894752 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 473894752 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85053999 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85053999 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 496613735 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 496613735 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 413000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 413000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4143059804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4143059804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4616954556 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4616954556 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298741750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298741750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826982999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826982999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125724749 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125724749 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014419 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014419 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014709 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014709 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360160 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360160 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050900 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050900 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.244209 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.244209 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014534 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014534 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016241 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.016241 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12810.948288 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12810.948288 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23951.617171 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23951.617171 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16076.217925 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.217925 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16742.913189 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16742.913189 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20981.610334 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20981.610334 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17371.406579 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17371.406579 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17360.861987 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17360.861987 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17288.321492 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17288.321492 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17155.555475 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17155.555475 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2019,425 +2285,425 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 607210 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system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 87889967 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 87889967 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43016771 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43016771 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43016771 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43016771 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43016771 # number of overall hits -system.cpu1.icache.overall_hits::total 43016771 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 624350 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 624350 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 624350 # number of demand (read+write) misses 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accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43641121 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43641121 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43641121 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43641121 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014306 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014306 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014306 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014306 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014306 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014306 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8160.932235 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8160.932235 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8160.932235 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8160.932235 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8160.932235 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8160.932235 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 275120 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 36110 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.618942 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 88611673 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 88611673 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 43363824 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 43363824 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 43363824 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 43363824 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 43363824 # number of overall hits +system.cpu1.icache.overall_hits::total 43363824 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 634277 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 634277 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 634277 # number of demand (read+write) misses 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accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43998101 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43998101 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43998101 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43998101 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014416 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014416 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014416 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014416 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014416 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014416 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8825.400730 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8825.400730 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8825.400730 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8825.400730 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 423261 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 12 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 39865 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.617359 # average number of cycles each access was blocked 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number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 607725 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 607725 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 607725 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4103508232 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4103508232 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4103508232 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4103508232 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4103508232 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4103508232 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6752.245229 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6752.245229 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6752.245229 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6752.245229 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6752.245229 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6752.245229 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18806 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 18806 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 18806 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 18806 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 18806 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 18806 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615471 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 615471 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 615471 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 615471 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 615471 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 615471 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4523939883 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4523939883 # number of ReadReq MSHR miss cycles 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overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841883 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43038 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4641023 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42756 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 5990 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109076 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564189 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85682 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15604.887972 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 847212 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100795 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.405298 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.num_hwpf_issued 229039 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 229849 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 714 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 59807 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 55576 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15296.446244 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 851759 # Total number of references to valid blocks. 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ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031751458 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3621000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 498710017 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2095215892 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2603480409 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3621000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 498710017 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2095215892 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1791435833 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4394916242 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7547000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182265750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189812750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737917999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737917999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7547000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3920183749 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927730749 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.397966 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.109457 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.925489 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.925489 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.963807 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.963807 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946055 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946055 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.957707 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.957707 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512528 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512528 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027491 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.033922 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007627 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.441047 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125760 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027491 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.033922 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007627 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.441047 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.507655 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.507655 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139631 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251487 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.593832 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.546147 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31757.007866 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14699.726879 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14699.726879 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13672.501574 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13672.501574 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 400999 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29828.575036 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29828.575036 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19772.603245 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20042.049679 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26901.894714 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19772.603245 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25898.777029 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.171625 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.442638 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17532.812215 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63187.747628 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14546.805631 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14546.805631 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13617.957074 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13617.957074 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 341000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 341000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30266.404353 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30266.404353 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21040.945973 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28897.762712 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2447,60 +2713,61 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1294463 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 865156 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11871 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11871 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 117580 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 157134 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 1181364 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 879041 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11863 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11863 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 125175 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 39550 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84893 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41888 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 87131 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75362 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41966 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86419 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 79541 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66364 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215649 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825187 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17442 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37966 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2096244 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38895824 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25442442 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31012 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67368 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 64436646 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 834109 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1797203 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.418253 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.493272 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 89279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 71717 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1231143 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 850974 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17917 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 40354 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2140388 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39391696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 26549567 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31836 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70792 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 66043891 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 585425 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1574316 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.319194 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.466164 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1045518 58.17% 58.17% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 751685 41.83% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1071804 68.08% 68.08% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 502512 31.92% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1797203 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 659823435 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1574316 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 680504524 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81245999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81017999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 912982594 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 924938756 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 403842731 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 418581676 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9829718 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 10092231 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 21193613 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 22735342 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31016 # Transaction distribution -system.iobus.trans_dist::ReadResp 31016 # Transaction distribution +system.iobus.trans_dist::ReadReq 31021 # Transaction distribution +system.iobus.trans_dist::ReadResp 31021 # Transaction distribution system.iobus.trans_dist::WriteReq 59439 # Transaction distribution system.iobus.trans_dist::WriteResp 23215 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution @@ -2526,9 +2793,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180920 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71598 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2551,9 +2818,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484096 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40134000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2594,52 +2861,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347117122 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347085145 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36830633 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36840554 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36453 # number of replacements -system.iocache.tags.tagsinuse 14.560350 # Cycle average of tags in use +system.iocache.tags.replacements 36458 # number of replacements +system.iocache.tags.tagsinuse 14.558041 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254140746000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.560350 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.910022 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.910022 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 254609644000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.558041 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909878 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909878 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328239 # Number of tag accesses -system.iocache.tags.data_accesses 328239 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses -system.iocache.ReadReq_misses::total 247 # number of ReadReq misses +system.iocache.tags.tag_accesses 328284 # Number of tag accesses +system.iocache.tags.data_accesses 328284 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses +system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses -system.iocache.demand_misses::total 247 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 247 # number of overall misses -system.iocache.overall_misses::total 247 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30846377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30846377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9649955112 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9649955112 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30846377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30846377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30846377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30846377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses +system.iocache.demand_misses::total 252 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 252 # number of overall misses +system.iocache.overall_misses::total 252 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31425377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31425377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9633411214 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9633411214 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31425377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31425377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31425377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31425377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2648,40 +2915,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124884.117409 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266396.729019 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 266396.729019 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124884.117409 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124884.117409 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124884.117409 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 57106 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124703.876984 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124703.876984 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265940.018054 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265940.018054 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124703.876984 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124703.876984 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56535 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7195 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7211 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.936901 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.840105 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 247 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 247 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 247 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18001377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18001377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7766041378 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7766041378 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18001377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18001377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18001377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18001377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18320377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18320377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7749655322 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7749655322 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18320377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18320377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18320377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18320377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2690,524 +2957,521 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214389.393165 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214389.393165 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72880.068826 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72699.908730 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72699.908730 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213937.039587 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213937.039587 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 153362 # number of replacements -system.l2c.tags.tagsinuse 64452.240621 # Cycle average of tags in use -system.l2c.tags.total_refs 520061 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 218026 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.385316 # Average number of references to valid blocks. +system.l2c.tags.replacements 131156 # number of replacements +system.l2c.tags.tagsinuse 63989.320892 # Cycle average of tags in use +system.l2c.tags.total_refs 352673 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195503 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.803926 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 14085.588040 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.542715 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.877015 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1413.412167 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2156.075780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39299.191861 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.498933 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 294.129683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 883.808465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6297.115959 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.214929 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.021567 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.032899 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599658 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004488 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096086 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983463 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 44393 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 11841.549695 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.064672 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 2.035376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7520.794001 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2869.625937 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37329.338161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.624339 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1925.336025 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 701.530072 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1779.513002 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.180688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.114758 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043787 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.569600 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000071 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.029378 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010704 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027153 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.976400 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31812 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 20252 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 7759 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 36223 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32516 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 220 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6391 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25201 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4616 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 15266 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.677383 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 410 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6149 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 25933 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.485413 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.309021 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6595512 # Number of tag accesses -system.l2c.tags.data_accesses 6595512 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 297 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 126 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 12544 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 38879 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182049 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 77 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11674 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44095 # number of ReadReq hits -system.l2c.ReadReq_hits::total 293955 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 252625 # number of Writeback hits -system.l2c.Writeback_hits::total 252625 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 11700 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 714 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12414 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 188 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 168 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3696 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1226 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4922 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 297 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 126 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 12544 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 42575 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 182049 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 77 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 44095 # number of demand (read+write) hits -system.l2c.demand_hits::total 298877 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 297 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 126 # number of overall hits -system.l2c.overall_hits::cpu0.inst 12544 # number of overall hits -system.l2c.overall_hits::cpu0.data 42575 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 182049 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 77 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4168 # number of overall hits -system.l2c.overall_hits::cpu1.data 12900 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 44095 # number of overall hits -system.l2c.overall_hits::total 298877 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3733 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8650 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164264 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses +system.l2c.tags.occ_task_id_percent::1024 0.496155 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5013444 # Number of tag accesses +system.l2c.tags.data_accesses 5013444 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 174 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 66 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 34010 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 46649 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45581 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 75 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits 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cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4247652000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158845000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6396633498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5557500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3456329250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10017365248 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163664 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.115842 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.523384 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748237 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.814447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.764130 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.799762 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.876062 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.847623 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.744212 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.835463 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.780528 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.286905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.452973 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.541543 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.286905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.452973 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.541543 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72210.099135 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73214.777182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 94027.774700 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10087.586010 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10066.837508 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10082.277585 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10193.962742 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10049.089733 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10100.038260 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75462.216144 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63008.133823 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70156.977731 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74000.876501 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64395.506453 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 91598.209717 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74000.876501 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64395.506453 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 91598.209717 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3222,57 +3486,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 237783 # Transaction distribution -system.membus.trans_dist::ReadResp 237783 # Transaction distribution -system.membus.trans_dist::WriteReq 30976 # Transaction distribution -system.membus.trans_dist::WriteResp 30976 # Transaction distribution -system.membus.trans_dist::Writeback 149598 # Transaction distribution +system.membus.trans_dist::ReadReq 210212 # Transaction distribution +system.membus.trans_dist::ReadResp 210211 # Transaction distribution +system.membus.trans_dist::WriteReq 30942 # Transaction distribution +system.membus.trans_dist::WriteResp 30942 # Transaction distribution +system.membus.trans_dist::Writeback 135769 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79558 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40675 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13780 # Transaction distribution -system.membus.trans_dist::ReadExReq 31194 # Transaction distribution -system.membus.trans_dist::ReadExResp 14873 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76140 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40614 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13546 # Transaction distribution +system.membus.trans_dist::ReadExReq 39344 # Transaction distribution +system.membus.trans_dist::ReadExResp 19397 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13732 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 830114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 939030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13598 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 770072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 878993 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21024476 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21215108 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18669148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18859512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25851588 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123388 # Total snoops (count) -system.membus.snoop_fanout::samples 537032 # Request fanout histogram +system.membus.pkt_size::total 23495992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123727 # Total snoops (count) +system.membus.snoop_fanout::samples 500337 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 537032 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 500337 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 537032 # Request fanout histogram -system.membus.reqLayer0.occupancy 81237991 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 500337 # Request fanout histogram +system.membus.reqLayer0.occupancy 81279500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 26000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11614997 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11516000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1967612498 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1822464250 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2113693587 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1904793274 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38580367 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38546446 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3305,48 +3569,48 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 659684 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 659669 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30976 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30976 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 252625 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 489006 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 488990 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30942 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30942 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 227099 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 91886 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41031 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 132917 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 40129 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 40129 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1298615 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426559 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1725174 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40738026 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8562330 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49300356 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 291348 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1083611 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033657 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.180345 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeReq 79612 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40957 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 120569 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50358 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50358 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1016462 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 341372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1357834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31696041 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5742799 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 37438840 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 287500 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 885309 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.041201 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.198756 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1047140 96.63% 96.63% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36471 3.37% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 848833 95.88% 95.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36476 4.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1083611 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1586551162 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 885309 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1431615961 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1066500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2272414912 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1714942226 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 846278221 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 674969400 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1853 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b41e9656d..8914a4f8a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827042 # Number of seconds simulated -sim_ticks 2827042159500 # Number of ticks simulated -final_tick 2827042159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827025 # Number of seconds simulated +sim_ticks 2827025397500 # Number of ticks simulated +final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100972 # Simulator instruction rate (inst/s) -host_op_rate 122474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2522254422 # Simulator tick rate (ticks/s) -host_mem_usage 564960 # Number of bytes of host memory used -host_seconds 1120.84 # Real time elapsed on the host -sim_insts 113173742 # Number of instructions simulated -sim_ops 137273263 # Number of ops (including micro ops) simulated +host_inst_rate 96738 # Simulator instruction rate (inst/s) +host_op_rate 117339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2415768223 # Simulator tick rate (ticks/s) +host_mem_usage 619580 # Number of bytes of host memory used +host_seconds 1170.24 # Real time elapsed on the host +sim_insts 113206948 # Number of instructions simulated +sim_ops 137314363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9496932 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10823604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8116352 # Number of bytes written to this memory +system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8133876 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171883 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126818 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131199 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3359317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3828597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2870970 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2877168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2870970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3365516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6705765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171884 # Number of read requests accepted -system.physmem.writeReqs 167423 # Number of write requests accepted -system.physmem.readBursts 171884 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167423 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10992576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.physmem.bytesWritten 10315392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10823668 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10452212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6228 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4543 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10965 # Per bank write bursts -system.physmem.perBankRdBursts::1 10116 # Per bank write bursts -system.physmem.perBankRdBursts::2 11197 # Per bank write bursts -system.physmem.perBankRdBursts::3 11389 # Per bank write bursts -system.physmem.perBankRdBursts::4 13120 # Per bank write bursts -system.physmem.perBankRdBursts::5 10535 # Per bank write bursts -system.physmem.perBankRdBursts::6 11120 # Per bank write bursts -system.physmem.perBankRdBursts::7 11540 # Per bank write bursts -system.physmem.perBankRdBursts::8 10348 # Per bank write bursts -system.physmem.perBankRdBursts::9 11053 # Per bank write bursts -system.physmem.perBankRdBursts::10 10478 # Per bank write bursts -system.physmem.perBankRdBursts::11 9244 # Per bank write bursts -system.physmem.perBankRdBursts::12 10124 # Per bank write bursts -system.physmem.perBankRdBursts::13 10758 # Per bank write bursts -system.physmem.perBankRdBursts::14 10029 # Per bank write bursts -system.physmem.perBankRdBursts::15 9743 # Per bank write bursts -system.physmem.perBankWrBursts::0 10407 # Per bank write bursts -system.physmem.perBankWrBursts::1 9909 # Per bank write bursts -system.physmem.perBankWrBursts::2 10642 # Per bank write bursts -system.physmem.perBankWrBursts::3 10446 # Per bank write bursts -system.physmem.perBankWrBursts::4 9703 # Per bank write bursts -system.physmem.perBankWrBursts::5 10218 # Per bank write bursts -system.physmem.perBankWrBursts::6 10399 # Per bank write bursts -system.physmem.perBankWrBursts::7 10626 # Per bank write bursts -system.physmem.perBankWrBursts::8 10202 # Per bank write bursts -system.physmem.perBankWrBursts::9 10761 # Per bank write bursts -system.physmem.perBankWrBursts::10 9802 # Per bank write bursts -system.physmem.perBankWrBursts::11 9030 # Per bank write bursts -system.physmem.perBankWrBursts::12 9755 # Per bank write bursts -system.physmem.perBankWrBursts::13 10443 # Per bank write bursts -system.physmem.perBankWrBursts::14 9720 # Per bank write bursts -system.physmem.perBankWrBursts::15 9115 # Per bank write bursts +system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171932 # Number of read requests accepted +system.physmem.writeReqs 167449 # Number of write requests accepted +system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11320 # Per bank write bursts +system.physmem.perBankRdBursts::1 10283 # Per bank write bursts +system.physmem.perBankRdBursts::2 11137 # Per bank write bursts +system.physmem.perBankRdBursts::3 11363 # Per bank write bursts +system.physmem.perBankRdBursts::4 13028 # Per bank write bursts +system.physmem.perBankRdBursts::5 10237 # Per bank write bursts +system.physmem.perBankRdBursts::6 10954 # Per bank write bursts +system.physmem.perBankRdBursts::7 11381 # Per bank write bursts +system.physmem.perBankRdBursts::8 10407 # Per bank write bursts +system.physmem.perBankRdBursts::9 11232 # Per bank write bursts +system.physmem.perBankRdBursts::10 10729 # Per bank write bursts +system.physmem.perBankRdBursts::11 9386 # Per bank write bursts +system.physmem.perBankRdBursts::12 9853 # Per bank write bursts +system.physmem.perBankRdBursts::13 10909 # Per bank write bursts +system.physmem.perBankRdBursts::14 9951 # Per bank write bursts +system.physmem.perBankRdBursts::15 9636 # Per bank write bursts +system.physmem.perBankWrBursts::0 10810 # Per bank write bursts +system.physmem.perBankWrBursts::1 10132 # Per bank write bursts +system.physmem.perBankWrBursts::2 10502 # Per bank write bursts +system.physmem.perBankWrBursts::3 10558 # Per bank write bursts +system.physmem.perBankWrBursts::4 9654 # Per bank write bursts +system.physmem.perBankWrBursts::5 9978 # Per bank write bursts +system.physmem.perBankWrBursts::6 10358 # Per bank write bursts +system.physmem.perBankWrBursts::7 10535 # Per bank write bursts +system.physmem.perBankWrBursts::8 10309 # Per bank write bursts +system.physmem.perBankWrBursts::9 10935 # Per bank write bursts +system.physmem.perBankWrBursts::10 10009 # Per bank write bursts +system.physmem.perBankWrBursts::11 9154 # Per bank write bursts +system.physmem.perBankWrBursts::12 9556 # Per bank write bursts +system.physmem.perBankWrBursts::13 10555 # Per bank write bursts +system.physmem.perBankWrBursts::14 9521 # Per bank write bursts +system.physmem.perBankWrBursts::15 9009 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2827041948500 # Total gap between requests +system.physmem.totGap 2827025186500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168336 # Read request sizes (log2) +system.physmem.readPktSize::6 168384 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 163042 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163068 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,137 +159,134 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64399 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.873212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.977516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.816153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23539 36.55% 36.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14785 22.96% 59.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6319 9.81% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3687 5.73% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2636 4.09% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1562 2.43% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1140 1.77% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1107 1.72% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9624 14.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64399 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.206340 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.339482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6812 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6814 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6814 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.653948 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.805353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.459775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5702 83.68% 83.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 39 0.57% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.38% 84.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 231 3.39% 88.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 131 1.92% 89.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 61 0.90% 90.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 35 0.51% 91.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 27 0.40% 91.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 123 1.81% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.19% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 19 0.28% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.16% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 31 0.45% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 13 0.19% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 13 0.19% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.38% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 61 0.90% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 10 0.15% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 9 0.13% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 11 0.16% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 89 1.31% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 18 0.26% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 5 0.07% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.38% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.06% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.16% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 11 0.16% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6814 # Writes before turning the bus around for reads -system.physmem.totQLat 2084525750 # Total ticks spent queuing -system.physmem.totMemAccLat 5305007000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 858795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12136.34 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads +system.physmem.totQLat 2011805750 # Total ticks spent queuing +system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30886.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -297,36 +294,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.50 # Average write queue length when enqueuing -system.physmem.readRowHits 141721 # Number of row buffer hits during reads -system.physmem.writeRowHits 126816 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.67 # Row buffer hit rate for writes -system.physmem.avgGap 8331811.45 # Average gap between requests -system.physmem.pageHitRate 80.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694668588500 # Time in different power states -system.physmem.memoryStateTime::REF 94401060000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37972497000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 254499840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 232356600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 138864000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 126781875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 701859600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 637852800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 533628000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 510805440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184648473360 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184648473360 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80377758270 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79142156730 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625717004000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626800865000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892372087070 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1892099291805 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.382923 # Core power per rank (mW) -system.physmem.averagePower::1 669.286428 # Core power per rank (mW) +system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing +system.physmem.readRowHits 141825 # Number of row buffer hits during reads +system.physmem.writeRowHits 127038 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes +system.physmem.avgGap 8329945.36 # Average gap between requests +system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.379373 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states +system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.289511 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states +system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory @@ -345,16 +347,24 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46933448 # Number of BP lookups -system.cpu.branchPred.condPredicted 24039449 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232882 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29542848 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21360620 # Number of BTB hits +system.cpu.branchPred.lookups 46965884 # Number of BP lookups +system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.303862 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754095 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33720 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -376,27 +386,89 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 69937 # Table walker walks requested +system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25465003 # DTB read hits -system.cpu.dtb.read_misses 60438 # DTB read misses -system.cpu.dtb.write_hits 19916425 # DTB write hits -system.cpu.dtb.write_misses 9382 # DTB write misses +system.cpu.dtb.read_hits 25472400 # DTB read hits +system.cpu.dtb.read_misses 60528 # DTB read misses +system.cpu.dtb.write_hits 19920178 # DTB write hits +system.cpu.dtb.write_misses 9409 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 344 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2309 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25525441 # DTB read accesses -system.cpu.dtb.write_accesses 19925807 # DTB write accesses +system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25532928 # DTB read accesses +system.cpu.dtb.write_accesses 19929587 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45381428 # DTB hits -system.cpu.dtb.misses 69820 # DTB misses -system.cpu.dtb.accesses 45451248 # DTB accesses +system.cpu.dtb.hits 45392578 # DTB hits +system.cpu.dtb.misses 69937 # DTB misses +system.cpu.dtb.accesses 45462515 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -418,8 +490,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66294026 # ITB inst hits -system.cpu.itb.inst_misses 11939 # ITB inst misses +system.cpu.itb.walker.walks 11957 # Table walker walks requested +system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66242388 # ITB inst hits +system.cpu.itb.inst_misses 11957 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -435,91 +554,91 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66305965 # ITB inst accesses -system.cpu.itb.hits 66294026 # DTB hits -system.cpu.itb.misses 11939 # DTB misses -system.cpu.itb.accesses 66305965 # DTB accesses -system.cpu.numCycles 260580731 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66254345 # ITB inst accesses +system.cpu.itb.hits 66242388 # DTB hits +system.cpu.itb.misses 11957 # DTB misses +system.cpu.itb.accesses 66254345 # DTB accesses +system.cpu.numCycles 260505842 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104873538 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184739295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46933448 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33114715 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145635789 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6158762 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 168952 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8750 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338958 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 503648 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66294321 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1128854 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4994 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254609122 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155317216 61.00% 61.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29235163 11.48% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14076452 5.53% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55980291 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254609122 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180111 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78085586 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105431733 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64660886 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829260 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2601657 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422216 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485978 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157447803 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691485 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2601657 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83925210 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10033565 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74541150 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62655394 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20852146 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146807646 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950357 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437123 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62766 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16447 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18089237 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150492315 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678770164 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164434086 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141835122 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8657190 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2845976 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2649716 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13845319 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26411369 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21300781 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686386 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2189128 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143541895 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120957 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143337283 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269192 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6251828 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14653372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125306 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254609122 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.562970 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882443 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166344309 65.33% 65.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45117660 17.72% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32035421 12.58% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10298180 4.04% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813519 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -527,9 +646,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254609122 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7370311 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -558,13 +677,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632420 24.93% 57.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9586874 42.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96009315 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113982 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -592,96 +711,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26194290 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21008765 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143337283 # Type of FU issued -system.cpu.iq.rate 0.550069 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22589637 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157598 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564106761 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151919680 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140223084 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35756 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued +system.cpu.iq.rate 0.550386 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165901147 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23436 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324147 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1490308 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18251 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701176 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88081 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6304 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2601657 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 950737 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 291154 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145863821 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26411369 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21300781 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096076 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17895 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 256263 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18251 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317548 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471732 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789280 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142394540 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25793108 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 873030 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200969 # number of nop insts executed -system.cpu.iew.exec_refs 46672402 # number of memory reference insts executed -system.cpu.iew.exec_branches 26533167 # Number of branches executed -system.cpu.iew.exec_stores 20879294 # Number of stores executed -system.cpu.iew.exec_rate 0.546451 # Inst execution rate -system.cpu.iew.wb_sent 142007306 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140234515 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63283849 # num instructions producing a value -system.cpu.iew.wb_consumers 95860591 # num instructions consuming a value +system.cpu.iew.exec_nop 200965 # number of nop insts executed +system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed +system.cpu.iew.exec_branches 26544582 # Number of branches executed +system.cpu.iew.exec_stores 20883032 # Number of stores executed +system.cpu.iew.exec_rate 0.546767 # Inst execution rate +system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63301991 # num instructions producing a value +system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538161 # insts written-back per cycle +system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591533 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995651 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755158 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251674404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546055 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.146686 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178222235 70.81% 70.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43294364 17.20% 88.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15476639 6.15% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357303 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6369018 2.53% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1679088 0.67% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777340 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414271 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1084146 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251674404 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113328647 # Number of instructions committed -system.cpu.commit.committedOps 137428168 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113361853 # Number of instructions committed +system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45520666 # Number of memory references committed -system.cpu.commit.loads 24921061 # Number of loads committed -system.cpu.commit.membars 814701 # Number of memory barriers committed -system.cpu.commit.branches 26049415 # Number of branches committed +system.cpu.commit.refs 45532382 # Number of memory references committed +system.cpu.commit.loads 24928817 # Number of loads committed +system.cpu.commit.membars 814713 # Number of memory barriers committed +system.cpu.commit.branches 26060941 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120247607 # Number of committed integer instructions. -system.cpu.commit.function_calls 4892692 # Number of function calls committed. +system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. +system.cpu.commit.function_calls 4896517 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91785919 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction @@ -710,210 +829,210 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24921061 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20599605 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137428168 # Class of committed instruction -system.cpu.commit.bw_lim_events 1084146 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction +system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373381031 # The number of ROB reads -system.cpu.rob.rob_writes 292971684 # The number of ROB writes -system.cpu.timesIdled 892930 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5971609 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393503589 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113173742 # Number of Instructions Simulated -system.cpu.committedOps 137273263 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.302484 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302484 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155831391 # number of integer regfile reads -system.cpu.int_regfile_writes 88636024 # number of integer regfile writes +system.cpu.rob.rob_reads 373323554 # The number of ROB reads +system.cpu.rob.rob_writes 293054802 # The number of ROB writes +system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113206948 # Number of Instructions Simulated +system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155872747 # number of integer regfile reads +system.cpu.int_regfile_writes 88664446 # number of integer regfile writes system.cpu.fp_regfile_reads 9607 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503020695 # number of cc regfile reads -system.cpu.cc_regfile_writes 53185327 # number of cc regfile writes -system.cpu.misc_regfile_reads 444130548 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521619 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837995 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958491 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40159583 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838507 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.894154 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 503168366 # number of cc regfile reads +system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes +system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes +system.cpu.dcache.tags.replacements 837844 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958491 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179379502 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179379502 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23322864 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23322864 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15584894 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15584894 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346636 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346636 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 442009 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 442009 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460310 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460310 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38907758 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38907758 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39254394 # number of overall hits -system.cpu.dcache.overall_hits::total 39254394 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700618 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700618 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3574058 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3574058 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177109 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177109 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26740 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26740 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4274676 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4274676 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4451785 # number of overall misses -system.cpu.dcache.overall_misses::total 4451785 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9939142148 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9939142148 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 135148977049 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356483749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 356483749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 189500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 189500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145088119197 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145088119197 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145088119197 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145088119197 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24023482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24023482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19158952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19158952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523745 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523745 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468749 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468749 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460315 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460315 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43182434 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43182434 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43706179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43706179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029164 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029164 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186548 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186548 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338159 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338159 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.098991 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.098991 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 37900 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 37900 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33941.313727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32590.998711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 505021 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits +system.cpu.dcache.overall_hits::total 39264228 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses 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ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 134775393563 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 355748499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 355748499 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 176500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 176500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144684504211 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144684504211 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144684504211 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144684504211 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24031170 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24031170 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19162882 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19162882 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523753 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523753 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468737 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468737 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460325 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460325 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43194052 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43194052 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43717805 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43717805 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029155 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029155 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186604 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186604 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338096 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338096 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057096 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057096 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.916691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.370238 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695574 # number of writebacks -system.cpu.dcache.writebacks::total 695574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286297 # number of ReadReq MSHR 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overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832977 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5358688665 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5358688665 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11888843709 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11888843709 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1476460251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1476460251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110246000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110246000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 179500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 179500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17247532374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17247532374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18723992625 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18723992625 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792718250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792718250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233175703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233175703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017247 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017247 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017756 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017756 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019059 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019059 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 35900 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 35900 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 695426 # number of writebacks +system.cpu.dcache.writebacks::total 695426 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286545 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286545 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3276416 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3276416 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18452 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18452 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3562961 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3562961 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3562961 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3562961 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414078 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414078 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299459 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299459 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119308 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119308 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8311 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8311 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713537 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713537 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832845 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832845 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5351526415 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5351526415 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11825722463 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11825722463 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1475435001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1475435001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109426500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109426500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17177248878 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17177248878 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18652683879 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019050 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42125 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -921,265 +1040,265 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1894210 # number of replacements -system.cpu.icache.tags.tagsinuse 511.373832 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64309690 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894722 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.941491 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1894041 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373863 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64258114 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894553 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.917296 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.373832 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373863 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68186062 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68186062 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64309690 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64309690 # number of ReadReq hits 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-system.cpu.icache.demand_miss_latency::cpu.inst 26770075875 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26770075875 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26770075875 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26770075875 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66291320 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66291320 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66291320 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66291320 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66291320 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66291320 # number of overall (read+write) accesses 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overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179407 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060884 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1250973750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9058246549 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10311368299 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157876500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387443500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545320000 # number of ReadReq MSHR uncacheable cycles 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+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013376 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988468 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988468 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461519 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461519 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060908 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060908 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62718.026171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64612.832850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10097.791834 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1300,54 +1419,54 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2565344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2565278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296684 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495832 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128794 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6451318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121309456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98375777 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219947773 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65392 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3562462 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.010230 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100625 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65703 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.010231 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3526018 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3525674 98.98% 98.98% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36444 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3562462 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503396529 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849706150 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334755109 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19527240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74897454 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution @@ -1444,23 +1563,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347066130 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776516 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.000725 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251942535000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000725 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062545 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062545 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1474,14 +1593,14 @@ system.iocache.demand_misses::realview.ide 220 # system.iocache.demand_misses::total 220 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 220 # number of overall misses system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26411377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26411377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9622478237 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9622478237 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26411377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26411377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26411377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26411377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1498,19 +1617,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120051.713636 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120051.713636 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120051.713636 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56749 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7275 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.800550 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1524,14 +1643,14 @@ system.iocache.demand_mshr_misses::realview.ide 220 system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14970377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14970377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7738798269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7738798269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14970377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14970377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14970377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14970377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1540,66 +1659,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67832 # Transaction distribution -system.membus.trans_dist::ReadResp 67831 # Transaction distribution +system.membus.trans_dist::ReadReq 67820 # Transaction distribution +system.membus.trans_dist::ReadResp 67819 # Transaction distribution system.membus.trans_dist::WriteReq 27608 # Transaction distribution system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 126818 # Transaction distribution +system.membus.trans_dist::Writeback 126844 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135125 # Transaction distribution -system.membus.trans_dist::ReadExResp 135125 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution +system.membus.trans_dist::ReadExReq 135185 # Transaction distribution +system.membus.trans_dist::ReadExResp 135185 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452492 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 669001 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16640360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16803825 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21439281 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 484 # Total snoops (count) -system.membus.snoop_fanout::samples 336405 # Request fanout histogram +system.membus.snoop_fanout::samples 336478 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 336405 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 336405 # Request fanout histogram -system.membus.reqLayer0.occupancy 94190000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 336478 # Request fanout histogram +system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1683660499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1677935457 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38220484 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 053f94faa..0523405d3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,153 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.818075 # Number of seconds simulated -sim_ticks 2818074786500 # Number of ticks simulated -final_tick 2818074786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.818071 # Number of seconds simulated +sim_ticks 2818071194500 # Number of ticks simulated +final_tick 2818071194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252135 # Simulator instruction rate (inst/s) -host_op_rate 306151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5631568448 # Simulator tick rate (ticks/s) -host_mem_usage 564964 # Number of bytes of host memory used -host_seconds 500.41 # Real time elapsed on the host -sim_insts 126169808 # Number of instructions simulated -sim_ops 153199842 # Number of ops (including micro ops) simulated +host_inst_rate 294940 # Simulator instruction rate (inst/s) +host_op_rate 358127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6587540433 # Simulator tick rate (ticks/s) +host_mem_usage 622484 # Number of bytes of host memory used +host_seconds 427.79 # Real time elapsed on the host +sim_insts 126171688 # Number of instructions simulated +sim_ops 153202470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 666212 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4384416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 666276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4385696 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 128384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1037892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 127360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1038980 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 6016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 504320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4231744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 505600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4227776 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10960328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 666212 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 128384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 504320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1298916 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8261760 # Number of bytes written to this memory +system.physmem.bytes_read::total 10959048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 666276 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 127360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 505600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1299236 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8262336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8279284 # Number of bytes written to this memory +system.physmem.bytes_written::total 8279860 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 69025 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 69045 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2006 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16218 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16235 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 94 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 7880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 66121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 66059 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180228 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129090 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180208 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129099 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133471 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133480 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 236407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1555820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 236430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1556276 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 368298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 368685 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 2135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 178959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1501644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 179413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1500237 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3889296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 236407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 178959 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 460923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2931704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3888847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 236430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 179413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2931912 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2937922 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2931704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2938130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2931912 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 236407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1562035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 236430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1562491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 368301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 368688 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 2135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 178959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1501644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 179413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1500237 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6827218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 92321 # Number of read requests accepted -system.physmem.writeReqs 90302 # Number of write requests accepted -system.physmem.readBursts 92321 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 90302 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5904000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4544 # Total number of bytes read from write queue -system.physmem.bytesWritten 5704128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5908484 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5779208 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 71 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1152 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2483 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6041 # Per bank write bursts -system.physmem.perBankRdBursts::1 5798 # Per bank write bursts -system.physmem.perBankRdBursts::2 5558 # Per bank write bursts -system.physmem.perBankRdBursts::3 6021 # Per bank write bursts -system.physmem.perBankRdBursts::4 5562 # Per bank write bursts -system.physmem.perBankRdBursts::5 5457 # Per bank write bursts -system.physmem.perBankRdBursts::6 6123 # Per bank write bursts -system.physmem.perBankRdBursts::7 6801 # Per bank write bursts -system.physmem.perBankRdBursts::8 6403 # Per bank write bursts -system.physmem.perBankRdBursts::9 6349 # Per bank write bursts -system.physmem.perBankRdBursts::10 5693 # Per bank write bursts -system.physmem.perBankRdBursts::11 5092 # Per bank write bursts -system.physmem.perBankRdBursts::12 5281 # Per bank write bursts -system.physmem.perBankRdBursts::13 5450 # Per bank write bursts -system.physmem.perBankRdBursts::14 5307 # Per bank write bursts -system.physmem.perBankRdBursts::15 5314 # Per bank write bursts -system.physmem.perBankWrBursts::0 5390 # Per bank write bursts -system.physmem.perBankWrBursts::1 4962 # Per bank write bursts -system.physmem.perBankWrBursts::2 5472 # Per bank write bursts -system.physmem.perBankWrBursts::3 5886 # Per bank write bursts -system.physmem.perBankWrBursts::4 5376 # Per bank write bursts -system.physmem.perBankWrBursts::5 5734 # Per bank write bursts -system.physmem.perBankWrBursts::6 5792 # Per bank write bursts -system.physmem.perBankWrBursts::7 6324 # Per bank write bursts -system.physmem.perBankWrBursts::8 6132 # Per bank write bursts -system.physmem.perBankWrBursts::9 6057 # Per bank write bursts -system.physmem.perBankWrBursts::10 5626 # Per bank write bursts -system.physmem.perBankWrBursts::11 4872 # Per bank write bursts -system.physmem.perBankWrBursts::12 5573 # Per bank write bursts -system.physmem.perBankWrBursts::13 5712 # Per bank write bursts -system.physmem.perBankWrBursts::14 5197 # Per bank write bursts -system.physmem.perBankWrBursts::15 5022 # Per bank write bursts +system.physmem.bw_total::total 6826977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 92280 # Number of read requests accepted +system.physmem.writeReqs 90311 # Number of write requests accepted +system.physmem.readBursts 92280 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 90311 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5901184 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4736 # Total number of bytes read from write queue +system.physmem.bytesWritten 5694528 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5905860 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5779784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 74 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1313 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2491 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6033 # Per bank write bursts +system.physmem.perBankRdBursts::1 5793 # Per bank write bursts +system.physmem.perBankRdBursts::2 5545 # Per bank write bursts +system.physmem.perBankRdBursts::3 6032 # Per bank write bursts +system.physmem.perBankRdBursts::4 5564 # Per bank write bursts +system.physmem.perBankRdBursts::5 5452 # Per bank write bursts +system.physmem.perBankRdBursts::6 6124 # Per bank write bursts +system.physmem.perBankRdBursts::7 6804 # Per bank write bursts +system.physmem.perBankRdBursts::8 6414 # Per bank write bursts +system.physmem.perBankRdBursts::9 6339 # Per bank write bursts +system.physmem.perBankRdBursts::10 5684 # Per bank write bursts +system.physmem.perBankRdBursts::11 5101 # Per bank write bursts +system.physmem.perBankRdBursts::12 5267 # Per bank write bursts +system.physmem.perBankRdBursts::13 5451 # Per bank write bursts +system.physmem.perBankRdBursts::14 5288 # Per bank write bursts +system.physmem.perBankRdBursts::15 5315 # Per bank write bursts +system.physmem.perBankWrBursts::0 5413 # Per bank write bursts +system.physmem.perBankWrBursts::1 4989 # Per bank write bursts +system.physmem.perBankWrBursts::2 5365 # Per bank write bursts +system.physmem.perBankWrBursts::3 5927 # Per bank write bursts +system.physmem.perBankWrBursts::4 5380 # Per bank write bursts +system.physmem.perBankWrBursts::5 5714 # Per bank write bursts +system.physmem.perBankWrBursts::6 5766 # Per bank write bursts +system.physmem.perBankWrBursts::7 6373 # Per bank write bursts +system.physmem.perBankWrBursts::8 6011 # Per bank write bursts +system.physmem.perBankWrBursts::9 5951 # Per bank write bursts +system.physmem.perBankWrBursts::10 5678 # Per bank write bursts +system.physmem.perBankWrBursts::11 4910 # Per bank write bursts +system.physmem.perBankWrBursts::12 5493 # Per bank write bursts +system.physmem.perBankWrBursts::13 5839 # Per bank write bursts +system.physmem.perBankWrBursts::14 5189 # Per bank write bursts +system.physmem.perBankWrBursts::15 4979 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2816508644000 # Total gap between requests +system.physmem.totGap 2816505052000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 92320 # Read request sizes (log2) +system.physmem.readPktSize::6 92279 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 90300 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 90309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -178,149 +178,149 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 8 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::20 5704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33954 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.872416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.139988 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 360.706061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12607 37.13% 37.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7646 22.52% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2942 8.66% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1742 5.13% 73.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1359 4.00% 77.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 780 2.30% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 533 1.57% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 565 1.66% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5780 17.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33954 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3432 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.875583 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 525.946384 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3431 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 33947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.579050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.896082 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.051588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12589 37.08% 37.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7648 22.53% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3047 8.98% 68.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1722 5.07% 73.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1227 3.61% 77.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 803 2.37% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 549 1.62% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 558 1.64% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5804 17.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33947 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3440 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.800581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 525.347088 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3439 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3432 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.969406 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.900383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 25.459060 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.17% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 3440 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3440 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.865407 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.895854 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 25.306431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 5 0.15% 0.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 3 0.09% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.06% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 2696 78.55% 78.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 29 0.84% 79.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 30 0.87% 80.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 138 4.02% 84.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 83 2.42% 87.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 30 0.87% 87.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 20 0.58% 88.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.67% 89.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 73 2.13% 91.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.20% 91.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.15% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.23% 91.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.58% 92.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.23% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.23% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.61% 93.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 41 1.19% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.23% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.09% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.26% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 65 1.89% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.12% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.20% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.15% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 7 0.20% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.09% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 8 0.23% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.09% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.12% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2693 78.28% 78.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 34 0.99% 79.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 21 0.61% 80.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 172 5.00% 85.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 62 1.80% 87.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 30 0.87% 87.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.49% 88.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 16 0.47% 88.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 84 2.44% 91.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.32% 91.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.41% 92.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.29% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 20 0.58% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.17% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.17% 93.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.73% 94.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 46 1.34% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.12% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.12% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.26% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 47 1.37% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.09% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 6 0.17% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.06% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 16 0.47% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.03% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 7 0.20% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.06% 98.28% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 22 0.64% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.20% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.06% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.09% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.03% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.09% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.15% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.09% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.06% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.17% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.09% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.09% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.03% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.09% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.12% 99.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.09% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.09% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 1 0.03% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::228-231 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3432 # Writes before turning the bus around for reads -system.physmem.totQLat 1184332750 # Total ticks spent queuing -system.physmem.totMemAccLat 2914020250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 461250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12838.30 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::248-251 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3440 # Writes before turning the bus around for reads +system.physmem.totQLat 1163516500 # Total ticks spent queuing +system.physmem.totMemAccLat 2892379000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 461030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12618.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31588.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31368.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.09 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.10 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.05 # Average system write bandwidth in MiByte/s @@ -329,36 +329,41 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.03 # Average write queue length when enqueuing -system.physmem.readRowHits 76434 # Number of row buffer hits during reads -system.physmem.writeRowHits 70988 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes -system.physmem.avgGap 15422529.71 # Average gap between requests -system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2704815148250 # Time in different power states -system.physmem.memoryStateTime::REF 94101540000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 19154581250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 134477280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 122214960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 73375500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 66684750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 369415800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 350110800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 291185280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 286357680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184062612240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184062612240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 70840900170 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 70013903985 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1628700821250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1629426256500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1884472787520 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1884328140915 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.710440 # Core power per rank (mW) -system.physmem.averagePower::1 668.659112 # Core power per rank (mW) +system.physmem.avgWrQLen 6.25 # Average write queue length when enqueuing +system.physmem.readRowHits 76428 # Number of row buffer hits during reads +system.physmem.writeRowHits 70807 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.56 # Row buffer hit rate for writes +system.physmem.avgGap 15425212.92 # Average gap between requests +system.physmem.pageHitRate 81.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 134288280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 73012500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 369306600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 291126960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 68915344410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1612195386000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1860850713630 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.510917 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2632883157750 # Time in different power states +system.physmem_0.memoryStateTime::REF 91447980000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14405588500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 122351040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 66577500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 349884600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 285444000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68134185630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1610493455250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1858324146900 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.557325 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2634053636000 # Time in different power states +system.physmem_1.memoryStateTime::REF 91447980000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13230281250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -378,6 +383,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -399,27 +412,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 5757 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5757 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5757 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5757 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5757 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.475514 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 87128456868 52.45% 52.45% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 78993152250 47.55% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 166121609118 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3229 67.67% 67.67% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1543 32.33% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4772 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5757 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5757 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10529 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14476474 # DTB read hits -system.cpu0.dtb.read_misses 4869 # DTB read misses -system.cpu0.dtb.write_hits 11056177 # DTB write hits -system.cpu0.dtb.write_misses 893 # DTB write misses +system.cpu0.dtb.read_hits 14474153 # DTB read hits +system.cpu0.dtb.read_misses 4865 # DTB read misses +system.cpu0.dtb.write_hits 11054581 # DTB write hits +system.cpu0.dtb.write_misses 892 # DTB write misses system.cpu0.dtb.flush_tlb 188 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3212 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3207 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 944 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 943 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 196 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14481343 # DTB read accesses -system.cpu0.dtb.write_accesses 11057070 # DTB write accesses +system.cpu0.dtb.perms_faults 195 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14479018 # DTB read accesses +system.cpu0.dtb.write_accesses 11055473 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25532651 # DTB hits -system.cpu0.dtb.misses 5762 # DTB misses -system.cpu0.dtb.accesses 25538413 # DTB accesses +system.cpu0.dtb.hits 25528734 # DTB hits +system.cpu0.dtb.misses 5757 # DTB misses +system.cpu0.dtb.accesses 25534491 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -441,8 +483,29 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 67995752 # ITB inst hits -system.cpu0.itb.inst_misses 2758 # ITB inst misses +system.cpu0.itb.walker.walks 2755 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2755 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2755 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2755 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2755 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.475515 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 87128348368 52.45% 52.45% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 78993260750 47.55% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 166121609118 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1528 75.53% 75.53% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 495 24.47% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2755 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2755 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4778 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 67991390 # ITB inst hits +system.cpu0.itb.inst_misses 2755 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -451,45 +514,45 @@ system.cpu0.itb.flush_tlb 188 # Nu system.cpu0.itb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1969 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1966 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67998510 # ITB inst accesses -system.cpu0.itb.hits 67995752 # DTB hits -system.cpu0.itb.misses 2758 # DTB misses -system.cpu0.itb.accesses 67998510 # DTB accesses -system.cpu0.numCycles 82558276 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67994145 # ITB inst accesses +system.cpu0.itb.hits 67991390 # DTB hits +system.cpu0.itb.misses 2755 # DTB misses +system.cpu0.itb.accesses 67994145 # DTB accesses +system.cpu0.numCycles 82552372 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66186941 # Number of instructions committed -system.cpu0.committedOps 80639436 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70858992 # Number of integer alu accesses +system.cpu0.committedInsts 66182532 # Number of instructions committed +system.cpu0.committedOps 80633643 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70853114 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5470 # Number of float alu accesses -system.cpu0.num_func_calls 7266542 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8791397 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70858992 # number of integer instructions +system.cpu0.num_func_calls 7266071 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8791663 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70853114 # number of integer instructions system.cpu0.num_fp_insts 5470 # number of float instructions -system.cpu0.num_int_register_reads 131380013 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49295072 # number of times the integer registers were written +system.cpu0.num_int_register_reads 131368884 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49289864 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4246 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245776790 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29457750 # number of times the CC registers were written -system.cpu0.num_mem_refs 26204570 # number of memory refs -system.cpu0.num_load_insts 14653679 # Number of load instructions -system.cpu0.num_store_insts 11550891 # Number of store instructions -system.cpu0.num_idle_cycles 77949108.406676 # Number of idle cycles -system.cpu0.num_busy_cycles 4609167.593324 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055829 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944171 # Percentage of idle cycles -system.cpu0.Branches 16455876 # Number of branches fetched +system.cpu0.num_cc_register_reads 245759484 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29458192 # number of times the CC registers were written +system.cpu0.num_mem_refs 26200850 # number of memory refs +system.cpu0.num_load_insts 14651277 # Number of load instructions +system.cpu0.num_store_insts 11549573 # Number of store instructions +system.cpu0.num_idle_cycles 77943726.541103 # Number of idle cycles +system.cpu0.num_busy_cycles 4608645.458897 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055827 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944173 # Percentage of idle cycles +system.cpu0.Branches 16455843 # Number of branches fetched system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55779692 67.98% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 58849 0.07% 68.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 55777669 67.99% 67.99% # Class of executed instruction +system.cpu0.op_class::IntMult 58831 0.07% 68.06% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction @@ -513,294 +576,294 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4532 0.01% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4520 0.01% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::MemRead 14653679 17.86% 85.92% # Class of executed instruction -system.cpu0.op_class::MemWrite 11550891 14.08% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 14651277 17.86% 85.92% # Class of executed instruction +system.cpu0.op_class::MemWrite 11549573 14.08% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 82049836 # Class of executed instruction +system.cpu0.op_class::total 82044063 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3055 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 833965 # number of replacements +system.cpu0.dcache.tags.replacements 833838 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 46972085 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834477 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.289251 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 46974042 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 834350 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.300164 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.818118 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.670897 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.507786 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948864 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032560 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018570 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.894462 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.632625 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.469713 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949013 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032486 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018496 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 198452344 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 198452344 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 13787811 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 4397354 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 8501200 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 26686365 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10663716 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3166111 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 5160414 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18990241 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190628 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60624 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130481 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 381733 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235896 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80331 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 134984 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 451211 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 237277 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82832 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 139583 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459692 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 24451527 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 7563465 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 13661614 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 45676606 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 24642155 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 7624089 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 13792095 # number of overall hits -system.cpu0.dcache.overall_hits::total 46058339 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 191712 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 58922 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 315531 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 566165 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 143864 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 35394 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 1531641 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1710899 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54000 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 21214 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65487 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 140701 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4460 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3296 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9679 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17435 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 198459549 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 198459549 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 13785736 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 4396523 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 8506631 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 26688890 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10662175 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3165503 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 5162158 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18989836 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190654 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60573 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130462 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 381689 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235825 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80326 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 134935 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 451086 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 237211 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82830 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 139650 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459691 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 24447911 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 7562026 # 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miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039413 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066907 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 24783293 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 7656388 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 15515929 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 47955610 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 25027959 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 7738138 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 15711943 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 48478040 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013701 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013233 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035704 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020746 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013315 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011060 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228876 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.082674 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.220758 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.259046 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334425 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269397 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018545 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039461 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.067072 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037258 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000107 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000037 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013538 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012316 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.119105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.047485 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015563 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014927 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121789 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.049875 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056448 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16821.983748 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10963.981973 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37534.226479 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46119.783369 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42064.106374 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14131.143811 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13679.124496 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10265.356811 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13800.066667 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12176.529412 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23623.265533 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41115.179568 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34331.428710 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19285.483528 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39707.448360 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32333.523062 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 374153 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25938 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 24753 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 535 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.115461 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 48.482243 # average number of cycles each access was blocked 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miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16642.926742 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10860.397820 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37446.527441 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46032.518019 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41985.058666 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14080.606061 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13612.771261 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10226.470413 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16219 # average StoreCondReq miss latency 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miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13255.624713 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13306.612595 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13292.917622 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35364.823699 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45295.005716 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43033.548717 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12774.723956 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14903.501933 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14216.565320 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16022.693452 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12431.523492 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13542.347986 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11799.933333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11799.933333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21563.033536 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27011.209802 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25640.284271 # average overall mshr miss latency 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MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5424851729 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6673760300 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 265951000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 654196260 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 920147260 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21422750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35664251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57087001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 227496 # number of StoreCondReq MSHR miss cycles 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average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13267.774790 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13255.421973 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35276.913567 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45203.707464 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42942.374463 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12789.180091 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14899.249795 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14221.091140 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15915.861813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12426.568293 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.560009 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14218.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14218.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21507.301340 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26949.033270 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25579.217590 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19931.303536 # average overall mshr miss latency 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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 11058289795 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2869743000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8188546795 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11058289795 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2869743000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8188546795 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11058289795 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for ReadReq accesses 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+system.cpu0.icache.demand_mshr_misses::total 930201 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 249012 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 681189 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 930201 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2873083500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8182514470 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11055597970 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2873083500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8182514470 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11055597970 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2873083500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8182514470 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11055597970 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009052 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.009052 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.009052 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11887.885913 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11887.885913 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11887.885913 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11885.171022 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11885.171022 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11885.171022 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -969,27 +1040,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 1854 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1854 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 620 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1234 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1854 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1854 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1854 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1496 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9777.746658 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7722.280706 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6250.292235 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 511 34.16% 34.16% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 754 50.40% 84.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 15.37% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1496 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1000015000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000015000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000015000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 885 59.16% 59.16% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 611 40.84% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1496 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1496 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1496 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3350 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4627532 # DTB read hits -system.cpu1.dtb.read_misses 1596 # DTB read misses -system.cpu1.dtb.write_hits 3288935 # DTB write hits -system.cpu1.dtb.write_misses 256 # DTB write misses +system.cpu1.dtb.read_hits 4626652 # DTB read hits +system.cpu1.dtb.read_misses 1593 # DTB read misses +system.cpu1.dtb.write_hits 3288334 # DTB write hits +system.cpu1.dtb.write_misses 261 # DTB write misses system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 148 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1270 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1268 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 69 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4629128 # DTB read accesses -system.cpu1.dtb.write_accesses 3289191 # DTB write accesses +system.cpu1.dtb.read_accesses 4628245 # DTB read accesses +system.cpu1.dtb.write_accesses 3288595 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7916467 # DTB hits -system.cpu1.dtb.misses 1852 # DTB misses -system.cpu1.dtb.accesses 7918319 # DTB accesses +system.cpu1.dtb.hits 7914986 # DTB hits +system.cpu1.dtb.misses 1854 # DTB misses +system.cpu1.dtb.accesses 7916840 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1011,55 +1119,86 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 21872882 # ITB inst hits -system.cpu1.itb.inst_misses 825 # ITB inst misses +system.cpu1.itb.walker.walks 832 # Table walker walks requested +system.cpu1.itb.walker.walksShort 832 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 221 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 611 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 832 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 832 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 832 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10456.699346 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8281.924765 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6395.528631 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 192 31.37% 31.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 1 0.16% 31.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 290 47.39% 78.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 12 1.96% 80.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 105 17.16% 98.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 12 1.96% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 391 63.89% 63.89% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 221 36.11% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 612 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 832 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 832 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 612 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 612 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1444 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 21867839 # ITB inst hits +system.cpu1.itb.inst_misses 832 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 148 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 668 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 672 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 21873707 # ITB inst accesses -system.cpu1.itb.hits 21872882 # DTB hits -system.cpu1.itb.misses 825 # DTB misses -system.cpu1.itb.accesses 21873707 # DTB accesses -system.cpu1.numCycles 158012156 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 21868671 # ITB inst accesses +system.cpu1.itb.hits 21867839 # DTB hits +system.cpu1.itb.misses 832 # DTB misses +system.cpu1.itb.accesses 21868671 # DTB accesses +system.cpu1.numCycles 158011786 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21172070 # Number of instructions committed -system.cpu1.committedOps 25390672 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22586857 # Number of integer alu accesses +system.cpu1.committedInsts 21167008 # Number of instructions committed +system.cpu1.committedOps 25384727 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22581810 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1738 # Number of float alu accesses -system.cpu1.num_func_calls 2402647 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2689176 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22586857 # number of integer instructions +system.cpu1.num_func_calls 2402385 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2688390 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22581810 # number of integer instructions system.cpu1.num_fp_insts 1738 # number of float instructions -system.cpu1.num_int_register_reads 41666783 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15854927 # number of times the integer registers were written +system.cpu1.num_int_register_reads 41656503 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15851657 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1290 # number of times the floating registers were read system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92283936 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9328431 # number of times the CC registers were written -system.cpu1.num_mem_refs 8130215 # number of memory refs -system.cpu1.num_load_insts 4674464 # Number of load instructions -system.cpu1.num_store_insts 3455751 # Number of store instructions -system.cpu1.num_idle_cycles 151523865.450182 # Number of idle cycles -system.cpu1.num_busy_cycles 6488290.549818 # Number of busy cycles -system.cpu1.not_idle_fraction 0.041062 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.958938 # Percentage of idle cycles -system.cpu1.Branches 5242761 # Number of branches fetched +system.cpu1.num_cc_register_reads 92262793 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9324878 # number of times the CC registers were written +system.cpu1.num_mem_refs 8128633 # number of memory refs +system.cpu1.num_load_insts 4673659 # Number of load instructions +system.cpu1.num_store_insts 3454974 # Number of store instructions +system.cpu1.num_idle_cycles 151523982.353984 # Number of idle cycles +system.cpu1.num_busy_cycles 6487803.646016 # Number of busy cycles +system.cpu1.not_idle_fraction 0.041059 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.958941 # Percentage of idle cycles +system.cpu1.Branches 5241513 # Number of branches fetched system.cpu1.op_class::No_OpClass 34 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17956106 68.78% 68.78% # Class of executed instruction -system.cpu1.op_class::IntMult 18827 0.07% 68.85% # Class of executed instruction +system.cpu1.op_class::IntAlu 17951469 68.78% 68.78% # Class of executed instruction +system.cpu1.op_class::IntMult 18860 0.07% 68.85% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.85% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 68.85% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 68.85% # Class of executed instruction @@ -1083,26 +1222,34 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.85% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.85% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.85% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1169 0.00% 68.86% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1172 0.00% 68.86% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 68.86% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.86% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::MemRead 4674464 17.91% 86.76% # Class of executed instruction -system.cpu1.op_class::MemWrite 3455751 13.24% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4673659 17.91% 86.76% # Class of executed instruction +system.cpu1.op_class::MemWrite 3454974 13.24% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26106351 # Class of executed instruction +system.cpu1.op_class::total 26100168 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17443399 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9460519 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 398611 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10920300 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8161771 # Number of BTB hits +system.cpu2.branchPred.lookups 17449157 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9464735 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 398390 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10718645 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8165775 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 74.739439 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4093630 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21092 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 76.182904 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4093661 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 20704 # Number of incorrect RAS predictions. +system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1124,27 +1271,100 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.dtb.walker.walks 43517 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 43517 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13970 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11118 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 18429 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 25088 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 493.961256 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 3141.545513 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-8191 24512 97.70% 97.70% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::8192-16383 373 1.49% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::16384-24575 135 0.54% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::24576-32767 33 0.13% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::32768-40959 15 0.06% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::40960-49151 7 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::49152-57343 6 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 25088 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 9234 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 11931.507147 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 9422.312939 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 7440.393288 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 2697 29.21% 29.21% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 4034 43.69% 72.89% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2262 24.50% 97.39% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 120 1.30% 98.69% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-40959 50 0.54% 99.23% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::40960-49151 64 0.69% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::49152-57343 4 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::73728-81919 2 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 9234 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 52111304876 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.433489 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.514696 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-1 52056176876 99.89% 99.89% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::2-3 40469500 0.08% 99.97% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-5 8303000 0.02% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::6-7 2155500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-9 1410500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::10-11 753500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-13 454000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::14-15 1056000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-17 83500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::18-19 122000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-21 61500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::22-23 86000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-25 164500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::26-27 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-29 4500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 52111304876 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 2902 72.88% 72.88% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 1080 27.12% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 3982 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43517 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43517 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3982 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3982 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 47499 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9671030 # DTB read hits -system.cpu2.dtb.read_misses 37752 # DTB read misses -system.cpu2.dtb.write_hits 7157940 # DTB write hits -system.cpu2.dtb.write_misses 5738 # DTB write misses +system.cpu2.dtb.read_hits 9677625 # DTB read hits +system.cpu2.dtb.read_misses 37716 # DTB read misses +system.cpu2.dtb.write_hits 7160348 # DTB write hits +system.cpu2.dtb.write_misses 5801 # DTB write misses system.cpu2.dtb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 368 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2464 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 439 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 949 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2469 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 945 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 419 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9708782 # DTB read accesses -system.cpu2.dtb.write_accesses 7163678 # DTB write accesses +system.cpu2.dtb.perms_faults 418 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9715341 # DTB read accesses +system.cpu2.dtb.write_accesses 7166149 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16828970 # DTB hits -system.cpu2.dtb.misses 43490 # DTB misses -system.cpu2.dtb.accesses 16872460 # DTB accesses +system.cpu2.dtb.hits 16837973 # DTB hits +system.cpu2.dtb.misses 43517 # DTB misses +system.cpu2.dtb.accesses 16881490 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1166,158 +1386,210 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 12894617 # ITB inst hits -system.cpu2.itb.inst_misses 6298 # ITB inst misses +system.cpu2.itb.walker.walks 6476 # Table walker walks requested +system.cpu2.itb.walker.walksShort 6476 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2218 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4151 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1246.035484 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 5374.992147 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-8191 6033 94.72% 94.72% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::8192-16383 153 2.40% 97.13% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::16384-24575 113 1.77% 98.90% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::24576-32767 28 0.44% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.30% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.13% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::49152-57343 9 0.14% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::73728-81919 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 1962 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12125.644750 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 9197.080965 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 8421.034460 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-8191 606 30.89% 30.89% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::8192-16383 818 41.69% 72.58% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::16384-24575 463 23.60% 96.18% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-32767 28 1.43% 97.60% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-40959 29 1.48% 99.08% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::40960-49151 11 0.56% 99.64% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::49152-57343 5 0.25% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::57344-65535 1 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::73728-81919 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 1962 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 4866645120 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.377306 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.486503 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 3033838520 62.34% 62.34% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 1830102100 37.61% 99.94% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 2122000 0.04% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 461500 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 121000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 4866645120 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 1443 77.79% 77.79% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 412 22.21% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 1855 # Table walker page sizes translated +system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6476 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6476 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1855 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1855 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 8331 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 12898498 # ITB inst hits +system.cpu2.itb.inst_misses 6476 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 368 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1799 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1789 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1027 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12900915 # ITB inst accesses -system.cpu2.itb.hits 12894617 # DTB hits -system.cpu2.itb.misses 6298 # DTB misses -system.cpu2.itb.accesses 12900915 # DTB accesses -system.cpu2.numCycles 69897742 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12904974 # ITB inst accesses +system.cpu2.itb.hits 12898498 # DTB hits +system.cpu2.itb.misses 6476 # DTB misses +system.cpu2.itb.accesses 12904974 # DTB accesses +system.cpu2.numCycles 69896550 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26768356 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 69154350 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17443399 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12255401 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39728052 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2075674 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 91833 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 964 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 303 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 279943 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 102540 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 510 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12893196 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 269600 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2749 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 68010313 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.222372 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.345734 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26772867 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 69167442 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17449157 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12259436 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39647350 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2075847 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 94572 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 925 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 261 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 361977 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 99094 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 575 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12897087 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 269205 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2824 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 68015518 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.222532 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.345771 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49396667 72.63% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2406815 3.54% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1558633 2.29% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4908408 7.22% 85.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1099721 1.62% 87.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 702073 1.03% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3889062 5.72% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 750470 1.10% 95.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3298464 4.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49396866 72.63% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2407853 3.54% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1558370 2.29% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4909650 7.22% 85.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1103212 1.62% 87.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 700919 1.03% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3889597 5.72% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 749830 1.10% 95.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3299221 4.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 68010313 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.249556 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.989365 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18657683 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36955851 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10391299 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1075131 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 930120 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1306172 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 109269 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59268734 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 353681 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 930120 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19279637 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4349454 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27177493 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10831041 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5442328 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56795330 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2300 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 936981 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 152434 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 3851730 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58689966 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 260889069 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63678439 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4318 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48634410 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10055540 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 957404 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 893614 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 6253924 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10259989 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7928891 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1377694 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1916931 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54575287 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 669934 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 51950842 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68646 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7267604 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18361034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 68925 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 68010313 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.763867 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.465859 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 68015518 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.249643 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.989569 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18660323 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36954486 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10395816 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1074729 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 929937 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1306815 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 109505 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59278443 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 354551 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 929937 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19281301 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4387069 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27167714 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10836297 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5412952 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56807794 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2395 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 934627 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 156415 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 3819110 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58701003 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 260943920 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63689416 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4317 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48649356 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10051631 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 957722 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 893887 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 6244990 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10262812 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7930622 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1370921 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1928187 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54587761 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 670112 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 51973443 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68390 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7260181 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18315253 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68730 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 68015518 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.466174 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47556715 69.93% 69.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6835010 10.05% 79.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5099948 7.50% 87.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4195226 6.17% 93.64% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1610331 2.37% 96.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1069065 1.57% 97.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1123688 1.65% 99.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 361159 0.53% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 159171 0.23% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47556774 69.92% 69.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6833375 10.05% 79.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5102327 7.50% 87.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4195165 6.17% 93.64% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1616653 2.38% 96.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1064575 1.57% 97.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1125788 1.66% 99.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 361184 0.53% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 159677 0.23% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 68010313 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 68015518 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 78624 9.78% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 373360 46.42% 56.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 352326 43.80% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 78584 9.71% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 374915 46.33% 56.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 355764 43.96% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 110 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34419657 66.25% 66.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39271 0.08% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34433275 66.25% 66.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39265 0.08% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued @@ -1330,10 +1602,10 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Ty system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 2 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued @@ -1341,101 +1613,101 @@ system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Ty system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2864 0.01% 66.34% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.34% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9952470 19.16% 85.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7536463 14.51% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2873 0.01% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9958899 19.16% 85.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7539012 14.51% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 51950842 # Type of FU issued -system.cpu2.iq.rate 0.743241 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 804311 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015482 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172775366 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 62545429 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50354259 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 5092 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4209 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52749857 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5186 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 265342 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 51973443 # Type of FU issued +system.cpu2.iq.rate 0.743577 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 809264 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015571 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172830468 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 62550700 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50376095 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9590 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 5049 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4207 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52777410 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5187 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 265138 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1601303 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38444 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 793651 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1600472 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1933 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38461 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 793125 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 130825 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 118759 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 131320 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 120276 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 930120 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3238109 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 943841 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55348166 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 92957 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10259989 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7928891 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 358502 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 33985 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 900757 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38444 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 183146 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 162363 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 345509 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51516440 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9776464 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 391010 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 929937 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3246832 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 971285 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55360766 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 91934 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10262812 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7930622 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 358706 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 34253 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 928134 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38461 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 182765 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 162631 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 345396 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51539725 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9783295 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 390308 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 102945 # number of nop insts executed -system.cpu2.iew.exec_refs 17239257 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9485344 # Number of branches executed -system.cpu2.iew.exec_stores 7462793 # Number of stores executed -system.cpu2.iew.exec_rate 0.737026 # Inst execution rate -system.cpu2.iew.wb_sent 51063802 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50358468 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26440569 # num instructions producing a value -system.cpu2.iew.wb_consumers 45930116 # num instructions consuming a value +system.cpu2.iew.exec_nop 102893 # number of nop insts executed +system.cpu2.iew.exec_refs 17248466 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9490874 # Number of branches executed +system.cpu2.iew.exec_stores 7465171 # Number of stores executed +system.cpu2.iew.exec_rate 0.737372 # Inst execution rate +system.cpu2.iew.wb_sent 51085657 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50380302 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26454346 # num instructions producing a value +system.cpu2.iew.wb_consumers 45953910 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.720459 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575670 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.720784 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575671 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8108589 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 601009 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 290869 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66287251 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.712520 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.616760 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8107084 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 601382 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 290377 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66292417 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.712682 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.616986 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48204047 72.72% 72.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 8094433 12.21% 84.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3998554 6.03% 90.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1723968 2.60% 93.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 875669 1.32% 94.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 615346 0.93% 95.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1257319 1.90% 97.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 299111 0.45% 98.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1218804 1.84% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48208105 72.72% 72.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 8091600 12.21% 84.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3999207 6.03% 90.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1724132 2.60% 93.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 877027 1.32% 94.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 615427 0.93% 95.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1259890 1.90% 97.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 297840 0.45% 98.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1219189 1.84% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66287251 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38872037 # Number of instructions committed -system.cpu2.commit.committedOps 47230974 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66292417 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38883433 # Number of instructions committed +system.cpu2.commit.committedOps 47245385 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15793926 # Number of memory references committed -system.cpu2.commit.loads 8658686 # Number of loads committed -system.cpu2.commit.membars 225734 # Number of memory barriers committed -system.cpu2.commit.branches 8913791 # Number of branches committed +system.cpu2.commit.refs 15799837 # Number of memory references committed +system.cpu2.commit.loads 8662340 # Number of loads committed +system.cpu2.commit.membars 225899 # Number of memory barriers committed +system.cpu2.commit.branches 8915887 # Number of branches committed system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41344274 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1642310 # Number of function calls committed. +system.cpu2.commit.int_insts 41357490 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1642928 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31396236 66.47% 66.47% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 37948 0.08% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31404754 66.47% 66.47% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 37921 0.08% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.55% # Class of committed instruction @@ -1459,36 +1731,36 @@ system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.55% # system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2864 0.01% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2873 0.01% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8658686 18.33% 84.89% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7135240 15.11% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8662340 18.33% 84.89% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7137497 15.11% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47230974 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1218804 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 47245385 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1219189 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 112988408 # The number of ROB reads -system.cpu2.rob.rob_writes 112405622 # The number of ROB writes -system.cpu2.timesIdled 280375 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1887429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 5250225403 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38810797 # Number of Instructions Simulated -system.cpu2.committedOps 47169734 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.800987 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.800987 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.555251 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.555251 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56393520 # number of integer regfile reads -system.cpu2.int_regfile_writes 31926452 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15872 # number of floating regfile reads -system.cpu2.fp_regfile_writes 13692 # number of floating regfile writes -system.cpu2.cc_regfile_reads 182232541 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19215539 # number of cc regfile writes -system.cpu2.misc_regfile_reads 124355307 # number of misc regfile reads -system.cpu2.misc_regfile_writes 481535 # number of misc regfile writes +system.cpu2.rob.rob_reads 113003070 # The number of ROB reads +system.cpu2.rob.rob_writes 112431430 # The number of ROB writes +system.cpu2.timesIdled 280451 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1881032 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5250223632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38822148 # Number of Instructions Simulated +system.cpu2.committedOps 47184100 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.800430 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.800430 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.555423 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.555423 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56420474 # number of integer regfile reads +system.cpu2.int_regfile_writes 31939226 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15888 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13694 # number of floating regfile writes +system.cpu2.cc_regfile_reads 182315650 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19227541 # number of cc regfile writes +system.cpu2.misc_regfile_reads 124375401 # number of misc regfile reads +system.cpu2.misc_regfile_writes 481787 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30188 # Transaction distribution system.iobus.trans_dist::ReadResp 30188 # Transaction distribution system.iobus.trans_dist::WriteReq 59019 # Transaction distribution @@ -1544,7 +1816,7 @@ system.iobus.pkt_size_system.bridge.master::total 159119 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 18225000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1570,25 +1842,25 @@ system.iobus.reqLayer23.occupancy 2807000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15727000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 217719639 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 217868633 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39873000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39885000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 22974011 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 22990014 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.993341 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.993331 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.993341 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062084 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062084 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 245002453509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.993331 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062083 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062083 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1604,8 +1876,8 @@ system.iocache.overall_misses::realview.ide 252 # system.iocache.overall_misses::total 252 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 14419928 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 14419928 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6029712700 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6029712700 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6024842691 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6024842691 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 14419928 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 14419928 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 14419928 # number of overall miss cycles @@ -1628,17 +1900,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 57221.936508 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166456.291409 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 166456.291409 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166321.849906 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 166321.849906 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency system.iocache.demand_avg_miss_latency::total 57221.936508 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency system.iocache.overall_avg_miss_latency::total 57221.936508 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34890 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 34568 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4513 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4486 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.730999 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.705751 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1646,323 +1918,327 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 127 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22720 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 22720 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22736 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 22736 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 127 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 127 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 127 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 127 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 7815928 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 7815928 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4848250722 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4848250722 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4842542719 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4842542719 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 7815928 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 7815928 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 7815928 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 7815928 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.503968 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627208 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627208 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627650 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627650 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.503968 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.503968 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61542.740157 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 61542.740157 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213391.316989 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213391.316989 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212990.091441 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212990.091441 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 100831 # number of replacements -system.l2c.tags.tagsinuse 65118.744874 # Cycle average of tags in use -system.l2c.tags.total_refs 2894730 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166072 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.430572 # Average number of references to valid blocks. +system.l2c.tags.replacements 100812 # number of replacements +system.l2c.tags.tagsinuse 65118.584894 # Cycle average of tags in use +system.l2c.tags.total_refs 2893892 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166052 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.427625 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49795.493403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939326 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49801.969845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939327 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5292.397633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2853.974292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1121.420686 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 949.232304 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.100226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3505.367496 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1539.850216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.759819 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5299.216432 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2852.911552 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969199 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1106.770268 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 948.162110 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 57.070020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3510.700878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1538.875168 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.759918 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080756 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043548 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080860 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043532 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000887 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.053488 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.023496 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993633 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65196 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 45 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.016888 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.014468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000871 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.053569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.023481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993631 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65191 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 49 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3290 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7951 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53614 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000687 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27445059 # Number of tag accesses -system.l2c.tags.data_accesses 27445059 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5016 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2571 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 858721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 243218 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1379 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 246795 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 78418 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 27414 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 673438 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 202274 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2346335 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 692650 # number of Writeback hits -system.l2c.Writeback_hits::total 692650 # number of Writeback hits +system.l2c.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7961 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53600 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000748 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994736 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27438611 # Number of tag accesses +system.l2c.tags.data_accesses 27438611 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2568 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 857894 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 243025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1381 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 686 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 247021 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 78422 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 27314 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 6601 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 673200 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 202331 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2345451 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 692729 # number of Writeback hits +system.l2c.Writeback_hits::total 692729 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 41 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 55 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 14 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 80155 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 20967 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 56516 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 157638 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5016 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2571 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 858721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 323373 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1379 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 679 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 246795 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 99385 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 27414 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 6412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 673438 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 258790 # number of demand (read+write) hits -system.l2c.demand_hits::total 2503973 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5016 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2571 # number of overall hits -system.l2c.overall_hits::cpu0.inst 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10002.341382 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.356268 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.676727 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57766.563505 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62320.767201 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61486.916547 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57472.558521 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62169.148043 # average ReadExReq mshr miss latency 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system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2117,55 +2393,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74228 # Transaction distribution -system.membus.trans_dist::ReadResp 74227 # Transaction distribution +system.membus.trans_dist::ReadReq 74222 # Transaction distribution +system.membus.trans_dist::ReadResp 74221 # Transaction distribution system.membus.trans_dist::WriteReq 27571 # Transaction distribution system.membus.trans_dist::WriteResp 27571 # Transaction distribution -system.membus.trans_dist::Writeback 129090 # Transaction distribution +system.membus.trans_dist::Writeback 129099 # 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slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 579048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 579034 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109015 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109015 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 688063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 688049 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16930172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17093291 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16929468 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17092587 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642496 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4642496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21735787 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 288 # Total snoops (count) -system.membus.snoop_fanout::samples 341037 # Request fanout histogram +system.membus.pkt_size::total 21735083 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 289 # Total snoops (count) +system.membus.snoop_fanout::samples 341035 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 341037 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 341035 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 341037 # Request fanout histogram -system.membus.reqLayer0.occupancy 40803000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 341035 # Request fanout histogram +system.membus.reqLayer0.occupancy 40827000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 460500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 469500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 937458500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 937138500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 904148767 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 904275509 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 23873989 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 23892986 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2198,54 +2474,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2443122 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2443118 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2442249 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2442245 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 692650 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22720 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2788 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296527 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296527 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3615529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484690 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88144 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6217293 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115152760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97928947 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213285547 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 51952 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3431323 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.010630 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102554 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 692729 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22736 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2762 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296542 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296542 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3613854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484499 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29280 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87986 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6215619 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115099320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97925875 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154964 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213229367 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 51973 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3430536 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102566 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3394847 98.94% 98.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3394060 98.94% 98.94% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36476 1.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3431323 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2376326693 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3430536 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2377189197 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 558000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4188826435 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4188720502 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2020844355 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2021336108 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11830425 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12001413 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39636892 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39606873 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 3bffe858b..355e87caf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.814521 # Number of seconds simulated -sim_ticks 2814521286500 # Number of ticks simulated -final_tick 2814521286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.814515 # Number of seconds simulated +sim_ticks 2814515403000 # Number of ticks simulated +final_tick 2814515403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106354 # Simulator instruction rate (inst/s) -host_op_rate 129085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2558515098 # Simulator tick rate (ticks/s) -host_mem_usage 570360 # Number of bytes of host memory used -host_seconds 1100.06 # Real time elapsed on the host -sim_insts 116996192 # Number of instructions simulated -sim_ops 142001364 # Number of ops (including micro ops) simulated +host_inst_rate 109456 # Simulator instruction rate (inst/s) +host_op_rate 132849 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2632808896 # Simulator tick rate (ticks/s) +host_mem_usage 624704 # Number of bytes of host memory used +host_seconds 1069.02 # Real time elapsed on the host +sim_insts 117010217 # Number of instructions simulated +sim_ops 142017883 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 4288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 4416 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 746368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5095008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 629952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4708740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 748224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5094496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 629568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4721220 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11189732 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 746368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 629952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1376320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8426816 # Number of bytes written to this memory +system.physmem.bytes_read::total 11203044 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 748224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 629568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1377792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8429952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8444340 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 67 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8447476 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 69 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 80128 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 68 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 73575 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11691 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 80120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 64 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9837 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 73770 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175359 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131669 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175567 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131718 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1524 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1569 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 265185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1810257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 223822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1673016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 265845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1810079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 223686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1677454 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3975714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 223822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 489007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2994049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3980452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 223686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 489531 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2995170 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6223 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3000276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2994049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3001396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2995170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1569 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1816481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 223822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1673019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1816303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 223686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1677457 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6975990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175360 # Number of read requests accepted -system.physmem.writeReqs 172246 # Number of write requests accepted -system.physmem.readBursts 175360 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 172246 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11215872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 10651968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11189796 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10760884 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5779 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4663 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11102 # Per bank write bursts -system.physmem.perBankRdBursts::1 11119 # Per bank write bursts -system.physmem.perBankRdBursts::2 11680 # Per bank write bursts -system.physmem.perBankRdBursts::3 11222 # Per bank write bursts -system.physmem.perBankRdBursts::4 11370 # Per bank write bursts -system.physmem.perBankRdBursts::5 11380 # Per bank write bursts -system.physmem.perBankRdBursts::6 11917 # Per bank write bursts -system.physmem.perBankRdBursts::7 11794 # Per bank write bursts -system.physmem.perBankRdBursts::8 10207 # Per bank write bursts -system.physmem.perBankRdBursts::9 10426 # Per bank write bursts -system.physmem.perBankRdBursts::10 10580 # Per bank write bursts -system.physmem.perBankRdBursts::11 9765 # Per bank write bursts -system.physmem.perBankRdBursts::12 10349 # Per bank write bursts -system.physmem.perBankRdBursts::13 11405 # Per bank write bursts -system.physmem.perBankRdBursts::14 10639 # Per bank write bursts -system.physmem.perBankRdBursts::15 10293 # Per bank write bursts -system.physmem.perBankWrBursts::0 10392 # Per bank write bursts -system.physmem.perBankWrBursts::1 10480 # Per bank write bursts -system.physmem.perBankWrBursts::2 10999 # Per bank write bursts -system.physmem.perBankWrBursts::3 10520 # Per bank write bursts -system.physmem.perBankWrBursts::4 10645 # Per bank write bursts -system.physmem.perBankWrBursts::5 10713 # Per bank write bursts -system.physmem.perBankWrBursts::6 11169 # Per bank write bursts -system.physmem.perBankWrBursts::7 10762 # Per bank write bursts -system.physmem.perBankWrBursts::8 9958 # Per bank write bursts -system.physmem.perBankWrBursts::9 10000 # Per bank write bursts -system.physmem.perBankWrBursts::10 9968 # Per bank write bursts -system.physmem.perBankWrBursts::11 9745 # Per bank write bursts -system.physmem.perBankWrBursts::12 10100 # Per bank write bursts -system.physmem.perBankWrBursts::13 10962 # Per bank write bursts -system.physmem.perBankWrBursts::14 10229 # Per bank write bursts -system.physmem.perBankWrBursts::15 9795 # Per bank write bursts +system.physmem.bw_total::total 6981848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175568 # Number of read requests accepted +system.physmem.writeReqs 172295 # Number of write requests accepted +system.physmem.readBursts 175568 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 172295 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11229120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 10657088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11203108 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10764020 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5755 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4657 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11278 # Per bank write bursts +system.physmem.perBankRdBursts::1 11187 # Per bank write bursts +system.physmem.perBankRdBursts::2 11389 # Per bank write bursts +system.physmem.perBankRdBursts::3 10916 # Per bank write bursts +system.physmem.perBankRdBursts::4 11527 # Per bank write bursts +system.physmem.perBankRdBursts::5 11542 # Per bank write bursts +system.physmem.perBankRdBursts::6 11806 # Per bank write bursts +system.physmem.perBankRdBursts::7 11898 # Per bank write bursts +system.physmem.perBankRdBursts::8 10235 # Per bank write bursts +system.physmem.perBankRdBursts::9 10554 # Per bank write bursts +system.physmem.perBankRdBursts::10 10596 # Per bank write bursts +system.physmem.perBankRdBursts::11 9816 # Per bank write bursts +system.physmem.perBankRdBursts::12 10461 # Per bank write bursts +system.physmem.perBankRdBursts::13 11360 # Per bank write bursts +system.physmem.perBankRdBursts::14 10541 # Per bank write bursts +system.physmem.perBankRdBursts::15 10349 # Per bank write bursts +system.physmem.perBankWrBursts::0 10520 # Per bank write bursts +system.physmem.perBankWrBursts::1 10540 # Per bank write bursts +system.physmem.perBankWrBursts::2 10805 # Per bank write bursts +system.physmem.perBankWrBursts::3 10377 # Per bank write bursts +system.physmem.perBankWrBursts::4 10808 # Per bank write bursts +system.physmem.perBankWrBursts::5 10825 # Per bank write bursts +system.physmem.perBankWrBursts::6 10943 # Per bank write bursts +system.physmem.perBankWrBursts::7 10998 # Per bank write bursts +system.physmem.perBankWrBursts::8 9971 # Per bank write bursts +system.physmem.perBankWrBursts::9 10108 # Per bank write bursts +system.physmem.perBankWrBursts::10 9937 # Per bank write bursts +system.physmem.perBankWrBursts::11 9693 # Per bank write bursts +system.physmem.perBankWrBursts::12 10233 # Per bank write bursts +system.physmem.perBankWrBursts::13 10896 # Per bank write bursts +system.physmem.perBankWrBursts::14 10053 # Per bank write bursts +system.physmem.perBankWrBursts::15 9810 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2814521100500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2814515217000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 174805 # Read request sizes (log2) +system.physmem.readPktSize::6 175013 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167865 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 104183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167914 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 104295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -161,192 +161,199 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 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req see -system.physmem.wrQLenPdf::28 10200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10784 # What write queue length does an incoming req see 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does an incoming req see -system.physmem.wrQLenPdf::39 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 325.854595 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.388710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 345.406571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24509 36.52% 36.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15902 23.70% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6498 9.68% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3742 5.58% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2828 4.21% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1529 2.28% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1119 1.67% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1119 1.67% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9863 14.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67109 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.571869 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 462.936248 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7128 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::31 8036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.722260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.177109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 345.277059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24335 36.33% 36.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15823 23.62% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6599 9.85% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3701 5.52% 75.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2840 4.24% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1617 2.41% 81.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1134 1.69% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1090 1.63% 85.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9848 14.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66987 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.589488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 462.801411 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7132 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7131 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7131 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.339924 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.576956 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.763951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 15 0.21% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.10% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 3 0.04% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 7 0.10% 0.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5889 82.58% 83.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 114 1.60% 84.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 53 0.74% 85.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 224 3.14% 88.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 142 1.99% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 0.76% 91.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 26 0.36% 91.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 40 0.56% 92.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 124 1.74% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.15% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 11 0.15% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.15% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 24 0.34% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 13 0.18% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 13 0.18% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 32 0.45% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 59 0.83% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.13% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.08% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.13% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 92 1.29% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.07% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 8 0.11% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 98.23% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.338052 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.587494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.995044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 12 0.17% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.08% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 5 0.07% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 6 0.08% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5911 82.85% 83.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.54% 84.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 53 0.74% 85.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 225 3.15% 88.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 144 2.02% 90.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 50 0.70% 91.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 36 0.50% 91.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 29 0.41% 92.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 105 1.47% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.24% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.14% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.20% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 31 0.43% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 18 0.25% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.13% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 33 0.46% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 56 0.78% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.20% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.08% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 11 0.15% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 75 1.05% 97.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 8 0.11% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 14 0.20% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 98.23% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 17 0.24% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 14 0.20% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 38 0.53% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.13% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.13% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.10% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7131 # Writes before turning the bus around for reads -system.physmem.totQLat 2737638250 # Total ticks spent queuing -system.physmem.totMemAccLat 6023538250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 876240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15621.51 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::116-119 5 0.07% 98.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 6 0.08% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.07% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 32 0.45% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.10% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.08% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.07% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 7 0.10% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 9 0.13% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads +system.physmem.totQLat 2670855500 # Total ticks spent queuing +system.physmem.totMemAccLat 5960636750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 877275000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15222.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34371.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33972.45 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.79 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.98 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing -system.physmem.readRowHits 144870 # Number of row buffer hits during reads -system.physmem.writeRowHits 129705 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.92 # Row buffer hit rate for writes -system.physmem.avgGap 8096871.46 # Average gap between requests -system.physmem.pageHitRate 80.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2688100208500 # Time in different power states -system.physmem.memoryStateTime::REF 93982980000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32438087000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 267820560 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 239523480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 146132250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 130692375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 714347400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 652579200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 555206400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 523305360 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 183830708880 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 183830708880 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 78196283910 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 77193580095 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1620118404000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1620997968750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1883828903400 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1883568358140 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.325253 # Core power per rank (mW) -system.physmem.averagePower::1 669.232681 # Core power per rank (mW) +system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.20 # Average write queue length when enqueuing +system.physmem.readRowHits 145151 # Number of row buffer hits during reads +system.physmem.writeRowHits 129833 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes +system.physmem.avgGap 8090872.61 # Average gap between requests +system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 265386240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 144804000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 714027600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 556087680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 183830200320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 77881590900 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1620389778750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1883781875490 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.310395 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2695567326750 # Time in different power states +system.physmem_0.memoryStateTime::REF 93982720000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24965345250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 241035480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131517375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654513600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 522942480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 183830200320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 77208822180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1620979926750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1883568958185 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.234745 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2696551299250 # Time in different power states +system.physmem_1.memoryStateTime::REF 93982720000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23977600750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory @@ -365,16 +372,24 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 27454524 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14302225 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 560028 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 17144432 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12924274 # Number of BTB hits +system.cpu0.branchPred.lookups 27466718 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14314218 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 559197 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 17107445 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12928393 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 75.384673 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6779174 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 30579 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.571735 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6777363 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 30194 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -396,27 +411,104 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 58720 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 58720 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 19962 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14154 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 24604 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 34116 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 475.187595 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3075.067201 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 33369 97.81% 97.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 426 1.25% 99.06% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 228 0.67% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 49 0.14% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 15 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 6 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 34116 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12168.830173 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9642.893366 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7992.253434 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 3564 27.47% 27.47% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 6077 46.85% 74.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2864 22.08% 96.40% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::24576-32767 230 1.77% 98.17% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-40959 90 0.69% 98.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::40960-49151 115 0.89% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-57343 10 0.08% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::73728-81919 10 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-90111 4 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::90112-98303 2 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-106495 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 12972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 78620736948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.741175 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.458010 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 78549397948 99.91% 99.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 52259000 0.07% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 9664500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 3325500 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2093000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1088000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 676500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1423500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 291000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 117500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 73500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 71500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 138500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 55500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 55500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 78620736948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3790 68.96% 68.96% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1706 31.04% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5496 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58720 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58720 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5496 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5496 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 64216 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14369333 # DTB read hits -system.cpu0.dtb.read_misses 50679 # DTB read misses -system.cpu0.dtb.write_hits 10383293 # DTB write hits -system.cpu0.dtb.write_misses 7631 # DTB write misses +system.cpu0.dtb.read_hits 14377700 # DTB read hits +system.cpu0.dtb.read_misses 50689 # DTB read misses +system.cpu0.dtb.write_hits 10391095 # DTB write hits +system.cpu0.dtb.write_misses 8031 # DTB write misses system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3537 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1074 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1312 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1016 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1359 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14420012 # DTB read accesses -system.cpu0.dtb.write_accesses 10390924 # DTB write accesses +system.cpu0.dtb.perms_faults 592 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14428389 # DTB read accesses +system.cpu0.dtb.write_accesses 10399126 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24752626 # DTB hits -system.cpu0.dtb.misses 58310 # DTB misses -system.cpu0.dtb.accesses 24810936 # DTB accesses +system.cpu0.dtb.hits 24768795 # DTB hits +system.cpu0.dtb.misses 58720 # DTB misses +system.cpu0.dtb.accesses 24827515 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -438,158 +530,209 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 20633477 # ITB inst hits -system.cpu0.itb.inst_misses 8891 # ITB inst misses +system.cpu0.itb.walker.walks 8876 # Table walker walks requested +system.cpu0.itb.walker.walksShort 8876 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3394 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5333 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 149 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 8727 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1034.949009 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 4440.773831 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 8334 95.50% 95.50% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 202 2.31% 97.81% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 114 1.31% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 44 0.50% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 18 0.21% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 9 0.10% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 3 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 8727 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2584 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12070.828560 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9384.773588 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7691.454372 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 754 29.18% 29.18% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1107 42.84% 72.02% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 648 25.08% 97.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 49 1.90% 98.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 17 0.66% 99.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 4 0.15% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.12% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::73728-81919 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2584 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 31375770192 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.875900 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.330034 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3896845928 12.42% 12.42% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 27476174764 87.57% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2435000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 275000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 39500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 31375770192 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1855 76.18% 76.18% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 580 23.82% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2435 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2435 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2435 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 11311 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 20634228 # ITB inst hits +system.cpu0.itb.inst_misses 8876 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2375 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2373 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1486 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1477 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20642368 # ITB inst accesses -system.cpu0.itb.hits 20633477 # DTB hits -system.cpu0.itb.misses 8891 # DTB misses -system.cpu0.itb.accesses 20642368 # DTB accesses -system.cpu0.numCycles 108176623 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20643104 # ITB inst accesses +system.cpu0.itb.hits 20634228 # DTB hits +system.cpu0.itb.misses 8876 # DTB misses +system.cpu0.itb.accesses 20643104 # DTB accesses +system.cpu0.numCycles 108167671 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 40839610 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 106163283 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 27454524 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19703448 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 62043143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3268003 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 133218 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 6760 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 444 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 566983 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 143911 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 303 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20632158 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 383201 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3475 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 105368337 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.210422 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.308267 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 40851007 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 106236775 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 27466718 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19705756 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 62062972 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3267693 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 153669 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 7048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 432 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 489783 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 144519 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20632894 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 382391 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3679 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 105343442 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.211364 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.309053 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 76140836 72.26% 72.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3909718 3.71% 75.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2409828 2.29% 78.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8201309 7.78% 86.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1666024 1.58% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1066995 1.01% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6252269 5.93% 94.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1076692 1.02% 95.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4644666 4.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 76103279 72.24% 72.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3910098 3.71% 75.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2412212 2.29% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8199484 7.78% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1671331 1.59% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1069053 1.01% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6251821 5.93% 94.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1074556 1.02% 95.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4651608 4.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 105368337 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.253794 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.981388 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 28207041 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58279935 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15901267 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1497528 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1482288 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1929977 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 153844 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 87989191 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 497994 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1482288 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 29073693 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7845343 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 44593101 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16518954 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 5854664 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 84134111 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 3122 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1216605 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 229511 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3673419 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 86811691 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 387318144 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 93734921 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6132 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72788537 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14023138 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1551068 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1456111 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8913232 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 15130036 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11520954 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1958410 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2751427 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 80936298 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1061855 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 77564111 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 93737 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10215309 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 25112322 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 116543 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 105368337 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.736124 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.430465 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 105343442 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.253927 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.982149 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 28225112 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58231710 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15904811 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1498973 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1482577 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1930879 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 153387 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 88028064 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 497001 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1482577 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 29091969 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7814173 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 44573853 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16523893 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 5856699 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 84168015 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2790 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1211369 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 234681 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3674238 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 86834114 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 387462225 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 93765985 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6215 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72808994 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14025104 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1551576 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1456348 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8924255 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 15135142 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11528605 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1955130 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2746979 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 80972727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1061733 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 77600115 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 93477 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10225467 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 25113988 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 116264 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 105343442 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.736639 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.430545 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74478008 70.68% 70.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10230371 9.71% 80.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7904463 7.50% 87.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6602787 6.27% 94.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2340926 2.22% 96.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1499410 1.42% 97.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1574332 1.49% 99.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 494613 0.47% 99.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 243427 0.23% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74430085 70.65% 70.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10248464 9.73% 80.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7900647 7.50% 87.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6607763 6.27% 94.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2341378 2.22% 96.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1506364 1.43% 97.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1572871 1.49% 99.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 494450 0.47% 99.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 241420 0.23% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 105368337 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 105343442 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 114999 10.01% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 537121 46.77% 56.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 496300 43.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 114775 10.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 538516 46.90% 56.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 494955 43.11% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2212 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 51748002 66.72% 66.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57664 0.07% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2213 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 51768146 66.71% 66.71% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57542 0.07% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued @@ -612,411 +755,411 @@ system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.79% # Ty system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4488 0.01% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14779498 19.05% 85.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10972237 14.15% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4481 0.01% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14787493 19.06% 85.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10980227 14.15% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 77564111 # Type of FU issued -system.cpu0.iq.rate 0.717014 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1148423 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014806 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 261725178 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 92258450 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 75089604 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 13541 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7156 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5898 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 78703023 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7299 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 349741 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 77600115 # Type of FU issued +system.cpu0.iq.rate 0.717406 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1148249 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014797 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 261771758 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 92305365 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 75123288 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 13640 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7254 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5910 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 78738792 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7359 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 349889 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2246191 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2538 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53151 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1141086 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2246274 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2500 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 53675 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1142950 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 210404 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 206292 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 210780 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 206750 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1482288 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5387849 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2181647 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 82121235 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 133747 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 15130036 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11520954 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 554131 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44613 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2124772 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53151 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 259624 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 223920 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 483544 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 76945762 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14537604 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 560147 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1482577 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5380945 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2158862 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 82157406 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 132522 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 15135142 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11528605 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 554173 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44324 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2102450 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 53675 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 259338 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 224546 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 483884 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 76981591 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14546003 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 559940 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 123082 # number of nop insts executed -system.cpu0.iew.exec_refs 25403316 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14507602 # Number of branches executed -system.cpu0.iew.exec_stores 10865712 # Number of stores executed -system.cpu0.iew.exec_rate 0.711298 # Inst execution rate -system.cpu0.iew.wb_sent 76276982 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 75095502 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 39231378 # num instructions producing a value -system.cpu0.iew.wb_consumers 67987446 # num instructions consuming a value +system.cpu0.iew.exec_nop 122946 # number of nop insts executed +system.cpu0.iew.exec_refs 25419191 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14512373 # Number of branches executed +system.cpu0.iew.exec_stores 10873188 # Number of stores executed +system.cpu0.iew.exec_rate 0.711688 # Inst execution rate +system.cpu0.iew.wb_sent 76311316 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 75129198 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 39246313 # num instructions producing a value +system.cpu0.iew.wb_consumers 68010606 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.694193 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.577039 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.694562 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.577062 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11493235 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 945312 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 408278 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102784889 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.686324 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.576953 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11503261 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 945469 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 407891 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102758261 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.686747 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.577053 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75343720 73.30% 73.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12296354 11.96% 85.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6287520 6.12% 91.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2655547 2.58% 93.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1297923 1.26% 95.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 837088 0.81% 96.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1893538 1.84% 97.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 418210 0.41% 98.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1754989 1.71% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 75291319 73.27% 73.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12321005 11.99% 85.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6288153 6.12% 91.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2655881 2.58% 93.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1298740 1.26% 95.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 839233 0.82% 96.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1891164 1.84% 97.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 416236 0.41% 98.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1756530 1.71% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102784889 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 58163617 # Number of instructions committed -system.cpu0.commit.committedOps 70543777 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102758261 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 58183568 # Number of instructions committed +system.cpu0.commit.committedOps 70568955 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23263713 # Number of memory references committed -system.cpu0.commit.loads 12883845 # Number of loads committed -system.cpu0.commit.membars 375648 # Number of memory barriers committed -system.cpu0.commit.branches 13703294 # Number of branches committed -system.cpu0.commit.fp_insts 5822 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61764808 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2662565 # Number of function calls committed. +system.cpu0.commit.refs 23274523 # Number of memory references committed +system.cpu0.commit.loads 12888868 # Number of loads committed +system.cpu0.commit.membars 375842 # Number of memory barriers committed +system.cpu0.commit.branches 13706650 # Number of branches committed +system.cpu0.commit.fp_insts 5838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 61788721 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2663542 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 47219648 66.94% 66.94% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55928 0.08% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4488 0.01% 67.02% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 47234123 66.93% 66.93% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55828 0.08% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4481 0.01% 67.02% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.02% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.02% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12883845 18.26% 85.29% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10379868 14.71% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12888868 18.26% 85.28% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10385655 14.72% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70543777 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1754989 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 70568955 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1756530 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 170407355 # The number of ROB reads -system.cpu0.rob.rob_writes 166661887 # The number of ROB writes -system.cpu0.timesIdled 403384 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2808286 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2462180041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 58092959 # Number of Instructions Simulated -system.cpu0.committedOps 70473119 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.862130 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.862130 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.537020 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.537020 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 83669019 # number of integer regfile reads -system.cpu0.int_regfile_writes 47858513 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16561 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13070 # number of floating regfile writes -system.cpu0.cc_regfile_reads 272007090 # number of cc regfile reads -system.cpu0.cc_regfile_writes 28371958 # number of cc regfile writes -system.cpu0.misc_regfile_reads 192053211 # number of misc regfile reads -system.cpu0.misc_regfile_writes 725022 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 853093 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984491 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42526051 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 853605 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.819356 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 170410924 # The number of ROB reads +system.cpu0.rob.rob_writes 166734025 # The number of ROB writes +system.cpu0.timesIdled 403289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2824229 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2462180705 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 58113002 # Number of Instructions Simulated +system.cpu0.committedOps 70498389 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.861333 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.861333 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.537249 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.537249 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 83710036 # number of integer regfile reads +system.cpu0.int_regfile_writes 47877732 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16593 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13071 # number of floating regfile writes +system.cpu0.cc_regfile_reads 272135235 # number of cc regfile reads +system.cpu0.cc_regfile_writes 28380305 # number of cc regfile writes +system.cpu0.misc_regfile_reads 192072102 # number of misc regfile reads +system.cpu0.misc_regfile_writes 725098 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 853107 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984634 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42535549 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 853619 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.829665 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 331.074612 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 180.909879 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.646630 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.353340 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 327.353563 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 184.631071 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.639362 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.360608 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189920314 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189920314 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12675400 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12670649 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25346049 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7759190 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8148697 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15907887 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181607 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180873 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 362480 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209218 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 237638 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446856 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 215214 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 244406 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459620 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20434590 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20819346 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41253936 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20616197 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21000219 # number of overall hits -system.cpu0.dcache.overall_hits::total 41616416 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 429328 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 400663 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 829991 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1922864 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1781286 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3704150 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 97758 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84121 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 181879 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13488 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14194 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27682 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 28 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 50 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 189955198 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189955198 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12681674 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12667533 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25349207 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7766233 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8148068 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15914301 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181732 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 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SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 121798 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4093 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5239 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9332 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 30 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 48 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 78 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 368071 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 357585 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 725656 # number of demand (read+write) MSHR misses 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cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 894015008 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1872436267 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46952751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79934003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 126886754 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 536492 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 753484 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 368098 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 357250 # number of demand (read+write) MSHR misses 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-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9599504714 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9164100290 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 18763605004 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10577925973 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10058115298 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 20636041271 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3170222000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2614349000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784571000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2418015877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2018079000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436094877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5588237877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4632428000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220665877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016308 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016242 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016275 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015943 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014630 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015279 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229359 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.217205 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223443 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017732 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020772 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019345 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000205 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9579661994 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9114622349 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18694284343 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10554816504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10014883855 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 20569700359 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3162299001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2622267000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784566001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2409236377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2026898500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436134877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5571535378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4649165500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220700878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016314 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016231 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016273 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015916 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014619 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015259 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228971 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.217977 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223626 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020800 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019653 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000139 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000196 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000170 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016153 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015546 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015848 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018735 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017843 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018287 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13478.219605 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13806.770002 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13641.954947 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43527.537428 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42902.554244 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43224.521409 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15269.937714 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15532.419612 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15394.146876 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11889.782477 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15280.826419 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13822.086492 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19160.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15069.680000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016145 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015839 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018726 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017839 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018281 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13459.810248 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13814.398698 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13636.369151 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43455.547807 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42615.796337 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43048.411223 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15217.292063 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15598.127140 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15397.757073 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11710.603714 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15295.572056 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13723.210780 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19449.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14718.458333 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26080.578785 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25627.753653 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25857.437965 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24477.667207 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24228.073936 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24355.374932 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26024.759694 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25513.288591 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25772.848816 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24422.269665 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24134.227515 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24281.175097 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1027,150 +1170,158 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 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+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49454750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49454750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 49454750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047509 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047029 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047270 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047509 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047029 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047270 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047509 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047029 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047270 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11973.159294 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.872103 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11939.242579 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11973.159294 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.872103 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11939.242579 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11973.159294 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.872103 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11939.242579 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27255758 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14164958 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 545624 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17245755 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 12796801 # Number of BTB hits +system.cpu1.branchPred.lookups 27252662 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14161158 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 545075 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17238794 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 12795126 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.202614 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6756979 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29539 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.222860 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6755804 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29339 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1192,27 +1343,102 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 58706 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 58706 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19477 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14176 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25053 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 33653 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 557.840311 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3475.112155 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-8191 32827 97.55% 97.55% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-16383 501 1.49% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-24575 206 0.61% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-32767 52 0.15% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-40959 23 0.07% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-49151 18 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-57343 14 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-73727 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::81920-90111 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::90112-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-106495 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 33653 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 11554 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10457.034101 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8151.140813 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7042.402736 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 4078 35.30% 35.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5524 47.81% 83.11% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1648 14.26% 97.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 166 1.44% 98.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 76 0.66% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 59 0.51% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 11554 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 82024244244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.681515 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.487291 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 81955384244 99.92% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 50513000 0.06% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 9145000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 3183000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 1958500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1084000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 660000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 995500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 376500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 124000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 98500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 69500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 91500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 76000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 274000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 211000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 82024244244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3372 68.52% 68.52% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1549 31.48% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 4921 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58706 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58706 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 4921 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 4921 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 63627 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14301761 # DTB read hits -system.cpu1.dtb.read_misses 48555 # DTB read misses -system.cpu1.dtb.write_hits 10652785 # DTB write hits -system.cpu1.dtb.write_misses 10002 # DTB write misses +system.cpu1.dtb.read_hits 14299827 # DTB read hits +system.cpu1.dtb.read_misses 48713 # DTB read misses +system.cpu1.dtb.write_hits 10649623 # DTB write hits +system.cpu1.dtb.write_misses 9993 # DTB write misses system.cpu1.dtb.flush_tlb 175 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3340 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3345 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 749 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1278 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1307 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 539 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14350316 # DTB read accesses -system.cpu1.dtb.write_accesses 10662787 # DTB write accesses +system.cpu1.dtb.perms_faults 516 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14348540 # DTB read accesses +system.cpu1.dtb.write_accesses 10659616 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 24954546 # DTB hits -system.cpu1.dtb.misses 58557 # DTB misses -system.cpu1.dtb.accesses 25013103 # DTB accesses +system.cpu1.dtb.hits 24949450 # DTB hits +system.cpu1.dtb.misses 58706 # DTB misses +system.cpu1.dtb.accesses 25008156 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1234,329 +1460,386 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20573712 # ITB inst hits -system.cpu1.itb.inst_misses 7567 # ITB inst misses +system.cpu1.itb.walker.walks 7607 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7607 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2551 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4918 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 138 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 7469 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1253.983130 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 5505.331618 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 7086 94.87% 94.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 200 2.68% 97.55% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 109 1.46% 99.01% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 32 0.43% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 14 0.19% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 11 0.15% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 6 0.08% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 6 0.08% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-90111 3 0.04% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::106496-114687 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 7469 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2377 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11683.850652 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8982.900240 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7620.243918 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 698 29.36% 29.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 50 2.10% 31.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 916 38.54% 70.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 82 3.45% 73.45% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 34 1.43% 74.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 536 22.55% 97.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 1.09% 98.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.17% 98.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 7 0.29% 98.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 17 0.72% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 6 0.25% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2377 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 26182117896 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.680154 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.466824 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 8377919500 32.00% 32.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 17801455396 67.99% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2155000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 325500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 194500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 68000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 26182117896 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1688 75.39% 75.39% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 551 24.61% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2239 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7607 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7607 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2239 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2239 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 9846 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20569517 # ITB inst hits +system.cpu1.itb.inst_misses 7607 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 175 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2209 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2207 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1224 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1289 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20581279 # ITB inst accesses -system.cpu1.itb.hits 20573712 # DTB hits -system.cpu1.itb.misses 7567 # DTB misses -system.cpu1.itb.accesses 20581279 # DTB accesses -system.cpu1.numCycles 106992745 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20577124 # ITB inst accesses +system.cpu1.itb.hits 20569517 # DTB hits +system.cpu1.itb.misses 7607 # DTB misses +system.cpu1.itb.accesses 20577124 # DTB accesses +system.cpu1.numCycles 107002102 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40476291 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 106336791 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27255758 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19553780 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 61749013 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3214085 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 109935 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 4125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 398 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 310457 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 137038 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20572028 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 377209 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3305 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104394378 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.225923 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.323476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40500350 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 106310459 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27252662 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19550930 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 61683449 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3213099 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 111780 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 3981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 436 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 347701 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 135656 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 234 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20567798 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 376508 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3292 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104390100 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.225611 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.323253 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 75141351 71.98% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3905835 3.74% 75.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2486724 2.38% 78.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8099869 7.76% 85.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1581267 1.51% 87.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1170303 1.12% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6153110 5.89% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1141979 1.09% 95.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4713940 4.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 75144035 71.98% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3907124 3.74% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2485008 2.38% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8099840 7.76% 85.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1578542 1.51% 87.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1169165 1.12% 88.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6151960 5.89% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1142182 1.09% 95.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4712244 4.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104394378 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.254744 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.993869 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27669699 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57891094 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15657559 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1717451 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1458318 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1956668 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 150768 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 88739686 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 487490 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1458318 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28613011 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6694397 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 45325373 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16423590 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 5879419 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 84880856 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2064 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1581177 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 275105 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 3240122 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 87684483 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 391488803 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 94864107 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5764 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 73992323 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13692160 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1588753 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1487965 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10049323 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15109971 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11816534 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2163704 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2733219 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 81632312 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1156422 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78295274 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93656 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9981310 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25207475 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 106198 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104394378 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.749995 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.429509 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104390100 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.254693 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.993536 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27682693 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 57882458 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15650277 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1716894 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1457466 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1955529 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 151159 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 88694873 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 489106 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1457466 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28625802 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6604433 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 45361321 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16416425 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 5924344 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 84834346 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2307 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1574765 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 278233 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 3285499 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 87641847 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 391276070 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 94803920 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5749 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 73988395 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13653452 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1589936 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1488982 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10049361 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15102779 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11808907 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2150791 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2768917 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 81595404 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1156818 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78284353 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93210 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9952134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25073057 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 106330 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104390100 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.749921 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.429238 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72878860 69.81% 69.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10639333 10.19% 80.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8017923 7.68% 87.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6659758 6.38% 94.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2479715 2.38% 96.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1538380 1.47% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1459445 1.40% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 494321 0.47% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 226643 0.22% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72870740 69.81% 69.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10640655 10.19% 80.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8029126 7.69% 87.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6654786 6.37% 94.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2478739 2.37% 96.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1537519 1.47% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1459463 1.40% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 490817 0.47% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 228255 0.22% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104394378 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104390100 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 101103 8.77% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 535174 46.44% 55.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 516045 44.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 100798 8.75% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 535574 46.51% 55.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 515204 44.74% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 125 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52268288 66.76% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59024 0.08% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.83% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4106 0.01% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 124 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52262651 66.76% 66.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59116 0.08% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4115 0.01% 66.84% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14700600 18.78% 85.61% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11263124 14.39% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 1 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14698419 18.78% 85.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11259924 14.38% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78295274 # Type of FU issued -system.cpu1.iq.rate 0.731781 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1152326 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014718 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 262217922 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 92814464 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 75924804 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12986 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6859 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5648 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79440457 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7018 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 366358 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78284353 # Type of FU issued +system.cpu1.iq.rate 0.731615 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1151580 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014710 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 262190696 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 92748647 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 75915598 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12900 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6883 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5649 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79428849 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6960 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 366149 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2171723 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2780 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 52487 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1144439 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2166601 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2614 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 52391 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1139774 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 191401 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 154292 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 191651 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 153600 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1458318 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4304329 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2156600 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 82933418 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 134740 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15109971 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11816534 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 582996 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 47778 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2096463 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 52487 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 251579 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 218702 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 470281 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 77694436 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14463933 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 542445 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1457466 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4280991 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2091777 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 82896193 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132170 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15102779 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11808907 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 583505 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 47325 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2032029 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 52391 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 250395 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 218336 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 468731 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 77684491 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14461832 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 541313 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 144684 # number of nop insts executed -system.cpu1.iew.exec_refs 25618626 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14454326 # Number of branches executed -system.cpu1.iew.exec_stores 11154693 # Number of stores executed -system.cpu1.iew.exec_rate 0.726165 # Inst execution rate -system.cpu1.iew.wb_sent 77075073 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 75930452 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39739983 # num instructions producing a value -system.cpu1.iew.wb_consumers 69711076 # num instructions consuming a value +system.cpu1.iew.exec_nop 143971 # number of nop insts executed +system.cpu1.iew.exec_refs 25613639 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14454387 # Number of branches executed +system.cpu1.iew.exec_stores 11151807 # Number of stores executed +system.cpu1.iew.exec_rate 0.726009 # Inst execution rate +system.cpu1.iew.wb_sent 77065601 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 75921247 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39733715 # num instructions producing a value +system.cpu1.iew.wb_consumers 69689049 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.709679 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570067 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.709530 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570157 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11308333 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1050224 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 396863 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 101852612 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703099 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.586744 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11280608 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1050488 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 395955 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 101852201 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.703017 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.586598 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73894552 72.55% 72.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12525380 12.30% 84.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6426003 6.31% 91.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2662589 2.61% 93.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1410437 1.38% 95.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 930996 0.91% 96.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1822810 1.79% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 425009 0.42% 98.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1754836 1.72% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73888394 72.54% 72.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12531229 12.30% 84.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6432271 6.32% 91.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2665520 2.62% 93.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1405579 1.38% 95.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 922819 0.91% 96.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1826114 1.79% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 423793 0.42% 98.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1756482 1.72% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 101852612 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 58987480 # Number of instructions committed -system.cpu1.commit.committedOps 71612492 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 101852201 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 58981554 # Number of instructions committed +system.cpu1.commit.committedOps 71603833 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23610343 # Number of memory references committed -system.cpu1.commit.loads 12938248 # Number of loads committed -system.cpu1.commit.membars 439261 # Number of memory barriers committed -system.cpu1.commit.branches 13694369 # Number of branches committed -system.cpu1.commit.fp_insts 5606 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 62760739 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2679383 # Number of function calls committed. +system.cpu1.commit.refs 23605311 # Number of memory references committed +system.cpu1.commit.loads 12936178 # Number of loads committed +system.cpu1.commit.membars 439363 # Number of memory barriers committed +system.cpu1.commit.branches 13694258 # Number of branches committed +system.cpu1.commit.fp_insts 5590 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 62751370 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2679190 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 47940825 66.94% 66.94% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57221 0.08% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.02% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4103 0.01% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 47937101 66.95% 66.95% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57311 0.08% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4110 0.01% 67.03% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 12938248 18.07% 85.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10672095 14.90% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 12936178 18.07% 85.10% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10669133 14.90% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71612492 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1754836 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 71603833 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1756482 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170535238 # The number of ROB reads -system.cpu1.rob.rob_writes 168387616 # The number of ROB writes -system.cpu1.timesIdled 388789 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2598367 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2951659136 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 58903233 # Number of Instructions Simulated -system.cpu1.committedOps 71528245 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.816415 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.816415 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550535 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550535 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84575323 # number of integer regfile reads -system.cpu1.int_regfile_writes 48329446 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16299 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13042 # number of floating regfile writes -system.cpu1.cc_regfile_reads 274393748 # number of cc regfile reads -system.cpu1.cc_regfile_writes 28845956 # number of cc regfile writes -system.cpu1.misc_regfile_reads 191595742 # number of misc regfile reads -system.cpu1.misc_regfile_writes 795775 # number of misc regfile writes +system.cpu1.rob.rob_reads 170496195 # The number of ROB reads +system.cpu1.rob.rob_writes 168311101 # The number of ROB writes +system.cpu1.timesIdled 389572 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2612002 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2951648369 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 58897215 # Number of Instructions Simulated +system.cpu1.committedOps 71519494 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.816760 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.816760 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550430 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550430 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84567520 # number of integer regfile reads +system.cpu1.int_regfile_writes 48323955 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16256 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13038 # number of floating regfile writes +system.cpu1.cc_regfile_reads 274360839 # number of cc regfile reads +system.cpu1.cc_regfile_writes 28850413 # number of cc regfile writes +system.cpu1.misc_regfile_reads 191580382 # number of misc regfile reads +system.cpu1.misc_regfile_writes 795927 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30210 # Transaction distribution system.iobus.trans_dist::ReadResp 30210 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution @@ -1652,21 +1935,21 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347069959 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347059161 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36834574 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36834571 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36411 # number of replacements -system.iocache.tags.tagsinuse 1.036467 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.036460 # Cycle average of tags in use system.iocache.tags.total_refs 28 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36427 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000769 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234012835000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.036467 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 234008190000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.036460 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.064779 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.064779 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1684,14 +1967,14 @@ system.iocache.demand_misses::realview.ide 249 # system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29650777 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29650777 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9620896608 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9620896608 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29650777 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29650777 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29650777 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29650777 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29657377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29657377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617288213 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9617288213 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29657377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29657377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29657377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29657377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1708,19 +1991,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119079.425703 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119079.425703 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265792.651546 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265792.651546 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119079.425703 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119079.425703 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119079.425703 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119079.425703 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56505 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 119105.931727 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119105.931727 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265692.963864 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265692.963864 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119105.931727 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119105.931727 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119105.931727 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119105.931727 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56457 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7228 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7214 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.817515 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.826033 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1734,14 +2017,14 @@ system.iocache.demand_mshr_misses::realview.ide 249 system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16701777 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16701777 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7738504756 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7738504756 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16701777 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16701777 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16701777 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16701777 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16708377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16708377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7734902355 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7734902355 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16708377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16708377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16708377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16708377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.999255 # mshr miss rate for WriteInvalidateReq accesses @@ -1750,258 +2033,258 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67075.409639 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67075.409639 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213788.566898 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213788.566898 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67075.409639 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67075.409639 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67075.409639 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67075.409639 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67101.915663 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67101.915663 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213689.044810 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213689.044810 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67101.915663 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67101.915663 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67101.915663 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67101.915663 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104261 # number of replacements -system.l2c.tags.tagsinuse 65126.190512 # Cycle average of tags in use -system.l2c.tags.total_refs 3112631 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169500 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.363605 # Average number of references to valid blocks. +system.l2c.tags.replacements 104467 # number of replacements +system.l2c.tags.tagsinuse 65129.957708 # Cycle average of tags in use +system.l2c.tags.total_refs 3116952 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169707 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.366667 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48604.861621 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.289581 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48713.108693 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.622899 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5571.225601 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2881.829872 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 43.411642 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4982.002827 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2994.569133 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741651 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000737 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5546.203044 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2803.513756 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 43.406508 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4962.784204 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3012.318369 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.743303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000742 # Average percentage of cache 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latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71153.569434 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 65815.992635 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.127916 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.450387 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10084.454182 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20050.800000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63329.770854 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67668.248940 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63649.761155 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71117.808078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 66017.778848 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10186.979971 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10096.098756 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18417.500000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13866.307692 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64141.581463 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65701.749106 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64881.275293 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13885.538462 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.019186 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64881.384750 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64334.531244 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62789.275336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64510.303765 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66293.042370 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 65072.025171 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66817.164179 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63329.770854 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64165.472427 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63649.761155 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65562.364403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64678.034623 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62789.275336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64510.303765 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65595.588235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62958.583037 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66293.042370 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 65072.025171 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63329.770854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64165.472427 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63649.761155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65562.364403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64678.034623 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -2182,57 +2465,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68031 # Transaction distribution -system.membus.trans_dist::ReadResp 68030 # Transaction distribution +system.membus.trans_dist::ReadReq 68075 # Transaction distribution +system.membus.trans_dist::ReadResp 68074 # Transaction distribution system.membus.trans_dist::WriteReq 27609 # Transaction distribution system.membus.trans_dist::WriteResp 27609 # Transaction distribution -system.membus.trans_dist::Writeback 131669 # Transaction distribution +system.membus.trans_dist::Writeback 131718 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36196 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4639 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4633 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4665 # Transaction distribution -system.membus.trans_dist::ReadExReq 138446 # Transaction distribution -system.membus.trans_dist::ReadExResp 138446 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4659 # Transaction distribution +system.membus.trans_dist::ReadExReq 138608 # Transaction distribution +system.membus.trans_dist::ReadExResp 138608 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465023 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572669 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108820 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681489 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17318744 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17482733 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17335192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17499181 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631872 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4631872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22114605 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 524 # Total snoops (count) -system.membus.snoop_fanout::samples 347207 # Request fanout histogram +system.membus.pkt_size::total 22131053 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 522 # Total snoops (count) +system.membus.snoop_fanout::samples 347455 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 347207 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 347455 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 347207 # Request fanout histogram -system.membus.reqLayer0.occupancy 81506999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 347455 # Request fanout histogram +system.membus.reqLayer0.occupancy 81552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1714000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1759264748 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1759525499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1730266590 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1732085345 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38512426 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38509429 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2265,54 +2548,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2657108 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2657013 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2659236 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2659139 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27609 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27609 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 704003 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 703765 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2844 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2841 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 78 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296844 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296844 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3893099 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2534750 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42773 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169663 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6640285 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124570688 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99881325 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 294780 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224812737 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 68939 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3665274 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.009944 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.099221 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2918 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296507 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296507 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3896051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2534528 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43103 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 170141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6643823 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124664384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99866733 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 66624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 296168 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224893909 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 68735 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3666824 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.009939 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099200 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3628828 99.01% 99.01% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3630378 99.01% 99.01% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36446 0.99% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3665274 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4674358232 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3666824 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4674174231 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 697500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 688500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 8766890883 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 8773601584 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3912089949 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3912223359 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26359345 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26520841 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96778607 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96916821 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3042 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 120ee67e1..15d0bc0bd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.904915 # Number of seconds simulated -sim_ticks 2904914753500 # Number of ticks simulated -final_tick 2904914753500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.904914 # Number of seconds simulated +sim_ticks 2904913754500 # Number of ticks simulated +final_tick 2904913754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 754235 # Simulator instruction rate (inst/s) -host_op_rate 909375 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19474929667 # Simulator tick rate (ticks/s) -host_mem_usage 559844 # Number of bytes of host memory used -host_seconds 149.16 # Real time elapsed on the host -sim_insts 112502966 # Number of instructions simulated -sim_ops 135643907 # Number of ops (including micro ops) simulated +host_inst_rate 719084 # Simulator instruction rate (inst/s) +host_op_rate 866994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18567568294 # Simulator tick rate (ticks/s) +host_mem_usage 616260 # Number of bytes of host memory used +host_seconds 156.45 # Real time elapsed on the host +sim_insts 112501381 # Number of instructions simulated +sim_ops 135642071 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 552740 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4263328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 553252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4270880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 636352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4758276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 635584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4758596 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10212232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 552740 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 636352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189092 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7616448 # Number of bytes written to this memory +system.physmem.bytes_read::total 10219848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 553252 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 635584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1188836 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7620224 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7633972 # Number of bytes written to this memory +system.physmem.bytes_written::total 7637748 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17098 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67251 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9943 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74349 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74354 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168539 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119007 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168658 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119066 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123388 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123447 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1467626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1470226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 219060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1638009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 218796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1638120 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3515501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 219060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2621918 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3518124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 218796 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2623219 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2627950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2621918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2629251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2623219 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1473656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1476256 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 219060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1638012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 218796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1638122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6143452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168539 # Number of read requests accepted -system.physmem.writeReqs 159612 # Number of write requests accepted -system.physmem.readBursts 168539 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159612 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10780160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue -system.physmem.bytesWritten 9866880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10212232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9952308 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5435 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 6147376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168658 # Number of read requests accepted +system.physmem.writeReqs 159671 # Number of write requests accepted +system.physmem.readBursts 168658 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159671 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10788160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 9869632 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10219848 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9956084 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5450 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4495 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9752 # Per bank write bursts -system.physmem.perBankRdBursts::1 9630 # Per bank write bursts -system.physmem.perBankRdBursts::2 10293 # Per bank write bursts -system.physmem.perBankRdBursts::3 9989 # Per bank write bursts -system.physmem.perBankRdBursts::4 18671 # Per bank write bursts +system.physmem.perBankRdBursts::0 9771 # Per bank write bursts +system.physmem.perBankRdBursts::1 9508 # Per bank write bursts +system.physmem.perBankRdBursts::2 10210 # Per bank write bursts +system.physmem.perBankRdBursts::3 9949 # Per bank write bursts +system.physmem.perBankRdBursts::4 18798 # Per bank write bursts system.physmem.perBankRdBursts::5 10140 # Per bank write bursts -system.physmem.perBankRdBursts::6 10341 # Per bank write bursts -system.physmem.perBankRdBursts::7 10423 # Per bank write bursts +system.physmem.perBankRdBursts::6 10351 # Per bank write bursts +system.physmem.perBankRdBursts::7 10416 # Per bank write bursts system.physmem.perBankRdBursts::8 9932 # Per bank write bursts -system.physmem.perBankRdBursts::9 10445 # Per bank write bursts -system.physmem.perBankRdBursts::10 9791 # Per bank write bursts -system.physmem.perBankRdBursts::11 9555 # Per bank write bursts -system.physmem.perBankRdBursts::12 9939 # Per bank write bursts -system.physmem.perBankRdBursts::13 9802 # Per bank write bursts +system.physmem.perBankRdBursts::9 10416 # Per bank write bursts +system.physmem.perBankRdBursts::10 9794 # Per bank write bursts +system.physmem.perBankRdBursts::11 9556 # Per bank write bursts +system.physmem.perBankRdBursts::12 10053 # Per bank write bursts +system.physmem.perBankRdBursts::13 9934 # Per bank write bursts system.physmem.perBankRdBursts::14 9961 # Per bank write bursts system.physmem.perBankRdBursts::15 9776 # Per bank write bursts -system.physmem.perBankWrBursts::0 9466 # Per bank write bursts -system.physmem.perBankWrBursts::1 9312 # Per bank write bursts -system.physmem.perBankWrBursts::2 10445 # Per bank write bursts -system.physmem.perBankWrBursts::3 9717 # Per bank write bursts -system.physmem.perBankWrBursts::4 9000 # Per bank write bursts -system.physmem.perBankWrBursts::5 9463 # Per bank write bursts -system.physmem.perBankWrBursts::6 9580 # Per bank write bursts -system.physmem.perBankWrBursts::7 9878 # Per bank write bursts -system.physmem.perBankWrBursts::8 9939 # Per bank write bursts -system.physmem.perBankWrBursts::9 10290 # Per bank write bursts -system.physmem.perBankWrBursts::10 9717 # Per bank write bursts -system.physmem.perBankWrBursts::11 9744 # Per bank write bursts -system.physmem.perBankWrBursts::12 9808 # Per bank write bursts -system.physmem.perBankWrBursts::13 9372 # Per bank write bursts -system.physmem.perBankWrBursts::14 9292 # Per bank write bursts -system.physmem.perBankWrBursts::15 9147 # Per bank write bursts +system.physmem.perBankWrBursts::0 9468 # Per bank write bursts +system.physmem.perBankWrBursts::1 9241 # Per bank write bursts +system.physmem.perBankWrBursts::2 10223 # Per bank write bursts +system.physmem.perBankWrBursts::3 9791 # Per bank write bursts +system.physmem.perBankWrBursts::4 9126 # Per bank write bursts +system.physmem.perBankWrBursts::5 9458 # Per bank write bursts +system.physmem.perBankWrBursts::6 9597 # Per bank write bursts +system.physmem.perBankWrBursts::7 9810 # Per bank write bursts +system.physmem.perBankWrBursts::8 9882 # Per bank write bursts +system.physmem.perBankWrBursts::9 10274 # Per bank write bursts +system.physmem.perBankWrBursts::10 9701 # Per bank write bursts +system.physmem.perBankWrBursts::11 9802 # Per bank write bursts +system.physmem.perBankWrBursts::12 9921 # Per bank write bursts +system.physmem.perBankWrBursts::13 9488 # Per bank write bursts +system.physmem.perBankWrBursts::14 9342 # Per bank write bursts +system.physmem.perBankWrBursts::15 9089 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2904914374000 # Total gap between requests +system.physmem.totGap 2904913375000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158967 # Read request sizes (log2) +system.physmem.readPktSize::6 159086 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 155231 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see +system.physmem.writePktSize::6 155290 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 243 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,152 +164,150 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 193 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9964 # What write queue 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# What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.349730 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.021429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.920810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21349 35.19% 35.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14624 24.11% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5778 9.52% 68.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3154 5.20% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2318 3.82% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1542 2.54% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1044 1.72% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1115 1.84% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9740 16.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60664 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6204 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.148614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 546.636063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6203 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60740 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.100889 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 196.092266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 354.277091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21340 35.13% 35.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14718 24.23% 59.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5632 9.27% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3268 5.38% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2341 3.85% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1599 2.63% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1029 1.69% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1125 1.85% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9688 15.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60740 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.064066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 545.583235 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6227 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6204 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.850097 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.346548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.047003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 14 0.23% 0.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 12 0.19% 0.42% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6228 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6228 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.761240 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.356568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.463142 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 15 0.24% 0.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 11 0.18% 0.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 8 0.13% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 18 0.29% 0.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4939 79.61% 80.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 68 1.10% 81.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 50 0.81% 82.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 255 4.11% 86.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 123 1.98% 88.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 43 0.69% 89.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.74% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 38 0.61% 90.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 127 2.05% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.18% 92.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 16 0.26% 92.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.13% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 34 0.55% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.27% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 13 0.21% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.45% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 70 1.13% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.18% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.11% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 13 0.21% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 92 1.48% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 13 0.21% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.08% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 13 0.21% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.10% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 29 0.47% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 12 0.19% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 7 0.11% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.10% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 6 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.06% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6204 # Writes before turning the bus around for reads -system.physmem.totQLat 1487388750 # Total ticks spent queuing -system.physmem.totMemAccLat 4645638750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 842200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8830.38 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::12-15 13 0.21% 0.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4938 79.29% 80.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 76 1.22% 81.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 62 1.00% 82.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 242 3.89% 86.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 139 2.23% 88.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 50 0.80% 89.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.50% 89.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 38 0.61% 90.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 131 2.10% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 23 0.37% 92.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 11 0.18% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 18 0.29% 93.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 33 0.53% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 12 0.19% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.14% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.47% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 74 1.19% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 10 0.16% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.10% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 12 0.19% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 105 1.69% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 8 0.13% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.08% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 14 0.22% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 5 0.08% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 10 0.16% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 36 0.58% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.08% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.05% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.08% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6228 # Writes before turning the bus around for reads +system.physmem.totQLat 1469432250 # Total ticks spent queuing +system.physmem.totMemAccLat 4630026000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 842825000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8717.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27580.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27467.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s @@ -319,36 +317,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.55 # Average write queue length when enqueuing -system.physmem.readRowHits 138839 # Number of row buffer hits during reads -system.physmem.writeRowHits 123106 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.21 # Average write queue length when enqueuing +system.physmem.readRowHits 138952 # Number of row buffer hits during reads +system.physmem.writeRowHits 123085 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes -system.physmem.avgGap 8852370.93 # Average gap between requests -system.physmem.pageHitRate 81.19 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2756204372250 # Time in different power states -system.physmem.memoryStateTime::REF 97001320000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 51708967750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 232462440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 226157400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 126839625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 123399375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 696064200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 617760000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 498059280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 500962320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189734581920 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189734581920 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86971409685 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 86091461640 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1666655279250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1667427163500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1944914696400 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1944721486155 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.526666 # Core power per rank (mW) -system.physmem.averagePower::1 669.460155 # Core power per rank (mW) +system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes +system.physmem.avgGap 8847568.67 # Average gap between requests +system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232530480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126876750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 695315400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 497106720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189734581920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86967425385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666658766000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944912602655 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.525949 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772474399000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97001320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35434263500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 226663920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123675750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 619483800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 502193520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189734581920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 86205812760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667326855500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1944739267170 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.466276 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2773597933750 # Time in different power states +system.physmem_1.memoryStateTime::REF 97001320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34314407250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -368,6 +371,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -389,27 +400,68 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7245 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7245 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2256 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4989 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7245 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7245 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7245 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6163 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11073.588350 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8976.658748 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6262.578720 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-2047 6 0.10% 0.10% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::2048-4095 1618 26.25% 26.35% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::4096-6143 2 0.03% 26.38% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::10240-12287 3154 51.18% 77.56% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::12288-14335 39 0.63% 78.19% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::14336-16383 18 0.29% 78.48% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::20480-22527 1281 20.79% 99.27% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::22528-24575 45 0.73% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6163 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 809116500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 809116500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 809116500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3931 63.78% 63.78% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2232 36.22% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6163 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6163 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6163 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 13408 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12308215 # DTB read hits -system.cpu0.dtb.read_misses 6223 # DTB read misses -system.cpu0.dtb.write_hits 9796614 # DTB write hits -system.cpu0.dtb.write_misses 1025 # DTB write misses +system.cpu0.dtb.read_hits 12308192 # DTB read hits +system.cpu0.dtb.read_misses 6208 # DTB read misses +system.cpu0.dtb.write_hits 9797532 # DTB write hits +system.cpu0.dtb.write_misses 1037 # DTB write misses system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4667 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4666 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 862 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 859 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12314438 # DTB read accesses -system.cpu0.dtb.write_accesses 9797639 # DTB write accesses +system.cpu0.dtb.read_accesses 12314400 # DTB read accesses +system.cpu0.dtb.write_accesses 9798569 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22104829 # DTB hits -system.cpu0.dtb.misses 7248 # DTB misses -system.cpu0.dtb.accesses 22112077 # DTB accesses +system.cpu0.dtb.hits 22105724 # DTB hits +system.cpu0.dtb.misses 7245 # DTB misses +system.cpu0.dtb.accesses 22112969 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -431,7 +483,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 58194599 # ITB inst hits +system.cpu0.itb.walker.walks 3600 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3600 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 840 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2760 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3600 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3600 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3600 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2772 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11755.230880 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9457.284814 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6774.641568 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 701 25.29% 25.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1365 49.24% 74.53% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 705 25.43% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::73728-81919 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2772 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1932 69.70% 69.70% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 840 30.30% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2772 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2772 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2772 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6372 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 58198432 # ITB inst hits system.cpu0.itb.inst_misses 3600 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -448,38 +529,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58198199 # ITB inst accesses -system.cpu0.itb.hits 58194599 # DTB hits +system.cpu0.itb.inst_accesses 58202032 # ITB inst accesses +system.cpu0.itb.hits 58198432 # DTB hits system.cpu0.itb.misses 3600 # DTB misses -system.cpu0.itb.accesses 58198199 # DTB accesses -system.cpu0.numCycles 2905784484 # number of cpu cycles simulated +system.cpu0.itb.accesses 58202032 # DTB accesses +system.cpu0.numCycles 2905779233 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56652370 # Number of instructions committed -system.cpu0.committedOps 68154355 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60226518 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5995 # Number of float alu accesses -system.cpu0.num_func_calls 4919534 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7679282 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60226518 # number of integer instructions -system.cpu0.num_fp_insts 5995 # number of float instructions -system.cpu0.num_int_register_reads 109459523 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41576844 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4468 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1530 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 246082665 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26221599 # number of times the CC registers were written -system.cpu0.num_mem_refs 22745945 # number of memory refs -system.cpu0.num_load_insts 12471278 # Number of load instructions -system.cpu0.num_store_insts 10274667 # Number of store instructions -system.cpu0.num_idle_cycles 2686990403.807933 # Number of idle cycles -system.cpu0.num_busy_cycles 218794080.192067 # Number of busy cycles -system.cpu0.not_idle_fraction 0.075296 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.924704 # Percentage of idle cycles -system.cpu0.Branches 13013332 # Number of branches fetched +system.cpu0.committedInsts 56657023 # Number of instructions committed +system.cpu0.committedOps 68159505 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60230099 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 6043 # Number of float alu accesses +system.cpu0.num_func_calls 4917301 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7681441 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60230099 # number of integer instructions +system.cpu0.num_fp_insts 6043 # number of float instructions +system.cpu0.num_int_register_reads 109460291 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41577079 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4484 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1562 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 246097869 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26230649 # number of times the CC registers were written +system.cpu0.num_mem_refs 22747427 # number of memory refs +system.cpu0.num_load_insts 12471045 # Number of load instructions +system.cpu0.num_store_insts 10276382 # Number of store instructions +system.cpu0.num_idle_cycles 2686979283.194706 # Number of idle cycles +system.cpu0.num_busy_cycles 218799949.805294 # Number of busy cycles +system.cpu0.not_idle_fraction 0.075298 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.924702 # Percentage of idle cycles +system.cpu0.Branches 13013493 # Number of branches fetched system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46892920 67.27% 67.28% # Class of executed instruction -system.cpu0.op_class::IntMult 58660 0.08% 67.36% # Class of executed instruction +system.cpu0.op_class::IntAlu 46896636 67.27% 67.28% # Class of executed instruction +system.cpu0.op_class::IntMult 58754 0.08% 67.36% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.36% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.36% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.36% # Class of executed instruction @@ -507,23 +588,23 @@ system.cpu0.op_class::SimdFloatMisc 4258 0.01% 67.37% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.37% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.37% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.37% # Class of executed instruction -system.cpu0.op_class::MemRead 12471278 17.89% 85.26% # Class of executed instruction -system.cpu0.op_class::MemWrite 10274667 14.74% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12471045 17.89% 85.26% # Class of executed instruction +system.cpu0.op_class::MemWrite 10276382 14.74% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 69703986 # Class of executed instruction +system.cpu0.op_class::total 69709278 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 822947 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.850765 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43250055 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 823459 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.522415 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 822797 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.850764 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43249693 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 823309 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.531544 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.083666 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.767099 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625163 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374545 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.252560 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.598204 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625493 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374215 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id @@ -531,128 +612,128 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 368 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177185510 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177185510 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11600521 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11519661 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23120182 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9401520 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9429674 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18831194 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198556 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193555 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392111 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227604 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215818 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443422 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235826 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 224574 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 177183348 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177183348 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11600363 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11519690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23120053 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9402507 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9428435 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18830942 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198621 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193510 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392131 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227529 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215892 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443421 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235788 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 224612 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460400 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21002041 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20949335 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41951376 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21200597 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21142890 # number of overall hits -system.cpu0.dcache.overall_hits::total 42343487 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 199517 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 203195 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 402712 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 147894 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 150849 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298743 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 56657 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 62315 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118972 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11128 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11639 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22767 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 21002870 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20948125 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41950995 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 21201491 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21141635 # number of overall hits +system.cpu0.dcache.overall_hits::total 42343126 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 199566 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 203021 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 402587 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 147875 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 150867 # number of WriteReq misses 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460402 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 21349452 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21303379 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42652831 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21604665 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21559249 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43163914 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016908 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017333 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017120 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015487 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015745 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 21350311 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21302013 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42652324 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21605662 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21557749 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43163411 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016912 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017319 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015484 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015749 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.221999 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.243542 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232784 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051170 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.222165 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.243321 # miss rate for SoftPFReq accesses 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24790.665837 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25719.208451 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25259.327321 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21314.605485 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21869.904186 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21596.414362 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24790.907697 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25658.188286 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25228.534250 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21311.221639 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21821.243544 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21569.945442 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -661,113 +742,113 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 2 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 686899 # number of writebacks -system.cpu0.dcache.writebacks::total 686899 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 272 # number of ReadReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 686778 # number of writebacks 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-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2600172750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5118071000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5366137441 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5759365015 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11125502456 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 677278250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 762448500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1439726750 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48257750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52710750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100968500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 347165 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 353544 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 700709 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 403007 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 414514 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 817521 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2517038250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2591733500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5108771750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5367510939 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5742623268 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11110134207 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 678934750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 762190250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1441125000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48430250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52495750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100926000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 73500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 73500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 147000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884035691 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8359537765 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16243573456 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8561313941 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9121986265 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17683300206 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688812000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3102617000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791429000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2186315500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2243484000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429799500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4875127500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5346101000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221228500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016885 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017094 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015745 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884549189 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8334356768 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16218905957 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8563483939 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9096547018 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17660030957 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2685824500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3105604250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791428750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2183466000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2246337500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429803500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4869290500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5351941750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221232250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016889 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017289 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017089 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015484 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015749 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218539 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238633 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228599 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017166 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019626 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018366 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218687 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238410 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228556 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017244 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019548 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018368 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016603 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016431 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018649 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019238 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018943 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12637.196667 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12818.141148 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12728.480263 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36283.672367 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38179.669835 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37241.048179 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12143.261197 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12487.078072 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12322.946000 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11775.927282 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11807.963710 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11792.630227 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016597 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016428 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018653 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019228 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12630.027849 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12787.506723 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12709.430749 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36297.622580 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38064.144366 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37189.729623 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12158.138140 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12501.070198 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12337.131459 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11766.338678 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11804.756015 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11786.289852 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73500 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73500 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.466274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23634.542734 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23177.325257 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.542343 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21993.461902 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21626.398123 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.244477 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23573.746883 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23146.421634 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.970710 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21945.089956 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21601.929439 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -778,16 +859,16 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699785 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.774941 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113901535 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1700297 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 66.989200 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1699876 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.774945 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113899876 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1700388 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 66.984639 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 418.326028 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.448913 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.817043 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180564 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.439814 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.335131 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.819218 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.178389 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id @@ -795,62 +876,62 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117302141 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117302141 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57346605 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56554930 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113901535 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57346605 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56554930 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113901535 # number of demand (read+write) hits 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10033302501 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19901259002 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9867956501 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10033302501 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19901259002 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9867956501 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10033302501 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19901259002 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014847 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014572 # mshr miss rate for overall accesses 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-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11764.580979 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11698.151448 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014709 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014709 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014709 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11703.910389 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11703.910389 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11703.910389 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -925,27 +1014,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 6287 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6287 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1877 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4409 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 6286 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6286 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6286 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5205 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10664.029395 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8432.528945 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7016.441417 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 4168 80.08% 80.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 1031 19.81% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-81919 3 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5205 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2238481496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.553158 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.497166 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000247500 44.68% 44.68% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1238233996 55.32% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2238481496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3350 64.37% 64.37% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1854 35.63% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5204 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5204 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5204 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11491 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12222550 # DTB read hits -system.cpu1.dtb.read_misses 5478 # DTB read misses -system.cpu1.dtb.write_hits 9817405 # DTB write hits -system.cpu1.dtb.write_misses 801 # DTB write misses +system.cpu1.dtb.read_hits 12222323 # DTB read hits +system.cpu1.dtb.read_misses 5479 # DTB read misses +system.cpu1.dtb.write_hits 9816234 # DTB write hits +system.cpu1.dtb.write_misses 808 # DTB write misses system.cpu1.dtb.flush_tlb 2935 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4101 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4100 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 936 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 935 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12228028 # DTB read accesses -system.cpu1.dtb.write_accesses 9818206 # DTB write accesses +system.cpu1.dtb.read_accesses 12227802 # DTB read accesses +system.cpu1.dtb.write_accesses 9817042 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22039955 # DTB hits -system.cpu1.dtb.misses 6279 # DTB misses -system.cpu1.dtb.accesses 22046234 # DTB accesses +system.cpu1.dtb.hits 22038557 # DTB hits +system.cpu1.dtb.misses 6287 # DTB misses +system.cpu1.dtb.accesses 22044844 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -967,8 +1098,40 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 57407239 # ITB inst hits -system.cpu1.itb.inst_misses 3155 # ITB inst misses +system.cpu1.itb.walker.walks 3158 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3158 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 699 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2459 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3158 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3158 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3158 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2331 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10972.758473 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8658.635701 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6654.132285 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 701 30.07% 30.07% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 5 0.21% 30.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 1063 45.60% 75.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 47 2.02% 77.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 1 0.04% 77.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 442 18.96% 96.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 72 3.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2331 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000205500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000205500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000205500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1632 70.01% 70.01% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 699 29.99% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2331 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3158 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3158 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2331 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2331 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5489 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 57401838 # ITB inst hits +system.cpu1.itb.inst_misses 3158 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -977,45 +1140,45 @@ system.cpu1.itb.flush_tlb 2935 # Nu system.cpu1.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2356 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2358 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57410394 # ITB inst accesses -system.cpu1.itb.hits 57407239 # DTB hits -system.cpu1.itb.misses 3155 # DTB misses -system.cpu1.itb.accesses 57410394 # DTB accesses -system.cpu1.numCycles 2904045023 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 57404996 # ITB inst accesses +system.cpu1.itb.hits 57401838 # DTB hits +system.cpu1.itb.misses 3158 # DTB misses +system.cpu1.itb.accesses 57404996 # DTB accesses +system.cpu1.numCycles 2904048276 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55850596 # Number of instructions committed -system.cpu1.committedOps 67489552 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59717976 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5231 # Number of float alu accesses -system.cpu1.num_func_calls 4978644 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7556287 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59717976 # number of integer instructions -system.cpu1.num_fp_insts 5231 # number of float instructions -system.cpu1.num_int_register_reads 108697708 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41105654 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4046 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1186 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 243864682 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25692319 # number of times the CC registers were written -system.cpu1.num_mem_refs 22680019 # number of memory refs -system.cpu1.num_load_insts 12382292 # Number of load instructions -system.cpu1.num_store_insts 10297727 # Number of store instructions -system.cpu1.num_idle_cycles 2693854199.172201 # Number of idle cycles -system.cpu1.num_busy_cycles 210190823.827799 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072379 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927621 # Percentage of idle cycles -system.cpu1.Branches 12914403 # Number of branches fetched +system.cpu1.committedInsts 55844358 # Number of instructions committed +system.cpu1.committedOps 67482566 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59712832 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5183 # Number of float alu accesses +system.cpu1.num_func_calls 4980648 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7553958 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59712832 # number of integer instructions +system.cpu1.num_fp_insts 5183 # number of float instructions +system.cpu1.num_int_register_reads 108693830 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41104260 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4030 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1154 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 243842957 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25682716 # number of times the CC registers were written +system.cpu1.num_mem_refs 22677996 # number of memory refs +system.cpu1.num_load_insts 12382220 # Number of load instructions +system.cpu1.num_store_insts 10295776 # Number of store instructions +system.cpu1.num_idle_cycles 2693878470.584054 # Number of idle cycles +system.cpu1.num_busy_cycles 210169805.415946 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072371 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927629 # Percentage of idle cycles +system.cpu1.Branches 12913817 # Number of branches fetched system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46321486 67.07% 67.07% # Class of executed instruction -system.cpu1.op_class::IntMult 56040 0.08% 67.15% # Class of executed instruction +system.cpu1.op_class::IntAlu 46316521 67.07% 67.07% # Class of executed instruction +system.cpu1.op_class::IntMult 55928 0.08% 67.15% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.15% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.15% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.15% # Class of executed instruction @@ -1043,11 +1206,11 @@ system.cpu1.op_class::SimdFloatMisc 4215 0.01% 67.16% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 67.16% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.16% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.16% # Class of executed instruction -system.cpu1.op_class::MemRead 12382292 17.93% 85.09% # Class of executed instruction -system.cpu1.op_class::MemWrite 10297727 14.91% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12382220 17.93% 85.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 10295776 14.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69061894 # Class of executed instruction +system.cpu1.op_class::total 69054794 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30195 # Transaction distribution @@ -1145,21 +1308,21 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347067538 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347068533 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804503 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.084296 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084285 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309429812000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084296 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 309430209000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084285 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.067768 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.067768 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1177,8 +1340,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9591408658 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9591408658 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9589202651 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9589202651 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles @@ -1201,17 +1364,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264780.495197 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264780.495197 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264719.596152 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264719.596152 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55572 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55434 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7176 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7152 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.744147 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.750839 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1227,8 +1390,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7707754664 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7707754664 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7705544661 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7705544661 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles @@ -1243,253 +1406,253 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212780.329726 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212780.329726 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212719.320368 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212719.320368 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 89435 # number of replacements -system.l2c.tags.tagsinuse 64927.975067 # Cycle average of tags in use -system.l2c.tags.total_refs 2767630 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.893080 # Average number of references to valid blocks. +system.l2c.tags.replacements 89554 # number of replacements +system.l2c.tags.tagsinuse 64927.556568 # Cycle average of tags in use +system.l2c.tags.total_refs 2767374 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154795 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.877670 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50554.064375 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per task id system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6816 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56245 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26305647 # Number of tag accesses -system.l2c.tags.data_accesses 26305647 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6459 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3454 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 839902 # number 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mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991196 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992035 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.991618 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.423860 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.459800 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.442008 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.424723 # mshr miss rate for ReadExReq accesses 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for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.167010 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001336 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011656 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.180404 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063393 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000155 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000289 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009520 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.166762 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001337 # mshr miss rate for overall accesses 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60112.752384 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64077.284218 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63444.730466 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61469.007922 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.370370 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10079.045222 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10055.391768 # average UpgradeReq mshr miss latency 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average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 60500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56703.765702 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56174.712113 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56425.862345 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56615.989603 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55923.751131 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56252.680432 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60112.752384 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57307.407335 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56812.065606 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57370.855040 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57217.681950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56507.069783 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57254.032801 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60112.752384 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57307.407335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59800.427350 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56812.065606 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57370.855040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57217.681950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56507.069783 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57254.032801 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1655,57 +1818,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70575 # Transaction distribution -system.membus.trans_dist::ReadResp 70575 # Transaction distribution +system.membus.trans_dist::ReadReq 70570 # Transaction distribution +system.membus.trans_dist::ReadResp 70570 # Transaction distribution system.membus.trans_dist::WriteReq 27613 # Transaction distribution system.membus.trans_dist::WriteResp 27613 # Transaction distribution -system.membus.trans_dist::Writeback 119007 # Transaction distribution +system.membus.trans_dist::Writeback 119066 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4495 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4497 # Transaction distribution -system.membus.trans_dist::ReadExReq 129060 # Transaction distribution -system.membus.trans_dist::ReadExResp 129060 # Transaction distribution +system.membus.trans_dist::ReadExReq 129184 # Transaction distribution +system.membus.trans_dist::ReadExResp 129184 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 437896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 545560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 545857 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 654447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 654744 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15529084 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15692509 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15540476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15703901 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20327965 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20339357 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 319191 # Request fanout histogram +system.membus.snoop_fanout::samples 319369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 319191 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 319369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 319191 # Request fanout histogram -system.membus.reqLayer0.occupancy 87172500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 319369 # Request fanout histogram +system.membus.reqLayer0.occupancy 87174000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1735000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1737000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1662315000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1663053000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1640286255 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1641418005 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38333497 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1738,54 +1901,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2303097 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2303082 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2303048 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2303033 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 686899 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 686778 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2744 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2746 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295999 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295999 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3418625 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457116 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18180 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34622 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5928543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108853880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96862117 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24836 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205787617 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 53694 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3284793 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011099 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104766 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 295998 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295998 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3418807 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2456695 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18188 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34627 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5928317 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108859704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96844773 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46792 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205776113 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 53699 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3284622 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011100 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104768 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3248335 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3248164 98.89% 98.89% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3284793 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4419462750 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3284622 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4418893499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 7665779999 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 7666187498 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3782690745 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3782041495 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11971000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11977000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22951201 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22953702 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index ecc4cd446..3b8bb2577 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.349389 # Number of seconds simulated -sim_ticks 47349388766500 # Number of ticks simulated -final_tick 47349388766500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.355615 # Number of seconds simulated +sim_ticks 47355615197500 # Number of ticks simulated +final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148460 # Simulator instruction rate (inst/s) -host_op_rate 174619 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7799944718 # Simulator tick rate (ticks/s) -host_mem_usage 883812 # Number of bytes of host memory used -host_seconds 6070.48 # Real time elapsed on the host -sim_insts 901223526 # Number of instructions simulated -sim_ops 1060022042 # Number of ops (including micro ops) simulated +host_inst_rate 178863 # Simulator instruction rate (inst/s) +host_op_rate 210359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9462962325 # Simulator tick rate (ticks/s) +host_mem_usage 759628 # Number of bytes of host memory used +host_seconds 5004.31 # Real time elapsed on the host +sim_insts 895084962 # Number of instructions simulated +sim_ops 1052703090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 108352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 12219800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 55224576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 171840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 160768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 11630176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 36221056 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 451968 # Number of bytes read from this memory -system.physmem.bytes_read::total 116315128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4075008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 659840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4734848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 84862912 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 18925144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 13767904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory +system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8104128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 84883728 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1693 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 190956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 862884 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 181736 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 565954 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7062 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1817460 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1325983 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 295727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 215138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1328586 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 258077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1166321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 245625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 764974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2456529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 86063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 13936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1792270 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 440 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 399639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 290734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 171133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1792710 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1792270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 258517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1166321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 245625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 764974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4249239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1817460 # Number of read requests accepted -system.physmem.writeReqs 1459105 # Number of write requests accepted -system.physmem.readBursts 1817460 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1459105 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 116259968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 57472 # Total number of bytes read from write queue -system.physmem.bytesWritten 92884608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 116315128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 93236944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 898 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7766 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 92270 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 109521 # Per bank write bursts -system.physmem.perBankRdBursts::1 125500 # Per bank write bursts -system.physmem.perBankRdBursts::2 109858 # Per bank write bursts -system.physmem.perBankRdBursts::3 118807 # Per bank write bursts -system.physmem.perBankRdBursts::4 114750 # Per bank write bursts -system.physmem.perBankRdBursts::5 133958 # Per bank write bursts -system.physmem.perBankRdBursts::6 108183 # Per bank write bursts -system.physmem.perBankRdBursts::7 109296 # Per bank write bursts -system.physmem.perBankRdBursts::8 104951 # Per bank write bursts -system.physmem.perBankRdBursts::9 157608 # Per bank write bursts -system.physmem.perBankRdBursts::10 96466 # Per bank write bursts -system.physmem.perBankRdBursts::11 111139 # Per bank write bursts -system.physmem.perBankRdBursts::12 103753 # Per bank write bursts -system.physmem.perBankRdBursts::13 116262 # Per bank write bursts -system.physmem.perBankRdBursts::14 95073 # Per bank write bursts -system.physmem.perBankRdBursts::15 101437 # Per bank write bursts -system.physmem.perBankWrBursts::0 88391 # Per bank write bursts -system.physmem.perBankWrBursts::1 94888 # Per bank write bursts -system.physmem.perBankWrBursts::2 89089 # Per bank write bursts -system.physmem.perBankWrBursts::3 94540 # Per bank write bursts -system.physmem.perBankWrBursts::4 92096 # Per bank write bursts -system.physmem.perBankWrBursts::5 104028 # Per bank write bursts -system.physmem.perBankWrBursts::6 87215 # Per bank write bursts -system.physmem.perBankWrBursts::7 89925 # Per bank write bursts -system.physmem.perBankWrBursts::8 85891 # Per bank write bursts -system.physmem.perBankWrBursts::9 90043 # Per bank write bursts -system.physmem.perBankWrBursts::10 85085 # Per bank write bursts -system.physmem.perBankWrBursts::11 94536 # Per bank write bursts -system.physmem.perBankWrBursts::12 86659 # Per bank write bursts -system.physmem.perBankWrBursts::13 94890 # Per bank write bursts -system.physmem.perBankWrBursts::14 85144 # Per bank write bursts -system.physmem.perBankWrBursts::15 88902 # Per bank write bursts +system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 400078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 290734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1055887 # Number of read requests accepted +system.physmem.writeReqs 1888199 # Number of write requests accepted +system.physmem.readBursts 1055887 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1888199 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 67557888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue +system.physmem.bytesWritten 120408192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 67574456 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 120698960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6789 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 114993 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 58784 # Per bank write bursts +system.physmem.perBankRdBursts::1 68771 # Per bank write bursts +system.physmem.perBankRdBursts::2 59130 # Per bank write bursts +system.physmem.perBankRdBursts::3 67531 # Per bank write bursts +system.physmem.perBankRdBursts::4 66855 # Per bank write bursts +system.physmem.perBankRdBursts::5 75133 # Per bank write bursts +system.physmem.perBankRdBursts::6 65903 # Per bank write bursts +system.physmem.perBankRdBursts::7 67407 # Per bank write bursts +system.physmem.perBankRdBursts::8 54196 # Per bank write bursts +system.physmem.perBankRdBursts::9 110706 # Per bank write bursts +system.physmem.perBankRdBursts::10 54461 # Per bank write bursts +system.physmem.perBankRdBursts::11 64104 # Per bank write bursts +system.physmem.perBankRdBursts::12 57097 # Per bank write bursts +system.physmem.perBankRdBursts::13 66166 # Per bank write bursts +system.physmem.perBankRdBursts::14 60751 # Per bank write bursts +system.physmem.perBankRdBursts::15 58597 # Per bank write bursts +system.physmem.perBankWrBursts::0 116651 # Per bank write bursts +system.physmem.perBankWrBursts::1 125865 # Per bank write bursts +system.physmem.perBankWrBursts::2 118664 # Per bank write bursts +system.physmem.perBankWrBursts::3 124773 # Per bank write bursts +system.physmem.perBankWrBursts::4 121001 # Per bank write bursts +system.physmem.perBankWrBursts::5 125597 # Per bank write bursts +system.physmem.perBankWrBursts::6 113710 # Per bank write bursts +system.physmem.perBankWrBursts::7 116980 # Per bank write bursts +system.physmem.perBankWrBursts::8 110183 # Per bank write bursts +system.physmem.perBankWrBursts::9 114411 # Per bank write bursts +system.physmem.perBankWrBursts::10 109841 # Per bank write bursts +system.physmem.perBankWrBursts::11 116847 # Per bank write bursts +system.physmem.perBankWrBursts::12 116927 # Per bank write bursts +system.physmem.perBankWrBursts::13 118874 # Per bank write bursts +system.physmem.perBankWrBursts::14 112844 # Per bank write bursts +system.physmem.perBankWrBursts::15 118210 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 47349386828500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 47355613259000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1817418 # Read request sizes (log2) +system.physmem.readPktSize::6 1055845 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1456502 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 724796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 275224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 218778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 130576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 121480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 92297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 78276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 67824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 54542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 6539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 4680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 500 # What read queue length does an incoming req see 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does an incoming req see +system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 894898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 233.707153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.846498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 284.283402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 463489 51.79% 51.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 185877 20.77% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 67737 7.57% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36988 4.13% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29329 3.28% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 22133 2.47% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15835 1.77% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13649 1.53% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 59861 6.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 894898 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 77790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.351999 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 144.403085 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 77788 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1046123 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 179.678328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 108.587927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 250.922876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 666099 63.67% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 200536 19.17% 82.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50293 4.81% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24222 2.32% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 17786 1.70% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12328 1.18% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8853 0.85% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7558 0.72% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 58448 5.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1046123 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 79224 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.323930 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 140.057237 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 79222 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 77790 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 77790 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.656922 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.550932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.537959 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 73893 94.99% 94.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 1079 1.39% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 616 0.79% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 255 0.33% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 611 0.79% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 159 0.20% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 204 0.26% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 127 0.16% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 198 0.25% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 57 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 225 0.29% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 47 0.06% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 57 0.07% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 49 0.06% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 102 0.13% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 22 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 26 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 10 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 13 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 9 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 77790 # Writes before turning the bus around for reads -system.physmem.totQLat 101322311265 # Total ticks spent queuing -system.physmem.totMemAccLat 135382848765 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9082810000 # Total ticks spent in databus transfers -system.physmem.avgQLat 55776.96 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 79224 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 79224 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.747576 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.323530 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.901705 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 65925 83.21% 83.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 5556 7.01% 90.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 2071 2.61% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 1166 1.47% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1087 1.37% 95.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 456 0.58% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 393 0.50% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 290 0.37% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 329 0.42% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 179 0.23% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 294 0.37% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 101 0.13% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 139 0.18% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 103 0.13% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 155 0.20% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 83 0.10% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 89 0.11% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 58 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 57 0.07% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 65 0.08% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 66 0.08% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 81 0.10% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 58 0.07% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 58 0.07% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 69 0.09% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 72 0.09% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 57 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 44 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 31 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 21 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 22 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 15 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::280-287 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-295 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::296-303 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-311 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::312-319 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-327 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::328-335 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-343 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::344-351 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-359 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::360-367 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-375 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::376-383 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-391 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::456-463 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-503 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 79224 # Writes before turning the bus around for reads +system.physmem.totQLat 39480003252 # Total ticks spent queuing +system.physmem.totMemAccLat 59272353252 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5277960000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37400.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 74526.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56150.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.53 # Average write queue length when enqueuing -system.physmem.readRowHits 1479200 # Number of row buffer hits during reads -system.physmem.writeRowHits 893785 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.58 # Row buffer hit rate for writes -system.physmem.avgGap 14450922.48 # Average gap between requests -system.physmem.pageHitRate 72.61 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45452153624500 # Time in different power states -system.physmem.memoryStateTime::REF 1581100040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 316134376000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3577346640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3188082240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1951925250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1739529000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7253009400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 6916111800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 4796314560 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 4608252000 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3092631678240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3092631678240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1196963299980 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1185023558430 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27359663548500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27370137006000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31666837122570 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31664244217710 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.790877 # Core power per rank (mW) -system.physmem.averagePower::1 668.736116 # Core power per rank (mW) +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing +system.physmem.readRowHits 797783 # Number of row buffer hits during reads +system.physmem.writeRowHits 1093063 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes +system.physmem.avgGap 16084996.59 # Average gap between requests +system.physmem.pageHitRate 64.38 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4126437000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2251528125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4130209200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6241801680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1193820708150 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27366157608000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31669766818395 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.764772 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45525574397500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 248732168750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3782252880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2063729250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4103353800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5949527760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1183965961905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27374802122250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31667705474085 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.721243 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45539970549502 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory @@ -354,16 +378,24 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 127854962 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91169153 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5795491 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97464931 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 70565780 # Number of BTB hits +system.cpu0.branchPred.lookups 131272413 # Number of BP lookups +system.cpu0.branchPred.condPredicted 92904470 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6038757 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 98925935 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 71271707 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.401200 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 14662444 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 979053 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.045523 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15434878 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1076370 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -385,27 +417,75 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 271399 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 271399 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8182 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72706 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 271399 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 271399 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 271399 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 80888 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 77350 95.63% 95.63% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2802 3.46% 99.09% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 370 0.46% 99.55% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 250 0.31% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 18 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 21 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 23 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 80888 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 644436704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 644436704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 644436704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 72706 89.88% 89.88% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8182 10.12% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 80888 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 80888 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 80888 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 352287 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 80634882 # DTB read hits -system.cpu0.dtb.read_misses 217470 # DTB read misses -system.cpu0.dtb.write_hits 71942682 # DTB write hits -system.cpu0.dtb.write_misses 47848 # DTB write misses +system.cpu0.dtb.read_hits 83830376 # DTB read hits +system.cpu0.dtb.read_misses 224800 # DTB read misses +system.cpu0.dtb.write_hits 74836136 # DTB write hits +system.cpu0.dtb.write_misses 46599 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34852 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1874 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8493 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 31986 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8713 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11561 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 80852352 # DTB read accesses -system.cpu0.dtb.write_accesses 71990530 # DTB write accesses +system.cpu0.dtb.perms_faults 10302 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 84055176 # DTB read accesses +system.cpu0.dtb.write_accesses 74882735 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 152577564 # DTB hits -system.cpu0.dtb.misses 265318 # DTB misses -system.cpu0.dtb.accesses 152842882 # DTB accesses +system.cpu0.dtb.hits 158666512 # DTB hits +system.cpu0.dtb.misses 271399 # DTB misses +system.cpu0.dtb.accesses 158937911 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -427,145 +507,185 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 228743332 # ITB inst hits -system.cpu0.itb.inst_misses 63317 # ITB inst misses +system.cpu0.itb.walker.walks 59516 # Table walker walks requested +system.cpu0.itb.walker.walksLong 59516 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51758 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 59516 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 59516 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 59516 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52388 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 19494.417176 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48500 92.58% 92.58% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3085 5.89% 98.47% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 277 0.53% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 436 0.83% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 31 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52388 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 643764704 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 643764704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 643764704 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 51758 98.80% 98.80% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 630 1.20% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52388 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59516 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59516 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52388 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52388 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 111904 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 234493726 # ITB inst hits +system.cpu0.itb.inst_misses 59516 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24510 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 22765 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 202277 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 197741 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 228806649 # ITB inst accesses -system.cpu0.itb.hits 228743332 # DTB hits -system.cpu0.itb.misses 63317 # DTB misses -system.cpu0.itb.accesses 228806649 # DTB accesses -system.cpu0.numCycles 867293351 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 234553242 # ITB inst accesses +system.cpu0.itb.hits 234493726 # DTB hits +system.cpu0.itb.misses 59516 # DTB misses +system.cpu0.itb.accesses 234553242 # DTB accesses +system.cpu0.numCycles 936626399 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 417325536 # Number of instructions committed -system.cpu0.committedOps 490736323 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 44793539 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4342 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93832115526 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.078218 # CPI: cycles per instruction -system.cpu0.ipc 0.481182 # IPC: instructions per cycle +system.cpu0.committedInsts 433367687 # Number of instructions committed +system.cpu0.committedOps 509515701 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 43981618 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 3754 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93775213530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.161274 # CPI: cycles per instruction +system.cpu0.ipc 0.462690 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4790 # number of quiesce instructions executed -system.cpu0.tickCycles 682045150 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 185248201 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5375859 # number of replacements -system.cpu0.dcache.tags.tagsinuse 504.387778 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 144555742 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5376371 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.887233 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 504.387778 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.985132 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.985132 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 12643 # number of quiesce instructions executed +system.cpu0.tickCycles 703108983 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 233517416 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5387052 # number of replacements +system.cpu0.dcache.tags.tagsinuse 501.034252 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 150576282 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 501.034252 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.978583 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 308078040 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 308078040 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 74032777 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 74032777 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 66638302 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 66638302 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 115191 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 115191 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1688442 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1688442 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1614699 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1614699 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 140671079 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 140671079 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 140671079 # number of overall hits -system.cpu0.dcache.overall_hits::total 140671079 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 3863790 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3863790 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 2319255 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2319255 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 742685 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 742685 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 105957 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 105957 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 178436 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 178436 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 6183045 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6183045 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 6183045 # number of overall misses -system.cpu0.dcache.overall_misses::total 6183045 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54382834533 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54382834533 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36195221997 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36195221997 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 21037893950 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 21037893950 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1466052740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 1466052740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3737583856 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3737583856 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 3062000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3062000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 90578056530 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 90578056530 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 90578056530 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 90578056530 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 77896567 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 77896567 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 68957557 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 68957557 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 857876 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 857876 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1794399 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1794399 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1793135 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1793135 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 146854124 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 146854124 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 146854124 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 146854124 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.049602 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.049602 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.033633 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033633 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.865725 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.865725 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.059049 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059049 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.099511 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099511 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.042103 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.042103 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.042103 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.042103 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13836.299065 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20946.355309 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20946.355309 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 77114778 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 69351990 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69351990 # number of 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478044747 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 224826074 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 224826074 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 224826074 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 224826074 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 224826074 # number of overall hits +system.cpu0.icache.overall_hits::total 224826074 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9464200 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9464200 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9464200 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9464200 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9464200 # number of overall misses +system.cpu0.icache.overall_misses::total 9464200 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93878607487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 93878607487 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 93878607487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 93878607487 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 93878607487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 93878607487 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290274 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 234290274 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 234290274 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 234290274 # number of demand (read+write) accesses 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overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9919.338928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9919.338928 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -723,353 +843,346 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8782067 # number of ReadReq MSHR misses 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-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.038428 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.038428 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7059.597216 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040395 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8415.776079 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency 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of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 12340800 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 12958439 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 470272 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 147367 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 12340800 # number of overall hits -system.cpu0.l2cache.overall_hits::total 12958439 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13865 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10088 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 947171 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 971124 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst 446451 # number of WriteInvalidateReq misses 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overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 157455 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 13519464 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 14161056 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064069 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.076529 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.074597 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst 0.602096 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.602096 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.588388 # miss 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miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.068454 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 1399370 # number of writebacks +system.cpu0.l2cache.writebacks::total 1399370 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 3403 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 3404 # number of ReadReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst 156 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 156 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 9658 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 9658 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) 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# number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11843 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8237 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1706228 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1726308 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11843 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8237 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1706228 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2763289 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 221721501 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 34355781249 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 34877337999 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47311809533 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 20034543782 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 20034543782 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2151275072 # number of UpgradeReq MSHR miss cycles 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demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 43888445260 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 44410002010 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 221721501 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 43888445260 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 91721811543 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9672004742 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9672004742 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5338553005 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15010557747 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110666 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.085266 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.085266 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.588388 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.588388 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.795546 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.795546 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.746347 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.648936 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813285 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.194529 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.194529 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.078629 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.231718 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.346044 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23637.177128 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23726.676861 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44479.809572 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22311.716595 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 22311.716595 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16850.081623 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16850.081623 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13956.633965 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13956.633965 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 269285.714286 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 269285.714286 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 28826.174828 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 28826.174828 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 24744.850767 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39995.599759 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23772.172383 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13624.298374 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 183500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 36521.098204 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1077,68 +1190,77 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 17406363 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13329872 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19688 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19687 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3741617 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 5530609 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 862152 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 741495 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 486160 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 325301 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 465486 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1278141 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1152631 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17668715 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15752783 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 346532 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1063511 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34831541 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 565398848 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598192623 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1259640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3873096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1168724207 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 10729638 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 29561564 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.351841 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.477545 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13994677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3733141 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1450559 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1135277 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 764525 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 439100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 331866 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 445825 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1265717 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1135924 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19032980 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15771109 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 324159 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1044893 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 36173141 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609055296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 597396947 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1171600 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3801480 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1211425323 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5254625 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24752436 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.199831 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.399873 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 19160579 64.82% 64.82% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 10400985 35.18% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 19806132 80.02% 80.02% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 4946304 19.98% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 29561564 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14119794312 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 24752436 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14477877088 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 225496496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 203336996 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 13269247990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14303799012 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7748577182 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7760036291 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 189385144 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 177959354 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 579874631 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 570171512 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 146637664 # Number of BP lookups -system.cpu1.branchPred.condPredicted 104244557 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6464776 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 109760718 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 80092874 # Number of BTB hits +system.cpu1.branchPred.lookups 141025153 # Number of BP lookups +system.cpu1.branchPred.condPredicted 100933183 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6236213 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 106937612 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 78176713 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.970436 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17287162 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1125459 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.104974 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16283768 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1021605 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1160,27 +1282,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 298651 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 298651 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11560 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94332 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 298651 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 298651 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 298651 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 105892 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 104531 98.71% 98.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1148 1.08% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 61 0.06% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 63 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 105892 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1172907556 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1172907556 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1172907556 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94332 89.08% 89.08% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11560 10.92% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 105892 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298651 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298651 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 404543 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 95196820 # DTB read hits -system.cpu1.dtb.read_misses 258683 # DTB read misses -system.cpu1.dtb.write_hits 82774540 # DTB write hits -system.cpu1.dtb.write_misses 48918 # DTB write misses +system.cpu1.dtb.read_hits 90905034 # DTB read hits +system.cpu1.dtb.read_misses 248418 # DTB read misses +system.cpu1.dtb.write_hits 78767149 # DTB write hits +system.cpu1.dtb.write_misses 50233 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40938 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1166 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8454 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 43819 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 923 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8321 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11190 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 95455503 # DTB read accesses -system.cpu1.dtb.write_accesses 82823458 # DTB write accesses +system.cpu1.dtb.perms_faults 12272 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91153452 # DTB read accesses +system.cpu1.dtb.write_accesses 78817382 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 177971360 # DTB hits -system.cpu1.dtb.misses 307601 # DTB misses -system.cpu1.dtb.accesses 178278961 # DTB accesses +system.cpu1.dtb.hits 169672183 # DTB hits +system.cpu1.dtb.misses 298651 # DTB misses +system.cpu1.dtb.accesses 169970834 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1202,145 +1366,179 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 262373201 # ITB inst hits -system.cpu1.itb.inst_misses 66107 # ITB inst misses +system.cpu1.itb.walker.walks 67610 # Table walker walks requested +system.cpu1.itb.walker.walksLong 67610 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 497 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58418 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 67610 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 67610 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 67610 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 58915 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 20253.386778 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 57403 97.43% 97.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1356 2.30% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 66 0.11% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 58915 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1173450056 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1173450056 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1173450056 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 58418 99.16% 99.16% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 497 0.84% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 58915 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67610 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67610 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58915 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58915 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 126525 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 252933263 # ITB inst hits +system.cpu1.itb.inst_misses 67610 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29545 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 31594 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 222220 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 222493 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 262439308 # ITB inst accesses -system.cpu1.itb.hits 262373201 # DTB hits -system.cpu1.itb.misses 66107 # DTB misses -system.cpu1.itb.accesses 262439308 # DTB accesses -system.cpu1.numCycles 965776076 # number of cpu cycles simulated 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hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1944639 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1944639 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 164766973 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 164766973 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 164766973 # number of overall hits -system.cpu1.dcache.overall_hits::total 164766973 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 4362572 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 4362572 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 2362737 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2362737 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 497251 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 497251 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 139927 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 139927 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 188742 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 188742 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 6725309 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 6725309 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 6725309 # number of overall misses -system.cpu1.dcache.overall_misses::total 6725309 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 63153941750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 63153941750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 37295206516 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 37295206516 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 9223332559 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 9223332559 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1921743254 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1921743254 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3886161820 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3886161820 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 3267000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3267000 # number of StoreCondFailReq miss cycles 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WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2134889 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2134889 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2133381 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2133381 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 171492282 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 171492282 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 171492282 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 171492282 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.047463 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.047463 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029691 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029691 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.701108 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.701108 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.065543 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.065543 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.088471 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088471 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.039216 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.039216 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.039216 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039216 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14476.309331 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14476.309331 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15784.747315 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 15784.747315 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 18548.645571 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 18548.645571 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13733.898776 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13733.898776 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20589.809475 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20589.809475 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5890 # number of quiesce instructions executed +system.cpu1.tickCycles 748189458 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 195594211 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5624476 # number of replacements +system.cpu1.dcache.tags.tagsinuse 426.107402 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 161270449 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 426.107402 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.832241 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses 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(read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 156964388 # number of overall hits +system.cpu1.dcache.overall_hits::total 156964388 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 4311289 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 2366929 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 476593 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 141331 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 141331 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 193852 # number of StoreCondReq misses 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number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1977833980 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3982712056 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2357000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 98815778897 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 98815778897 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 98815778897 # number of overall miss cycles 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number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 163642606 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 163642606 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.049103 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.031209 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.868771 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.068952 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.094646 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.040810 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.040810 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14084.555044 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16093.930856 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 24366.929930 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13994.339388 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20545.117182 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14935.990044 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14935.990044 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1349,88 +1547,88 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3739270 # number of writebacks -system.cpu1.dcache.writebacks::total 3739270 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 400087 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 400087 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 959724 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 959724 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 47 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 67 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 75 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 75 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1359811 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1359811 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1359811 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1359811 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3962485 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3962485 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1403013 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1403013 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 497204 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497204 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 139860 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 139860 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 188667 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 188667 # number of StoreCondReq MSHR misses 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# number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1640188222 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1640188222 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3498307132 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498307132 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 2504000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2504000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 69333852610 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 69333852610 # number of demand (read+write) MSHR miss cycles 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ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043110 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017631 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017631 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.701042 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.701042 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.065512 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065512 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.088436 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088436 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031287 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031287 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12391.309416 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12391.309416 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14421.445075 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14421.445075 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 16533.144225 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 16533.144225 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11727.357515 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11727.357515 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18542.231190 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18542.231190 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks +system.cpu1.dcache.writebacks::total 3711348 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 397792 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 970938 # number of WriteReq MSHR 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overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3913497 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3913497 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1395991 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1395991 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 476533 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 476533 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 141284 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141284 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 193784 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses 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10653380764 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1693632498 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3584420895 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 67166622911 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 67166622911 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 548139751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 613571252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 1161711003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.044572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.018407 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.868662 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.068929 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.094612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11953.436273 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14603.880625 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 22356.018920 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11987.433099 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1438,58 +1636,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 10003641 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.113561 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 252141010 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 10004153 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.203634 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8364450905000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.113561 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990456 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990456 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 9215030 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.228865 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 243489253 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9215542 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 26.421588 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8367568177500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.228865 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990681 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990681 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 534294484 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 534294484 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 252141010 # number of ReadReq hits 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miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8498.421941 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 514625132 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 514625132 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 243489253 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 243489253 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 243489253 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 243489253 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 243489253 # number of overall hits +system.cpu1.icache.overall_hits::total 243489253 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9215542 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9215542 # number of ReadReq misses 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(read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 77617743273 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77617743273 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 77617743273 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8388750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8388750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8388750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8388750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036468 # mshr miss rate for ReadReq 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8422.482722 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 91266400 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2590593 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 83739964 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 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367223255 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 296231251 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 43186089631 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 43849544137 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 296231251 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 43186089631 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 85138632301 # number of overall MSHR miss cycles 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rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115120 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.128744 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.128744 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.598714 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.598714 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.779186 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.779186 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.573995 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.573995 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.639408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.639408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.784248 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784248 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.192693 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.192693 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.076921 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.200339 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.305025 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22582.384880 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 26038.478163 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 1461500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30747.372117 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1852,65 +2052,66 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 19283354 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 15081139 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 18583 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 18583 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3739269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 5170827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 625737 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495851 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 477449 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330499 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 473092 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1314338 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1188302 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 20008489 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16359278 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 359533 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1226091 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 37953391 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640271616 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615594373 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1295960 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4483448 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1261645397 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10423087 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 30921485 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.327379 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.469257 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 14230777 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3711346 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1418597 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1143341 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 475262 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 452039 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 340076 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 470072 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1342662 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1189275 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18431264 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16132557 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 369420 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1220438 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36153679 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 589800448 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609347251 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1339184 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4456624 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1204943507 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5386490 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 25000724 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.203488 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.402593 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 20798445 67.26% 67.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 10123040 32.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 19913365 79.65% 79.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 5087359 20.35% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 30921485 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14664539498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 25000724 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14152090513 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176010242 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175296997 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 15012316370 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13837074197 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8461463125 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8360530852 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 197959664 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 202402154 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 666269864 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 663973984 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40348 # Transaction distribution -system.iobus.trans_dist::ReadResp 40348 # Transaction distribution -system.iobus.trans_dist::WriteReq 136740 # Transaction distribution -system.iobus.trans_dist::WriteResp 30012 # Transaction distribution +system.iobus.trans_dist::ReadReq 40424 # Transaction distribution +system.iobus.trans_dist::ReadResp 40424 # Transaction distribution +system.iobus.trans_dist::WriteReq 136766 # Transaction distribution +system.iobus.trans_dist::WriteResp 30038 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48186 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1925,13 +2126,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122926 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123068 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231232 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48206 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1946,13 +2147,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156198 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338944 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338944 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496838 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36517000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497228 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36614000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1980,71 +2181,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042881499 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1043031468 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92917000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179159841 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179210230 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115566 # number of replacements -system.iocache.tags.tagsinuse 11.298842 # Cycle average of tags in use +system.iocache.tags.replacements 115597 # number of replacements +system.iocache.tags.tagsinuse 11.297216 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115582 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9120788284000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841658 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.457184 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240104 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466074 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706178 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9126956441000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841188 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.456028 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240074 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466002 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706076 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040622 # Number of tag accesses -system.iocache.tags.data_accesses 1040622 # Number of data accesses +system.iocache.tags.tag_accesses 1040901 # Number of tag accesses +system.iocache.tags.data_accesses 1040901 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8888 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8925 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8857 # number of demand (read+write) misses -system.iocache.demand_misses::total 8897 # number of demand (read+write) misses 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miss cycles +system.iocache.ReadReq_miss_latency::total 1940207608 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28907198811 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28907198811 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1971462847 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1977526847 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1971462847 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1977526847 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28977416630 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28977416630 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6016000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1934548608 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1940564608 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6016000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1934548608 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1940564608 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8888 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8925 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8857 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8897 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8888 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8928 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8857 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8897 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8888 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8928 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2058,55 +2259,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 222588.105115 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 222303.783112 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217390.208179 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270849.250534 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270849.250534 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 222268.949871 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 222268.949871 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228015 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 150400 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217357.146953 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 150400 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217357.146953 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228934 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27566 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27737 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.271603 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.253740 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8888 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8857 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8897 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8888 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8928 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8857 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8897 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1510755865 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1514538865 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8888 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8928 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3735000 # number of ReadReq MSHR miss cycles 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-system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1510755865 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1514739865 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427107084 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427107084 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3936000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1472256614 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1476192614 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3936000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1472256614 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1476192614 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2120,493 +2321,484 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218843.035333 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1797599 # number of replacements -system.l2c.tags.tagsinuse 64905.725288 # Cycle average of tags in use -system.l2c.tags.total_refs 8591301 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1860596 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.617499 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6896032000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 7600.616161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.639535 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 9.409863 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1890.006249 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 324.497512 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 441.216776 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 10554.786238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 27107.423418 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.115976 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000254 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.028839 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.258806 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004951 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006732 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.161053 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.413626 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990383 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 43530 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 179 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1656 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 35370 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1730 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 16555 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.664215 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002731 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.294312 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 89688959 # Number of tag accesses -system.l2c.tags.data_accesses 89688959 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8987 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6604 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 578381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2301852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 8168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5333 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 630016 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2353942 # number of ReadReq hits -system.l2c.ReadReq_hits::total 5893283 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2942617 # number of Writeback hits -system.l2c.Writeback_hits::total 2942617 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.inst 6235 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.inst 6750 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 12985 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.inst 39044 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 35229 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 74273 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 7514 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 7779 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15293 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 64131 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 55187 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 119318 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8987 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6604 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 642512 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 2301852 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 8168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5333 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 685203 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 2353942 # number of demand (read+write) hits -system.l2c.demand_hits::total 6012601 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8987 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6604 # number of overall hits -system.l2c.overall_hits::cpu0.inst 642512 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 2301852 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 8168 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5333 # number of overall hits -system.l2c.overall_hits::cpu1.inst 685203 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 2353942 # number of overall hits -system.l2c.overall_hits::total 6012601 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1978 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1693 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 95514 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 863521 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2685 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2512 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 131326 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 566480 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1665709 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.inst 16918 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.inst 7174 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 24092 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 36442 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 33251 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 69693 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 9494 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 9010 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18504 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 45340 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 52041 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 97381 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1978 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1693 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 140854 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 863521 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2685 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2512 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 183367 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 566480 # number of demand (read+write) misses -system.l2c.demand_misses::total 1763090 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1978 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1693 # number of overall misses -system.l2c.overall_misses::cpu0.inst 140854 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 863521 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2685 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2512 # number of overall misses -system.l2c.overall_misses::cpu1.inst 183367 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 566480 # number of overall misses -system.l2c.overall_misses::total 1763090 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 165226748 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 144557248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 7974806913 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 222345248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 209364000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 10644136699 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 220050587910 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst 3639850 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.inst 3440357 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 7080207 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 167282107 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 155790979 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 323073086 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 53447323 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 50683879 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 104131202 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 3468272337 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 3934530582 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7402802919 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 165226748 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 144557248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 11443079250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 222345248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 209364000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 14578667281 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 227453390829 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 165226748 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 144557248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 11443079250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 222345248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 209364000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 14578667281 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of overall miss cycles -system.l2c.overall_miss_latency::total 227453390829 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 10965 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 8297 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 673895 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 3165373 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10853 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7845 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 761342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2920422 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 7558992 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2942617 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2942617 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.inst 23153 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.inst 13924 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 37077 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 75486 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 68480 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 143966 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 17008 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 16789 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 33797 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 109471 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 107228 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 216699 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10965 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 8297 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 783366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 3165373 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10853 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 868570 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2920422 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 7775691 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10965 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 8297 # number of overall (read+write) accesses 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ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.320204 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.172493 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.220361 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst 0.730704 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst 0.515226 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.649783 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.482765 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.485558 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.484093 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.558208 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.536661 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.547504 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.414174 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.485330 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.449384 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.204050 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.179806 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for demand accesses 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latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 76494.758205 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 75604.438462 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76018.965907 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 129008.383480 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency 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per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 14361.821399 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.117232 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy 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per task id +system.l2c.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4894 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 38831 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.221329 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.696625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 65568567 # Number of tag accesses +system.l2c.tags.data_accesses 65568567 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits 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# number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2478 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2309 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 217381 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) misses +system.l2c.demand_misses::total 1002083 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1664 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1301 # number of overall misses +system.l2c.overall_misses::cpu0.inst 245732 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 274703 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2478 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2309 # number of overall misses +system.l2c.overall_misses::cpu1.inst 217381 # number of overall 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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7718194748 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 418305498 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8136500246 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4773990997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 484709502 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5258700499 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 12492185745 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 903015000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13395200745 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.138323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120052 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.207871 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.775863 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.467828 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.601667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.583921 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.584394 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.585970 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.576077 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.508392 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.226304 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.226304 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67591.919720 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2617,57 +2809,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1764688 # Transaction distribution -system.membus.trans_dist::ReadResp 1764688 # Transaction distribution -system.membus.trans_dist::WriteReq 38271 # Transaction distribution -system.membus.trans_dist::WriteResp 38271 # Transaction distribution -system.membus.trans_dist::Writeback 1325983 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 130519 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 130519 # Transaction distribution -system.membus.trans_dist::UpgradeReq 461811 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 273493 # Transaction distribution -system.membus.trans_dist::UpgradeResp 92294 # Transaction distribution -system.membus.trans_dist::ReadExReq 109929 # Transaction distribution -system.membus.trans_dist::ReadExResp 93588 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122926 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 969598 # Transaction distribution +system.membus.trans_dist::ReadResp 969598 # Transaction distribution +system.membus.trans_dist::WriteReq 38347 # Transaction distribution +system.membus.trans_dist::WriteResp 38347 # Transaction distribution +system.membus.trans_dist::Writeback 1222910 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 662686 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 662686 # Transaction distribution +system.membus.trans_dist::UpgradeReq 426453 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 285961 # Transaction distribution +system.membus.trans_dist::UpgradeResp 115017 # Transaction distribution +system.membus.trans_dist::ReadExReq 144468 # Transaction distribution +system.membus.trans_dist::ReadExResp 127604 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123068 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5737506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5885368 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336109 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336109 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6221477 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5176712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5324942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335765 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335765 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5660707 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156198 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 195441096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 195648244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14110976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 209759220 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 661928 # Total snoops (count) -system.membus.snoop_fanout::samples 3975767 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50220 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174186440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 174394182 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14086976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 188481158 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 617229 # Total snoops (count) +system.membus.snoop_fanout::samples 3621307 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3975767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3621307 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3975767 # Request fanout histogram -system.membus.reqLayer0.occupancy 109763969 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3621307 # Request fanout histogram +system.membus.reqLayer0.occupancy 109998990 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20835993 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20906994 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 15443357238 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 18632739306 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 16944581187 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10660858032 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187180159 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187340770 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2711,45 +2903,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 8566773 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 8559524 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38271 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38271 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2942617 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 143810 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 37077 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 531990 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 288786 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 820776 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 266520 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 266520 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10703555 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10080815 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 20784370 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 361515951 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 330513413 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 692029364 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1718447 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12650717 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.009140 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.095166 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5129422 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5122206 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38347 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38347 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2491671 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 932101 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 825371 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 481339 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 298222 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 779561 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298688 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298688 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8006212 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7112719 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15118931 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267664595 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231600691 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 499265286 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1616950 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9541409 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012122 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109429 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12535087 99.09% 99.09% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115630 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9425751 98.79% 98.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115658 1.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12650717 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 18290340474 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9541409 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 18624671874 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7404000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7692000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20424320611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 12569931680 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 19750107809 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 12640622488 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 0607c3606..3ebfb1ad5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.688410 # Number of seconds simulated -sim_ticks 51688410348500 # Number of ticks simulated -final_tick 51688410348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.728175 # Number of seconds simulated +sim_ticks 51728174627500 # Number of ticks simulated +final_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152333 # Simulator instruction rate (inst/s) -host_op_rate 179011 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8275752383 # Simulator tick rate (ticks/s) -host_mem_usage 662164 # Number of bytes of host memory used -host_seconds 6245.77 # Real time elapsed on the host -sim_insts 951433762 # Number of instructions simulated -sim_ops 1118058358 # Number of ops (including micro ops) simulated +host_inst_rate 184836 # Simulator instruction rate (inst/s) +host_op_rate 217188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10028441874 # Simulator tick rate (ticks/s) +host_mem_usage 718288 # Number of bytes of host memory used +host_seconds 5158.15 # Real time elapsed on the host +sim_insts 953410832 # Number of instructions simulated +sim_ops 1120287994 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 411264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 350272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 77213320 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 415808 # Number of bytes read from this memory -system.physmem.bytes_read::total 78390664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10284736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10284736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 94966144 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 77628104 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory +system.physmem.bytes_read::total 78782088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 94986724 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6426 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5473 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 1206471 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6497 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1224867 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1483846 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 95124388 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1212952 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1486419 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 1493823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1516600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1837281 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1500693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.inst 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1837679 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1837281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1494221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3354280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1224867 # Number of read requests accepted -system.physmem.writeReqs 2137165 # Number of write requests accepted -system.physmem.readBursts 1224867 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2137165 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 78347456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44032 # Total number of bytes read from write queue -system.physmem.bytesWritten 136289472 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78390664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 136634468 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 688 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7616 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39979 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71039 # Per bank write bursts -system.physmem.perBankRdBursts::1 73325 # Per bank write bursts -system.physmem.perBankRdBursts::2 71985 # Per bank write bursts -system.physmem.perBankRdBursts::3 70214 # Per bank write bursts -system.physmem.perBankRdBursts::4 72864 # Per bank write bursts -system.physmem.perBankRdBursts::5 82821 # Per bank write bursts -system.physmem.perBankRdBursts::6 75004 # Per bank write bursts -system.physmem.perBankRdBursts::7 73137 # Per bank write bursts -system.physmem.perBankRdBursts::8 67826 # Per bank write bursts -system.physmem.perBankRdBursts::9 129786 # Per bank write bursts -system.physmem.perBankRdBursts::10 72316 # Per bank write bursts -system.physmem.perBankRdBursts::11 77203 # Per bank write bursts -system.physmem.perBankRdBursts::12 71594 # Per bank write bursts -system.physmem.perBankRdBursts::13 74115 # Per bank write bursts -system.physmem.perBankRdBursts::14 68849 # Per bank write bursts -system.physmem.perBankRdBursts::15 72101 # Per bank write bursts -system.physmem.perBankWrBursts::0 128045 # Per bank write bursts -system.physmem.perBankWrBursts::1 133141 # Per bank write bursts -system.physmem.perBankWrBursts::2 133329 # Per bank write bursts -system.physmem.perBankWrBursts::3 132983 # Per bank write bursts -system.physmem.perBankWrBursts::4 135529 # Per bank write bursts -system.physmem.perBankWrBursts::5 141007 # Per bank write bursts -system.physmem.perBankWrBursts::6 130525 # Per bank write bursts -system.physmem.perBankWrBursts::7 133720 # Per bank write bursts -system.physmem.perBankWrBursts::8 132879 # Per bank write bursts -system.physmem.perBankWrBursts::9 138815 # Per bank write bursts -system.physmem.perBankWrBursts::10 133616 # Per bank write bursts -system.physmem.perBankWrBursts::11 135999 # Per bank write bursts -system.physmem.perBankWrBursts::12 129210 # Per bank write bursts -system.physmem.perBankWrBursts::13 131804 # Per bank write bursts -system.physmem.perBankWrBursts::14 128438 # Per bank write bursts -system.physmem.perBankWrBursts::15 130483 # Per bank write bursts +system.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1501091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1230983 # Number of read requests accepted +system.physmem.writeReqs 2135785 # Number of write requests accepted +system.physmem.readBursts 1230983 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2135785 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 78738176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 44736 # Total number of bytes read from write queue +system.physmem.bytesWritten 136238784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 78782088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 136546148 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 699 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7032 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39789 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 72855 # Per bank write bursts +system.physmem.perBankRdBursts::1 77589 # Per bank write bursts +system.physmem.perBankRdBursts::2 71702 # Per bank write bursts +system.physmem.perBankRdBursts::3 69206 # Per bank write bursts +system.physmem.perBankRdBursts::4 71012 # Per bank write bursts +system.physmem.perBankRdBursts::5 79882 # Per bank write bursts +system.physmem.perBankRdBursts::6 74555 # Per bank write bursts +system.physmem.perBankRdBursts::7 73696 # Per bank write bursts +system.physmem.perBankRdBursts::8 66951 # Per bank write bursts +system.physmem.perBankRdBursts::9 130748 # Per bank write bursts +system.physmem.perBankRdBursts::10 72702 # Per bank write bursts +system.physmem.perBankRdBursts::11 77684 # Per bank write bursts +system.physmem.perBankRdBursts::12 73029 # Per bank write bursts +system.physmem.perBankRdBursts::13 75645 # Per bank write bursts +system.physmem.perBankRdBursts::14 69035 # Per bank write bursts +system.physmem.perBankRdBursts::15 73993 # Per bank write bursts +system.physmem.perBankWrBursts::0 130105 # Per bank write bursts +system.physmem.perBankWrBursts::1 136647 # Per bank write bursts +system.physmem.perBankWrBursts::2 132594 # Per bank write bursts +system.physmem.perBankWrBursts::3 132058 # Per bank write bursts +system.physmem.perBankWrBursts::4 132790 # Per bank write bursts +system.physmem.perBankWrBursts::5 135723 # Per bank write bursts +system.physmem.perBankWrBursts::6 131916 # Per bank write bursts +system.physmem.perBankWrBursts::7 135307 # Per bank write bursts +system.physmem.perBankWrBursts::8 129762 # Per bank write bursts +system.physmem.perBankWrBursts::9 138269 # Per bank write bursts +system.physmem.perBankWrBursts::10 133041 # Per bank write bursts +system.physmem.perBankWrBursts::11 135411 # Per bank write bursts +system.physmem.perBankWrBursts::12 131809 # Per bank write bursts +system.physmem.perBankWrBursts::13 134107 # Per bank write bursts +system.physmem.perBankWrBursts::14 128778 # Per bank write bursts +system.physmem.perBankWrBursts::15 130414 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51688408694500 # Total gap between requests +system.physmem.totGap 51728172924500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1224852 # Read request sizes (log2) +system.physmem.readPktSize::6 1230968 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2134592 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1187733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2133212 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1193516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 30294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -155,118 +155,120 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 48573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 74403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 119873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 132680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 128553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 131972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 134309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 139176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 138776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 133829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 121319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 116942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 113077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 105310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 728572 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.598947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.664587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.125501 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 296144 40.65% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 177091 24.31% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 64790 8.89% 73.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35671 4.90% 78.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25285 3.47% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 17267 2.37% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13064 1.79% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11522 1.58% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 87738 12.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 728572 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97844 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.511242 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 125.941708 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 97842 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 48810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 75161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 120471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 133680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 129638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 132279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 134371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 139270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 139351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 138718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 134041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 121456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 116921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 112653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 104822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 724941 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.543548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 170.840359 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.964737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 292739 40.38% 40.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 175978 24.27% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 64522 8.90% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 36242 5.00% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25200 3.48% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 17306 2.39% 84.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13334 1.84% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11857 1.64% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 87763 12.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 724941 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98383 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.504427 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 125.607658 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 98380 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97844 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97844 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.764472 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.107027 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.533220 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 71394 72.97% 72.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 19346 19.77% 92.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 3261 3.33% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 806 0.82% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 888 0.91% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 399 0.41% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 342 0.35% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 242 0.25% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 261 0.27% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 243 0.25% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 222 0.23% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 63 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 71 0.07% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 48 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 149 0.15% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 24 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 24 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 7 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 12 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 10 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 98383 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.637183 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.054808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.113777 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 71754 72.93% 72.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 19885 20.21% 93.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 3061 3.11% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 745 0.76% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 867 0.88% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 408 0.41% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 354 0.36% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 234 0.24% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 298 0.30% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 183 0.19% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 211 0.21% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 51 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 56 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 41 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 125 0.13% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 21 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 37 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 9 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 12 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97844 # Writes before turning the bus around for reads -system.physmem.totQLat 16127261998 # Total ticks spent queuing -system.physmem.totMemAccLat 39080618248 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6120895000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13173.94 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 98383 # Writes before turning the bus around for reads +system.physmem.totQLat 15890716010 # Total ticks spent queuing +system.physmem.totMemAccLat 38958541010 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6151420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12916.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31923.94 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31666.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -274,36 +276,41 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.82 # Average write queue length when enqueuing -system.physmem.readRowHits 946951 # Number of row buffer hits during reads -system.physmem.writeRowHits 1678178 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.80 # Row buffer hit rate for writes -system.physmem.avgGap 15374157.26 # Average gap between requests -system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49562808778250 # Time in different power states -system.physmem.memoryStateTime::REF 1725989460000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 399611675250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2776243680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2731760640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1514815500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1490544000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 4604987400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 4943562000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6922447920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 6876861120 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3376035383760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3376035383760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1310091236460 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1307916167760 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29863840623750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29865748578750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34565785738470 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34565742858030 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.733833 # Core power per rank (mW) -system.physmem.averagePower::1 668.733004 # Core power per rank (mW) +system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing +system.physmem.readRowHits 953619 # Number of row buffer hits during reads +system.physmem.writeRowHits 1680454 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes +system.physmem.avgGap 15364341.39 # Average gap between requests +system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2748558960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1499709750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4605829800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6915067200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1310572243215 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29887277315250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34592251323855 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.731394 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49719326487750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1727317280000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 281530424750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2731995000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1490671875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4990338600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6879109680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1309819963770 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29887937201250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34592481879855 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.735851 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49720391571002 # Time in different power states +system.physmem_1.memoryStateTime::REF 1727317280000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory @@ -322,16 +329,24 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261297703 # Number of BP lookups -system.cpu.branchPred.condPredicted 183348683 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12210638 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193789546 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136743179 # Number of BTB hits +system.cpu.branchPred.lookups 261740307 # Number of BP lookups +system.cpu.branchPred.condPredicted 183617747 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12193617 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193974198 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136954935 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.562722 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31690204 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2146162 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.604718 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31757981 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2120874 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -353,27 +368,69 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 587644 # Table walker walks requested +system.cpu.dtb.walker.walksLong 587644 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20971 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 193860 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 587644 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 587644 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 587644 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 214831 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23073.231987 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18856.280230 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 14797.492454 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 212337 98.84% 98.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2138 1.00% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 152 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 133 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 38 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 214831 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -243009796 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -243009796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -243009796 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 193861 90.24% 90.24% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 20971 9.76% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 214832 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 587644 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 587644 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 214832 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 214832 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 802476 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183672011 # DTB read hits -system.cpu.dtb.read_misses 484545 # DTB read misses -system.cpu.dtb.write_hits 163011983 # DTB write hits -system.cpu.dtb.write_misses 101734 # DTB write misses +system.cpu.dtb.read_hits 184101010 # DTB read hits +system.cpu.dtb.read_misses 486113 # DTB read misses +system.cpu.dtb.write_hits 163332837 # DTB write hits +system.cpu.dtb.write_misses 101531 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47427 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80165 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 779 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14148 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 79171 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14871 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23574 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184156556 # DTB read accesses -system.cpu.dtb.write_accesses 163113717 # DTB write accesses +system.cpu.dtb.perms_faults 23598 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 184587123 # DTB read accesses +system.cpu.dtb.write_accesses 163434368 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 346683994 # DTB hits -system.cpu.dtb.misses 586279 # DTB misses -system.cpu.dtb.accesses 347270273 # DTB accesses +system.cpu.dtb.hits 347433847 # DTB hits +system.cpu.dtb.misses 587644 # DTB misses +system.cpu.dtb.accesses 348021491 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -395,142 +452,175 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 455292001 # ITB inst hits -system.cpu.itb.inst_misses 136900 # ITB inst misses +system.cpu.itb.walker.walks 136955 # Table walker walks requested +system.cpu.itb.walker.walksLong 136955 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1083 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 119238 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136955 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136955 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136955 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 120321 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 25178.697160 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 21090.590253 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 16725.174106 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 117467 97.63% 97.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2593 2.16% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 161 0.13% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 40 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 38 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 120321 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -243525796 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -243525796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -243525796 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 119238 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1083 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 120321 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136955 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136955 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120321 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 120321 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 257276 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 455989522 # ITB inst hits +system.cpu.itb.inst_misses 136955 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47427 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57667 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 56761 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 366615 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 364272 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 455428901 # ITB inst accesses -system.cpu.itb.hits 455292001 # DTB hits -system.cpu.itb.misses 136900 # DTB misses -system.cpu.itb.accesses 455428901 # DTB accesses -system.cpu.numCycles 2518825477 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 456126477 # ITB inst accesses +system.cpu.itb.hits 455989522 # DTB hits +system.cpu.itb.misses 136955 # DTB misses +system.cpu.itb.accesses 456126477 # DTB accesses +system.cpu.numCycles 2523007146 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 951433762 # Number of instructions committed -system.cpu.committedOps 1118058358 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97427430 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7769 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100859175256 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.647400 # CPI: cycles per instruction -system.cpu.ipc 0.377729 # IPC: instructions per cycle +system.cpu.committedInsts 953410832 # Number of instructions committed +system.cpu.committedOps 1120287994 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97416264 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100934517430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.646296 # CPI: cycles per instruction +system.cpu.ipc 0.377887 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16629 # number of quiesce instructions executed -system.cpu.tickCycles 1804872231 # Number of cycles that the object actually ticked -system.cpu.idleCycles 713953246 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11184340 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.959663 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 330369377 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11184852 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.537215 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed +system.cpu.tickCycles 1807938889 # Number of cycles that the object actually ticked +system.cpu.idleCycles 715068257 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11209162 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.959689 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 331084794 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959663 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959689 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1387996074 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1387996074 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 169370817 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 169370817 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 152148495 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 152148495 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 336885 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 336885 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4109295 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4109295 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 4353813 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4353813 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 321519312 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 321519312 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 321519312 # number of overall hits -system.cpu.dcache.overall_hits::total 321519312 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 8065146 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 8065146 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 4327048 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4327048 # number of WriteReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst 1245044 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245044 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 246250 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 246250 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 169770938 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 152453541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 337498 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 337498 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4114364 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4114364 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 4358642 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4358642 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 322224479 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322224479 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 322224479 # number of overall hits +system.cpu.dcache.overall_hits::total 322224479 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 8085158 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 8085158 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 4338895 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4338895 # number of WriteReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst 1245002 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1245002 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 246013 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 246013 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 12392194 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12392194 # number of demand (read+write) misses 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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12525.316945 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12525.316945 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029191 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029191 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13988.652101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30209.600192 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192 # average WriteReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21781.079621 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12510.001654 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 73250 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18038.011625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18038.011625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18038.011625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18038.011625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -622,58 +712,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24658250 # number of replacements -system.cpu.icache.tags.tagsinuse 511.931964 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 430254710 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24658762 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.448350 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 21183887000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.931964 # Average occupied blocks per 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-system.cpu.icache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 479572253 # Number of tag accesses -system.cpu.icache.tags.data_accesses 479572253 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 430254710 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 430254710 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 430254710 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 430254710 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 430254710 # number of overall hits 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latency +system.cpu.icache.demand_avg_miss_latency::total 13288.974753 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13288.974753 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,189 +772,188 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24658772 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24658772 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24658772 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24658772 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24658772 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24658772 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 278428644242 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 278428644242 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 278428644242 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 278428644242 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 278428644242 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 278428644242 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24726512 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24726512 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24726512 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24726512 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24726512 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24726512 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279088621775 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 279088621775 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 279088621775 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 279088621775 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 279088621775 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 279088621775 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812277750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812277750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812277750 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 3812277750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054205 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054205 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054205 # mshr miss rate for demand accesses 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11287.019446 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1618781 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65312.211718 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 40301488 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1682083 # Sample count of references to valid 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miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66353.874883 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67053.809611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62314.213317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62358.670485 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61582.977042 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -974,58 +1063,58 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 34021842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 34013749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8574653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244894 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 50067 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 34111380 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 34103268 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8593512 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49806 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 50069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2383072 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2383072 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49422067 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31180667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697225 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2277994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 83577953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581505984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1264852800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2305528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7806528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2856470840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 563561 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 46295151 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002496 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.049898 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 49808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2389846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2389846 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49557548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31248640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2279215 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83780992 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585841408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1267646988 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2291264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7787728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2863567388 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 571370 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 46410026 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002490 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049834 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 46179597 99.75% 99.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115554 0.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 46294483 99.75% 99.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115543 0.25% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46295151 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32987192886 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 46410026 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 33063458385 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1194000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1149000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37103090732 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37204558207 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15825165926 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15864083234 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 409755911 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 409855669 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1302956232 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1306481232 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40416 # Transaction distribution -system.iobus.trans_dist::ReadResp 40416 # Transaction distribution +system.iobus.trans_dist::ReadReq 40405 # Transaction distribution +system.iobus.trans_dist::ReadResp 40405 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1045,11 +1134,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231028 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354298 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354276 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1066,11 +1155,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334544 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492950 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492862 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1099,71 +1188,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042369212 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042384689 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179072505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179052263 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115495 # number of replacements -system.iocache.tags.tagsinuse 10.448328 # Cycle average of tags in use +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.452585 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115511 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13141221301000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519405 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928922 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219963 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433058 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653020 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13141230176000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.516704 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935881 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219794 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433493 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653287 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039983 # Number of tag accesses -system.iocache.tags.data_accesses 1039983 # Number of data accesses +system.iocache.tags.tag_accesses 1039884 # Number of tag accesses +system.iocache.tags.data_accesses 1039884 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8850 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8887 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8850 # number of demand (read+write) misses -system.iocache.demand_misses::total 8890 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses +system.iocache.demand_misses::total 8879 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8850 # number of overall misses -system.iocache.overall_misses::total 8890 # number of overall misses +system.iocache.overall_misses::realview.ide 8839 # number of overall misses +system.iocache.overall_misses::total 8879 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1921500610 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1926985610 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1924538358 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1930023358 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28836803097 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28836803097 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28851084068 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28851084068 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1921500610 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1927324610 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1924538358 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1930362358 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1921500610 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1927324610 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1924538358 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1930362358 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8850 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8887 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8850 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8890 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8850 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8890 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1178,54 +1267,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217118.712994 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 216831.957916 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 217732.589433 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217442.920009 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270351.787829 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270351.787829 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270485.675279 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270485.675279 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217118.712994 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 216796.919010 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217407.631265 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217118.712994 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 216796.919010 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 224459 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217407.631265 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 225366 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27520 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27560 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.156214 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.177286 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8850 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8887 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8850 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8890 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8850 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8890 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1461199612 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1464760612 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1464798862 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1468359862 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23290267105 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23290267105 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23304534090 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23304534090 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1461199612 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1464943612 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1464798862 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1468542862 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1461199612 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1464943612 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1464798862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1468542862 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1240,70 +1329,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165107.300791 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 164820.593226 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165719.975337 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165430.358495 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218351.712902 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218351.712902 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218485.469230 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218485.469230 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165107.300791 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 164785.558155 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165107.300791 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 164785.558155 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 549050 # Transaction distribution -system.membus.trans_dist::ReadResp 549050 # Transaction distribution -system.membus.trans_dist::WriteReq 33869 # Transaction distribution -system.membus.trans_dist::WriteResp 33869 # Transaction distribution -system.membus.trans_dist::Writeback 1483846 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 650746 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 650746 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39985 # Transaction distribution +system.membus.trans_dist::ReadReq 548979 # Transaction distribution +system.membus.trans_dist::ReadResp 548979 # Transaction distribution +system.membus.trans_dist::WriteReq 33870 # Transaction distribution +system.membus.trans_dist::WriteResp 33870 # Transaction distribution +system.membus.trans_dist::Writeback 1485997 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 647215 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 647215 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39795 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39987 # Transaction distribution -system.membus.trans_dist::ReadExReq 712642 # Transaction distribution -system.membus.trans_dist::ReadExResp 712642 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39797 # Transaction distribution +system.membus.trans_dist::ReadExReq 718688 # Transaction distribution +system.membus.trans_dist::ReadExResp 718688 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4987889 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5118031 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335345 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335345 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5453376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4994566 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5124714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5460180 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 200958508 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201129408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14066624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 215196032 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3058 # Total snoops (count) -system.membus.snoop_fanout::samples 3350229 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13852 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201253164 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201424076 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14075072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14075072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 215499148 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2915 # Total snoops (count) +system.membus.snoop_fanout::samples 3354632 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3350229 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3354632 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3350229 # Request fanout histogram -system.membus.reqLayer0.occupancy 113834500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3354632 # Request fanout histogram +system.membus.reqLayer0.occupancy 113785000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5697498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5606499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 21359860992 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 21358745741 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12431404244 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 12484485177 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186704495 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186617737 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1314,11 +1403,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 4496ee012..3916ea1cc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.320621 # Number of seconds simulated -sim_ticks 51320620981500 # Number of ticks simulated -final_tick 51320620981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.320647 # Number of seconds simulated +sim_ticks 51320647066500 # Number of ticks simulated +final_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75246 # Simulator instruction rate (inst/s) -host_op_rate 88415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4505389037 # Simulator tick rate (ticks/s) -host_mem_usage 667676 # Number of bytes of host memory used -host_seconds 11390.94 # Real time elapsed on the host -sim_insts 857117694 # Number of instructions simulated -sim_ops 1007133124 # Number of ops (including micro ops) simulated +host_inst_rate 81694 # Simulator instruction rate (inst/s) +host_op_rate 95992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4889396972 # Simulator tick rate (ticks/s) +host_mem_usage 723156 # Number of bytes of host memory used +host_seconds 10496.31 # Real time elapsed on the host +sim_insts 857487967 # Number of instructions simulated +sim_ops 1007562352 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 227264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 206272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5756576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43073416 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 400256 # Number of bytes read from this memory -system.physmem.bytes_read::total 49663784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5756576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5756576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69780544 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory +system.physmem.bytes_read::total 49637032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69801124 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3551 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3223 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 673035 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6254 # Number of read requests responded to by this memory -system.physmem.num_reads::total 791962 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1090321 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69739044 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory +system.physmem.num_reads::total 791544 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1092894 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 112169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 839300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 967716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 112169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 112169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1359698 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1360099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1359698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 112169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 839701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2327815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 791962 # Number of read requests accepted -system.physmem.writeReqs 1696531 # Number of write requests accepted -system.physmem.readBursts 791962 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1696531 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 50649920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35648 # Total number of bytes read from write queue -system.physmem.bytesWritten 108090368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49663784 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 108433892 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 557 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7601 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35291 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 50546 # Per bank write bursts -system.physmem.perBankRdBursts::1 51810 # Per bank write bursts -system.physmem.perBankRdBursts::2 46789 # Per bank write bursts -system.physmem.perBankRdBursts::3 46242 # Per bank write bursts -system.physmem.perBankRdBursts::4 46096 # Per bank write bursts -system.physmem.perBankRdBursts::5 52242 # Per bank write bursts -system.physmem.perBankRdBursts::6 46925 # Per bank write bursts -system.physmem.perBankRdBursts::7 49452 # Per bank write bursts -system.physmem.perBankRdBursts::8 44750 # Per bank write bursts -system.physmem.perBankRdBursts::9 73148 # Per bank write bursts -system.physmem.perBankRdBursts::10 48402 # Per bank write bursts -system.physmem.perBankRdBursts::11 51457 # Per bank write bursts -system.physmem.perBankRdBursts::12 45806 # Per bank write bursts -system.physmem.perBankRdBursts::13 48601 # Per bank write bursts -system.physmem.perBankRdBursts::14 42635 # Per bank write bursts -system.physmem.perBankRdBursts::15 46504 # Per bank write bursts -system.physmem.perBankWrBursts::0 106325 # Per bank write bursts -system.physmem.perBankWrBursts::1 106592 # Per bank write bursts -system.physmem.perBankWrBursts::2 106293 # Per bank write bursts -system.physmem.perBankWrBursts::3 105191 # Per bank write bursts -system.physmem.perBankWrBursts::4 106687 # Per bank write bursts -system.physmem.perBankWrBursts::5 109171 # Per bank write bursts -system.physmem.perBankWrBursts::6 103226 # Per bank write bursts -system.physmem.perBankWrBursts::7 105745 # Per bank write bursts -system.physmem.perBankWrBursts::8 103090 # Per bank write bursts -system.physmem.perBankWrBursts::9 109771 # Per bank write bursts -system.physmem.perBankWrBursts::10 107182 # Per bank write bursts -system.physmem.perBankWrBursts::11 108709 # Per bank write bursts -system.physmem.perBankWrBursts::12 102154 # Per bank write bursts -system.physmem.perBankWrBursts::13 106063 # Per bank write bursts -system.physmem.perBankWrBursts::14 100653 # Per bank write bursts -system.physmem.perBankWrBursts::15 102060 # Per bank write bursts +system.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 791544 # Number of read requests accepted +system.physmem.writeReqs 1694292 # Number of write requests accepted +system.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue +system.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 48315 # Per bank write bursts +system.physmem.perBankRdBursts::1 50150 # Per bank write bursts +system.physmem.perBankRdBursts::2 46175 # Per bank write bursts +system.physmem.perBankRdBursts::3 46946 # Per bank write bursts +system.physmem.perBankRdBursts::4 45323 # Per bank write bursts +system.physmem.perBankRdBursts::5 52981 # Per bank write bursts +system.physmem.perBankRdBursts::6 47646 # Per bank write bursts +system.physmem.perBankRdBursts::7 48748 # Per bank write bursts +system.physmem.perBankRdBursts::8 44337 # Per bank write bursts +system.physmem.perBankRdBursts::9 72322 # Per bank write bursts +system.physmem.perBankRdBursts::10 50834 # Per bank write bursts +system.physmem.perBankRdBursts::11 50772 # Per bank write bursts +system.physmem.perBankRdBursts::12 48451 # Per bank write bursts +system.physmem.perBankRdBursts::13 47387 # Per bank write bursts +system.physmem.perBankRdBursts::14 44232 # Per bank write bursts +system.physmem.perBankRdBursts::15 46363 # Per bank write bursts +system.physmem.perBankWrBursts::0 103979 # Per bank write bursts +system.physmem.perBankWrBursts::1 105038 # Per bank write bursts +system.physmem.perBankWrBursts::2 105754 # Per bank write bursts +system.physmem.perBankWrBursts::3 105161 # Per bank write bursts +system.physmem.perBankWrBursts::4 103562 # Per bank write bursts +system.physmem.perBankWrBursts::5 108435 # Per bank write bursts +system.physmem.perBankWrBursts::6 103867 # Per bank write bursts +system.physmem.perBankWrBursts::7 105467 # Per bank write bursts +system.physmem.perBankWrBursts::8 102645 # Per bank write bursts +system.physmem.perBankWrBursts::9 108407 # Per bank write bursts +system.physmem.perBankWrBursts::10 108582 # Per bank write bursts +system.physmem.perBankWrBursts::11 107982 # Per bank write bursts +system.physmem.perBankWrBursts::12 105330 # Per bank write bursts +system.physmem.perBankWrBursts::13 105345 # Per bank write bursts +system.physmem.perBankWrBursts::14 103911 # Per bank write bursts +system.physmem.perBankWrBursts::15 104029 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 63 # Number of times write queue was full causing retry -system.physmem.totGap 51320619748500 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 51320645833500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 770677 # Read request sizes (log2) +system.physmem.readPktSize::6 770259 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1693958 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 524690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 218670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1691719 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,122 +159,122 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 66510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 80685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 95220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 95674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 107871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 105650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 115186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 109604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 123316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 110089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 89808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 90193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 76388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 74826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 71320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 2041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 151 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 519847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.358892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.693203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.458813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210597 40.51% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 125304 24.10% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44434 8.55% 73.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23828 4.58% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16026 3.08% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10297 1.98% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8038 1.55% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7736 1.49% 85.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 73587 14.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 519847 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65806 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.026092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 69.420005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 65801 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 97233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 109038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 106907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 116227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 110532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 123491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 110542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 98237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 89628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 89775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 76304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 74747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 73803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 70600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4308 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::46 2307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 519566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 305.297267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65806 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65806 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.665015 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 22.295407 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 18.784846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 44130 67.06% 67.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6726 10.22% 77.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 8110 12.32% 89.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 2086 3.17% 92.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1158 1.76% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 536 0.81% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 588 0.89% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 530 0.81% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 479 0.73% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 220 0.33% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 383 0.58% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 149 0.23% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 276 0.42% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 79 0.12% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 128 0.19% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 41 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 35 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 20 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 44 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 20 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 23 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 10 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65806 # Writes before turning the bus around for reads -system.physmem.totQLat 15790981009 # Total ticks spent queuing -system.physmem.totMemAccLat 30629824759 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3957025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19953.10 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads +system.physmem.totQLat 15484448260 # Total ticks spent queuing +system.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38703.10 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -282,36 +282,41 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.05 # Average write queue length when enqueuing -system.physmem.readRowHits 603831 # Number of row buffer hits during reads -system.physmem.writeRowHits 1356638 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes -system.physmem.avgGap 20623172.24 # Average gap between requests +system.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing +system.physmem.readRowHits 603455 # Number of row buffer hits during reads +system.physmem.writeRowHits 1355453 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes +system.physmem.avgGap 20645225.93 # Average gap between requests system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49368372569000 # Time in different power states -system.physmem.memoryStateTime::REF 1713708100000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 238539960500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 1984348800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1945694520 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1082730000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1061638875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3042748800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3130163400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5503010400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5441139360 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3352013043600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3352013043600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1228384903950 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1226638074825 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29714838054000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29716370360250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34306848839550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34306600114830 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.480867 # Core power per rank (mW) -system.physmem.averagePower::1 668.476020 # Core power per rank (mW) +system.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.473889 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.480369 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory @@ -334,16 +339,24 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 226428976 # Number of BP lookups -system.cpu.branchPred.condPredicted 151471445 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12246087 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159886473 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104578062 # Number of BTB hits +system.cpu.branchPred.lookups 226505876 # Number of BP lookups +system.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104610641 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.407698 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31061917 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 345275 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -365,27 +378,53 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 200647 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 200647 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 200647 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 200647 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 200647 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 1467106000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 1467106000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 1467106000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 155618 91.17% 91.17% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 15067 8.83% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 170685 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 200647 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 200647 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 170685 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 170685 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 371332 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 161215407 # DTB read hits -system.cpu.checker.dtb.read_misses 149229 # DTB read misses -system.cpu.checker.dtb.write_hits 146260364 # DTB write hits -system.cpu.checker.dtb.write_misses 51460 # DTB write misses +system.cpu.checker.dtb.read_hits 161284967 # DTB read hits +system.cpu.checker.dtb.read_misses 149209 # DTB read misses +system.cpu.checker.dtb.write_hits 146334371 # DTB write hits +system.cpu.checker.dtb.write_misses 51438 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 72721 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 72843 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 7177 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 7088 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 19208 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 161364636 # DTB read accesses -system.cpu.checker.dtb.write_accesses 146311824 # DTB write accesses +system.cpu.checker.dtb.read_accesses 161434176 # DTB read accesses +system.cpu.checker.dtb.write_accesses 146385809 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 307475771 # DTB hits -system.cpu.checker.dtb.misses 200689 # DTB misses -system.cpu.checker.dtb.accesses 307676460 # DTB accesses +system.cpu.checker.dtb.hits 307619338 # DTB hits +system.cpu.checker.dtb.misses 200647 # DTB misses +system.cpu.checker.dtb.accesses 307819985 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -407,8 +446,26 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 857529218 # ITB inst hits -system.cpu.checker.itb.inst_misses 120798 # ITB inst misses +system.cpu.checker.itb.walker.walks 120779 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 120779 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 120779 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 120779 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 120779 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples 1466561000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 1466561000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 1466561000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 108783 98.83% 98.83% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1287 1.17% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 110070 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120779 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120779 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 110070 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 110070 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 230849 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 857899518 # ITB inst hits +system.cpu.checker.itb.inst_misses 120779 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits @@ -417,20 +474,28 @@ system.cpu.checker.itb.flush_tlb 20 # Nu system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 52233 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 52284 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 857650016 # ITB inst accesses -system.cpu.checker.itb.hits 857529218 # DTB hits -system.cpu.checker.itb.misses 120798 # DTB misses -system.cpu.checker.itb.accesses 857650016 # DTB accesses -system.cpu.checker.numCycles 1007708571 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 858020297 # ITB inst accesses +system.cpu.checker.itb.hits 857899518 # DTB hits +system.cpu.checker.itb.misses 120779 # DTB misses +system.cpu.checker.itb.accesses 858020297 # DTB accesses +system.cpu.checker.numCycles 1008137807 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -452,27 +517,95 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 931379 # Table walker walks requested +system.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 171196432 # DTB read hits -system.cpu.dtb.read_misses 671544 # DTB read misses -system.cpu.dtb.write_hits 149025904 # DTB write hits -system.cpu.dtb.write_misses 258759 # DTB write misses +system.cpu.dtb.read_hits 171278986 # DTB read hits +system.cpu.dtb.read_misses 671795 # DTB read misses +system.cpu.dtb.write_hits 149102166 # DTB write hits +system.cpu.dtb.write_misses 259584 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72979 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 104 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10362 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 68614 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171867976 # DTB read accesses -system.cpu.dtb.write_accesses 149284663 # DTB write accesses +system.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171950781 # DTB read accesses +system.cpu.dtb.write_accesses 149361750 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320222336 # DTB hits -system.cpu.dtb.misses 930303 # DTB misses -system.cpu.dtb.accesses 321152639 # DTB accesses +system.cpu.dtb.hits 320381152 # DTB hits +system.cpu.dtb.misses 931379 # DTB misses +system.cpu.dtb.accesses 321312531 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -494,8 +627,66 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 360051885 # ITB inst hits -system.cpu.itb.inst_misses 161655 # ITB inst misses +system.cpu.itb.walker.walks 161841 # Table walker walks requested +system.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 360168043 # ITB inst hits +system.cpu.itb.inst_misses 161841 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -504,111 +695,111 @@ system.cpu.itb.flush_tlb 20 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53701 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372863 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 360213540 # ITB inst accesses -system.cpu.itb.hits 360051885 # DTB hits -system.cpu.itb.misses 161655 # DTB misses -system.cpu.itb.accesses 360213540 # DTB accesses -system.cpu.numCycles 1576874693 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 360329884 # ITB inst accesses +system.cpu.itb.hits 360168043 # DTB hits +system.cpu.itb.misses 161841 # DTB misses +system.cpu.itb.accesses 360329884 # DTB accesses +system.cpu.numCycles 1576983833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 648679854 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1010290403 # Number of instructions fetch has processed -system.cpu.fetch.Branches 226428976 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135639979 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 852655064 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26160452 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3389644 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9240220 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1021673 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 359662567 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6136086 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47510 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1528093850 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.774691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed +system.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 965958627 63.21% 63.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215893777 14.13% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70817340 4.63% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 275424106 18.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1528093850 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.143594 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.640692 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 527180052 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 504302107 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 436284853 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51059674 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9267164 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33905862 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3872221 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1095429909 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29099398 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9267164 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 572442291 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46180186 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363186865 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 441948285 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 95069059 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1075584704 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6788495 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4945824 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 318864 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 589123 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 42956715 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 21763 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1023437611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1659121727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1272319582 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1685396 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 957674620 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65762988 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27435128 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23745394 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104747763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 175168030 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 152601618 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9963388 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9061948 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1040022976 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27737741 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1056135120 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3300763 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53598061 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33623556 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 314928 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1528093850 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691145 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.927830 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 436470729 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 442135288 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 873977548 57.19% 57.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 338098484 22.13% 79.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 236626258 15.49% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72801252 4.76% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6571176 0.43% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19132 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1528093850 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58371154 35.14% 35.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100885 0.06% 35.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26756 0.02% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available @@ -631,19 +822,19 @@ system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # at system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 767 0.00% 35.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44544414 26.81% 62.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63075062 37.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 727332382 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2546997 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 123061 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -665,102 +856,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 120668 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 175096796 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150915164 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1056135120 # Type of FU issued -system.cpu.iq.rate 0.669765 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166119038 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3807304115 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1120557954 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1038099529 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2479775 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 941816 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 907592 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1220693938 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1560218 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4348848 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued +system.cpu.iq.rate 0.670005 # Inst issue rate +system.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13855252 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14404 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142361 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6337064 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2552747 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1859122 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9267164 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6379535 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3965873 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1067985048 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 175168030 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 152601618 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23314125 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 62024 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3832996 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142361 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3691152 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5135953 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8827105 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1044930592 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171186057 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10287379 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224331 # number of nop insts executed -system.cpu.iew.exec_refs 320208959 # number of memory reference insts executed -system.cpu.iew.exec_branches 198322451 # Number of branches executed -system.cpu.iew.exec_stores 149022902 # Number of stores executed -system.cpu.iew.exec_rate 0.662659 # Inst execution rate -system.cpu.iew.wb_sent 1039793819 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1039007121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 442154878 # num instructions producing a value -system.cpu.iew.wb_consumers 715627882 # num instructions consuming a value +system.cpu.iew.exec_nop 224348 # number of nop insts executed +system.cpu.iew.exec_refs 320367802 # number of memory reference insts executed +system.cpu.iew.exec_branches 198404489 # Number of branches executed +system.cpu.iew.exec_stores 149099070 # Number of stores executed +system.cpu.iew.exec_rate 0.662897 # Inst execution rate +system.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back +system.cpu.iew.wb_producers 442335874 # num instructions producing a value +system.cpu.iew.wb_consumers 715873221 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.658903 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.617856 # average fanout of values written-back +system.cpu.iew.wb_rate 0.659130 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51471265 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27422813 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8433025 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1516084212 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.664299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.291990 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 998537580 65.86% 65.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 291350566 19.22% 85.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121957393 8.04% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36696853 2.42% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28610485 1.89% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14255849 0.94% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8557612 0.56% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4232636 0.28% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11885238 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1516084212 # Number of insts commited each cycle -system.cpu.commit.committedInsts 857117694 # Number of instructions committed -system.cpu.commit.committedOps 1007133124 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle +system.cpu.commit.committedInsts 857487967 # Number of instructions committed +system.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 307577331 # Number of memory references committed -system.cpu.commit.loads 161312777 # Number of loads committed -system.cpu.commit.membars 7014752 # Number of memory barriers committed -system.cpu.commit.branches 191334741 # Number of branches committed -system.cpu.commit.fp_insts 896026 # Number of committed floating point instructions. -system.cpu.commit.int_insts 925144388 # Number of committed integer instructions. -system.cpu.commit.function_calls 25493443 # Number of function calls committed. +system.cpu.commit.refs 307720812 # Number of memory references committed +system.cpu.commit.loads 161382253 # Number of loads committed +system.cpu.commit.membars 7017472 # Number of memory barriers committed +system.cpu.commit.branches 191417503 # Number of branches committed +system.cpu.commit.fp_insts 895898 # Number of committed floating point instructions. +system.cpu.commit.int_insts 925548459 # Number of committed integer instructions. +system.cpu.commit.function_calls 25509836 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 697181314 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2164633 0.21% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98281 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction @@ -787,233 +978,232 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 161312777 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 146264554 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1007133124 # Class of committed instruction -system.cpu.commit.bw_lim_events 11885238 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction +system.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2555181565 # The number of ROB reads -system.cpu.rob.rob_writes 2129123637 # The number of ROB writes -system.cpu.timesIdled 8137810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 48780843 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101064367400 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 857117694 # Number of Instructions Simulated -system.cpu.committedOps 1007133124 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.839741 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.839741 # CPI: Total CPI of All Threads -system.cpu.ipc 0.543555 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.543555 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237020079 # number of integer regfile reads -system.cpu.int_regfile_writes 738429838 # number of integer regfile writes -system.cpu.fp_regfile_reads 1457787 # number of floating regfile reads -system.cpu.fp_regfile_writes 782552 # number of floating regfile writes -system.cpu.cc_regfile_reads 228125574 # number of cc regfile reads -system.cpu.cc_regfile_writes 228731881 # number of cc regfile writes -system.cpu.misc_regfile_reads 5247037954 # number of misc regfile reads -system.cpu.misc_regfile_writes 27486572 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9822538 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.985265 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 286045243 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9823050 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.119799 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.985265 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 2555751551 # The number of ROB reads +system.cpu.rob.rob_writes 2129995502 # The number of ROB writes +system.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 857487967 # Number of Instructions Simulated +system.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.839074 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads +system.cpu.ipc 0.543752 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237547063 # number of integer regfile reads +system.cpu.int_regfile_writes 738733253 # number of integer regfile writes +system.cpu.fp_regfile_reads 1457540 # number of floating regfile reads +system.cpu.fp_regfile_writes 782548 # number of floating regfile writes +system.cpu.cc_regfile_reads 228190122 # number of cc regfile reads +system.cpu.cc_regfile_writes 228796042 # number of cc regfile writes +system.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads +system.cpu.misc_regfile_writes 27489325 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9822587 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1249214859 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1249214859 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148712432 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148712432 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 129479125 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 129479125 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 381594 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 381594 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324870 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 324870 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352883 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3352883 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3750315 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3750315 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 278191557 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 278191557 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 278573151 # number of overall hits -system.cpu.dcache.overall_hits::total 278573151 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9502058 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9502058 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11465174 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11465174 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1197022 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1197022 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233022 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1233022 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 449448 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 449448 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 129548885 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 381333 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 381333 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324563 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 324563 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352422 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3352422 # number of LoadLockedReq hits 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-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118203 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses) 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number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses 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average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22126.282237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20931.310973 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21466802 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1401851 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.313184 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7593763 # number of writebacks -system.cpu.dcache.writebacks::total 7593763 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4321399 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4321399 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 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miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753971 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753971 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786940 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786940 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060498 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060498 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 142481111443 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729238749 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729238749 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587095483 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587095483 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316334232 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316334232 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 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average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024123 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024123 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027953 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027953 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1021,276 +1211,277 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 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(read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208192919846 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208192919846 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208192919846 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 359757746 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 359757746 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 359757746 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 359757746 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 359757746 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 359757746 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043924 # miss rate for ReadReq accesses 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cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 53771748899 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 239359749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 220243499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5475082762 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47837062889 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 53771748899 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1103982250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289733251 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393715501 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176071500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176071500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103982250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465804751 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569787001 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.039032 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.405499 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.405499 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784600 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29394156879 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29394156879 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 240086499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 221074750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5441255518 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47510992143 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 53413408910 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 240086499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 221074750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5441255518 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47510992143 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 53413408910 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1103864500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289749251 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393613751 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176073500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176073500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103864500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465822751 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569687251 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038843 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015245 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404389 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404389 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784594 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784594 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208413 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208413 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078433 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030898 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078433 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030898 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64684.412911 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70909.720754 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69340.102872 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39429.331460 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39429.331460 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10015.230943 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.230943 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208727 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030869 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030869 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70964.035146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1416,32 +1607,32 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23341232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23333163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7593763 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1225967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43982 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1999866 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1999866 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30208899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27463876 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 731462 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1967033 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 60371270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965659760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1114918084 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2404176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6408648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2089390668 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 611685 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34508223 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.003348 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.057762 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 606880 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.003347 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram @@ -1452,26 +1643,26 @@ system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 34392703 99.67% 99.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 115520 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 34397489 99.67% 99.67% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 115519 0.33% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34508223 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 26206492236 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1177500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22671590732 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13674088224 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 431886005 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1166711358 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40382 # Transaction distribution -system.iobus.trans_dist::ReadResp 40382 # Transaction distribution +system.iobus.trans_dist::ReadReq 40381 # Transaction distribution +system.iobus.trans_dist::ReadResp 40381 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1491,11 +1682,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1512,11 +1703,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1545,71 +1736,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042360658 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179004169 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115462 # number of replacements -system.iocache.tags.tagsinuse 10.424613 # Cycle average of tags in use +system.iocache.tags.replacements 115461 # number of replacements +system.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115478 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13092189065000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544618 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879995 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039677 # Number of tag accesses -system.iocache.tags.data_accesses 1039677 # Number of data accesses +system.iocache.tags.tag_accesses 1039668 # Number of tag accesses +system.iocache.tags.data_accesses 1039668 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses -system.iocache.demand_misses::total 8856 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses +system.iocache.demand_misses::total 8855 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8816 # number of overall misses -system.iocache.overall_misses::total 8856 # number of overall misses +system.iocache.overall_misses::realview.ide 8815 # number of overall misses +system.iocache.overall_misses::total 8855 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1927411613 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1932938613 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1934147111 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1939674111 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28910124876 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28910124876 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28899223848 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28899223848 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1927411613 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1933277613 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1934147111 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1940013111 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1927411613 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1933277613 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1934147111 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1940013111 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1624,54 +1815,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 218337.130125 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 218301.446816 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 218301.446816 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 226675 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27646 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.199197 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8816 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8856 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1468863623 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1472466623 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23363269204 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23363269204 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1468863623 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1472649623 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1468863623 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1472649623 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1686,70 +1877,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 412825 # Transaction distribution -system.membus.trans_dist::ReadResp 412825 # Transaction distribution +system.membus.trans_dist::ReadReq 411277 # Transaction distribution +system.membus.trans_dist::ReadResp 411277 # Transaction distribution system.membus.trans_dist::WriteReq 33858 # Transaction distribution system.membus.trans_dist::WriteResp 33858 # Transaction distribution -system.membus.trans_dist::Writeback 1090321 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 603637 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 603637 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35296 # Transaction distribution +system.membus.trans_dist::Writeback 1089351 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35261 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35298 # Transaction distribution -system.membus.trans_dist::ReadExReq 416163 # Transaction distribution -system.membus.trans_dist::ReadExResp 416163 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35263 # Transaction distribution +system.membus.trans_dist::ReadExReq 417183 # Transaction distribution +system.membus.trans_dist::ReadExResp 417183 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3625442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3755550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4090619 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144046540 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144217012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14051136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14051136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 158268148 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3264 # Total snoops (count) -system.membus.snoop_fanout::samples 2503253 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3154 # Total snoops (count) +system.membus.snoop_fanout::samples 2500418 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2503253 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2503253 # Request fanout histogram -system.membus.reqLayer0.occupancy 109702500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2500418 # Request fanout histogram +system.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5437999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16337638979 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7836649146 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186565831 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index e64b12ad0..828771ce9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,178 +1,178 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.422278 # Number of seconds simulated -sim_ticks 47422277747000 # Number of ticks simulated -final_tick 47422277747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.345385 # Number of seconds simulated +sim_ticks 47345385235500 # Number of ticks simulated +final_tick 47345385235500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91986 # Simulator instruction rate (inst/s) -host_op_rate 108182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4717167353 # Simulator tick rate (ticks/s) -host_mem_usage 870208 # Number of bytes of host memory used -host_seconds 10053.13 # Real time elapsed on the host -sim_insts 924745220 # Number of instructions simulated -sim_ops 1087564829 # Number of ops (including micro ops) simulated +host_inst_rate 106392 # Simulator instruction rate (inst/s) +host_op_rate 125133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5453309126 # Simulator tick rate (ticks/s) +host_mem_usage 767036 # Number of bytes of host memory used +host_seconds 8681.96 # Real time elapsed on the host +sim_insts 923688991 # Number of instructions simulated +sim_ops 1086395427 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 123008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 83392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1145824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12461528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 54523392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 250240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 244864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 679904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13804768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 35481280 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 451200 # Number of bytes read from this memory -system.physmem.bytes_read::total 119249400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1145824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 679904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1825728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 92428416 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 161152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 146432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4268768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16023832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 20180672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 179840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 156416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3463536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 11559072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14510464 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437312 # Number of bytes read from this memory +system.physmem.bytes_read::total 71087496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4268768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3463536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7732304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 86253568 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 92449232 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1922 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 33856 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 194733 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 851928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3826 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10667 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 215714 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 554395 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7050 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1879304 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1444194 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 86274384 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2288 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82652 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 250394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 315323 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2810 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 54162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 180625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 226726 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6833 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1126775 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1347712 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1446797 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 24162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 262778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1149742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 5277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 5163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 291103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 748199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2514628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 24162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14337 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 38499 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1949051 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1350315 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 90162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 338445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 426244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 73155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 244144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 306481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1501466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 90162 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 73155 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 163317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1821795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1949489 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1949051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 24162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 263217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1149742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 5277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 5163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 291103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 748199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4464118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1879304 # Number of read requests accepted -system.physmem.writeReqs 1600997 # Number of write requests accepted -system.physmem.readBursts 1879304 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1600997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 120227392 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48064 # Total number of bytes read from write queue -system.physmem.bytesWritten 101998144 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 119249400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 102318032 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 751 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7249 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 97584 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 111371 # Per bank write bursts -system.physmem.perBankRdBursts::1 133364 # Per bank write bursts -system.physmem.perBankRdBursts::2 107237 # Per bank write bursts -system.physmem.perBankRdBursts::3 129396 # Per bank write bursts -system.physmem.perBankRdBursts::4 116369 # Per bank write bursts -system.physmem.perBankRdBursts::5 129089 # Per bank write bursts -system.physmem.perBankRdBursts::6 116664 # Per bank write bursts -system.physmem.perBankRdBursts::7 120571 # Per bank write bursts -system.physmem.perBankRdBursts::8 118226 # Per bank write bursts -system.physmem.perBankRdBursts::9 133705 # Per bank write bursts -system.physmem.perBankRdBursts::10 98234 # Per bank write bursts -system.physmem.perBankRdBursts::11 110272 # Per bank write bursts -system.physmem.perBankRdBursts::12 110364 # Per bank write bursts -system.physmem.perBankRdBursts::13 124983 # Per bank write bursts -system.physmem.perBankRdBursts::14 111960 # Per bank write bursts -system.physmem.perBankRdBursts::15 106748 # Per bank write bursts -system.physmem.perBankWrBursts::0 99185 # Per bank write bursts -system.physmem.perBankWrBursts::1 109011 # Per bank write bursts -system.physmem.perBankWrBursts::2 97054 # Per bank write bursts -system.physmem.perBankWrBursts::3 108172 # Per bank write bursts -system.physmem.perBankWrBursts::4 98286 # Per bank write bursts -system.physmem.perBankWrBursts::5 106076 # Per bank write bursts -system.physmem.perBankWrBursts::6 100140 # Per bank write bursts -system.physmem.perBankWrBursts::7 103851 # Per bank write bursts -system.physmem.perBankWrBursts::8 98795 # Per bank write bursts -system.physmem.perBankWrBursts::9 98239 # Per bank write bursts -system.physmem.perBankWrBursts::10 89198 # Per bank write bursts -system.physmem.perBankWrBursts::11 97505 # Per bank write bursts -system.physmem.perBankWrBursts::12 95822 # Per bank write bursts -system.physmem.perBankWrBursts::13 102116 # Per bank write bursts -system.physmem.perBankWrBursts::14 95043 # Per bank write bursts -system.physmem.perBankWrBursts::15 95228 # Per bank write bursts +system.physmem.bw_write::total 1822234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1821795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 90162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 338885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 426244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 73155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 244144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 306481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3323700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1126775 # Number of read requests accepted +system.physmem.writeReqs 2040290 # Number of write requests accepted +system.physmem.readBursts 1126775 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2040290 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72094336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19264 # Total number of bytes read from write queue +system.physmem.bytesWritten 130093376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 71087496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 130432784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7556 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 121134 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65675 # Per bank write bursts +system.physmem.perBankRdBursts::1 75833 # Per bank write bursts +system.physmem.perBankRdBursts::2 67256 # Per bank write bursts +system.physmem.perBankRdBursts::3 67290 # Per bank write bursts +system.physmem.perBankRdBursts::4 71240 # Per bank write bursts +system.physmem.perBankRdBursts::5 82191 # Per bank write bursts +system.physmem.perBankRdBursts::6 67013 # Per bank write bursts +system.physmem.perBankRdBursts::7 67787 # Per bank write bursts +system.physmem.perBankRdBursts::8 61707 # Per bank write bursts +system.physmem.perBankRdBursts::9 85775 # Per bank write bursts +system.physmem.perBankRdBursts::10 61014 # Per bank write bursts +system.physmem.perBankRdBursts::11 72520 # Per bank write bursts +system.physmem.perBankRdBursts::12 65793 # Per bank write bursts +system.physmem.perBankRdBursts::13 74631 # Per bank write bursts +system.physmem.perBankRdBursts::14 69278 # Per bank write bursts +system.physmem.perBankRdBursts::15 71471 # Per bank write bursts +system.physmem.perBankWrBursts::0 122526 # Per bank write bursts +system.physmem.perBankWrBursts::1 130111 # Per bank write bursts +system.physmem.perBankWrBursts::2 125889 # Per bank write bursts +system.physmem.perBankWrBursts::3 127486 # Per bank write bursts +system.physmem.perBankWrBursts::4 126972 # Per bank write bursts +system.physmem.perBankWrBursts::5 136977 # Per bank write bursts +system.physmem.perBankWrBursts::6 126845 # Per bank write bursts +system.physmem.perBankWrBursts::7 128268 # Per bank write bursts +system.physmem.perBankWrBursts::8 123854 # Per bank write bursts +system.physmem.perBankWrBursts::9 125736 # Per bank write bursts +system.physmem.perBankWrBursts::10 125360 # Per bank write bursts +system.physmem.perBankWrBursts::11 131761 # Per bank write bursts +system.physmem.perBankWrBursts::12 119984 # Per bank write bursts +system.physmem.perBankWrBursts::13 126166 # Per bank write bursts +system.physmem.perBankWrBursts::14 125889 # Per bank write bursts +system.physmem.perBankWrBursts::15 128885 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 47422276363500 # Total gap between requests +system.physmem.numWrRetry 614 # Number of times write queue was full causing retry +system.physmem.totGap 47345383810500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) -system.physmem.readPktSize::4 21333 # Read request sizes (log2) +system.physmem.readPktSize::4 21334 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1857934 # Read request sizes (log2) +system.physmem.readPktSize::6 1105404 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1598394 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 506038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 360780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 156907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 129304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 95738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 81613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 74114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 66527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 41507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 21466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2037687 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 495851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 118863 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 70028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 51854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39852 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -188,184 +188,141 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 37353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 76742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 83422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 92810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 99100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 114191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 124207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 117512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 121939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 125600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 118087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 27656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 15466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 10008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 975956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.699905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.562466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 280.517231 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 518192 53.10% 53.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197775 20.26% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 73464 7.53% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 39205 4.02% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 32875 3.37% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 20645 2.12% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14690 1.51% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16974 1.74% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 62136 6.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 975956 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 85700 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.919883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.914571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 85693 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 30752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 58821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 69578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 77864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 89177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 97306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 106336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 112038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 121912 # What write queue length does an incoming req see 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# What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 16980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 15279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 13444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 11652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 10311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 9180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 8124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 5145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 4620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 4249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 3131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1502 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1131657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.664737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 108.493979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.059793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 718344 63.48% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 219262 19.38% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56669 5.01% 87.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25497 2.25% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20148 1.78% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11584 1.02% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9545 0.84% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8895 0.79% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61713 5.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1131657 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 74075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.207155 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.468886 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 74072 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 85700 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 85700 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.596511 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.559355 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.221946 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 76419 89.17% 89.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4825 5.63% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 861 1.00% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 776 0.91% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 493 0.58% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 137 0.16% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 117 0.14% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 137 0.16% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 585 0.68% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 72 0.08% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 76 0.09% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 72 0.08% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 110 0.13% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 48 0.06% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 42 0.05% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 81 0.09% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 124 0.14% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 28 0.03% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 35 0.04% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 50 0.06% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 194 0.23% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 14 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 23 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 54 0.06% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 16 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 21 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 26 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 106 0.12% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 28 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 8 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 15 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 15 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 11 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 85700 # Writes before turning the bus around for reads -system.physmem.totQLat 131185455773 # Total ticks spent queuing -system.physmem.totMemAccLat 166408324523 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9392765000 # Total ticks spent in databus transfers -system.physmem.avgQLat 69833.25 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 74075 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 74075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.441228 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.793858 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 451.068024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1023 74039 99.95% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1024-2047 13 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2048-3071 9 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3072-4095 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4096-5119 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5120-6143 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26624-27647 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33792-34815 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64512-65535 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 74075 # Writes before turning the bus around for reads +system.physmem.totQLat 56140564025 # Total ticks spent queuing +system.physmem.totMemAccLat 77261951525 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5632370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 49837.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 88583.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 68587.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing -system.physmem.readRowHits 1529879 # Number of row buffer hits during reads -system.physmem.writeRowHits 966437 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.64 # Row buffer hit rate for writes -system.physmem.avgGap 13625912.35 # Average gap between requests -system.physmem.pageHitRate 71.89 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45568926392500 # Time in different power states -system.physmem.memoryStateTime::REF 1583533900000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 269814192000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3837713040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3540506760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2093990250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1931824125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7519675800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7132967400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5325102000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5002210080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3097392308400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3097392308400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1175879799405 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1172220553305 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27421890099000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27425099964000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31713938687895 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31712320334070 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.756196 # Core power per rank (mW) -system.physmem.averagePower::1 668.722070 # Core power per rank (mW) +system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing +system.physmem.readRowHits 851046 # Number of row buffer hits during reads +system.physmem.writeRowHits 1176475 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes +system.physmem.avgGap 14949293.37 # Average gap between requests +system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4318120800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2356117500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4401423000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6642421200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1163515422960 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27386602512000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31660206295860 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.707358 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45559855793000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1580966400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 204562609000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4237153200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2311938750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4385027400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6529429440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1165548686490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27384818947500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31660201461180 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.707256 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45556862760500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1580966400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 207555509500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -398,16 +355,24 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 136692903 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91051024 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6675955 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 96641264 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 62499971 # Number of BTB hits +system.cpu0.branchPred.lookups 145356452 # Number of BP lookups +system.cpu0.branchPred.condPredicted 96435082 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7088203 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 101789401 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67765064 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.672137 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18343531 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 188881 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.573792 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20004195 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 205158 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -429,27 +394,97 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 580611 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 580611 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13679 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93135 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 259311 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 321300 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 1669.368192 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 10492.971715 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-32767 317448 98.80% 98.80% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-65535 2037 0.63% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-98303 845 0.26% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-131071 576 0.18% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-163839 232 0.07% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::163840-196607 45 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-229375 28 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::229376-262143 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-294911 42 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::294912-327679 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-360447 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 321300 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 293805 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 15781.864128 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 13334.413537 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14277.098383 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 291279 99.14% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1809 0.62% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 367 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 189 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 105 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 293805 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 521650035508 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.610400 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.526555 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 520697119508 99.82% 99.82% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 543124000 0.10% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 195186500 0.04% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 85165500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 70245500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 34070500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 11934000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 12740000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 448500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 521650035508 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 93135 87.19% 87.19% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13679 12.81% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106814 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 580611 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 580611 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 687425 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 98285730 # DTB read hits -system.cpu0.dtb.read_misses 371363 # DTB read misses -system.cpu0.dtb.write_hits 82429878 # DTB write hits -system.cpu0.dtb.write_misses 160428 # DTB write misses +system.cpu0.dtb.read_hits 105404836 # DTB read hits +system.cpu0.dtb.read_misses 420652 # DTB read misses +system.cpu0.dtb.write_hits 86890500 # DTB write hits +system.cpu0.dtb.write_misses 159959 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34259 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6211 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 40944 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 605 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8089 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 37781 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 98657093 # DTB read accesses -system.cpu0.dtb.write_accesses 82590306 # DTB write accesses +system.cpu0.dtb.perms_faults 40127 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 105825488 # DTB read accesses +system.cpu0.dtb.write_accesses 87050459 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 180715608 # DTB hits -system.cpu0.dtb.misses 531791 # DTB misses -system.cpu0.dtb.accesses 181247399 # DTB accesses +system.cpu0.dtb.hits 192295336 # DTB hits +system.cpu0.dtb.misses 580611 # DTB misses +system.cpu0.dtb.accesses 192875947 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -471,533 +506,588 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 214588445 # ITB inst hits -system.cpu0.itb.inst_misses 81035 # ITB inst misses +system.cpu0.itb.walker.walks 84622 # Table walker walks requested +system.cpu0.itb.walker.walksLong 84622 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 994 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61729 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9515 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 75107 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1146.297948 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8819.384812 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 74551 99.26% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 182 0.24% 99.50% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 223 0.30% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 112 0.15% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 5 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 75107 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72238 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20242.257302 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17307.169845 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18587.015651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 70635 97.78% 97.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1318 1.82% 99.61% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 148 0.20% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.11% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72238 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 405678068016 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.851697 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.355553 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 60184359568 14.84% 14.84% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 345473805948 85.16% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 18871000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1025500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 405678068016 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 61729 98.42% 98.42% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 994 1.58% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 62723 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84622 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84622 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62723 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62723 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 147345 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 229226252 # ITB inst hits +system.cpu0.itb.inst_misses 84622 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24176 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29308 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 217359 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 225641 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 214669480 # ITB inst accesses -system.cpu0.itb.hits 214588445 # DTB hits -system.cpu0.itb.misses 81035 # DTB misses -system.cpu0.itb.accesses 214669480 # DTB accesses -system.cpu0.numCycles 723605959 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 229310874 # ITB inst accesses +system.cpu0.itb.hits 229226252 # DTB hits +system.cpu0.itb.misses 84622 # DTB misses +system.cpu0.itb.accesses 229310874 # DTB accesses +system.cpu0.numCycles 787784387 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 84128505 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 603958712 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 136692903 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 80843502 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 610845531 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14389096 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1590613 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 145998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6064926 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 691327 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 308415 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 214371554 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1629958 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 26989 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 710969863 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.995603 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.223531 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 93175923 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 642526185 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 145356452 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 87769259 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 654798115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15283958 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1702071 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 255624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6308926 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 745987 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 671334 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 229000663 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1782311 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27660 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 765299959 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.983676 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.220176 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 371943625 52.31% 52.31% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 132005479 18.57% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 45223870 6.36% 77.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 161796889 22.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 404626902 52.87% 52.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 139960190 18.29% 71.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 49291261 6.44% 77.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 171421606 22.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 710969863 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.188905 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.834651 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 100859820 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 341670501 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 226894689 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 36450722 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5094131 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19684552 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2143149 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 625299942 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23465263 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5094131 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 135677386 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 49836875 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 228336608 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 227963533 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 64061330 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 608231586 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 5949574 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 8548374 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 231810 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 263882 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 30185355 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 12581 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 579905224 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 937754781 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 718843517 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 1013139 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 522903039 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 57002179 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15055979 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13152707 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 73956769 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 99026206 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85770687 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8763922 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7686093 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 586686508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15156086 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 590156830 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2681738 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 50409396 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 34542071 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 266225 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 710969863 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.830073 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.072195 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 765299959 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.184513 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.815612 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 110781464 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 368356745 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 241543971 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39160465 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5457314 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 20998766 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2230758 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 666506782 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 24554495 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5457314 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 147799214 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53385858 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 247347968 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 243020975 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 68288630 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 648373688 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6354822 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 9340488 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 358878 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 691420 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 31770877 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 13042 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 618836498 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1000163983 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 765756832 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 980941 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 557557100 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 61279388 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16104693 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13959035 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79116837 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 106280749 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90455195 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9698755 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8363084 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 625354037 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16149817 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 628774014 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2896491 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 54006760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 37569824 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 287316 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 765299959 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.821605 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.068919 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 390297771 54.90% 54.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 132320625 18.61% 73.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 115120103 16.19% 89.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 65333726 9.19% 98.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7893369 1.11% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4269 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 423230722 55.30% 55.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 141522259 18.49% 73.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 122647115 16.03% 89.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 69647275 9.10% 98.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8247243 1.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5342 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 710969863 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 765299959 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61459839 45.63% 45.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 50531 0.04% 45.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 24866 0.02% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 22 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34471783 25.59% 71.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 38693635 28.73% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65414267 45.68% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 59912 0.04% 45.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 17829 0.01% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 19 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37349884 26.08% 71.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40363750 28.19% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 403696370 68.40% 68.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1373917 0.23% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 72713 0.01% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 2 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 82685 0.01% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 101222055 17.15% 85.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83709039 14.18% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 430163495 68.41% 68.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1578221 0.25% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 81407 0.01% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 125 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 78656 0.01% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108646479 17.28% 85.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88225631 14.03% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 590156830 # Type of FU issued -system.cpu0.iq.rate 0.815578 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 134700676 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228246 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2027250728 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 651818194 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 574107974 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1415207 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 570288 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 525567 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 723981962 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 875543 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2649036 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 628774014 # Type of FU issued +system.cpu0.iq.rate 0.798155 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 143205661 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227754 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2167577171 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 695106277 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 611404783 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1372966 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 554126 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 508083 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 771129089 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 850586 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2930031 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12005066 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15997 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 137574 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5832630 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13213228 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17078 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 150900 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6091069 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2633268 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 3783846 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2819130 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4221569 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5094131 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6289107 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 4809356 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 601961701 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5457314 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7826815 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 3783393 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 641629807 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 99026206 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85770687 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12881584 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 63147 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4682481 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 137574 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1984191 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2898838 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4883029 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 582493668 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 98279194 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7144205 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 106280749 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90455195 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13677015 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 59030 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3651240 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 150900 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2214888 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3025224 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5240112 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 620548589 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105398618 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7653008 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119107 # number of nop insts executed -system.cpu0.iew.exec_refs 180711366 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110157991 # Number of branches executed -system.cpu0.iew.exec_stores 82432172 # Number of stores executed -system.cpu0.iew.exec_rate 0.804987 # Inst execution rate -system.cpu0.iew.wb_sent 575359382 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 574633541 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 278757047 # num instructions producing a value -system.cpu0.iew.wb_consumers 457962623 # num instructions consuming a value +system.cpu0.iew.exec_nop 125953 # number of nop insts executed +system.cpu0.iew.exec_refs 192287971 # number of memory reference insts executed +system.cpu0.iew.exec_branches 117275797 # Number of branches executed +system.cpu0.iew.exec_stores 86889353 # Number of stores executed +system.cpu0.iew.exec_rate 0.787714 # Inst execution rate +system.cpu0.iew.wb_sent 612710943 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 611912866 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 297952907 # num instructions producing a value +system.cpu0.iew.wb_consumers 488842231 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.794125 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.608690 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.776752 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609507 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 46943290 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14889861 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4575538 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 702085405 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.780670 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.579297 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 50177444 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15862501 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4903538 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 755787028 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.772749 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.571704 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 463334360 65.99% 65.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 122538358 17.45% 83.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 53278812 7.59% 91.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18006181 2.56% 93.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13261797 1.89% 95.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8597155 1.22% 96.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5895517 0.84% 97.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3809437 0.54% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13363788 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 501065306 66.30% 66.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 130810768 17.31% 83.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 56911365 7.53% 91.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19253126 2.55% 93.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13929285 1.84% 95.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9339201 1.24% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6281388 0.83% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 4033068 0.53% 98.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14163521 1.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 702085405 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 466411686 # Number of instructions committed -system.cpu0.commit.committedOps 548096953 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 755787028 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 497564314 # Number of instructions committed +system.cpu0.commit.committedOps 584033993 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 166959196 # Number of memory references committed -system.cpu0.commit.loads 87021139 # Number of loads committed -system.cpu0.commit.membars 3711025 # Number of memory barriers committed -system.cpu0.commit.branches 104496556 # Number of branches committed -system.cpu0.commit.fp_insts 513447 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 502627891 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13679873 # Number of function calls committed. +system.cpu0.commit.refs 177431645 # Number of memory references committed +system.cpu0.commit.loads 93067519 # Number of loads committed +system.cpu0.commit.membars 3925399 # Number of memory barriers committed +system.cpu0.commit.branches 111370146 # Number of branches committed +system.cpu0.commit.fp_insts 496516 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 535821487 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14891305 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 379865208 69.31% 69.31% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1141082 0.21% 69.51% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 57492 0.01% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 73933 0.01% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 87021139 15.88% 85.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 79938057 14.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 405157799 69.37% 69.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1311833 0.22% 69.60% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 63039 0.01% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 69677 0.01% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 93067519 15.94% 85.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84364126 14.45% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 548096953 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13363788 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 584033993 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14163521 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1279505618 # The number of ROB reads -system.cpu0.rob.rob_writes 1198929363 # The number of ROB writes -system.cpu0.timesIdled 780048 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 12636096 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 94120949562 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 466411686 # Number of Instructions Simulated -system.cpu0.committedOps 548096953 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.551432 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.551432 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.644566 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.644566 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 688144011 # number of integer regfile reads -system.cpu0.int_regfile_writes 408577767 # number of integer regfile writes -system.cpu0.fp_regfile_reads 842658 # number of floating regfile reads -system.cpu0.fp_regfile_writes 455584 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127446024 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128164594 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2855519856 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15107964 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 5838402 # number of replacements -system.cpu0.dcache.tags.tagsinuse 504.465464 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155155227 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5838912 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.572626 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.465464 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985284 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.985284 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 346167633 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 346167633 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80535549 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80535549 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69641264 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69641264 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207056 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 207056 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 203093 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 203093 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877400 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1877400 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1900232 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1900232 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150176813 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 150176813 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150383869 # number of overall hits -system.cpu0.dcache.overall_hits::total 150383869 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6642832 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6642832 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7191098 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7191098 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 692118 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 692118 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 798159 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 798159 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 243998 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 243998 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 184133 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 184133 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13833930 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13833930 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 14526048 # number of overall misses -system.cpu0.dcache.overall_misses::total 14526048 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 99514286008 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 99514286008 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 115098035706 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 115098035706 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 53560236062 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 53560236062 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3359260407 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3359260407 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3823760481 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3823760481 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2172500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2172500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 214612321714 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 214612321714 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 214612321714 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 214612321714 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87178381 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 87178381 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76832362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76832362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899174 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 899174 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1001252 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1001252 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2121398 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2121398 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2084365 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2084365 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 164010743 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 164010743 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164909917 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164909917 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076198 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.076198 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093595 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.093595 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769726 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769726 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.797161 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.797161 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115018 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088340 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088340 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084348 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084348 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088085 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088085 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14980.701907 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14980.701907 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16005.627472 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16005.627472 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 67104.719814 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 67104.719814 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13767.573533 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13767.573533 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20766.296541 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20766.296541 # average StoreCondReq miss latency +system.cpu0.rob.rob_reads 1371348086 # The number of ROB reads +system.cpu0.rob.rob_writes 1277898548 # The number of ROB writes +system.cpu0.timesIdled 1050969 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22484428 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93902986117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 497564314 # Number of Instructions Simulated +system.cpu0.committedOps 584033993 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.583282 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.583282 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.631600 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.631600 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 732616408 # number of integer regfile reads +system.cpu0.int_regfile_writes 435784003 # number of integer regfile writes +system.cpu0.fp_regfile_reads 812591 # number of floating regfile reads +system.cpu0.fp_regfile_writes 450624 # number of floating regfile writes +system.cpu0.cc_regfile_reads 135724425 # number of cc regfile reads +system.cpu0.cc_regfile_writes 136350840 # number of cc regfile writes +system.cpu0.misc_regfile_reads 3048491910 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15942846 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6332598 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.098749 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 164710199 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6333110 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.007791 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1750140500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.098749 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.945505 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.945505 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 368140426 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 368140426 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86285504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86285504 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73342402 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73342402 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 227851 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 227851 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 264480 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 264480 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878345 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1878345 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1911240 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1911240 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 159627906 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 159627906 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 159855757 # number of overall hits +system.cpu0.dcache.overall_hits::total 159855757 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7088092 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7088092 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7774496 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7774496 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 746133 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 746133 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 842824 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 842824 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 281020 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 281020 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209055 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 209055 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14862588 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14862588 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15608721 # number of overall misses +system.cpu0.dcache.overall_misses::total 15608721 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 105859717159 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 105859717159 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137077029934 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 137077029934 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 45622327717 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 45622327717 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4025426932 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4025426932 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4395434712 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4395434712 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3232000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3232000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 242936747093 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 242936747093 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 242936747093 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 242936747093 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 93373596 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 93373596 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81116898 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81116898 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 973984 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 973984 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1107304 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1107304 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2159365 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2159365 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2120295 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2120295 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 174490494 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 174490494 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 175464478 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 175464478 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075911 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.075911 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095843 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.095843 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766063 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766063 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.761150 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.761150 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130140 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130140 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098597 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098597 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085177 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.085177 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088957 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088957 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14934.867826 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14934.867826 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17631.629103 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17631.629103 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 54130.313941 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 54130.313941 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14324.343221 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14324.343221 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21025.255134 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21025.255134 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15513.474603 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15513.474603 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14774.309001 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14774.309001 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 16118603 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 16176348 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 692801 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 696412 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.265848 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 23.228129 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16345.521190 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16345.521190 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15564.167435 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15564.167435 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 13488103 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 19786702 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 752105 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 757651 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.933803 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 26.115853 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3975125 # number of writebacks -system.cpu0.dcache.writebacks::total 3975125 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3497983 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3497983 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5763188 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5763188 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4492 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4492 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123982 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123982 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9261171 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9261171 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9261171 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9261171 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3144849 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3144849 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1427910 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1427910 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685927 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 685927 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 793667 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 793667 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120016 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120016 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 184129 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 184129 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4572759 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4572759 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5258686 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5258686 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40981205496 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40981205496 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22755476630 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22755476630 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17996613568 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17996613568 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 51855736982 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 51855736982 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1434297417 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1434297417 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3446370519 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3446370519 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2070500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2070500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63736682126 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 63736682126 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81733295694 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 81733295694 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5581760391 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5581760391 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5277895398 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5277895398 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10859655789 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10859655789 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036074 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036074 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018585 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018585 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762841 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762841 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.792675 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.792675 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056574 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056574 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088338 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088338 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027881 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027881 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031888 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031888 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13031.215647 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13031.215647 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15936.212107 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15936.212107 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26236.922541 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26236.922541 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 65336.894418 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 65336.894418 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11950.885024 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11950.885024 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18717.152209 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18717.152209 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4276528 # number of writebacks +system.cpu0.dcache.writebacks::total 4276528 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664529 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3664529 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6233308 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6233308 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4741 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4741 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141328 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141328 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9897837 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9897837 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9897837 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9897837 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3423563 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3423563 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1541188 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1541188 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 739665 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 739665 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 838083 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 838083 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139692 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139692 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209050 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 209050 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4964751 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4964751 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5704416 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5704416 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44975748199 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44975748199 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28501279892 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28501279892 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16804666332 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16804666332 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 43773018566 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 43773018566 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1737566757 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1737566757 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3967184288 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3967184288 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3082000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3082000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73477028091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 73477028091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90281694423 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 90281694423 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5575976491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5575976491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5325987989 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5325987989 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10901964480 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10901964480 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036665 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036665 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019000 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019000 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759422 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759422 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.756868 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.756868 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064691 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064691 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098595 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098595 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032510 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032510 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13137.117149 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13137.117149 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18493.058531 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18493.058531 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22719.293642 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22719.293642 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 52229.932556 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 52229.932556 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12438.555945 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12438.555945 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18977.203004 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18977.203004 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13938.342722 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13938.342722 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15542.532050 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15542.532050 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14799.740831 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14799.740831 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15826.632283 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15826.632283 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1005,463 +1095,461 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6042830 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.967320 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 208050611 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6043342 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.426417 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 11201042000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.967320 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999936 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999936 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 6368542 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.961816 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 222275153 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6369054 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.899241 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14184385750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.961816 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999925 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999925 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 434737408 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 434737408 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 208050611 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 208050611 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 208050611 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 208050611 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 208050611 # number of overall hits -system.cpu0.icache.overall_hits::total 208050611 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6296413 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6296413 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6296413 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6296413 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6296413 # number of overall misses -system.cpu0.icache.overall_misses::total 6296413 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55127710497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 55127710497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 55127710497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 55127710497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 55127710497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 55127710497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 214347024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 214347024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 214347024 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 214347024 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 214347024 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 214347024 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029375 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029375 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029375 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029375 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029375 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029375 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8755.415265 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8755.415265 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8755.415265 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8755.415265 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4477144 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 62 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 570538 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.847232 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 62 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 464315009 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 464315009 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 222275153 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 222275153 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 222275153 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 222275153 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 222275153 # number of overall hits +system.cpu0.icache.overall_hits::total 222275153 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6697664 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6697664 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6697664 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6697664 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6697664 # number of overall misses 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228972817 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 228972817 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 228972817 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029251 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029251 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029251 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029251 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029251 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029251 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10590.016569 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10590.016569 # average ReadReq miss latency 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7397.810351 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7397.810351 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 328289 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 328289 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 328289 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 328289 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 328289 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 328289 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6369375 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6369375 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6369375 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6369375 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6369375 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6369375 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 57966761800 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 57966761800 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 57966761800 # number of demand (read+write) MSHR miss cycles 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average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 60184765 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4393414 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 48808124 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3087530 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 452633 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3443064 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5114963 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 4158550 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16214.275256 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 12594287 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 4174696 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.016815 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 9944532000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 3315.303513 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.862270 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.140550 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 967.067959 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2910.372119 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8960.528846 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.202350 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002372 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001351 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.059025 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.177635 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.546907 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989641 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8340 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7728 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 111 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 951 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3646 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 2631 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1001 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 51 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1103 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3816 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2122 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 566 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509033 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.471680 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 280330704 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 280330704 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522125 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 166946 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5796903 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2821623 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 9307597 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3975115 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3975115 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222232 # number 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of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 114256010592 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5322353508 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6841527758 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5082599974 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5082599974 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10404953482 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11924127732 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258030 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160084 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.129074 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.129074 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.503091 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.503091 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.790514 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.790514 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762335 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.762335 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.546175 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.546175 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823890 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823890 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.185504 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.185504 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128447 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207527 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207527 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.164920 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.417806 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27642.980057 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27083.574890 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55593.563487 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32521.484628 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32521.484628 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17427.856472 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17427.856472 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13830.282341 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13830.282341 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 237500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 237500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 33377.085578 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 33377.085578 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27996.319261 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47109.300568 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229475 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 28489.841187 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26188.713793 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66837.897451 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 56932.579225 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 56932.579225 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17437.518651 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17437.518651 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13547.478192 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13547.478192 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 496400 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496400 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41446.125704 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41446.125704 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28146.040729 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39030.566104 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1471,69 +1559,77 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 15173335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11005084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31316 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31316 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3975122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 5222365 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 963549 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 792291 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 491639 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 333223 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 494297 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1332515 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1202467 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12129286 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16997895 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390025 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1185916 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 30703122 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 387114336 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641181457 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1414144 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4287888 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1033997825 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 10518238 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27441081 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.371527 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.483213 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 13921371 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11750633 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31686 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31686 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4276525 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1274288 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1162561 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 836505 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 509905 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 381643 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 535354 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 87 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1437620 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1309284 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12781022 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18390339 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414542 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294088 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 32879991 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407960480 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 693234728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1535584 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4758096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1107488888 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4767578 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22911203 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.193957 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.395396 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 17245975 62.85% 62.85% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 10195106 37.15% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 18467409 80.60% 80.60% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 4443794 19.40% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27441081 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13452656135 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 22911203 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14408211332 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 192867736 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 208870495 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9099601288 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9596174213 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8421572630 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9165770534 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 213967447 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 223497560 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 651243914 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 700918244 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 133961841 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89061347 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6618163 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 94585757 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 62217505 # Number of BTB hits +system.cpu1.branchPred.lookups 124370032 # Number of BP lookups +system.cpu1.branchPred.condPredicted 83075187 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6189003 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 87824878 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 56905034 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.778936 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 18340774 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 186545 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 64.793752 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16687776 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 168367 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1555,27 +1651,98 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 538943 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 538943 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11373 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87574 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 237839 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 301104 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 1852.353340 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 11107.804354 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 297190 98.70% 98.70% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 2030 0.67% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 795 0.26% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 637 0.21% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 257 0.09% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 66 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 39 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 48 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 301104 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 268131 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 15772.437909 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 12981.371112 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15992.673962 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 265367 98.97% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1941 0.72% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 396 0.15% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 232 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 106 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 37 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 268131 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 435751861088 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.614829 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.532518 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 434859464588 99.80% 99.80% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 474800000 0.11% 99.90% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 202701000 0.05% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 89682000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 62866500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 34103000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 13310500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 14713000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 214000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 435751861088 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 87574 88.51% 88.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11373 11.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 98947 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 538943 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 538943 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98947 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98947 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 637890 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 98830623 # DTB read hits -system.cpu1.dtb.read_misses 443426 # DTB read misses -system.cpu1.dtb.write_hits 80619639 # DTB write hits -system.cpu1.dtb.write_misses 165440 # DTB write misses +system.cpu1.dtb.read_hits 91392867 # DTB read hits +system.cpu1.dtb.read_misses 373745 # DTB read misses +system.cpu1.dtb.write_hits 75805429 # DTB write hits +system.cpu1.dtb.write_misses 165198 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44150 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 612 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6848 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37451 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5879 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 42554 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 99274049 # DTB read accesses -system.cpu1.dtb.write_accesses 80785079 # DTB write accesses +system.cpu1.dtb.perms_faults 40297 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91766612 # DTB read accesses +system.cpu1.dtb.write_accesses 75970627 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 179450262 # DTB hits -system.cpu1.dtb.misses 608866 # DTB misses -system.cpu1.dtb.accesses 180059128 # DTB accesses +system.cpu1.dtb.hits 167198296 # DTB hits +system.cpu1.dtb.misses 538943 # DTB misses +system.cpu1.dtb.accesses 167737239 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1597,163 +1764,217 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 211899162 # ITB inst hits -system.cpu1.itb.inst_misses 88988 # ITB inst misses +system.cpu1.itb.walker.walks 85244 # Table walker walks requested +system.cpu1.itb.walker.walksLong 85244 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 675 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61262 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9941 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 75303 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1139.330438 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8399.837182 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 74771 99.29% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 180 0.24% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 193 0.26% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 128 0.17% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 12 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75303 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71878 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 20268.763168 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 17115.147893 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19721.935997 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 70231 97.71% 97.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1324 1.84% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 179 0.25% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 46 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71878 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 397094361424 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.878531 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.326828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 48253813024 12.15% 12.15% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 348822790900 87.84% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 16535000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1219500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 397094361424 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61262 98.91% 98.91% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 675 1.09% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 61937 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85244 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85244 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61937 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61937 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 147181 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 196146030 # ITB inst hits +system.cpu1.itb.inst_misses 85244 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 32114 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26780 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 230833 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 213163 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 211988150 # ITB inst accesses -system.cpu1.itb.hits 211899162 # DTB hits -system.cpu1.itb.misses 88988 # DTB misses -system.cpu1.itb.accesses 211988150 # DTB accesses -system.cpu1.numCycles 705261968 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 196231274 # ITB inst accesses +system.cpu1.itb.hits 196146030 # DTB hits +system.cpu1.itb.misses 85244 # DTB misses +system.cpu1.itb.accesses 196231274 # DTB accesses +system.cpu1.numCycles 664388878 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 81258744 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 595261780 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 133961841 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 80558279 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 597026773 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14270848 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1888771 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 137791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6543938 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 793820 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 311963 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 211646234 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1619349 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28847 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 695097224 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.005850 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.225976 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 79880322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 552169788 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 124370032 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 73592810 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 551328487 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13340182 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1707326 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 246511 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6080767 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 727313 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 602439 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 195911596 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1586691 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647243256 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.003235 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.226187 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 360486788 51.86% 51.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 129920524 18.69% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 44826389 6.45% 77.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 159863523 23.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 336573756 52.00% 52.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 120960986 18.69% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 40749741 6.30% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 148958773 23.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 695097224 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.189946 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.844029 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 99752260 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 332349824 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 219841712 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 38085588 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5067840 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18995502 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2109796 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 616514692 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22877728 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5067840 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 135033848 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 48639647 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 225189127 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 222148294 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 59018468 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 599774214 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5804898 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8803158 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 361913 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 923044 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 23085631 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 14113 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 571116000 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 927515458 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 708750961 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 721490 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 514023695 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 57092304 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 16265387 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 14239236 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76589893 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 99537313 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 83963206 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 9607701 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 8257946 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 576970515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 16478044 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 581773999 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2685793 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 50643585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 34938077 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 295595 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 695097224 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.836968 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.068825 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 647243256 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.187195 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.831094 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 96356177 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 306396299 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 204571849 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 35206357 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4712574 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17589142 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1996203 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 573391383 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21361954 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4712574 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 129172911 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 40460241 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 212107385 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 206565063 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 54225082 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 557977037 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5352379 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8193976 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 222351 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 303036 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 21276416 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 13923 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 530659712 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 862978619 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 659902858 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 766208 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 478267677 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 52392029 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15246817 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13453544 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 71065053 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 91863812 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 78915989 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8629555 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7664780 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 536633802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15513444 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 541699362 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2485495 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 46695905 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 31776612 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 271399 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647243256 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.836933 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.069144 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 375720628 54.05% 54.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 136500819 19.64% 73.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 111041420 15.97% 89.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 64151608 9.23% 98.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7678235 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4508 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 6 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 349912497 54.06% 54.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 127097301 19.64% 73.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 103346931 15.97% 89.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 59640858 9.21% 98.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7242720 1.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2949 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 695097224 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647243256 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 58467261 44.14% 44.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 65736 0.05% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 8975 0.01% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 28 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 36077917 27.24% 71.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 37847209 28.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 54464030 43.99% 43.99% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 55578 0.04% 44.03% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 15828 0.01% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 9 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33234382 26.84% 70.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 36043585 29.11% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 396486231 68.15% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1392625 0.24% 68.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 78812 0.01% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 369233279 68.16% 68.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1193564 0.22% 68.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69127 0.01% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued @@ -1763,367 +1984,367 @@ system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Ty system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.40% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 42928 0.01% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 101899765 17.52% 85.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 81873638 14.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 46847 0.01% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94164053 17.38% 85.79% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 76992429 14.21% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 581773999 # Type of FU issued -system.cpu1.iq.rate 0.824905 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 132467126 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227695 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1992741902 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 643831652 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 565540483 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1056239 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 418449 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 388115 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 713583395 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 657730 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2682619 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 541699362 # Type of FU issued +system.cpu1.iq.rate 0.815335 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 123813412 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.228565 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1855831634 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 598546046 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 526634223 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1109251 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 439129 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 408402 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 664822270 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 690492 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2431611 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12570649 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16823 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 158978 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5834378 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11396985 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16347 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 143339 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5491640 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2724944 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3729174 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2526857 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3486247 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5067840 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8144414 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2028582 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 593577386 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4712574 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5829545 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1427417 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 552265728 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 99537313 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 83963206 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 14010879 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 57965 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1901764 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 158978 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2040667 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2820650 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4861317 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 574179310 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 98827451 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6993764 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 91863812 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 78915989 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13236985 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 56254 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1314129 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 143339 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1858186 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2653609 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4511795 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 534690067 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 91388435 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6481283 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 128827 # number of nop insts executed -system.cpu1.iew.exec_refs 179445358 # number of memory reference insts executed -system.cpu1.iew.exec_branches 107524158 # Number of branches executed -system.cpu1.iew.exec_stores 80617907 # Number of stores executed -system.cpu1.iew.exec_rate 0.814136 # Inst execution rate -system.cpu1.iew.wb_sent 566651750 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 565928598 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 274900610 # num instructions producing a value -system.cpu1.iew.wb_consumers 450009146 # num instructions consuming a value +system.cpu1.iew.exec_nop 118482 # number of nop insts executed +system.cpu1.iew.exec_refs 167194328 # number of memory reference insts executed +system.cpu1.iew.exec_branches 100087893 # Number of branches executed +system.cpu1.iew.exec_stores 75805893 # Number of stores executed +system.cpu1.iew.exec_rate 0.804785 # Inst execution rate +system.cpu1.iew.wb_sent 527704335 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 527042625 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 254576573 # num instructions producing a value +system.cpu1.iew.wb_consumers 416898701 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.802437 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610878 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.793274 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610644 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 47337627 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 16182449 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4550579 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 686146419 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.786229 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.582193 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 43642021 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15242045 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4231486 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 638973832 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.786200 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.579868 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 448874592 65.42% 65.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 124520992 18.15% 83.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 51724584 7.54% 91.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17115210 2.49% 93.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12441515 1.81% 95.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8692682 1.27% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5812900 0.85% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3666336 0.53% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 13297608 1.94% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 417556945 65.35% 65.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 116379063 18.21% 83.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 48152991 7.54% 91.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16068254 2.51% 93.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11811974 1.85% 95.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7886914 1.23% 96.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5403679 0.85% 97.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3345009 0.52% 98.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12369003 1.94% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 686146419 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 458333534 # Number of instructions committed -system.cpu1.commit.committedOps 539467876 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 638973832 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 426124677 # Number of instructions committed +system.cpu1.commit.committedOps 502361434 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 165095491 # Number of memory references committed -system.cpu1.commit.loads 86966664 # Number of loads committed -system.cpu1.commit.membars 3858042 # Number of memory barriers committed -system.cpu1.commit.branches 101991370 # Number of branches committed -system.cpu1.commit.fp_insts 379596 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 495494093 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13607824 # Number of function calls committed. +system.cpu1.commit.refs 153891175 # Number of memory references committed +system.cpu1.commit.loads 80466826 # Number of loads committed +system.cpu1.commit.membars 3635433 # Number of memory barriers committed +system.cpu1.commit.branches 94895008 # Number of branches committed +system.cpu1.commit.fp_insts 399904 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 461321486 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12405087 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 373132612 69.17% 69.17% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1140635 0.21% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 62088 0.01% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 37050 0.01% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 86966664 16.12% 85.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 78128827 14.48% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 347396188 69.15% 69.15% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 977319 0.19% 69.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 55389 0.01% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 41321 0.01% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 80466826 16.02% 85.38% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 73424349 14.62% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 539467876 # Class of committed instruction -system.cpu1.commit.bw_lim_events 13297608 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 502361434 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12369003 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1255653176 # The number of ROB reads -system.cpu1.rob.rob_writes 1182522736 # The number of ROB writes -system.cpu1.timesIdled 784634 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 10164744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94139293558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 458333534 # Number of Instructions Simulated -system.cpu1.committedOps 539467876 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.538753 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.538753 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.649877 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.649877 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 678371688 # number of integer regfile reads -system.cpu1.int_regfile_writes 402814905 # number of integer regfile writes -system.cpu1.fp_regfile_reads 627803 # number of floating regfile reads -system.cpu1.fp_regfile_writes 323588 # number of floating regfile writes -system.cpu1.cc_regfile_reads 123299886 # number of cc regfile reads -system.cpu1.cc_regfile_writes 123979632 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2817640596 # number of misc regfile reads -system.cpu1.misc_regfile_writes 16155257 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5719154 # number of replacements -system.cpu1.dcache.tags.tagsinuse 428.720007 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153241322 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5719665 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 26.792010 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8515430590500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.720007 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837344 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.837344 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 342874086 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 342874086 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 80584085 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 80584085 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68058878 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68058878 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187635 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 187635 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 112453 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 112453 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1764554 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1764554 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1816897 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1816897 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 148642963 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 148642963 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 148830598 # number of overall hits -system.cpu1.dcache.overall_hits::total 148830598 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6869643 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6869643 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7494314 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7494314 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 706318 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 706318 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 458418 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 458418 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288948 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 288948 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190861 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 190861 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 14363957 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 14363957 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 15070275 # number of overall misses -system.cpu1.dcache.overall_misses::total 15070275 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 105402463849 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 105402463849 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 121649241613 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 121649241613 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 17403154350 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 17403154350 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4078869410 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4078869410 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3937390159 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3937390159 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1956500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1956500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 227051705462 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 227051705462 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 227051705462 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 227051705462 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87453728 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87453728 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75553192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75553192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 893953 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 893953 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 570871 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 570871 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2053502 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2053502 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2007758 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2007758 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 163006920 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 163006920 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 163900873 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 163900873 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099193 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.099193 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790106 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790106 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.803015 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.803015 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140710 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140710 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095062 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095062 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088119 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.088119 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.091947 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.091947 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.222908 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.222908 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16232.205057 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16232.205057 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 37963.505687 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 37963.505687 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14116.274935 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14116.274935 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20629.621342 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20629.621342 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 1168820475 # The number of ROB reads +system.cpu1.rob.rob_writes 1100237743 # The number of ROB writes +system.cpu1.timesIdled 913492 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 17145622 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94026381638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 426124677 # Number of Instructions Simulated +system.cpu1.committedOps 502361434 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.559142 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.559142 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.641378 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.641378 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 632226075 # number of integer regfile reads +system.cpu1.int_regfile_writes 374528717 # number of integer regfile writes +system.cpu1.fp_regfile_reads 661926 # number of floating regfile reads +system.cpu1.fp_regfile_writes 331836 # number of floating regfile writes +system.cpu1.cc_regfile_reads 114587184 # number of cc regfile reads +system.cpu1.cc_regfile_writes 115385602 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2619636946 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15333141 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5236220 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.332610 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 143091306 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5236730 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.324553 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8478701081000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.332610 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893228 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.893228 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 319394188 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 319394188 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 74655263 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 74655263 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64023189 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64023189 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 163779 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 163779 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 39797 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 39797 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1738928 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1738928 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1751406 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1751406 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 138678452 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 138678452 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 138842231 # number of overall hits +system.cpu1.dcache.overall_hits::total 138842231 # number of overall hits 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204152 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13109760 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13109760 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13769293 # number of overall misses +system.cpu1.dcache.overall_misses::total 13769293 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92549514245 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 92549514245 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 116311286360 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 116311286360 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11708163921 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11708163921 # number of WriteInvalidateReq miss cycles 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208860800605 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 80782202 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 80782202 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71006010 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71006010 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823312 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 823312 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 465174 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 465174 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1999506 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1999506 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1955558 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1955558 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 151788212 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 151788212 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 152611524 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 152611524 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075845 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.075845 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098341 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.098341 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801073 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801073 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.914447 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.914447 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130321 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130321 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104396 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104396 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086369 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.086369 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090224 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.090224 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15105.342855 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15105.342855 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16656.776160 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16656.776160 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.205401 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.205401 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14423.717444 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14423.717444 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21164.860790 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21164.860790 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15807.044358 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15807.044358 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15066.195239 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15066.195239 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4622048 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18188306 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 368036 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 754235 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.558684 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 24.114906 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15931.702839 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15931.702839 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15168.592941 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15168.592941 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2855420 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17544431 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 337066 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 700468 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.471397 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 25.046727 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3658567 # number of writebacks -system.cpu1.dcache.writebacks::total 3658567 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3579229 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3579229 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6058526 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 6058526 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3270 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3270 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 146042 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 146042 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9637755 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9637755 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9637755 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9637755 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3290414 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3290414 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1435788 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1435788 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706224 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 706224 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 455148 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 455148 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 142906 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 142906 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 190858 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 190858 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4726202 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4726202 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5432426 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5432426 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44800014998 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44800014998 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23381887855 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23381887855 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16359112476 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16359112476 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 16414544257 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 16414544257 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1722097666 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1722097666 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3546227841 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3546227841 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1864500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1864500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68181902853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 68181902853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84541015329 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 84541015329 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 790979694 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 790979694 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 944680456 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 944680456 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1735660150 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1735660150 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037625 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037625 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019004 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019004 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790001 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790001 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.797287 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.797287 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069591 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069591 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095060 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095060 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028994 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028994 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033145 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033145 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13615.312541 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13615.312541 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16285.055910 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16285.055910 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23164.197869 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23164.197869 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 36064.190674 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 36064.190674 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12050.562370 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12050.562370 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18580.451650 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18580.451650 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3392584 # number of writebacks +system.cpu1.dcache.writebacks::total 3392584 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3127909 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3127909 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5647115 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5647115 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3296 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3296 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132105 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132105 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8775024 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8775024 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8775024 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8775024 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2999030 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2999030 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335706 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1335706 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659449 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 659449 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 422081 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 422081 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 128473 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 128473 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204145 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 204145 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4334736 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4334736 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4994185 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4994185 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38225367292 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38225367292 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21845579142 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21845579142 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15240654080 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15240654080 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10753431338 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10753431338 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1629520255 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1629520255 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3904363340 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3904363340 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3325000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3325000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60070946434 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 60070946434 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75311600514 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 75311600514 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 796916503 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 796916503 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 897774501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 897774501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1694691004 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1694691004 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037125 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037125 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018811 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018811 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800971 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800971 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.907362 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.907362 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064252 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064252 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028558 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028558 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032725 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032725 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12745.910275 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12745.910275 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16355.080491 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16355.080491 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23111.194467 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23111.194467 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25477.174613 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25477.174613 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12683.756548 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12683.756548 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19125.441916 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19125.441916 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14426.362405 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14426.362405 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15562.294881 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15562.294881 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13858.040359 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13858.040359 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15079.857978 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15079.857978 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2131,464 +2352,461 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5881686 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.904324 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 205507195 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5882198 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.937143 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8555135625500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.904324 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980282 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980282 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5522406 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.856310 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 190094169 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5522918 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.419155 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8518418347000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.856310 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980188 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980188 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 371 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 335 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 429168724 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 429168724 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 205507195 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 205507195 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 205507195 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 205507195 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 205507195 # number of overall hits -system.cpu1.icache.overall_hits::total 205507195 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6136058 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6136058 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6136058 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6136058 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6136058 # number of overall misses -system.cpu1.icache.overall_misses::total 6136058 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53889413624 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 53889413624 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 53889413624 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 53889413624 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 53889413624 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 53889413624 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 211643253 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 211643253 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 211643253 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 211643253 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 211643253 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 211643253 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028992 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028992 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028992 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028992 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028992 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028992 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8782.415946 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8782.415946 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8782.415946 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8782.415946 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 4496430 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 574651 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.824627 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 397333844 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 397333844 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 190094169 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 190094169 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 190094169 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 190094169 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 190094169 # number of overall hits +system.cpu1.icache.overall_hits::total 190094169 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5811281 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5811281 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5811281 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5811281 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5811281 # number of overall misses +system.cpu1.icache.overall_misses::total 5811281 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61520167992 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 61520167992 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 61520167992 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 61520167992 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 61520167992 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 61520167992 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 195905450 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 195905450 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 195905450 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 195905450 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 195905450 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 195905450 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029664 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029664 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029664 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029664 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029664 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029664 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10586.335094 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10586.335094 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10586.335094 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10586.335094 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10586.335094 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10586.335094 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 7857995 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 642168 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.236665 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 39 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 253840 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 253840 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 253840 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 253840 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 253840 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 253840 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5882218 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5882218 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5882218 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5882218 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5882218 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5882218 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43727434357 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 43727434357 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43727434357 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 43727434357 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43727434357 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 43727434357 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6637997 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6637997 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6637997 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6637997 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027793 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027793 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7433.834373 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 288337 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 288337 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 288337 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 288337 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 288337 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 288337 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5522944 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5522944 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5522944 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5522944 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5522944 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5522944 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50254087338 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 50254087338 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50254087338 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 50254087338 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50254087338 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 50254087338 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5802498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5802498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5802498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5802498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028192 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028192 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9099.148450 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 56932742 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2823095 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 47812216 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2677811 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 382726 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3236886 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4916498 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 4092617 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13780.930785 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 12621619 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 4108487 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.072084 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9637211064000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 3757.362843 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.809020 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 56.863279 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.057552 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3491.075179 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5813.762913 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.229331 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003834 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003471 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036564 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.213078 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.354844 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.841121 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8933 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6853 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 68 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 777 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3625 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2921 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1542 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3137 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2007 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 750 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.545227 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.418274 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 271640392 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 271640392 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 596119 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 184681 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5616426 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2971260 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 9368486 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3658557 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3658557 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 182266 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 182266 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 95807 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 95807 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41710 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 41710 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 960995 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 960995 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 596119 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 184681 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5616426 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3932255 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 10329481 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 596119 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 184681 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5616426 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3932255 # number of overall hits -system.cpu1.l2cache.overall_hits::total 10329481 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 16104 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 12169 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 265788 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1166045 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1460106 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 9 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 9 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 271820 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 271820 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 129531 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 129531 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 149141 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 149141 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255657 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 255657 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 16104 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 12169 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 265788 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1421702 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1715763 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 16104 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 12169 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 265788 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1421702 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1715763 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 666484538 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 571688851 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 6944017926 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 40559833009 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 48742024324 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 11677447356 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 11677447356 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2603211060 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2603211060 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3027794367 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3027794367 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1818500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1818500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11891425269 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11891425269 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 666484538 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 571688851 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 6944017926 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 52451258278 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 60633449593 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 666484538 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 571688851 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 6944017926 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 52451258278 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 60633449593 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 612223 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 196850 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5882214 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4137305 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 10828592 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3658566 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3658566 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 454086 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 454086 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 225338 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 225338 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 190851 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 190851 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1216652 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1216652 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 612223 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 196850 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5882214 # number of demand (read+write) accesses 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7509818481 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 327287462 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13621135743 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34464397241 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 48818419677 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 327287462 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13621135743 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34464397241 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39485552404 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 88303972081 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5233250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 741632996 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 746866246 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 846035990 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 846035990 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5233250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1587668986 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1592902236 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.263023 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.161369 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000005 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000005 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.198134 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.198134 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.574830 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.574830 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.781453 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.781453 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.544047 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.544047 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.669881 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.669881 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845860 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.845860 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.180399 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.180399 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132931 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211837 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211837 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.166458 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.401623 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27705.527306 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27112.291240 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36830.440224 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31073.249872 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31073.249872 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17075.365387 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17075.365387 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13826.798875 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13826.798875 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213785.714286 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213785.714286 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33235.203246 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33235.203246 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27951.592092 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33891.685533 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.229614 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27088.613218 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25479.272145 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55953.826735 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30220.826364 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30220.826364 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17019.129327 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17019.129327 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13344.779958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13344.779958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 205307.692308 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 205307.692308 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31462.643936 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31462.643936 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26247.125426 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34417.992621 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2598,66 +2816,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 15325840 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 11081361 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7210 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7210 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3658566 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 4807205 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 18 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 637593 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 454086 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 471082 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 336358 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 477965 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1352070 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1222067 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11764566 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16293479 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 431287 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1341589 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 29830921 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 376462768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 612089908 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1574800 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4897784 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 995025260 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10166385 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 26584709 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.370632 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.482974 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 12802922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10291743 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3392582 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1076196 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1156933 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 420701 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 464615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 376292 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 486818 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1296360 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1132878 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11046012 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15089863 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 415115 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1210522 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27761512 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353468736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 564735319 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1532736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4394080 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 924130871 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5316111 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 20559073 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.243524 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.429209 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 16731578 62.94% 62.94% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 9853131 37.06% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 15552442 75.65% 75.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 5006631 24.35% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 26584709 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12493291014 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 20559073 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11602796673 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175961487 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 182870488 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8832336643 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8299279905 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8528127192 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7848510644 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 235484276 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 224378946 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 730977975 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 662954125 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40396 # Transaction distribution -system.iobus.trans_dist::ReadResp 40396 # Transaction distribution -system.iobus.trans_dist::WriteReq 136775 # Transaction distribution -system.iobus.trans_dist::WriteResp 30047 # Transaction distribution +system.iobus.trans_dist::ReadReq 40399 # Transaction distribution +system.iobus.trans_dist::ReadResp 40399 # Transaction distribution +system.iobus.trans_dist::WriteReq 136785 # Transaction distribution +system.iobus.trans_dist::WriteResp 30057 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2672,13 +2890,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48148 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354368 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48174 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2693,13 +2911,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156169 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156195 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497071 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36581000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497097 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36604000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2727,27 +2945,27 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1043032876 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1043087367 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93018000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93034000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179190812 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179187461 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115581 # number of replacements -system.iocache.tags.tagsinuse 11.295325 # Cycle average of tags in use +system.iocache.tags.replacements 115604 # number of replacements +system.iocache.tags.tagsinuse 11.301402 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9153631711000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.835501 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.459825 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239719 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466239 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705958 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9117040369000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.419209 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.882193 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463701 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242637 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706338 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2767,18 +2985,18 @@ system.iocache.overall_misses::realview.ethernet 40 system.iocache.overall_misses::realview.ide 8872 # number of overall misses system.iocache.overall_misses::total 8912 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1960529318 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1966236318 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 365000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 365000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28841569746 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28841569746 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6072000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1960529318 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1966601318 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6072000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1960529318 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1966601318 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1954318592 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1960025592 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28939092314 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28939092314 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1954318592 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1960382592 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1954318592 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1960382592 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) @@ -2806,28 +3024,28 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220979.409152 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220702.246941 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 121666.666667 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270234.331628 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270234.331628 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220668.909111 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220668.909111 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 224453 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 220279.372408 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 220005.117522 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271148.080298 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271148.080298 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 219971.116697 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 219971.116697 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228427 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27297 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.222625 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.295878 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106702 # number of writebacks +system.iocache.writebacks::total 106702 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses @@ -2842,18 +3060,18 @@ system.iocache.overall_mshr_misses::realview.ethernet 40 system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1499010380 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1502793380 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 209000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 209000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23291152308 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23291152308 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3992000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1499010380 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1503002380 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3992000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1499010380 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1503002380 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492830122 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1496613122 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23388843706 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23388843706 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1492830122 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1496814122 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1492830122 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1496814122 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2868,569 +3086,561 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168959.691163 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 168682.610843 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.071172 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.071172 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168263.088593 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 167988.901336 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219144.401713 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219144.401713 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1916125 # number of replacements -system.l2c.tags.tagsinuse 64884.880884 # Cycle average of tags in use -system.l2c.tags.total_refs 8755676 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1978999 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.424295 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3437261500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 8337.656958 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.346754 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 14.129416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 627.039592 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3445.654069 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15412.309931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 351.392171 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 435.207962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 621.389971 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11403.863316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 24218.890744 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.127223 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000265 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000216 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.009568 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.052577 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.235173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005362 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006641 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.009482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.174009 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.369551 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990065 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 38428 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 24245 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 2926 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6291 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29058 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1447 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2670 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 19923 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.586365 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.369949 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 93004482 # Number of tag accesses -system.l2c.tags.data_accesses 93004482 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9030 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6306 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 171973 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 713080 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1991967 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 8819 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5864 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 186687 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 740221 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2136612 # number of ReadReq hits -system.l2c.ReadReq_hits::total 5970559 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 3063024 # number of Writeback hits -system.l2c.Writeback_hits::total 3063024 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 47241 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 45742 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 92983 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 33885 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 29324 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 63209 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7714 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7828 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15542 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60878 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59021 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 119899 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9030 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6306 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 171973 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 773958 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1991967 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 8819 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5864 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 186687 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 799242 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 2136612 # number of demand (read+write) hits -system.l2c.demand_hits::total 6090458 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9030 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6306 # number of overall hits -system.l2c.overall_hits::cpu0.inst 171973 # number of overall hits -system.l2c.overall_hits::cpu0.data 773958 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1991967 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 8819 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5864 # number of overall hits -system.l2c.overall_hits::cpu1.inst 186687 # number of overall hits -system.l2c.overall_hits::cpu1.data 799242 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 2136612 # number of overall hits -system.l2c.overall_hits::total 6090458 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1923 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1303 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 12603 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 144091 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 852232 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3910 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 3826 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 10632 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 164104 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 554912 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1749536 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 29537 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 18781 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 48318 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 37338 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 36221 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 73559 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9578 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9902 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 19480 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 52901 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 53544 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 106445 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1923 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1303 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 12603 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 196992 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 852232 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3910 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3826 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10632 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 217648 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 554912 # number of demand (read+write) misses -system.l2c.demand_misses::total 1855981 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1923 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1303 # number of overall misses -system.l2c.overall_misses::cpu0.inst 12603 # number of overall misses -system.l2c.overall_misses::cpu0.data 196992 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 852232 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3910 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3826 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10632 # number of overall misses -system.l2c.overall_misses::cpu1.data 217648 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 554912 # number of overall misses -system.l2c.overall_misses::total 1855981 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 177025748 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 119617998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1238513239 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 13834613079 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 153097994602 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 331865247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 326979750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1012532239 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 14885938635 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 79345151118 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 264370231655 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 10044630 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 10457617 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 20502247 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 175354905 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 165935687 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 341290592 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 48698982 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 55173706 # number of SCUpgradeReq miss cycles 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accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 12729 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 9690 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 197319 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 904325 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2691524 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 7720095 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 3063024 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 3063024 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 76778 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 64523 # number of WriteInvalidateReq accesses(hits+misses) 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10953 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7609 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 184576 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 970950 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2844199 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 12729 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 9690 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 197319 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1016890 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2691524 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 7946439 # number of demand (read+write) accesses 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overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.175568 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.171245 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.068281 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.168101 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.299639 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.307173 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.394840 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.053882 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.181466 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.206170 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.226621 # miss rate for ReadReq accesses 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for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.470280 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.175568 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.171245 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.068281 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.202886 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.299639 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.307173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.394840 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.053882 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.214033 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.206170 # miss rate for demand accesses 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warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 19101.398352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 185.742619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 228.186438 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3981.341018 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11353.199987 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11643.208368 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.349370 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 266.651363 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3248.685748 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4974.329517 # Average occupied blocks per requestor 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140034 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.981740 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10683 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49559 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 995 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9444 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 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123170 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 261828 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 30955 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 32781 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 63736 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6525 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5847 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12372 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 54058 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53543 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107601 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6508 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4319 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 640995 # number of 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+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80292.648521 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 80445.957655 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 107317.450557 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80292.648521 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 80445.957655 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 107317.450557 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3445,57 +3655,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1817706 # Transaction distribution -system.membus.trans_dist::ReadResp 1817706 # Transaction distribution -system.membus.trans_dist::WriteReq 38526 # Transaction distribution -system.membus.trans_dist::WriteResp 38526 # Transaction distribution -system.membus.trans_dist::Writeback 1444194 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 154200 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 154200 # Transaction distribution -system.membus.trans_dist::UpgradeReq 434662 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 279066 # Transaction distribution -system.membus.trans_dist::UpgradeResp 97607 # Transaction distribution -system.membus.trans_dist::ReadExReq 117028 # Transaction distribution -system.membus.trans_dist::ReadExResp 102726 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123062 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1032278 # Transaction distribution +system.membus.trans_dist::ReadResp 1032278 # Transaction distribution +system.membus.trans_dist::WriteReq 38581 # Transaction distribution +system.membus.trans_dist::WriteResp 38581 # Transaction distribution +system.membus.trans_dist::Writeback 1347712 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 689975 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 689975 # Transaction distribution +system.membus.trans_dist::UpgradeReq 447979 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 332386 # Transaction distribution +system.membus.trans_dist::UpgradeResp 121150 # Transaction distribution +system.membus.trans_dist::ReadExReq 152231 # Transaction distribution +system.membus.trans_dist::ReadExResp 135895 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123088 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25796 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6008493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6157429 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6493541 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156169 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25972 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5571157 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5720295 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6056198 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156195 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 207457224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 207665557 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14110208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 221775765 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 633029 # Total snoops (count) -system.membus.snoop_fanout::samples 4186947 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 187423448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 187632159 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14096832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 201728991 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 678374 # Total snoops (count) +system.membus.snoop_fanout::samples 3943213 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4186947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3943213 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4186947 # Request fanout histogram -system.membus.reqLayer0.occupancy 98514469 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3943213 # Request fanout histogram +system.membus.reqLayer0.occupancy 98700492 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21244987 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21600991 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16738053981 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 19952700228 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17312327015 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 11115498245 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187280188 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187180539 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3539,49 +3749,49 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 8653355 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 8646086 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38526 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38526 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3063024 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 248029 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 141301 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 493306 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 294608 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 787914 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 273153 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 273153 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10956928 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10351144 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 21308072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 369780529 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 344544100 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 714324629 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1644746 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12968411 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.008917 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.094008 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4932840 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4925609 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38581 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38581 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2564009 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 955023 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 848293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 504313 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 344758 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 849071 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 157 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 306644 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 306644 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8600677 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6275419 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14876096 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 289885704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198430935 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 488316639 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1740265 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9550575 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012108 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109370 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12852771 99.11% 99.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115640 0.89% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9434933 98.79% 98.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115642 1.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12968411 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 19352517195 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9550575 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 18722164156 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7381500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7552500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20456793572 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 13115425494 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 20083133002 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 11201753623 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13518 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13602 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5604 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5345 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 5bc8e2e71..48ca1dfde 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.320621 # Number of seconds simulated -sim_ticks 51320620981500 # Number of ticks simulated -final_tick 51320620981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.320647 # Number of seconds simulated +sim_ticks 51320647066500 # Number of ticks simulated +final_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107709 # Simulator instruction rate (inst/s) -host_op_rate 126560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6449160479 # Simulator tick rate (ticks/s) -host_mem_usage 667684 # Number of bytes of host memory used -host_seconds 7957.72 # Real time elapsed on the host -sim_insts 857117694 # Number of instructions simulated -sim_ops 1007133124 # Number of ops (including micro ops) simulated +host_inst_rate 114690 # Simulator instruction rate (inst/s) +host_op_rate 134762 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6864170011 # Simulator tick rate (ticks/s) +host_mem_usage 721888 # Number of bytes of host memory used +host_seconds 7476.60 # Real time elapsed on the host +sim_insts 857487967 # Number of instructions simulated +sim_ops 1007562352 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 227264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 206272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5756576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43073416 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 400256 # Number of bytes read from this memory -system.physmem.bytes_read::total 49663784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5756576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5756576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69780544 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory +system.physmem.bytes_read::total 49637032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69801124 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3551 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3223 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 673035 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6254 # Number of read requests responded to by this memory -system.physmem.num_reads::total 791962 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1090321 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69739044 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory +system.physmem.num_reads::total 791544 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1092894 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 112169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 839300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 967716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 112169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 112169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1359698 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1360099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1359698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 112169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 839701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2327815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 791962 # Number of read requests accepted -system.physmem.writeReqs 1696531 # Number of write requests accepted -system.physmem.readBursts 791962 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1696531 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 50649920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35648 # Total number of bytes read from write queue -system.physmem.bytesWritten 108090368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49663784 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 108433892 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 557 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7601 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35291 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 50546 # Per bank write bursts -system.physmem.perBankRdBursts::1 51810 # Per bank write bursts -system.physmem.perBankRdBursts::2 46789 # Per bank write bursts -system.physmem.perBankRdBursts::3 46242 # Per bank write bursts -system.physmem.perBankRdBursts::4 46096 # Per bank write bursts -system.physmem.perBankRdBursts::5 52242 # Per bank write bursts -system.physmem.perBankRdBursts::6 46925 # Per bank write bursts -system.physmem.perBankRdBursts::7 49452 # Per bank write bursts -system.physmem.perBankRdBursts::8 44750 # Per bank write bursts -system.physmem.perBankRdBursts::9 73148 # Per bank write bursts -system.physmem.perBankRdBursts::10 48402 # Per bank write bursts -system.physmem.perBankRdBursts::11 51457 # Per bank write bursts -system.physmem.perBankRdBursts::12 45806 # Per bank write bursts -system.physmem.perBankRdBursts::13 48601 # Per bank write bursts -system.physmem.perBankRdBursts::14 42635 # Per bank write bursts -system.physmem.perBankRdBursts::15 46504 # Per bank write bursts -system.physmem.perBankWrBursts::0 106325 # Per bank write bursts -system.physmem.perBankWrBursts::1 106592 # Per bank write bursts -system.physmem.perBankWrBursts::2 106293 # Per bank write bursts -system.physmem.perBankWrBursts::3 105191 # Per bank write bursts -system.physmem.perBankWrBursts::4 106687 # Per bank write bursts -system.physmem.perBankWrBursts::5 109171 # Per bank write bursts -system.physmem.perBankWrBursts::6 103226 # Per bank write bursts -system.physmem.perBankWrBursts::7 105745 # Per bank write bursts -system.physmem.perBankWrBursts::8 103090 # Per bank write bursts -system.physmem.perBankWrBursts::9 109771 # Per bank write bursts -system.physmem.perBankWrBursts::10 107182 # Per bank write bursts -system.physmem.perBankWrBursts::11 108709 # Per bank write bursts -system.physmem.perBankWrBursts::12 102154 # Per bank write bursts -system.physmem.perBankWrBursts::13 106063 # Per bank write bursts -system.physmem.perBankWrBursts::14 100653 # Per bank write bursts -system.physmem.perBankWrBursts::15 102060 # Per bank write bursts +system.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 791544 # Number of read requests accepted +system.physmem.writeReqs 1694292 # Number of write requests accepted +system.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue +system.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 48315 # Per bank write bursts +system.physmem.perBankRdBursts::1 50150 # Per bank write bursts +system.physmem.perBankRdBursts::2 46175 # Per bank write bursts +system.physmem.perBankRdBursts::3 46946 # Per bank write bursts +system.physmem.perBankRdBursts::4 45323 # Per bank write bursts +system.physmem.perBankRdBursts::5 52981 # Per bank write bursts +system.physmem.perBankRdBursts::6 47646 # Per bank write bursts +system.physmem.perBankRdBursts::7 48748 # Per bank write bursts +system.physmem.perBankRdBursts::8 44337 # Per bank write bursts +system.physmem.perBankRdBursts::9 72322 # Per bank write bursts +system.physmem.perBankRdBursts::10 50834 # Per bank write bursts +system.physmem.perBankRdBursts::11 50772 # Per bank write bursts +system.physmem.perBankRdBursts::12 48451 # Per bank write bursts +system.physmem.perBankRdBursts::13 47387 # Per bank write bursts +system.physmem.perBankRdBursts::14 44232 # Per bank write bursts +system.physmem.perBankRdBursts::15 46363 # Per bank write bursts +system.physmem.perBankWrBursts::0 103979 # Per bank write bursts +system.physmem.perBankWrBursts::1 105038 # Per bank write bursts +system.physmem.perBankWrBursts::2 105754 # Per bank write bursts +system.physmem.perBankWrBursts::3 105161 # Per bank write bursts +system.physmem.perBankWrBursts::4 103562 # Per bank write bursts +system.physmem.perBankWrBursts::5 108435 # Per bank write bursts +system.physmem.perBankWrBursts::6 103867 # Per bank write bursts +system.physmem.perBankWrBursts::7 105467 # Per bank write bursts +system.physmem.perBankWrBursts::8 102645 # Per bank write bursts +system.physmem.perBankWrBursts::9 108407 # Per bank write bursts +system.physmem.perBankWrBursts::10 108582 # Per bank write bursts +system.physmem.perBankWrBursts::11 107982 # Per bank write bursts +system.physmem.perBankWrBursts::12 105330 # Per bank write bursts +system.physmem.perBankWrBursts::13 105345 # Per bank write bursts +system.physmem.perBankWrBursts::14 103911 # Per bank write bursts +system.physmem.perBankWrBursts::15 104029 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 63 # Number of times write queue was full causing retry -system.physmem.totGap 51320619748500 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 51320645833500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 770677 # Read request sizes (log2) +system.physmem.readPktSize::6 770259 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1693958 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 524690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 218670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1691719 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157 # What read queue length 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does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,122 +159,122 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 66510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 80685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 95220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 95674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 107871 # What write queue length does an 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-system.physmem.wrQLenPdf::55 1152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 151 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 519847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.358892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.693203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.458813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210597 40.51% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 125304 24.10% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44434 8.55% 73.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23828 4.58% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16026 3.08% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10297 1.98% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8038 1.55% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7736 1.49% 85.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 73587 14.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 519847 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65806 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.026092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 69.420005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 65801 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 97233 # What write queue length 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per row activation +system.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65806 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65806 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.665015 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 22.295407 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 18.784846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 44130 67.06% 67.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6726 10.22% 77.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 8110 12.32% 89.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 2086 3.17% 92.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1158 1.76% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 536 0.81% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 588 0.89% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 530 0.81% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 479 0.73% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 220 0.33% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 383 0.58% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 149 0.23% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 276 0.42% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 79 0.12% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 128 0.19% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 41 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 35 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 20 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 44 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 20 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 23 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 10 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65806 # Writes before turning the bus around for reads -system.physmem.totQLat 15790981009 # Total ticks spent queuing -system.physmem.totMemAccLat 30629824759 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3957025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19953.10 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads +system.physmem.totQLat 15484448260 # Total ticks spent queuing +system.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38703.10 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -282,36 +282,41 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.05 # Average write queue length when enqueuing -system.physmem.readRowHits 603831 # Number of row buffer hits during reads -system.physmem.writeRowHits 1356638 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes -system.physmem.avgGap 20623172.24 # Average gap between requests +system.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing +system.physmem.readRowHits 603455 # Number of row buffer hits during reads +system.physmem.writeRowHits 1355453 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes +system.physmem.avgGap 20645225.93 # Average gap between requests system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49368372569000 # Time in different power states -system.physmem.memoryStateTime::REF 1713708100000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 238539960500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 1984348800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1945694520 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1082730000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1061638875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3042748800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3130163400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5503010400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5441139360 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3352013043600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3352013043600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1228384903950 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1226638074825 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29714838054000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29716370360250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34306848839550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34306600114830 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.480867 # Core power per rank (mW) -system.physmem.averagePower::1 668.476020 # Core power per rank (mW) +system.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.473889 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.480369 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory @@ -334,16 +339,24 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 226428976 # Number of BP lookups -system.cpu.branchPred.condPredicted 151471445 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12246087 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159886473 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104578062 # Number of BTB hits +system.cpu.branchPred.lookups 226505876 # Number of BP lookups +system.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104610641 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.407698 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31061917 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 345275 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -365,27 +378,95 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 931379 # Table walker walks requested +system.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 171196432 # DTB read hits -system.cpu.dtb.read_misses 671544 # DTB read misses -system.cpu.dtb.write_hits 149025904 # DTB write hits -system.cpu.dtb.write_misses 258759 # DTB write misses +system.cpu.dtb.read_hits 171278986 # DTB read hits +system.cpu.dtb.read_misses 671795 # DTB read misses +system.cpu.dtb.write_hits 149102166 # DTB write hits +system.cpu.dtb.write_misses 259584 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72979 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 104 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10362 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 68614 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171867976 # DTB read accesses -system.cpu.dtb.write_accesses 149284663 # DTB write accesses +system.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171950781 # DTB read accesses +system.cpu.dtb.write_accesses 149361750 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320222336 # DTB hits -system.cpu.dtb.misses 930303 # DTB misses -system.cpu.dtb.accesses 321152639 # DTB accesses +system.cpu.dtb.hits 320381152 # DTB hits +system.cpu.dtb.misses 931379 # DTB misses +system.cpu.dtb.accesses 321312531 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -407,8 +488,66 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 360051885 # ITB inst hits -system.cpu.itb.inst_misses 161655 # ITB inst misses +system.cpu.itb.walker.walks 161841 # Table walker walks requested +system.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 360168043 # ITB inst hits +system.cpu.itb.inst_misses 161841 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -417,111 +556,111 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53701 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372863 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 360213540 # ITB inst accesses -system.cpu.itb.hits 360051885 # DTB hits -system.cpu.itb.misses 161655 # DTB misses -system.cpu.itb.accesses 360213540 # DTB accesses -system.cpu.numCycles 1576874693 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 360329884 # ITB inst accesses +system.cpu.itb.hits 360168043 # DTB hits +system.cpu.itb.misses 161841 # DTB misses +system.cpu.itb.accesses 360329884 # DTB accesses +system.cpu.numCycles 1576983833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 648679854 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1010290403 # Number of instructions fetch has processed -system.cpu.fetch.Branches 226428976 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135639979 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 852655064 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26160452 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3389644 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9240220 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1021673 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 359662567 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6136086 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47510 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1528093850 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.774691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed +system.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 965958627 63.21% 63.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215893777 14.13% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70817340 4.63% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 275424106 18.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1528093850 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.143594 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.640692 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 527180052 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 504302107 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 436284853 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51059674 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9267164 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33905862 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3872221 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1095429909 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29099398 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9267164 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 572442291 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46180186 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363186865 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 441948285 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 95069059 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1075584704 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6788495 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4945824 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 318864 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 589123 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 42956715 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 21763 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1023437611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1659121727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1272319582 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1685396 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 957674620 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65762988 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27435128 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23745394 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104747763 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 175168030 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 152601618 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9963388 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9061948 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1040022976 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27737741 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1056135120 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3300763 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53598061 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33623556 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 314928 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1528093850 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691145 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.927830 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 436470729 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 442135288 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 873977548 57.19% 57.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 338098484 22.13% 79.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 236626258 15.49% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72801252 4.76% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6571176 0.43% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19132 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1528093850 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58371154 35.14% 35.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100885 0.06% 35.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26756 0.02% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available @@ -544,19 +683,19 @@ system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # at system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 767 0.00% 35.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44544414 26.81% 62.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63075062 37.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 727332382 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2546997 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 123061 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -578,102 +717,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 120668 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 175096796 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150915164 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1056135120 # Type of FU issued -system.cpu.iq.rate 0.669765 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166119038 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3807304115 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1120557954 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1038099529 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2479775 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 941816 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 907592 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1220693938 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1560218 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4348848 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued +system.cpu.iq.rate 0.670005 # Inst issue rate +system.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13855252 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14404 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142361 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6337064 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2552747 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1859122 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9267164 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6379535 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3965873 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1067985048 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 175168030 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 152601618 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23314125 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 62024 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3832996 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142361 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3691152 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5135953 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8827105 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1044930592 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171186057 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10287379 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224331 # number of nop insts executed -system.cpu.iew.exec_refs 320208959 # number of memory reference insts executed -system.cpu.iew.exec_branches 198322451 # Number of branches executed -system.cpu.iew.exec_stores 149022902 # Number of stores executed -system.cpu.iew.exec_rate 0.662659 # Inst execution rate -system.cpu.iew.wb_sent 1039793819 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1039007121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 442154878 # num instructions producing a value -system.cpu.iew.wb_consumers 715627882 # num instructions consuming a value +system.cpu.iew.exec_nop 224348 # number of nop insts executed +system.cpu.iew.exec_refs 320367802 # number of memory reference insts executed +system.cpu.iew.exec_branches 198404489 # Number of branches executed +system.cpu.iew.exec_stores 149099070 # Number of stores executed +system.cpu.iew.exec_rate 0.662897 # Inst execution rate +system.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back +system.cpu.iew.wb_producers 442335874 # num instructions producing a value +system.cpu.iew.wb_consumers 715873221 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.658903 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.617856 # average fanout of values written-back +system.cpu.iew.wb_rate 0.659130 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51471265 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27422813 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8433025 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1516084212 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.664299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.291990 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 998537580 65.86% 65.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 291350566 19.22% 85.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121957393 8.04% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36696853 2.42% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28610485 1.89% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14255849 0.94% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8557612 0.56% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4232636 0.28% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11885238 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1516084212 # Number of insts commited each cycle -system.cpu.commit.committedInsts 857117694 # Number of instructions committed -system.cpu.commit.committedOps 1007133124 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle +system.cpu.commit.committedInsts 857487967 # Number of instructions committed +system.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 307577331 # Number of memory references committed -system.cpu.commit.loads 161312777 # Number of loads committed -system.cpu.commit.membars 7014752 # Number of memory barriers committed -system.cpu.commit.branches 191334741 # Number of branches committed -system.cpu.commit.fp_insts 896026 # Number of committed floating point instructions. -system.cpu.commit.int_insts 925144388 # Number of committed integer instructions. -system.cpu.commit.function_calls 25493443 # Number of function calls committed. +system.cpu.commit.refs 307720812 # Number of memory references committed +system.cpu.commit.loads 161382253 # Number of loads committed +system.cpu.commit.membars 7017472 # Number of memory barriers committed +system.cpu.commit.branches 191417503 # Number of branches committed +system.cpu.commit.fp_insts 895898 # Number of committed floating point instructions. +system.cpu.commit.int_insts 925548459 # Number of committed integer instructions. +system.cpu.commit.function_calls 25509836 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 697181314 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2164633 0.21% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98281 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction @@ -700,233 +839,232 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 161312777 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 146264554 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1007133124 # Class of committed instruction -system.cpu.commit.bw_lim_events 11885238 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction +system.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2555181565 # The number of ROB reads -system.cpu.rob.rob_writes 2129123637 # The number of ROB writes -system.cpu.timesIdled 8137810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 48780843 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101064367400 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 857117694 # Number of Instructions Simulated -system.cpu.committedOps 1007133124 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.839741 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.839741 # CPI: Total CPI of All Threads -system.cpu.ipc 0.543555 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.543555 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237020079 # number of integer regfile reads -system.cpu.int_regfile_writes 738429626 # number of integer regfile writes -system.cpu.fp_regfile_reads 1457787 # number of floating regfile reads -system.cpu.fp_regfile_writes 782552 # number of floating regfile writes -system.cpu.cc_regfile_reads 228125574 # number of cc regfile reads -system.cpu.cc_regfile_writes 228731881 # number of cc regfile writes -system.cpu.misc_regfile_reads 5247037954 # number of misc regfile reads -system.cpu.misc_regfile_writes 27486572 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9822538 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.985265 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 286045243 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9823050 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.119799 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.985265 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 2555751551 # The number of ROB reads +system.cpu.rob.rob_writes 2129995502 # The number of ROB writes +system.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 857487967 # Number of Instructions Simulated +system.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.839074 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads +system.cpu.ipc 0.543752 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237547063 # number of integer regfile reads +system.cpu.int_regfile_writes 738733043 # number of integer regfile writes +system.cpu.fp_regfile_reads 1457540 # number of floating regfile reads +system.cpu.fp_regfile_writes 782548 # number of floating regfile writes +system.cpu.cc_regfile_reads 228190122 # number of cc regfile reads +system.cpu.cc_regfile_writes 228796042 # number of cc regfile writes +system.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads +system.cpu.misc_regfile_writes 27489325 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9822587 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1249214859 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1249214859 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148712432 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148712432 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 129479125 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 129479125 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 381594 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 381594 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324870 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 324870 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352883 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3352883 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3750315 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3750315 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 278191557 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 278191557 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 278573151 # number of overall hits -system.cpu.dcache.overall_hits::total 278573151 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9502058 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9502058 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11465174 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11465174 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1197022 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1197022 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233022 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1233022 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 449448 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 449448 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits 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hits +system.cpu.dcache.overall_hits::total 278710234 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9497038 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9497038 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11468447 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11468447 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1197141 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1197141 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233328 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1233328 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 450623 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 450623 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20967232 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20967232 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22164254 # number of overall misses -system.cpu.dcache.overall_misses::total 22164254 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 140935225401 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 322991667568 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38675981880 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38675981880 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6315194753 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6315194753 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 20965485 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20965485 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22162626 # number of overall misses +system.cpu.dcache.overall_misses::total 22162626 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 140713387644 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 321962948230 # number of WriteReq miss cycles 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 158214490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 158214490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 140944299 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 140944299 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578616 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1578616 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557892 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1557892 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3802331 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3802331 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3750320 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3750320 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 299158789 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 299158789 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300737405 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300737405 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060058 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060058 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081345 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081345 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758273 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758273 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791468 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791468 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118203 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118203 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1578474 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557891 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1557891 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3803045 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3803045 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3751275 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3751275 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 299294386 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 299294386 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300872860 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118490 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070087 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070087 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073700 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073700 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency 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access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1401851 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.313184 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7593763 # number of writebacks -system.cpu.dcache.writebacks::total 7593763 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4321399 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4321399 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9425025 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9425025 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7055 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7055 # number of WriteInvalidateReq MSHR hits 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-system.cpu.dcache.SoftPFReq_mshr_misses::total 1190231 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1225967 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1225967 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230034 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 230034 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 7597183 # number of writebacks +system.cpu.dcache.writebacks::total 7597183 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4319062 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4319062 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9426489 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9426489 # number of WriteReq MSHR hits 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WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2041958 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1190352 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1190352 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226180 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226180 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230589 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 230589 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7220808 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7220808 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8411039 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8411039 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70208074682 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70208074682 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53752252884 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53752252884 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18853760746 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18853760746 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35977742828 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35977742828 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2809792248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2809792248 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 7219934 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7219934 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8410286 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8410286 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70110899674 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70110899674 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53589743024 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53589743024 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18780468745 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18780468745 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35955294132 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35955294132 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2813771248 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2813771248 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123960327566 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123960327566 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142814088312 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 142814088312 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729213249 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729213249 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587099983 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587099983 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316313232 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316313232 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032745 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032745 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753971 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753971 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786940 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786940 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060498 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060498 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 142481111443 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729238749 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729238749 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587095483 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587095483 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316334232 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316334232 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024137 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024137 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027968 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027968 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13551.958290 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13551.958290 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26347.219190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26347.219190 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15840.421520 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024123 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024123 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027953 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027953 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -934,276 +1072,277 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15082585 # number of replacements -system.cpu.icache.tags.tagsinuse 511.954216 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 343840613 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15083097 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.796420 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14175734000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.954216 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 15084162 # number of replacements +system.cpu.icache.tags.tagsinuse 511.954207 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 343955623 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15084674 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.801661 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14174936000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.954207 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 374724467 # Number of tag accesses -system.cpu.icache.tags.data_accesses 374724467 # Number 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68334.936084 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1329,58 +1468,58 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23341232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23333163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7593763 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1225967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43982 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1999866 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1999866 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30208899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27463876 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 731462 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1967033 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 60371270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965659760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1114918084 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2404176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6408648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2089390668 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 611685 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34508223 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003348 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.057762 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 606880 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003347 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 34392703 99.67% 99.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115520 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 34397489 99.67% 99.67% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115519 0.33% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34508223 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 26206492236 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1177500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22671590732 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13674088224 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 431886005 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1166711358 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40382 # Transaction distribution -system.iobus.trans_dist::ReadResp 40382 # Transaction distribution +system.iobus.trans_dist::ReadReq 40381 # Transaction distribution +system.iobus.trans_dist::ReadResp 40381 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1400,11 +1539,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1421,11 +1560,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1454,71 +1593,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042360658 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179004169 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115462 # number of replacements -system.iocache.tags.tagsinuse 10.424613 # Cycle average of tags in use +system.iocache.tags.replacements 115461 # number of replacements +system.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115478 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13092189065000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544618 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879995 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039677 # Number of tag accesses -system.iocache.tags.data_accesses 1039677 # Number of data accesses +system.iocache.tags.tag_accesses 1039668 # Number of tag accesses +system.iocache.tags.data_accesses 1039668 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses -system.iocache.demand_misses::total 8856 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses +system.iocache.demand_misses::total 8855 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8816 # number of overall misses -system.iocache.overall_misses::total 8856 # number of overall misses +system.iocache.overall_misses::realview.ide 8815 # number of overall misses +system.iocache.overall_misses::total 8855 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1927411613 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1932938613 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1934147111 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1939674111 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28910124876 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28910124876 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28899223848 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28899223848 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1927411613 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1933277613 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1934147111 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1940013111 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1927411613 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1933277613 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1934147111 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1940013111 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1533,54 +1672,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 218337.130125 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 218301.446816 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 218301.446816 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 226675 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27646 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.199197 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8816 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8856 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1468863623 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1472466623 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23363269204 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23363269204 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1468863623 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1472649623 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1468863623 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1472649623 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1595,70 +1734,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 412825 # Transaction distribution -system.membus.trans_dist::ReadResp 412825 # Transaction distribution +system.membus.trans_dist::ReadReq 411277 # Transaction distribution +system.membus.trans_dist::ReadResp 411277 # Transaction distribution system.membus.trans_dist::WriteReq 33858 # Transaction distribution system.membus.trans_dist::WriteResp 33858 # Transaction distribution -system.membus.trans_dist::Writeback 1090321 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 603637 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 603637 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35296 # Transaction distribution +system.membus.trans_dist::Writeback 1089351 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35261 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35298 # Transaction distribution -system.membus.trans_dist::ReadExReq 416163 # Transaction distribution -system.membus.trans_dist::ReadExResp 416163 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35263 # Transaction distribution +system.membus.trans_dist::ReadExReq 417183 # Transaction distribution +system.membus.trans_dist::ReadExResp 417183 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3625442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3755550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4090619 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144046540 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144217012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14051136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14051136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 158268148 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3264 # Total snoops (count) -system.membus.snoop_fanout::samples 2503253 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3154 # Total snoops (count) +system.membus.snoop_fanout::samples 2500418 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2503253 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2503253 # Request fanout histogram -system.membus.reqLayer0.occupancy 109702500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2500418 # Request fanout histogram +system.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5437999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16337638979 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7836649146 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186565831 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index a91165258..e7103dcb2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.234988 # Number of seconds simulated -sim_ticks 51234988037500 # Number of ticks simulated -final_tick 51234988037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.234984 # Number of seconds simulated +sim_ticks 51234983764500 # Number of ticks simulated +final_tick 51234983764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253332 # Simulator instruction rate (inst/s) -host_op_rate 297695 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14683650995 # Simulator tick rate (ticks/s) -host_mem_usage 666424 # Number of bytes of host memory used -host_seconds 3489.25 # Real time elapsed on the host -sim_insts 883939374 # Number of instructions simulated -sim_ops 1038732312 # Number of ops (including micro ops) simulated +host_inst_rate 293597 # Simulator instruction rate (inst/s) +host_op_rate 345003 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16999127000 # Simulator tick rate (ticks/s) +host_mem_usage 723216 # Number of bytes of host memory used +host_seconds 3013.98 # Real time elapsed on the host +sim_insts 884896163 # Number of instructions simulated +sim_ops 1039832130 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 127040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 124736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3010420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25072712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 36992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 30656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 716608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7359168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 93568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 90944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 2126784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 17729152 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417856 # Number of bytes read from this memory -system.physmem.bytes_read::total 56936636 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3010420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 716608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 2126784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5853812 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77081408 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 129856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 125184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2903796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24969352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 34560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 29888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 811648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7348736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 94656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 89280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 2169408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 17774080 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 413120 # Number of bytes read from this memory +system.physmem.bytes_read::total 56893564 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2903796 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 811648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 2169408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5884852 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77105472 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 77101988 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 87445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 391774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 11197 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 114987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 1462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 33231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 277018 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6529 # Number of read requests responded to by this memory -system.physmem.num_reads::total 930055 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1204397 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77126052 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 85779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 390159 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 540 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 12682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 114824 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 1479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 33897 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 277720 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 929382 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1204773 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1206970 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 58757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 489367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 13987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 143636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 1826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 1775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 41510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 346036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1111284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 58757 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 13987 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 41510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 114254 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1504468 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1207346 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 56676 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 487350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 675 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 15842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 143432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 1847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 1743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 346913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1110444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 56676 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 15842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42342 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 114860 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1504938 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1504870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1504468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 58757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 489769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 13987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 143636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 1826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 1775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 41510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 346036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2616154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 440433 # Number of read requests accepted -system.physmem.writeReqs 603232 # Number of write requests accepted -system.physmem.readBursts 440433 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 603232 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28170752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16960 # Total number of bytes read from write queue -system.physmem.bytesWritten 38511488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28187712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 38606848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 265 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1490 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18504 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25157 # Per bank write bursts -system.physmem.perBankRdBursts::1 28496 # Per bank write bursts -system.physmem.perBankRdBursts::2 28335 # Per bank write bursts -system.physmem.perBankRdBursts::3 27633 # Per bank write bursts -system.physmem.perBankRdBursts::4 27808 # Per bank write bursts -system.physmem.perBankRdBursts::5 30320 # Per bank write bursts -system.physmem.perBankRdBursts::6 26148 # Per bank write bursts -system.physmem.perBankRdBursts::7 26657 # Per bank write bursts -system.physmem.perBankRdBursts::8 26790 # Per bank write bursts -system.physmem.perBankRdBursts::9 29797 # Per bank write bursts -system.physmem.perBankRdBursts::10 28841 # Per bank write bursts -system.physmem.perBankRdBursts::11 30668 # Per bank write bursts -system.physmem.perBankRdBursts::12 26625 # Per bank write bursts -system.physmem.perBankRdBursts::13 26518 # Per bank write bursts -system.physmem.perBankRdBursts::14 25131 # Per bank write bursts -system.physmem.perBankRdBursts::15 25244 # Per bank write bursts -system.physmem.perBankWrBursts::0 36236 # Per bank write bursts -system.physmem.perBankWrBursts::1 36759 # Per bank write bursts -system.physmem.perBankWrBursts::2 37480 # Per bank write bursts -system.physmem.perBankWrBursts::3 39199 # Per bank write bursts -system.physmem.perBankWrBursts::4 39135 # Per bank write bursts -system.physmem.perBankWrBursts::5 41156 # Per bank write bursts -system.physmem.perBankWrBursts::6 37007 # Per bank write bursts -system.physmem.perBankWrBursts::7 36943 # Per bank write bursts -system.physmem.perBankWrBursts::8 37618 # Per bank write bursts -system.physmem.perBankWrBursts::9 39787 # Per bank write bursts -system.physmem.perBankWrBursts::10 38447 # Per bank write bursts -system.physmem.perBankWrBursts::11 38818 # Per bank write bursts -system.physmem.perBankWrBursts::12 34864 # Per bank write bursts -system.physmem.perBankWrBursts::13 36482 # Per bank write bursts -system.physmem.perBankWrBursts::14 35714 # Per bank write bursts -system.physmem.perBankWrBursts::15 36097 # Per bank write bursts +system.physmem.bw_write::total 1505340 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1504938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 56676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 487751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 15842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 143432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 1847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 1743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 346913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2615783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443127 # Number of read requests accepted +system.physmem.writeReqs 607625 # Number of write requests accepted +system.physmem.readBursts 443127 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 607625 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28344960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 15168 # Total number of bytes read from write queue +system.physmem.bytesWritten 38801344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28360128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 38888000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 237 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1354 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 18550 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25211 # Per bank write bursts +system.physmem.perBankRdBursts::1 29295 # Per bank write bursts +system.physmem.perBankRdBursts::2 27890 # Per bank write bursts +system.physmem.perBankRdBursts::3 27887 # Per bank write bursts +system.physmem.perBankRdBursts::4 27824 # Per bank write bursts +system.physmem.perBankRdBursts::5 30839 # Per bank write bursts +system.physmem.perBankRdBursts::6 26245 # Per bank write bursts +system.physmem.perBankRdBursts::7 26732 # Per bank write bursts +system.physmem.perBankRdBursts::8 26610 # Per bank write bursts +system.physmem.perBankRdBursts::9 29578 # Per bank write bursts +system.physmem.perBankRdBursts::10 29152 # Per bank write bursts +system.physmem.perBankRdBursts::11 31219 # Per bank write bursts +system.physmem.perBankRdBursts::12 26466 # Per bank write bursts +system.physmem.perBankRdBursts::13 26838 # Per bank write bursts +system.physmem.perBankRdBursts::14 25148 # Per bank write bursts +system.physmem.perBankRdBursts::15 25956 # Per bank write bursts +system.physmem.perBankWrBursts::0 36103 # Per bank write bursts +system.physmem.perBankWrBursts::1 37925 # Per bank write bursts +system.physmem.perBankWrBursts::2 36544 # Per bank write bursts +system.physmem.perBankWrBursts::3 38823 # Per bank write bursts +system.physmem.perBankWrBursts::4 41056 # Per bank write bursts +system.physmem.perBankWrBursts::5 42229 # Per bank write bursts +system.physmem.perBankWrBursts::6 37594 # Per bank write bursts +system.physmem.perBankWrBursts::7 36950 # Per bank write bursts +system.physmem.perBankWrBursts::8 37999 # Per bank write bursts +system.physmem.perBankWrBursts::9 38649 # Per bank write bursts +system.physmem.perBankWrBursts::10 38477 # Per bank write bursts +system.physmem.perBankWrBursts::11 38558 # Per bank write bursts +system.physmem.perBankWrBursts::12 34649 # Per bank write bursts +system.physmem.perBankWrBursts::13 36757 # Per bank write bursts +system.physmem.perBankWrBursts::14 36686 # Per bank write bursts +system.physmem.perBankWrBursts::15 37272 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 51233791781500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 51233787261500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 440433 # Read request sizes (log2) +system.physmem.readPktSize::6 443127 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 603232 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 309302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 102 # What read queue length does an incoming req see +system.physmem.writePktSize::6 607625 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 312054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 88763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -180,220 +180,199 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 24225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 27652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 32938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 36604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 38132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 38614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 39680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 39064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 37806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 36835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 37288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 31145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 24672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 28080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 33366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 36383 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 146 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 270943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.111691 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.841271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 289.814348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 123351 45.53% 45.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 67798 25.02% 70.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24089 8.89% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12477 4.61% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8623 3.18% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5501 2.03% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4269 1.58% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3914 1.44% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20921 7.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 270943 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 29531 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.905286 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10.293446 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-15 12117 41.03% 41.03% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16-31 16080 54.45% 95.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-47 1080 3.66% 99.14% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::48-63 183 0.62% 99.76% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-79 43 0.15% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::80-95 13 0.04% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-111 6 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::112-127 3 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-143 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::176-191 2 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::320-335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 29531 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 29531 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.376621 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.754514 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.014003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 5 0.02% 0.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 10 0.03% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 10 0.03% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 38 0.13% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 24052 81.45% 81.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2161 7.32% 88.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 399 1.35% 90.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 574 1.94% 92.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 563 1.91% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 287 0.97% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 195 0.66% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 150 0.51% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 203 0.69% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 86 0.29% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 51 0.17% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 59 0.20% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 110 0.37% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 84 0.28% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 56 0.19% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 59 0.20% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 85 0.29% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 34 0.12% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 26 0.09% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 18 0.06% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 70 0.24% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 10 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 9 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 14 0.05% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 8 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.02% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 7 0.02% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 32 0.11% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 8 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 29531 # Writes before turning the bus around for reads -system.physmem.totQLat 10316676500 # Total ticks spent queuing -system.physmem.totMemAccLat 18569826500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2200840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23438.04 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 274343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.749383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.139289 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 288.784627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 125431 45.72% 45.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 68607 25.01% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24542 8.95% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12363 4.51% 84.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8633 3.15% 87.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5464 1.99% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4467 1.63% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3979 1.45% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20857 7.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 274343 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 29886 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.819313 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.330264 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-15 12451 41.66% 41.66% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-31 16121 53.94% 95.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-47 1059 3.54% 99.15% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-63 175 0.59% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-79 53 0.18% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-95 15 0.05% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-111 5 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-143 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-271 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::304-319 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 29886 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 29886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.286121 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.739916 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.649180 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 14 0.05% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 35 0.12% 0.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 26501 88.67% 88.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 1006 3.37% 92.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 913 3.05% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 433 1.45% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 255 0.85% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 96 0.32% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 167 0.56% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 135 0.45% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 90 0.30% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 37 0.12% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 67 0.22% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 27 0.09% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 22 0.07% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 15 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 37 0.12% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 6 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 4 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 7 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 29886 # Writes before turning the bus around for reads +system.physmem.totQLat 10134279500 # Total ticks spent queuing +system.physmem.totMemAccLat 18438467000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2214450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22882.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42188.04 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41632.16 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 0.76 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.75 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing -system.physmem.readRowHits 332271 # Number of row buffer hits during reads -system.physmem.writeRowHits 438696 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.90 # Row buffer hit rate for writes -system.physmem.avgGap 49090265.35 # Average gap between requests -system.physmem.pageHitRate 74.00 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49384314860250 # Time in different power states -system.physmem.memoryStateTime::REF 1710848620000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 139817808500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 1046447640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1001881440 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 570978375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 546661500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1720321200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1712989200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 1969369200 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 1929918960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3346419900720 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3346419900720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1177540520625 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1174853241090 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29708058483750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29710415746500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34237326021510 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34236880339410 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.241213 # Core power per rank (mW) -system.physmem.averagePower::1 668.232514 # Core power per rank (mW) +system.physmem.avgWrQLen 20.35 # Average write queue length when enqueuing +system.physmem.readRowHits 333517 # Number of row buffer hits during reads +system.physmem.writeRowHits 441289 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.79 # Row buffer hit rate for writes +system.physmem.avgGap 48759162.26 # Average gap between requests +system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1059231600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 575701500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1730999400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1990714320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3304502351280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1163638516455 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29573392417500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34046889932055 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.714209 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48801846776250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1689418380000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 103138521750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 1014703200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 551648625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1723542600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1937720880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3304502351280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1160546619285 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29579668954500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34049945540370 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.696345 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48806318983250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1689418380000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 98691186250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -401,6 +380,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -422,27 +409,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 113519 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 113519 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 113519 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 113519 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 113519 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 1125423795568 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.567721 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.495393 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 486496827068 43.23% 43.23% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 638926968500 56.77% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1125423795568 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 82853 84.60% 84.60% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 15081 15.40% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 97934 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 113519 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 113519 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97934 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97934 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 211453 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 78485873 # DTB read hits -system.cpu0.dtb.read_misses 85123 # DTB read misses -system.cpu0.dtb.write_hits 72027961 # DTB write hits -system.cpu0.dtb.write_misses 28205 # DTB write misses -system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 78562985 # DTB read hits +system.cpu0.dtb.read_misses 85240 # DTB read misses +system.cpu0.dtb.write_hits 72018023 # DTB write hits +system.cpu0.dtb.write_misses 28279 # DTB write misses +system.cpu0.dtb.flush_tlb 1287 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21048 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 51602 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21013 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 51639 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4002 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3776 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9811 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78570996 # DTB read accesses -system.cpu0.dtb.write_accesses 72056166 # DTB write accesses +system.cpu0.dtb.perms_faults 9794 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78648225 # DTB read accesses +system.cpu0.dtb.write_accesses 72046302 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 150513834 # DTB hits -system.cpu0.dtb.misses 113328 # DTB misses -system.cpu0.dtb.accesses 150627162 # DTB accesses +system.cpu0.dtb.hits 150581008 # DTB hits +system.cpu0.dtb.misses 113519 # DTB misses +system.cpu0.dtb.accesses 150694527 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -464,411 +480,432 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 421004293 # ITB inst hits -system.cpu0.itb.inst_misses 63363 # ITB inst misses +system.cpu0.itb.walker.walks 63212 # Table walker walks requested +system.cpu0.itb.walker.walksLong 63212 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 63212 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 63212 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 63212 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 1125423794068 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.567766 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.495387 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 486446960568 43.22% 43.22% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 638976833500 56.78% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1125423794068 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54978 95.14% 95.14% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2806 4.86% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57784 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63212 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63212 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57784 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57784 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 120996 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 421062407 # ITB inst hits +system.cpu0.itb.inst_misses 63212 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1287 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21048 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 36267 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21013 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 36180 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 421067656 # ITB inst accesses -system.cpu0.itb.hits 421004293 # DTB hits -system.cpu0.itb.misses 63363 # DTB misses -system.cpu0.itb.accesses 421067656 # DTB accesses -system.cpu0.numCycles 506516508 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 421125619 # ITB inst accesses +system.cpu0.itb.hits 421062407 # DTB hits +system.cpu0.itb.misses 63212 # DTB misses +system.cpu0.itb.accesses 421125619 # DTB accesses +system.cpu0.numCycles 506570818 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 420811760 # Number of instructions committed -system.cpu0.committedOps 495213745 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 454628715 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 411957 # Number of float alu accesses -system.cpu0.num_func_calls 25378118 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 63987651 # number of instructions that are conditional controls -system.cpu0.num_int_insts 454628715 # number of integer instructions -system.cpu0.num_fp_insts 411957 # number of float instructions -system.cpu0.num_int_register_reads 670075882 # number of times the integer registers were read -system.cpu0.num_int_register_writes 361231436 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 665979 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 343448 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 110680974 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 110422200 # number of times the CC registers were written -system.cpu0.num_mem_refs 150607491 # number of memory refs -system.cpu0.num_load_insts 78559078 # Number of load instructions -system.cpu0.num_store_insts 72048413 # Number of store instructions -system.cpu0.num_idle_cycles 494422986.191521 # Number of idle cycles -system.cpu0.num_busy_cycles 12093521.808479 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023876 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976124 # Percentage of idle cycles -system.cpu0.Branches 93934421 # Number of branches fetched +system.cpu0.committedInsts 420869800 # Number of instructions committed +system.cpu0.committedOps 495253800 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 454669961 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 407169 # Number of float alu accesses +system.cpu0.num_func_calls 25355566 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 64011433 # number of instructions that are conditional controls +system.cpu0.num_int_insts 454669961 # number of integer instructions +system.cpu0.num_fp_insts 407169 # number of float instructions +system.cpu0.num_int_register_reads 669912724 # number of times the integer registers were read +system.cpu0.num_int_register_writes 361261423 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 658306 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 339356 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 110690043 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 110438637 # number of times the CC registers were written +system.cpu0.num_mem_refs 150674741 # number of memory refs +system.cpu0.num_load_insts 78636195 # Number of load instructions +system.cpu0.num_store_insts 72038546 # Number of store instructions +system.cpu0.num_idle_cycles 494843268.961767 # Number of idle cycles +system.cpu0.num_busy_cycles 11727549.038232 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023151 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976849 # Percentage of idle cycles +system.cpu0.Branches 93932517 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 343753597 69.37% 69.37% # Class of executed instruction -system.cpu0.op_class::IntMult 1048568 0.21% 69.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 47671 0.01% 69.60% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 50027 0.01% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::MemRead 78559078 15.85% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 72048413 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 343715794 69.36% 69.36% # Class of executed instruction +system.cpu0.op_class::IntMult 1059861 0.21% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 47874 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 49044 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 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-system.cpu0.dcache.tags.sampled_refs 10204261 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.834068 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 10214702 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999720 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 304791830 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10215214 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.837048 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.228127 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.974365 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.797225 # Average occupied blocks per requestor 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# average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17154.258300 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11581.482010 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28973.297407 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36813.017170 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29327.242340 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 17614.478663 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 31245.049820 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 10656.400668 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14692.893780 # average LoadLockedReq miss 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MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 2773158 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 3896502 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1318320 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 3221462 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4539782 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10425295500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30694668987 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41119964487 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 8981852045 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24997038072 # number of WriteReq MSHR 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(read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 75098854604 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22314698045 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 64974352749 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 87289050794 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 887936500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1414128501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2302065001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 802092250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1441281461 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2243373711 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1690028750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2855409962 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4545438712 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032284 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031796 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017219 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015013 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013530 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007316 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.768833 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.752492 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.385346 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.726609 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.719371 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.304444 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056805 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.061626 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031219 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 202999 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19410768882 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 55596137872 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 75006906754 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22377765382 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 64782643827 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 87160409209 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 886387500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1429299000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2315686500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 799886500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1453115957 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2253002457 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1686274000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2882414957 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4568688957 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032229 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031863 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017233 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015263 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013430 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007324 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.772612 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.750803 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.386644 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.728409 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.721153 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.306997 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054833 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.062149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031161 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024105 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023439 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.012573 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028135 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027092 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.014570 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13163.135553 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15040.390210 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14515.543148 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27107.905380 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34133.011724 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31944.684550 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14912.350751 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20706.140677 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18950.062477 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15658.567201 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29165.855970 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25226.679048 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12226.372215 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12637.002899 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12522.889240 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024189 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023419 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.012583 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028342 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027034 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.014585 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13174.512020 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15018.399262 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14506.104274 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26840.685559 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34004.539272 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31745.347553 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14804.559131 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20646.617420 # average SoftPFReq mshr miss latency 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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13999.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33749.833333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17276.228426 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20082.414006 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19273.403325 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16926.617244 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20169.212845 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19227.586433 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss 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(read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 23501092750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 67935136085 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 91436228835 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012600 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012600 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015312 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083285 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012600 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.850868 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.850868 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11384.489500 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11672.170324 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.850868 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 421946 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 421946 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 421946 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 421946 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 421946 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 421946 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2066459 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5847297 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 7913756 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 2066459 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 5847297 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 7913756 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 2066459 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 5847297 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 7913756 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 23615838750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 68291553899 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 91907392649 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 23615838750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 68291553899 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 91907392649 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 23615838750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 68291553899 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 91907392649 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015337 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083401 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012642 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015337 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083401 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012642 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015337 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083401 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012642 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11613.624763 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11613.624763 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11613.624763 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1037,27 +1082,80 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 39379 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 39379 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 5977 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 28234 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 39373 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.279379 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 55.436197 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-1023 39372 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::10240-11263 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 39373 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 34217 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21462.701289 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17640.355852 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13201.639709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 33415 97.66% 97.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 571 1.67% 99.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 171 0.50% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 26 0.08% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 5 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 6 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 6 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 34217 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1508431008 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.298098 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.457423 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1058770000 70.19% 70.19% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 449661008 29.81% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1508431008 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 28234 82.53% 82.53% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 5977 17.47% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 34211 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 39379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 39379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 34211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 34211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 73590 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25401715 # DTB read hits -system.cpu1.dtb.read_misses 30145 # DTB read misses -system.cpu1.dtb.write_hits 22878884 # DTB write hits -system.cpu1.dtb.write_misses 9290 # DTB write misses -system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25323699 # DTB read hits +system.cpu1.dtb.read_misses 30085 # DTB read misses +system.cpu1.dtb.write_hits 22831654 # DTB write hits +system.cpu1.dtb.write_misses 9294 # DTB write misses +system.cpu1.dtb.flush_tlb 1278 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 6765 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 155 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 21663 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 6693 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 149 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 21869 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1295 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1270 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 3011 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25431860 # DTB read accesses -system.cpu1.dtb.write_accesses 22888174 # DTB write accesses +system.cpu1.dtb.perms_faults 3016 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25353784 # DTB read accesses +system.cpu1.dtb.write_accesses 22840948 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 48280599 # DTB hits -system.cpu1.dtb.misses 39435 # DTB misses -system.cpu1.dtb.accesses 48320034 # DTB accesses +system.cpu1.dtb.hits 48155353 # DTB hits +system.cpu1.dtb.misses 39379 # DTB misses +system.cpu1.dtb.accesses 48194732 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1079,98 +1177,143 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 134812630 # ITB inst hits -system.cpu1.itb.inst_misses 23831 # ITB inst misses +system.cpu1.itb.walker.walks 23659 # Table walker walks requested +system.cpu1.itb.walker.walksLong 23659 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1141 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20683 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 23659 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 23659 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 23659 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 21824 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24542.418897 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21182.327207 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14187.388293 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 20284 92.94% 92.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 1308 5.99% 98.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 160 0.73% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 37 0.17% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 9 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 7 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 21824 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 20683 94.77% 94.77% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1141 5.23% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 21824 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23659 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23659 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 21824 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 21824 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 45483 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 134740091 # ITB inst hits +system.cpu1.itb.inst_misses 23659 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1278 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 6765 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 155 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 16095 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 6693 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 149 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 16092 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 134836461 # ITB inst accesses -system.cpu1.itb.hits 134812630 # DTB hits -system.cpu1.itb.misses 23831 # DTB misses -system.cpu1.itb.accesses 134836461 # DTB accesses -system.cpu1.numCycles 1276129163 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 134763750 # ITB inst accesses +system.cpu1.itb.hits 134740091 # DTB hits +system.cpu1.itb.misses 23659 # DTB misses +system.cpu1.itb.accesses 134763750 # DTB accesses +system.cpu1.numCycles 1278124825 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 134717323 # Number of instructions committed -system.cpu1.committedOps 158229449 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 145215192 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 135383 # Number of float alu accesses -system.cpu1.num_func_calls 7898602 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 20639469 # number of instructions that are conditional controls -system.cpu1.num_int_insts 145215192 # number of integer instructions -system.cpu1.num_fp_insts 135383 # number of float instructions -system.cpu1.num_int_register_reads 211626069 # number of times the integer registers were read -system.cpu1.num_int_register_writes 115298933 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 217457 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 117636 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35416182 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 35358802 # number of times the CC registers were written -system.cpu1.num_mem_refs 48278390 # number of memory refs -system.cpu1.num_load_insts 25401257 # Number of load instructions -system.cpu1.num_store_insts 22877133 # Number of store instructions -system.cpu1.num_idle_cycles 1248602360.762588 # Number of idle cycles -system.cpu1.num_busy_cycles 27526802.237412 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021571 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978429 # Percentage of idle cycles -system.cpu1.Branches 30073331 # Number of branches fetched +system.cpu1.committedInsts 134646225 # Number of instructions committed +system.cpu1.committedOps 158126706 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 145069492 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 137737 # Number of float alu accesses +system.cpu1.num_func_calls 7885244 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 20644863 # number of instructions that are conditional controls +system.cpu1.num_int_insts 145069492 # number of integer instructions +system.cpu1.num_fp_insts 137737 # number of float instructions +system.cpu1.num_int_register_reads 212132646 # number of times the integer registers were read +system.cpu1.num_int_register_writes 115229722 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 221669 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 118820 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 35576682 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 35511484 # number of times the CC registers were written +system.cpu1.num_mem_refs 48152949 # number of memory refs +system.cpu1.num_load_insts 25322940 # Number of load instructions +system.cpu1.num_store_insts 22830009 # Number of store instructions +system.cpu1.num_idle_cycles 1251340382.439470 # Number of idle cycles +system.cpu1.num_busy_cycles 26784442.560530 # Number of busy cycles +system.cpu1.not_idle_fraction 0.020956 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.979044 # Percentage of idle cycles +system.cpu1.Branches 30070128 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 109658909 69.26% 69.26% # Class of executed instruction -system.cpu1.op_class::IntMult 355788 0.22% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 13920 0.01% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 17708 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::MemRead 25401257 16.04% 85.55% # Class of executed instruction -system.cpu1.op_class::MemWrite 22877133 14.45% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 109684380 69.32% 69.32% # Class of executed instruction +system.cpu1.op_class::IntMult 350403 0.22% 69.55% # Class of executed instruction +system.cpu1.op_class::IntDiv 14329 0.01% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 18470 0.01% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu1.op_class::MemRead 25322940 16.00% 85.57% # Class of executed instruction +system.cpu1.op_class::MemWrite 22830009 14.43% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 158324756 # Class of executed instruction +system.cpu1.op_class::total 158220572 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 96972708 # Number of BP lookups -system.cpu2.branchPred.condPredicted 66097998 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 4361259 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 65994487 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 47080178 # Number of BTB hits +system.cpu2.branchPred.lookups 97203672 # Number of BP lookups +system.cpu2.branchPred.condPredicted 66186757 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 4359750 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 65808751 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 47109720 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.339562 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 12396082 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 131444 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.585799 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 12465679 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 131865 # Number of incorrect RAS predictions. +system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1192,27 +1335,89 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.dtb.walker.walks 641865 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 641865 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11159 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 66692 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 388613 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 253252 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 1931.812977 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 11499.357470 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-65535 251854 99.45% 99.45% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-131071 1074 0.42% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::131072-196607 172 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::196608-262143 83 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::262144-327679 31 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 253252 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 288612 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 20860.236245 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 16529.214515 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 15237.417207 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 285772 99.02% 99.02% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-131071 2386 0.83% 99.84% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 259 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 137 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 41 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 288612 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 644386966916 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.557890 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.603276 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-3 643756648416 99.90% 99.90% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-7 358289000 0.06% 99.96% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-11 119891000 0.02% 99.98% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-15 74898000 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-19 28944500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-23 14290500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-27 13699500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-31 16934500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::32-35 3107500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::36-39 253000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::40-43 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 644386966916 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 66692 85.67% 85.67% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 11159 14.33% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 77851 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 641865 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 641865 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 77851 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 77851 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 719716 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 77639620 # DTB read hits -system.cpu2.dtb.read_misses 447330 # DTB read misses -system.cpu2.dtb.write_hits 59480935 # DTB write hits -system.cpu2.dtb.write_misses 199454 # DTB write misses -system.cpu2.dtb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 77755602 # DTB read hits +system.cpu2.dtb.read_misses 445998 # DTB read misses +system.cpu2.dtb.write_hits 59736492 # DTB write hits +system.cpu2.dtb.write_misses 195867 # DTB write misses +system.cpu2.dtb.flush_tlb 1279 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 14382 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 391 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 38430 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 78 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 6154 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 14489 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 395 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 38251 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 105 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 6104 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 38837 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 78086950 # DTB read accesses -system.cpu2.dtb.write_accesses 59680389 # DTB write accesses +system.cpu2.dtb.perms_faults 37697 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 78201600 # DTB read accesses +system.cpu2.dtb.write_accesses 59932359 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 137120555 # DTB hits -system.cpu2.dtb.misses 646784 # DTB misses -system.cpu2.dtb.accesses 137767339 # DTB accesses +system.cpu2.dtb.hits 137492094 # DTB hits +system.cpu2.dtb.misses 641865 # DTB misses +system.cpu2.dtb.accesses 138133959 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1234,161 +1439,221 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 70053409 # ITB inst hits -system.cpu2.itb.inst_misses 78615 # ITB inst misses +system.cpu2.itb.walker.walks 80363 # Table walker walks requested +system.cpu2.itb.walker.walksLong 80363 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2481 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 55642 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 10291 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 70072 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1335.283708 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 8007.621087 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-32767 69580 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-65535 258 0.37% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-98303 168 0.24% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::98304-131071 29 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::131072-163839 18 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 70072 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 68414 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 25615.416172 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 21446.317164 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 15929.809681 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 60316 88.16% 88.16% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 7055 10.31% 98.48% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 610 0.89% 99.37% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 277 0.40% 99.77% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 68 0.10% 99.87% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 37 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 13 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 11 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 68414 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 468293315780 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.887572 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.316276 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 52695891356 11.25% 11.25% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 415558218424 88.74% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 33808000 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 3984500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 940500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 404000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::6 21500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::7 47500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 468293315780 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 55642 95.73% 95.73% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 2481 4.27% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 58123 # Table walker page sizes translated +system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 80363 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 80363 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 58123 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 58123 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 138486 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70281222 # ITB inst hits +system.cpu2.itb.inst_misses 80363 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1279 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 14382 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 391 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 29938 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 14489 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 395 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 29841 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 146701 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 147172 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70132024 # ITB inst accesses -system.cpu2.itb.hits 70053409 # DTB hits -system.cpu2.itb.misses 78615 # DTB misses -system.cpu2.itb.accesses 70132024 # DTB accesses -system.cpu2.numCycles 464363800 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70361585 # ITB inst accesses +system.cpu2.itb.hits 70281222 # DTB hits +system.cpu2.itb.misses 80363 # DTB misses +system.cpu2.itb.accesses 70361585 # DTB accesses +system.cpu2.numCycles 465003102 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 179489584 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 430854602 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 96972708 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 59476260 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 257591256 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 9826419 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 1844126 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 7503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 2868 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 3763568 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 118840 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 3975 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 69883749 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 2672352 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 30337 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 447734787 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.124399 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.366335 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 180276648 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 431826640 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 97203672 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 59575399 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 257301281 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 9838745 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 1858453 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 8409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1979 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 3769521 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 119476 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 4195 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 70111000 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 2676908 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 31653 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 448259178 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.125687 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.367693 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 341635028 76.30% 76.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 13406310 2.99% 79.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 13636635 3.05% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 9872032 2.20% 84.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 19981367 4.46% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 6599798 1.47% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 7144304 1.60% 92.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 6328128 1.41% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 29131185 6.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 341932387 76.28% 76.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 13442109 3.00% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 13673824 3.05% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 9898176 2.21% 84.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 19945540 4.45% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 6633561 1.48% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 7181223 1.60% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 6340938 1.41% 93.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 29211420 6.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 447734787 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.208829 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.927838 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 146627317 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 209331987 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 78382912 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 9473245 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 3917341 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 14361500 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 1009950 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 470418171 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 3106090 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 3917341 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 152067726 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18239112 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 166025180 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82266415 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 25216691 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 459074168 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 65027 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 1852942 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 1258209 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 11783264 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 3675 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 439034296 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 699577887 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 541505861 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 695779 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 366271083 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 72763213 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 10011965 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 8575733 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 52414102 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 74518711 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 62619461 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 9405778 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 10283621 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 436211457 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 9985811 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 434881060 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 606856 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 56709441 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 39627449 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 236091 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 447734787 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.971292 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.683506 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 448259178 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.209039 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.928653 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 147221492 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 209051737 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 78610938 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 9453516 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 3919439 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 14421531 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 1013878 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 471467563 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 3120361 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 3919439 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 152659562 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 18224952 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 165892682 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82476717 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 25083567 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 460107253 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 59923 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 1862817 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 1245864 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 11710592 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 3796 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 439693345 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 700325975 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 542687716 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 700561 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 367082877 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 72610468 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 9962331 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 8523572 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 52244758 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 74674759 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 62877107 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 9528051 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 10323504 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 437324992 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 9951593 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 435965427 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 606984 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 56598171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 39504404 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 237598 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 448259178 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.972574 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.684760 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 279611354 62.45% 62.45% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 68418670 15.28% 77.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 31957007 7.14% 84.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22824194 5.10% 89.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 17260103 3.85% 93.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 11876528 2.65% 96.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 7949958 1.78% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 4742790 1.06% 99.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 3094183 0.69% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 279914977 62.44% 62.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 68317821 15.24% 77.69% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 32057682 7.15% 84.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 22901153 5.11% 89.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 17277675 3.85% 93.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 11955785 2.67% 96.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 7990147 1.78% 98.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 4753228 1.06% 99.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 3090710 0.69% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 447734787 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 448259178 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2194515 25.29% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 17472 0.20% 25.49% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 1369 0.02% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 1 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.50% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 3568581 41.12% 66.62% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 2897037 33.38% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2208249 25.46% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 17979 0.21% 25.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 1386 0.02% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 1 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 3543832 40.86% 66.55% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 2901485 33.45% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 294218561 67.65% 67.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 1060208 0.24% 67.90% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 49487 0.01% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 203 0.00% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 294954302 67.66% 67.66% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 1046783 0.24% 67.90% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49286 0.01% 67.91% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 204 0.00% 67.91% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.91% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.91% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.91% # Type of FU issued @@ -1410,156 +1675,156 @@ system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Ty system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 49890 0.01% 67.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 50291 0.01% 67.92% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 79213886 18.22% 86.14% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 60288825 13.86% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 79323839 18.19% 86.11% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 60540722 13.89% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 434881060 # Type of FU issued -system.cpu2.iq.rate 0.936509 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 8678975 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.019957 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 1325952907 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 503003259 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 418204813 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 829831 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 395434 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 359511 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 443116084 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 443951 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 3398365 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 435965427 # Type of FU issued +system.cpu2.iq.rate 0.937554 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 8672932 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.019894 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 1328634186 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 503978442 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 419353037 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 835762 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 397688 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 361980 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 444191291 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 447068 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 3425545 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 12383710 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 15996 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 500564 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 6611339 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 12352202 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 15972 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 509888 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 6626020 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 2691934 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 6258076 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 2713782 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 6189069 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 3917341 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10960428 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 5883186 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 446296417 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 1350381 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 74518711 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 62619461 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 8384922 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 176072 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 5630257 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 500564 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 2018361 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1727301 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3745662 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 429773841 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77626990 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 4469356 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 3919439 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10963120 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 5851568 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 447374999 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 1338773 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 74674759 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 62877107 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 8331773 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 175433 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 5598830 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 509888 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 2010429 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1729641 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3740070 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 430866261 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77742862 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 4466264 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 99149 # number of nop insts executed -system.cpu2.iew.exec_refs 137107534 # number of memory reference insts executed -system.cpu2.iew.exec_branches 79765421 # Number of branches executed -system.cpu2.iew.exec_stores 59480544 # Number of stores executed -system.cpu2.iew.exec_rate 0.925511 # Inst execution rate -system.cpu2.iew.wb_sent 419443427 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 418564324 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 206922501 # num instructions producing a value -system.cpu2.iew.wb_consumers 359375214 # num instructions consuming a value +system.cpu2.iew.exec_nop 98414 # number of nop insts executed +system.cpu2.iew.exec_refs 137478821 # number of memory reference insts executed +system.cpu2.iew.exec_branches 79993995 # Number of branches executed +system.cpu2.iew.exec_stores 59735959 # Number of stores executed +system.cpu2.iew.exec_rate 0.926588 # Inst execution rate +system.cpu2.iew.wb_sent 420591447 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 419715017 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 207428552 # num instructions producing a value +system.cpu2.iew.wb_consumers 360230847 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.901372 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575784 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.902607 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575821 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 60955622 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9749720 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 3365248 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 437429844 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.880802 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.877626 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 60870503 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9713995 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 3359660 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 437963055 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.882384 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.879484 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 298552711 68.25% 68.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 66327454 15.16% 83.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 24603217 5.62% 89.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 11085486 2.53% 91.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 7951378 1.82% 93.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 4924801 1.13% 94.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 4385642 1.00% 95.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 3037837 0.69% 96.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 16561318 3.79% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 298875540 68.24% 68.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 66218430 15.12% 83.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 24721461 5.64% 89.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 11149325 2.55% 91.55% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 8001884 1.83% 93.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 4923567 1.12% 94.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 4422174 1.01% 95.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 3021510 0.69% 96.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 16629164 3.80% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 437429844 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 328410291 # Number of instructions committed -system.cpu2.commit.committedOps 385289118 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 437963055 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 329380138 # Number of instructions committed +system.cpu2.commit.committedOps 386451624 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 118143123 # Number of memory references committed -system.cpu2.commit.loads 62135001 # Number of loads committed -system.cpu2.commit.membars 2566531 # Number of memory barriers committed -system.cpu2.commit.branches 73369628 # Number of branches committed -system.cpu2.commit.fp_insts 345769 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 353907438 # Number of committed integer instructions. -system.cpu2.commit.function_calls 9528374 # Number of function calls committed. +system.cpu2.commit.refs 118573644 # Number of memory references committed +system.cpu2.commit.loads 62322557 # Number of loads committed +system.cpu2.commit.membars 2596368 # Number of memory barriers committed +system.cpu2.commit.branches 73601182 # Number of branches committed +system.cpu2.commit.fp_insts 348235 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 355043998 # Number of committed integer instructions. +system.cpu2.commit.function_calls 9589619 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 266264239 69.11% 69.11% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 801904 0.21% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 36966 0.01% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 42886 0.01% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 62135001 16.13% 85.46% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 56008122 14.54% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 267002089 69.09% 69.09% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 796041 0.21% 69.30% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 36743 0.01% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 43107 0.01% 69.32% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 62322557 16.13% 85.44% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 56251087 14.56% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 385289118 # Class of committed instruction -system.cpu2.commit.bw_lim_events 16561318 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 386451624 # Class of committed instruction +system.cpu2.commit.bw_lim_events 16629164 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 864512984 # The number of ROB reads -system.cpu2.rob.rob_writes 902807617 # The number of ROB writes -system.cpu2.timesIdled 2960923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 16629013 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 99452987332 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 328410291 # Number of Instructions Simulated -system.cpu2.committedOps 385289118 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.413975 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.413975 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.707226 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.707226 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 505452117 # number of integer regfile reads -system.cpu2.int_regfile_writes 299365113 # number of integer regfile writes -system.cpu2.fp_regfile_reads 681432 # number of floating regfile reads -system.cpu2.fp_regfile_writes 426556 # number of floating regfile writes -system.cpu2.cc_regfile_reads 91860984 # number of cc regfile reads -system.cpu2.cc_regfile_writes 92633679 # number of cc regfile writes -system.cpu2.misc_regfile_reads 1668736685 # number of misc regfile reads -system.cpu2.misc_regfile_writes 9854923 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40323 # Transaction distribution -system.iobus.trans_dist::ReadResp 40323 # Transaction distribution +system.cpu2.rob.rob_reads 866035132 # The number of ROB reads +system.cpu2.rob.rob_writes 904953656 # The number of ROB writes +system.cpu2.timesIdled 2976137 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 16743924 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 99448354933 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 329380138 # Number of Instructions Simulated +system.cpu2.committedOps 386451624 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.411752 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.411752 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.708340 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.708340 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 506713870 # number of integer regfile reads +system.cpu2.int_regfile_writes 300217827 # number of integer regfile writes +system.cpu2.fp_regfile_reads 684649 # number of floating regfile reads +system.cpu2.fp_regfile_writes 429068 # number of floating regfile writes +system.cpu2.cc_regfile_reads 91867416 # number of cc regfile reads +system.cpu2.cc_regfile_writes 92641749 # number of cc regfile writes +system.cpu2.misc_regfile_reads 1672272175 # number of misc regfile reads +system.cpu2.misc_regfile_writes 9817116 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40335 # Transaction distribution +system.iobus.trans_dist::ReadResp 40335 # Transaction distribution system.iobus.trans_dist::WriteReq 136665 # Transaction distribution system.iobus.trans_dist::WriteResp 30001 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1579,11 +1844,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354000 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1600,18 +1865,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13663000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13687000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 7273000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 7449000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1619,67 +1884,67 @@ system.iobus.reqLayer25.occupancy 16992000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 330247943 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 331631076 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 38409000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 38629000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36054619 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36767371 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115453 # number of replacements -system.iocache.tags.tagsinuse 10.417239 # Cycle average of tags in use +system.iocache.tags.replacements 115465 # number of replacements +system.iocache.tags.tagsinuse 10.417241 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13085938891009 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13085934181009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.549977 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.867262 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.867264 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221874 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.429204 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651077 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651078 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039605 # Number of tag accesses -system.iocache.tags.data_accesses 1039605 # Number of data accesses +system.iocache.tags.tag_accesses 1039713 # Number of tag accesses +system.iocache.tags.data_accesses 1039713 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8808 # number of demand (read+write) misses -system.iocache.demand_misses::total 8848 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8820 # number of demand (read+write) misses +system.iocache.demand_misses::total 8860 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8808 # number of overall misses -system.iocache.overall_misses::total 8848 # number of overall misses +system.iocache.overall_misses::realview.ide 8820 # number of overall misses +system.iocache.overall_misses::total 8860 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 2752000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 58617716 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 61369716 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9336377608 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9336377608 # number of WriteInvalidateReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 78330160 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 81082160 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9376503545 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9376503545 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 2752000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 58617716 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 61369716 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 78330160 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 81082160 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 2752000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 58617716 # number of overall miss cycles -system.iocache.overall_miss_latency::total 61369716 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 78330160 # number of overall miss cycles +system.iocache.overall_miss_latency::total 81082160 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8808 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8848 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8820 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8860 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8808 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8848 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8820 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8860 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1694,414 +1959,415 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 6655.054042 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 6938.351159 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87530.728343 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 87530.728343 # average WriteInvalidateReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 8880.970522 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 9154.585074 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87906.918407 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 87906.918407 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 6655.054042 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 6935.998644 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 8880.970522 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 9151.485327 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 6655.054042 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 6935.998644 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56930 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 8880.970522 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 9151.485327 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 58174 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7229 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7340 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.875225 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.925613 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 391 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 407 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 34376 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 34376 # number of WriteInvalidateReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 459 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 34504 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 34504 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 391 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 407 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 459 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 391 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 407 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 459 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 475 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1920000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 38284716 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 40204716 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7548587846 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7548587846 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 54458660 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 56378660 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7582053787 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7582053787 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 1920000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 38284716 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 40204716 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 54458660 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 56378660 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 1920000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 38284716 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 40204716 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 54458660 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 56378660 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.046015 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.322283 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.322283 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.053630 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.323483 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.323483 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.045999 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.053612 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.044391 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.045999 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.053612 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 120000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 97914.874680 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98783.085995 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219588.894752 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219588.894752 # average WriteInvalidateReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 118646.318083 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 118691.915789 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219744.197397 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219744.197397 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 97914.874680 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 98783.085995 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 118646.318083 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 118691.915789 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 97914.874680 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 98783.085995 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 118646.318083 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 118691.915789 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1295349 # number of replacements -system.l2c.tags.tagsinuse 65279.372199 # Cycle average of tags in use -system.l2c.tags.total_refs 28812912 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1358291 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.212621 # Average number of references to valid blocks. +system.l2c.tags.replacements 1296056 # number of replacements +system.l2c.tags.tagsinuse 65324.265743 # Cycle average of tags in use +system.l2c.tags.total_refs 28829950 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1358778 # Sample count of references to valid blocks. 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requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 115.755562 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 187.843721 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2139.828130 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 8959.798251 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.567043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003694 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.058955 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.128566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000805 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001206 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.013099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.046189 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001766 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.002866 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032651 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.136716 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996084 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62643 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 299 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id 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of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001154 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.016275 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.047841 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001791 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.002808 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032656 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.135371 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996769 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 311 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62411 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 310 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4926 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54001 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004745 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.952316 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 273473120 # Number of tag accesses +system.l2c.tags.data_accesses 273473120 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 199000 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 127150 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 6565279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3138242 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 69576 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 49228 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 2053777 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 983926 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 389952 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 151346 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 5813280 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 2472232 # number of ReadReq hits +system.l2c.ReadReq_hits::total 22012988 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7876656 # number of Writeback hits +system.l2c.Writeback_hits::total 7876656 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 347388 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 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UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.401614 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.239097 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.233358 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.116541 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008094 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009528 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005424 # mshr miss rate for demand accesses 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009390 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005710 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.084150 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.018006 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61294.498526 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63316.887276 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66080.983690 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 74343.104475 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 69935.784042 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20452.168530 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 27030.577817 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 25080.741367 # average WriteInvalidateReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.234895 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.235279 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.116851 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007702 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006137 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.085113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.009132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005797 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.084268 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.018101 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007702 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006137 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.085113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005797 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.084268 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.018101 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63444.451824 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73925.270446 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 69662.173862 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20456.882185 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 26943.763266 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 25030.403741 # average WriteInvalidateReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10007.846988 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.737540 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10004.602396 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.512234 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60250 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 43500.333333 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61497.517450 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 83774.518321 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76744.769232 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61294.498526 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62092.053730 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66080.983690 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 80060.763927 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 73729.815854 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65563.581315 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66299.582463 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61294.498526 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62092.053730 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66409.367989 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 71380.892329 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66080.983690 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 80060.763927 # average overall mshr miss latency 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69117.382796 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 79214.264043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 73157.282017 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62052.824983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 79214.264043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 73157.282017 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2299,57 +2565,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 464434 # Transaction distribution -system.membus.trans_dist::ReadResp 464434 # Transaction distribution +system.membus.trans_dist::ReadReq 464425 # Transaction distribution +system.membus.trans_dist::ReadResp 464425 # Transaction distribution system.membus.trans_dist::WriteReq 33772 # Transaction distribution system.membus.trans_dist::WriteResp 33772 # Transaction distribution -system.membus.trans_dist::Writeback 1204397 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 613284 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 613284 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36382 # Transaction distribution +system.membus.trans_dist::Writeback 1204773 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 613884 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 613884 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36393 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36386 # Transaction distribution -system.membus.trans_dist::ReadExReq 502275 # Transaction distribution -system.membus.trans_dist::ReadExResp 502275 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36397 # Transaction distribution +system.membus.trans_dist::ReadExReq 501696 # Transaction distribution +system.membus.trans_dist::ReadExResp 501696 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4037051 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4166813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337307 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337307 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4504120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4037435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4167195 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337326 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337326 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4504521 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156082 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159247392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 159417170 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14194688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14194688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173611858 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 579 # Total snoops (count) -system.membus.snoop_fanout::samples 2743991 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159270496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159440210 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14195136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14195136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173635346 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 600 # Total snoops (count) +system.membus.snoop_fanout::samples 2744389 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2743991 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2744389 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2743991 # Request fanout histogram -system.membus.reqLayer0.occupancy 42257500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2744389 # Request fanout histogram +system.membus.reqLayer0.occupancy 42480999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1290500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1323000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6097591000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6141947499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4309666748 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4337026701 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 38158381 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38901629 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2393,55 +2657,55 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 22879889 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 22879700 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 22911195 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22910936 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7869277 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1265786 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1231410 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45609 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7876656 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1266229 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1231725 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45591 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2107606 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2107606 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29099470 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28504181 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 848529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1761011 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 60213191 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 928591700 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1156912126 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3110208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6320128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2094934162 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 368424 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 34177702 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003380 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.058037 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 45598 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2107463 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2107463 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29129582 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28533410 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 850957 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760816 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 60274765 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 929555284 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1158084670 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3113192 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6291728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2097044874 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 377016 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 34216462 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003376 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.058008 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 34062190 99.66% 99.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115512 0.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 34100938 99.66% 99.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115524 0.34% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 34177702 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 26362663917 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 34216462 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 26470973727 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 981000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 972000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 35502866905 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 35634626823 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 21222039348 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 21264279204 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 273701566 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 276240027 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 651522269 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 654460701 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index cd3f04231..726dee18b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.358466 # Number of seconds simulated -sim_ticks 51358465585500 # Number of ticks simulated -final_tick 51358465585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.358448 # Number of seconds simulated +sim_ticks 51358448410500 # Number of ticks simulated +final_tick 51358448410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124397 # Simulator instruction rate (inst/s) -host_op_rate 146176 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7088870517 # Simulator tick rate (ticks/s) -host_mem_usage 677952 # Number of bytes of host memory used -host_seconds 7244.94 # Real time elapsed on the host -sim_insts 901249371 # Number of instructions simulated -sim_ops 1059038863 # Number of ops (including micro ops) simulated +host_inst_rate 129809 # Simulator instruction rate (inst/s) +host_op_rate 152542 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7366025588 # Simulator tick rate (ticks/s) +host_mem_usage 732256 # Number of bytes of host memory used +host_seconds 6972.34 # Real time elapsed on the host +sim_insts 905073903 # Number of instructions simulated +sim_ops 1063573170 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 144192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 134400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3960256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 28248856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 172736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 160128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3375488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 26920496 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 423040 # Number of bytes read from this memory -system.physmem.bytes_read::total 63539592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3960256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3375488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7335744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 82068736 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 167040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 151040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3952000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 28582936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 161216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 144320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3546944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 27869040 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 401920 # Number of bytes read from this memory +system.physmem.bytes_read::total 64976456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3952000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3546944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7498944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83152960 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 82089316 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2253 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 61879 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 441396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2502 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 52742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 420638 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6610 # Number of read requests responded to by this memory -system.physmem.num_reads::total 992819 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1282324 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83173540 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 61750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 446616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2255 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 55421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 435459 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6280 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1015270 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1299265 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1284897 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 77110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 550033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 65724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 524169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1237179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 77110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 65724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 142834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1597959 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1301838 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 76949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 556538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 69063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 542638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1265156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 76949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 69063 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 146012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1619071 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1598360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1597959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 77110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 550434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 65724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 524169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2835539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 992819 # Number of read requests accepted -system.physmem.writeReqs 1909642 # Number of write requests accepted -system.physmem.readBursts 992819 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1909642 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 63506944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue -system.physmem.bytesWritten 121761344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 63539592 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 122072996 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7111 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 37069 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 60948 # Per bank write bursts -system.physmem.perBankRdBursts::1 60211 # Per bank write bursts -system.physmem.perBankRdBursts::2 58469 # Per bank write bursts -system.physmem.perBankRdBursts::3 57182 # Per bank write bursts -system.physmem.perBankRdBursts::4 59427 # Per bank write bursts -system.physmem.perBankRdBursts::5 69894 # Per bank write bursts -system.physmem.perBankRdBursts::6 60719 # Per bank write bursts -system.physmem.perBankRdBursts::7 60135 # Per bank write bursts -system.physmem.perBankRdBursts::8 57063 # Per bank write bursts -system.physmem.perBankRdBursts::9 84498 # Per bank write bursts -system.physmem.perBankRdBursts::10 60252 # Per bank write bursts -system.physmem.perBankRdBursts::11 64911 # Per bank write bursts -system.physmem.perBankRdBursts::12 58664 # Per bank write bursts -system.physmem.perBankRdBursts::13 62105 # Per bank write bursts -system.physmem.perBankRdBursts::14 58293 # Per bank write bursts -system.physmem.perBankRdBursts::15 59525 # Per bank write bursts -system.physmem.perBankWrBursts::0 119395 # Per bank write bursts -system.physmem.perBankWrBursts::1 117730 # Per bank write bursts -system.physmem.perBankWrBursts::2 117506 # Per bank write bursts -system.physmem.perBankWrBursts::3 117615 # Per bank write bursts -system.physmem.perBankWrBursts::4 116969 # Per bank write bursts -system.physmem.perBankWrBursts::5 124824 # Per bank write bursts -system.physmem.perBankWrBursts::6 116994 # Per bank write bursts -system.physmem.perBankWrBursts::7 119672 # Per bank write bursts -system.physmem.perBankWrBursts::8 117205 # Per bank write bursts -system.physmem.perBankWrBursts::9 123532 # Per bank write bursts -system.physmem.perBankWrBursts::10 118074 # Per bank write bursts -system.physmem.perBankWrBursts::11 121555 # Per bank write bursts -system.physmem.perBankWrBursts::12 115761 # Per bank write bursts -system.physmem.perBankWrBursts::13 122535 # Per bank write bursts -system.physmem.perBankWrBursts::14 116498 # Per bank write bursts -system.physmem.perBankWrBursts::15 116656 # Per bank write bursts +system.physmem.bw_write::total 1619471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1619071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 76949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 556939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 69063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 542638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2884628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1015270 # Number of read requests accepted +system.physmem.writeReqs 1929008 # Number of write requests accepted +system.physmem.readBursts 1015270 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1929008 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 64941248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36032 # Total number of bytes read from write queue +system.physmem.bytesWritten 123000896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 64976456 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 123312420 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 563 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7116 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 37405 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 61592 # Per bank write bursts +system.physmem.perBankRdBursts::1 63105 # Per bank write bursts +system.physmem.perBankRdBursts::2 59504 # Per bank write bursts +system.physmem.perBankRdBursts::3 58627 # Per bank write bursts +system.physmem.perBankRdBursts::4 63182 # Per bank write bursts +system.physmem.perBankRdBursts::5 72471 # Per bank write bursts +system.physmem.perBankRdBursts::6 63664 # Per bank write bursts +system.physmem.perBankRdBursts::7 61386 # Per bank write bursts +system.physmem.perBankRdBursts::8 55404 # Per bank write bursts +system.physmem.perBankRdBursts::9 84358 # Per bank write bursts +system.physmem.perBankRdBursts::10 61903 # Per bank write bursts +system.physmem.perBankRdBursts::11 68457 # Per bank write bursts +system.physmem.perBankRdBursts::12 58658 # Per bank write bursts +system.physmem.perBankRdBursts::13 64087 # Per bank write bursts +system.physmem.perBankRdBursts::14 58698 # Per bank write bursts +system.physmem.perBankRdBursts::15 59611 # Per bank write bursts +system.physmem.perBankWrBursts::0 118843 # Per bank write bursts +system.physmem.perBankWrBursts::1 118980 # Per bank write bursts +system.physmem.perBankWrBursts::2 119959 # Per bank write bursts +system.physmem.perBankWrBursts::3 120276 # Per bank write bursts +system.physmem.perBankWrBursts::4 119980 # Per bank write bursts +system.physmem.perBankWrBursts::5 124689 # Per bank write bursts +system.physmem.perBankWrBursts::6 121042 # Per bank write bursts +system.physmem.perBankWrBursts::7 120315 # Per bank write bursts +system.physmem.perBankWrBursts::8 116178 # Per bank write bursts +system.physmem.perBankWrBursts::9 121715 # Per bank write bursts +system.physmem.perBankWrBursts::10 120153 # Per bank write bursts +system.physmem.perBankWrBursts::11 124890 # Per bank write bursts +system.physmem.perBankWrBursts::12 118317 # Per bank write bursts +system.physmem.perBankWrBursts::13 123673 # Per bank write bursts +system.physmem.perBankWrBursts::14 117041 # Per bank write bursts +system.physmem.perBankWrBursts::15 115838 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 94 # Number of times write queue was full causing retry -system.physmem.totGap 51358464467000 # Total gap between requests +system.physmem.numWrRetry 47 # Number of times write queue was full causing retry +system.physmem.totGap 51358447292000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 992804 # Read request sizes (log2) +system.physmem.readPktSize::6 1015255 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1907069 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 594810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 261742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 92458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 111 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1926435 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 609091 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 267826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 93793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 40314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -162,207 +162,211 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 38063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 69896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 79199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 93003 # What write queue length does an incoming req see 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90503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 89684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 85602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 2077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 225 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 619163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 299.223151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 170.216009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.259099 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 254617 41.12% 41.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146485 23.66% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55354 8.94% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28104 4.54% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20475 3.31% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12983 2.10% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10576 1.71% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9506 1.54% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 81063 13.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 619163 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 77925 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.733693 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 58.402560 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 77917 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 758 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 633988 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.443718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.837628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.480307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 262069 41.34% 41.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 150940 23.81% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56528 8.92% 74.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28800 4.54% 78.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20482 3.23% 81.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13112 2.07% 83.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10788 1.70% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9843 1.55% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 81426 12.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 633988 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 79397 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.779954 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 57.830581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 79390 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 77925 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 77925 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.414771 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.404795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.389828 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 83 0.11% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 12 0.02% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 10 0.01% 0.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 84 0.11% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 52239 67.04% 67.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2830 3.63% 70.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 709 0.91% 71.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6561 8.42% 80.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7338 9.42% 89.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1031 1.32% 90.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1085 1.39% 92.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1174 1.51% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 800 1.03% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 285 0.37% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 381 0.49% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 214 0.27% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 366 0.47% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 298 0.38% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 251 0.32% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 217 0.28% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 385 0.49% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 175 0.22% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 111 0.14% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 109 0.14% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 293 0.38% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 79 0.10% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 56 0.07% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 98 0.13% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 168 0.22% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 47 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 31 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 43 0.06% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 108 0.14% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 28 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 23 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 23 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 29 0.04% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 14 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 15 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 12 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 14 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 22 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 10 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 7 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 16 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 7 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 79397 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 79397 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.206066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.327441 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 16.891492 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 78 0.10% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 11 0.01% 0.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.01% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 74 0.09% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 53395 67.25% 67.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2838 3.57% 71.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 719 0.91% 71.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 6583 8.29% 80.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7477 9.42% 89.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1320 1.66% 91.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1452 1.83% 93.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 838 1.06% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 841 1.06% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 314 0.40% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 349 0.44% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 180 0.23% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 342 0.43% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 280 0.35% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 234 0.29% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 238 0.30% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 362 0.46% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 134 0.17% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 99 0.12% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 90 0.11% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 295 0.37% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 94 0.12% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 72 0.09% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 132 0.17% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 106 0.13% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 42 0.05% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 41 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 32 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 104 0.13% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 22 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 10 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 15 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 22 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 21 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 15 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 11 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 20 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 17 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 9 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 9 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 3 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::228-231 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::244-247 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::248-251 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 77925 # Writes before turning the bus around for reads -system.physmem.totQLat 27174725250 # Total ticks spent queuing -system.physmem.totMemAccLat 45780275250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4961480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27385.70 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 79397 # Writes before turning the bus around for reads +system.physmem.totQLat 27026112263 # Total ticks spent queuing +system.physmem.totMemAccLat 46051868513 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5073535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26634.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46135.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.37 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45384.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.84 # Average write queue length when enqueuing -system.physmem.readRowHits 765740 # Number of row buffer hits during reads -system.physmem.writeRowHits 1509913 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.36 # Row buffer hit rate for writes -system.physmem.avgGap 17694799.16 # Average gap between requests -system.physmem.pageHitRate 78.61 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49399135941008 # Time in different power states -system.physmem.memoryStateTime::REF 1714971960000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 244357347492 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2363029200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2317843080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1289351250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1264696125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3798436200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3941425800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6160568400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 6167767680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3354485153760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3354485153760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1233743623290 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1233089726130 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29732846799750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29733420393750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34334686961850 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34334687006325 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.530261 # Core power per rank (mW) -system.physmem.averagePower::1 668.530262 # Core power per rank (mW) +system.physmem.avgWrQLen 10.31 # Average write queue length when enqueuing +system.physmem.readRowHits 781715 # Number of row buffer hits during reads +system.physmem.writeRowHits 1520891 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes +system.physmem.avgGap 17443477.58 # Average gap between requests +system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2437517880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1329994875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3927541800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6247264320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3354484136640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1237564295100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29729485998000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34335476748615 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.545842 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49457442122001 # Time in different power states +system.physmem_0.memoryStateTime::REF 1714971440000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 186034306749 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2355431400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1285205625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3987126000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6206576400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3354484136640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1235795450580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29731037607750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34335151534395 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.539510 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49460023829001 # Time in different power states +system.physmem_1.memoryStateTime::REF 1714971440000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 183452804499 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory @@ -391,16 +395,24 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131952150 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89649773 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5822015 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 90992883 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 64634149 # Number of BTB hits +system.cpu0.branchPred.lookups 134182977 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91246699 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5930019 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 92418572 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 65829087 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.032093 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17244860 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187476 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.229284 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17386110 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 187768 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -422,27 +434,105 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 898809 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 898809 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17395 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94113 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 544060 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 354749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2049.828188 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 11956.771667 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-32767 349905 98.63% 98.63% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-65535 2560 0.72% 99.36% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-98303 1330 0.37% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-131071 450 0.13% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-163839 167 0.05% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::163840-196607 126 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-229375 45 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::229376-262143 59 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-294911 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::294912-327679 16 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-360447 24 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::360448-393215 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-425983 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 354749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 411281 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21163.528109 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 16798.259479 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15588.127658 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 367100 89.26% 89.26% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 39499 9.60% 98.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2985 0.73% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 830 0.20% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 180 0.04% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 394 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 143 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 73 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 22 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 14 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 17 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 411281 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 359646036796 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.131612 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.643594 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 358749976796 99.75% 99.75% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 501279000 0.14% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 178636500 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 105104000 0.03% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 41922000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 20797500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 20431000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 22734000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 4793500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 308500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 38000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 8500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 3500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 359646036796 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 94113 84.40% 84.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17395 15.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 111508 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 898809 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 898809 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111508 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111508 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1010317 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 105327476 # DTB read hits -system.cpu0.dtb.read_misses 614604 # DTB read misses -system.cpu0.dtb.write_hits 81433492 # DTB write hits -system.cpu0.dtb.write_misses 261715 # DTB write misses -system.cpu0.dtb.flush_tlb 1084 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 106848795 # DTB read hits +system.cpu0.dtb.read_misses 623268 # DTB read misses +system.cpu0.dtb.write_hits 83024984 # DTB write hits +system.cpu0.dtb.write_misses 275541 # DTB write misses +system.cpu0.dtb.flush_tlb 1088 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21241 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 54785 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 190 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8902 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 21670 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56194 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 160 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9669 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 53829 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105942080 # DTB read accesses -system.cpu0.dtb.write_accesses 81695207 # DTB write accesses +system.cpu0.dtb.perms_faults 56033 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 107472063 # DTB read accesses +system.cpu0.dtb.write_accesses 83300525 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 186760968 # DTB hits -system.cpu0.dtb.misses 876319 # DTB misses -system.cpu0.dtb.accesses 187637287 # DTB accesses +system.cpu0.dtb.hits 189873779 # DTB hits +system.cpu0.dtb.misses 898809 # DTB misses +system.cpu0.dtb.accesses 190772588 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -464,619 +554,673 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 94794688 # ITB inst hits -system.cpu0.itb.inst_misses 101824 # ITB inst misses +system.cpu0.itb.walker.walks 108604 # Table walker walks requested +system.cpu0.itb.walker.walksLong 108604 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3026 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 75552 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14309 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 94295 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1394.214964 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8384.902945 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 93563 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 326 0.35% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 303 0.32% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 55 0.06% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 94295 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 92887 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25650.201395 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21071.590317 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17522.957706 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 91125 98.10% 98.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1488 1.60% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 173 0.19% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 92887 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 604413242668 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.909243 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.287630 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 54912274056 9.09% 9.09% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 549448743612 90.91% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 47582500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 4106500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 406500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 121000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 8500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 604413242668 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 75552 96.15% 96.15% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 3026 3.85% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 78578 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 108604 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 108604 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 78578 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 78578 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 187182 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 96451691 # ITB inst hits +system.cpu0.itb.inst_misses 108604 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1084 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1088 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21241 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41122 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21670 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 42484 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 203923 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 204587 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94896512 # ITB inst accesses -system.cpu0.itb.hits 94794688 # DTB hits -system.cpu0.itb.misses 101824 # DTB misses -system.cpu0.itb.accesses 94896512 # DTB accesses -system.cpu0.numCycles 673746678 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 96560295 # ITB inst accesses +system.cpu0.itb.hits 96451691 # DTB hits +system.cpu0.itb.misses 108604 # DTB misses +system.cpu0.itb.accesses 96560295 # DTB accesses +system.cpu0.numCycles 678169162 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 246770894 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 586838334 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 131952150 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81879009 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 386930341 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13253583 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2358226 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 20576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 5110 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5338145 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 169787 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 2046 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94573624 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3603023 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 38939 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 648221646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.060144 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.307830 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 248888472 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 597668364 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 134182977 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83215197 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 388705337 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13495131 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2539677 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 4430 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5365960 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 171714 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 1942 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 96228071 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3656691 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 42208 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 652445982 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.071952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.318616 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 503028040 77.60% 77.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18376002 2.83% 80.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18277372 2.82% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13314289 2.05% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28669690 4.42% 89.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8974243 1.38% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9730545 1.50% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8410547 1.30% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39440918 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 504779765 77.37% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18600914 2.85% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18675892 2.86% 83.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13601130 2.08% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28939785 4.44% 89.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9186194 1.41% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9881419 1.51% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8590984 1.32% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 40189899 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 648221646 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.195848 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.871007 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 200186064 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 323821330 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105067312 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13887509 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5257280 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19546951 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1388336 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 640651678 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4275147 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5257280 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 207892852 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 28836524 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 254594010 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111072647 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 40565977 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 625329125 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 73391 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2369804 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1783636 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 20590537 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 4721 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 598881072 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 965488055 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 739733763 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 970310 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 502829107 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 96051965 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15333341 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13384841 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78497988 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100792231 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85691546 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13482087 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14436592 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 593155856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15408534 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 593869164 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 811141 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 75391106 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 52735595 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 350692 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 648221646 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.916151 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.637744 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 652445982 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.197861 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.881297 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 202230502 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 323725330 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 107157055 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13964232 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5366791 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19957602 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1400195 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 652122035 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4310941 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5366791 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 210017200 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 28890111 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 254295095 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 113145299 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 40729265 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 636448025 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 83808 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2425012 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1797238 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 20704845 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 5054 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 608929978 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 980367872 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 752692960 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 918645 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 510273791 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 98656187 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15296129 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13303285 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78526904 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 102548023 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 87419598 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13782768 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14655222 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 603808817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15342366 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 603678166 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 829707 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 77491896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 54214041 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 352970 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 652445982 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.925254 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.646571 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 413675393 63.82% 63.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 99838135 15.40% 79.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43354420 6.69% 85.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30999055 4.78% 90.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 23185151 3.58% 94.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 15937923 2.46% 96.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10813303 1.67% 98.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6331141 0.98% 99.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4087125 0.63% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 415092251 63.62% 63.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 100237257 15.36% 78.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 44034564 6.75% 85.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31483239 4.83% 90.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23657330 3.63% 94.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16258445 2.49% 96.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10998020 1.69% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6466609 0.99% 99.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4218267 0.65% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 648221646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 652445982 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2980479 25.39% 25.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 23946 0.20% 25.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2481 0.02% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 3 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4885958 41.63% 67.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3844513 32.75% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3031745 25.47% 25.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 22352 0.19% 25.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2380 0.02% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4899657 41.16% 66.83% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3948703 33.17% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 402330448 67.75% 67.75% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1450246 0.24% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 67448 0.01% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 71724 0.01% 68.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 408914830 67.74% 67.74% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1483700 0.25% 67.98% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 67594 0.01% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 189 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 10 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 26 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 67735 0.01% 68.01% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.01% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.01% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 107439270 18.09% 86.11% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82509979 13.89% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 109003987 18.06% 86.06% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 84140078 13.94% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 593869164 # Type of FU issued -system.cpu0.iq.rate 0.881443 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11737380 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019764 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1847356027 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 684092325 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 571253396 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1152468 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 551459 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 500772 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 604990335 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 616209 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4719298 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 603678166 # Type of FU issued +system.cpu0.iq.rate 0.890159 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11904839 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019721 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1871435984 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 696824280 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 580857585 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1100876 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 525941 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 475487 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 614994656 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 588349 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4797344 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16584124 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 22051 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 699484 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8981937 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16957941 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 22519 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 718505 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 9238289 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3863484 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8859794 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3918093 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 8730401 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5257280 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15355080 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 11717568 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 608700724 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1772426 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100792231 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85691546 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13094550 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 251810 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 11354978 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 699484 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2666409 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2277536 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4943945 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 587171511 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 105317678 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5833659 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5366791 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15638409 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 11458161 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 619287399 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1818065 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 102548023 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 87419598 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13010956 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 256814 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 11089494 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 718505 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2724850 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2330540 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5055390 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 596785117 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 106839289 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6007087 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 136334 # number of nop insts executed -system.cpu0.iew.exec_refs 186754203 # number of memory reference insts executed -system.cpu0.iew.exec_branches 108711734 # Number of branches executed -system.cpu0.iew.exec_stores 81436525 # Number of stores executed -system.cpu0.iew.exec_rate 0.871502 # Inst execution rate -system.cpu0.iew.wb_sent 572939308 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 571754168 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 281506422 # num instructions producing a value -system.cpu0.iew.wb_consumers 489082927 # num instructions consuming a value +system.cpu0.iew.exec_nop 136216 # number of nop insts executed +system.cpu0.iew.exec_refs 189866682 # number of memory reference insts executed +system.cpu0.iew.exec_branches 110402162 # Number of branches executed +system.cpu0.iew.exec_stores 83027393 # Number of stores executed +system.cpu0.iew.exec_rate 0.879994 # Inst execution rate +system.cpu0.iew.wb_sent 582539449 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 581333072 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 286508471 # num instructions producing a value +system.cpu0.iew.wb_consumers 497555384 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.848619 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575580 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.857210 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575832 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 81075036 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15057842 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4452233 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 634439872 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.831521 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.823079 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 83249738 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14989396 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4548973 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 638320811 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.839633 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.833868 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 439457438 69.27% 69.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 96886239 15.27% 84.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33460731 5.27% 89.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15060049 2.37% 92.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10644464 1.68% 93.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6550765 1.03% 94.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5894426 0.93% 95.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 4022234 0.63% 96.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22463526 3.54% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 441333872 69.14% 69.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 97259629 15.24% 84.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33853962 5.30% 89.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15327337 2.40% 92.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10781377 1.69% 93.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6688169 1.05% 94.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6042869 0.95% 95.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 4086388 0.64% 96.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22947208 3.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 634439872 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 448815056 # Number of instructions committed -system.cpu0.commit.committedOps 527549931 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 638320811 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 456208771 # Number of instructions committed +system.cpu0.commit.committedOps 535955511 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 160917716 # Number of memory references committed -system.cpu0.commit.loads 84208107 # Number of loads committed -system.cpu0.commit.membars 3677805 # Number of memory barriers committed -system.cpu0.commit.branches 100249360 # Number of branches committed -system.cpu0.commit.fp_insts 481111 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 484287281 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13244362 # Number of function calls committed. +system.cpu0.commit.refs 163771391 # Number of memory references committed +system.cpu0.commit.loads 85590082 # Number of loads committed +system.cpu0.commit.membars 3686850 # Number of memory barriers committed +system.cpu0.commit.branches 101715990 # Number of branches committed +system.cpu0.commit.fp_insts 455933 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 492018334 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13342246 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 365417797 69.27% 69.27% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1102287 0.21% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 49909 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 62180 0.01% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84208107 15.96% 85.46% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 76709609 14.54% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 370951931 69.21% 69.21% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1123996 0.21% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 50135 0.01% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 58016 0.01% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.44% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 85590082 15.97% 85.41% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 78181309 14.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 527549931 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22463526 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 535955511 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22947208 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1216684794 # The number of ROB reads -system.cpu0.rob.rob_writes 1231052317 # The number of ROB writes -system.cpu0.timesIdled 4081993 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25525032 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 47131326354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 448815056 # Number of Instructions Simulated -system.cpu0.committedOps 527549931 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.501168 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.501168 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.666148 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.666148 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 692564361 # number of integer regfile reads -system.cpu0.int_regfile_writes 407943900 # number of integer regfile writes -system.cpu0.fp_regfile_reads 896391 # number of floating regfile reads -system.cpu0.fp_regfile_writes 528896 # number of floating regfile writes -system.cpu0.cc_regfile_reads 125905812 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126977702 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2322757937 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15198906 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10638925 # number of replacements +system.cpu0.rob.rob_reads 1230638929 # The number of ROB reads +system.cpu0.rob.rob_writes 1252557383 # The number of ROB writes +system.cpu0.timesIdled 4102528 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25723180 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 48923483834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 456208771 # Number of Instructions Simulated +system.cpu0.committedOps 535955511 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.486532 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.486532 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.672706 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.672706 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 703703491 # number of integer regfile reads +system.cpu0.int_regfile_writes 414789220 # number of integer regfile writes +system.cpu0.fp_regfile_reads 851205 # number of floating regfile reads +system.cpu0.fp_regfile_writes 517790 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127713204 # number of cc regfile reads +system.cpu0.cc_regfile_writes 128825628 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2353610328 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15112961 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10694855 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.983549 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 304517896 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10639437 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.621617 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 305873629 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10695367 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.598703 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1654841000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 289.769940 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 222.213609 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.565957 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.434011 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 310.817389 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 201.166160 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.607065 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.392903 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1345465491 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1345465491 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79979109 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80848758 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 160827867 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67346505 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67891780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135238285 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204132 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 199440 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 403572 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171160 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 153591 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 324751 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1784441 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1798021 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3582462 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2031437 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2062591 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4094028 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147325614 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 148740538 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 296066152 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147529746 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 148939978 # number of overall hits -system.cpu0.dcache.overall_hits::total 296469724 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6500737 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6533272 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 13034009 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6519313 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6481267 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13000580 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 668156 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 654202 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1322358 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 633593 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 607646 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1241239 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 311874 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 325474 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 637348 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 10 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13020050 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 13014539 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 26034589 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 13688206 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 13668741 # number of overall misses -system.cpu0.dcache.overall_misses::total 27356947 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111607932917 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111225009746 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 222832942663 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 259750103307 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 246979475075 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 506729578382 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 25310357673 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 23982059689 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 49292417362 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4526632473 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4625804945 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 9152437418 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 268001 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 294001 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 371358036224 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 358204484821 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 729562521045 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 371358036224 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 358204484821 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 729562521045 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 86479846 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 87382030 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 173861876 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73865818 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 74373047 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 148238865 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 872288 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 853642 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1725930 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 804753 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 761237 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1565990 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2096315 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2123495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4219810 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2031439 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2062601 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4094040 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160345664 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 161755077 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 322100741 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161217952 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 162608719 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 323826671 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075171 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074767 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.074968 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.088259 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087145 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.087700 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.765981 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.766366 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766171 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.787314 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.798235 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.792623 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.148772 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153273 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.151037 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081200 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.080458 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.080827 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.084905 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.084059 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.084480 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17168.504574 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17024.396006 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17096.270431 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39843.171099 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38106.665730 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38977.459343 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39947.344230 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 39467.156353 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39712.269242 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14514.298957 # average LoadLockedReq miss latency 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number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 161052462 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 325258663 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074126 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.075676 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.074895 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.086198 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.089359 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.087760 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767067 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.766521 # miss rate for SoftPFReq accesses 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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26800.100000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24500.083333 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28522.013066 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27523.409382 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28022.816917 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27129.781377 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26206.106680 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26668.272635 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 59155859 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 42706 # number of cycles access was blocked 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cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716560502 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2798393044 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2781680461 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5580073505 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675572794 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5621061213 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296634007 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032825 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032847 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032836 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014776 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014677 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014726 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758321 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759308 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758809 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.783171 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.793649 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.788264 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058421 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059937 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059184 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024511 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024493 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024502 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028481 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028415 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15156.089384 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15210.044438 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15183.215768 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37199.032326 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35590.404279 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36394.675195 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19912.289892 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19404.769822 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19661.106305 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 37958.129466 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37470.665844 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37719.551821 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13184.439315 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12807.526101 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12992.354595 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 8181117 # number of writebacks +system.cpu0.dcache.writebacks::total 8181117 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664959 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3663666 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7328625 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5405222 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5470276 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10875498 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 3366 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3580 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 6946 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 193804 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 194772 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 388576 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9070181 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 9133942 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 18204123 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9070181 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 9133942 # number of overall MSHR hits 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WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 606885 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1233761 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124685 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 126170 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 250855 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3947267 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3995278 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7942545 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4603132 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4654373 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 9257505 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43426889493 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 44103833792 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 87530723285 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40333598117 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 39629888189 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 79963486306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12970544028 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12958416533 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25928960561 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 23908668069 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 22678349912 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 46587017981 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1638689162 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1618682187 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3257371349 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 136500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 147500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83760487610 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83733721981 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 167494209591 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 96731031638 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 96692138514 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 193423170152 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2840564251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2875998253 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716562504 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2826497047 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2753568465 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5580065512 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5667061298 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5629566718 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296628016 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032478 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033364 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032917 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014457 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015033 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014742 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759266 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759942 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759604 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.782045 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.793348 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787564 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059588 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058772 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059175 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024166 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024942 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024550 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028033 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028900 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028462 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15194.842233 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15267.007055 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15231.118222 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37028.269629 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35817.314181 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36418.054436 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19776.240580 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19660.923741 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19718.440531 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38139.389718 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37368.446925 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37760.164230 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.632730 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12829.374550 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12985.076435 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 24799.900000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22499.916667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21277.620994 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20825.293708 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21050.551263 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21080.931642 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20625.563924 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20852.794451 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21071.428571 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21219.868737 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20958.171617 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21088.229225 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21014.177225 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20774.471344 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20893.660889 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1087,137 +1231,137 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 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occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.463931 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 16173930 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.955160 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 173933615 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16174442 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.753608 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13621642000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 273.473305 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 238.481855 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.534128 # Average percentage of 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+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084567 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084567 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084567 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11689.412648 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11689.412648 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11689.412648 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1225,15 +1369,23 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 133577738 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90779695 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5949901 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 90899106 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 65330171 # Number of BTB hits +system.cpu1.branchPred.lookups 132595782 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89991047 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5894262 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 90157022 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 64704998 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.871082 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17378415 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 188946 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.769227 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17429206 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 189878 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1255,27 +1407,103 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 890417 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 890417 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17386 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91593 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 535956 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 354461 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2058.191169 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12119.324471 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 349672 98.65% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 2519 0.71% 99.36% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 1342 0.38% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 424 0.12% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 149 0.04% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 114 0.03% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 53 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 10 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 34 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::360448-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-425983 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 354461 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 404532 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20689.820452 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 16434.872295 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15113.304602 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 363916 89.96% 89.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 36589 9.04% 99.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 2703 0.67% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 595 0.15% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 189 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 278 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 138 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 43 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 30 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 13 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 404532 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 334236526020 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.086173 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.625283 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 333380386520 99.74% 99.74% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 477486500 0.14% 99.89% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 168839000 0.05% 99.94% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 100636500 0.03% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 41145500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 20471500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 20409500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 23342000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 3487500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 317500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 334236526020 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 91594 84.05% 84.05% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17386 15.95% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 108980 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 890417 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 890417 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108980 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108980 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 999397 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 106064392 # DTB read hits -system.cpu1.dtb.read_misses 610373 # DTB read misses -system.cpu1.dtb.write_hits 82025488 # DTB write hits -system.cpu1.dtb.write_misses 271302 # DTB write misses -system.cpu1.dtb.flush_tlb 1088 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 105460349 # DTB read hits +system.cpu1.dtb.read_misses 614707 # DTB read misses +system.cpu1.dtb.write_hits 81263219 # DTB write hits +system.cpu1.dtb.write_misses 275710 # DTB write misses +system.cpu1.dtb.flush_tlb 1092 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 22250 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55877 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 229 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8683 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21988 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 544 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 55487 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 238 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9789 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 56886 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 106674765 # DTB read accesses -system.cpu1.dtb.write_accesses 82296790 # DTB write accesses +system.cpu1.dtb.perms_faults 55163 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 106075056 # DTB read accesses +system.cpu1.dtb.write_accesses 81538929 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 188089880 # DTB hits -system.cpu1.dtb.misses 881675 # DTB misses -system.cpu1.dtb.accesses 188971555 # DTB accesses +system.cpu1.dtb.hits 186723568 # DTB hits +system.cpu1.dtb.misses 890417 # DTB misses +system.cpu1.dtb.accesses 187613985 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1297,126 +1525,182 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 96043604 # ITB inst hits -system.cpu1.itb.inst_misses 103294 # ITB inst misses +system.cpu1.itb.walker.walks 101825 # Table walker walks requested +system.cpu1.itb.walker.walksLong 101825 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2978 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69124 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 13788 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 88037 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1472.687620 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8948.821118 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 87265 99.12% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 389 0.44% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 275 0.31% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.05% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 27 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 88037 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 85890 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25260.851287 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 20589.361475 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17130.840101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 84234 98.07% 98.07% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1438 1.67% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 145 0.17% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 40 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 85890 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 299874193152 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 1.837074 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -250957583628 -83.69% -83.69% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 550779312780 183.67% 99.98% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 46468000 0.02% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5344000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 484000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 65500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 54500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::7 48000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 299874193152 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 69124 95.87% 95.87% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2978 4.13% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72102 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101825 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101825 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72102 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72102 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 173927 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 95285493 # ITB inst hits +system.cpu1.itb.inst_misses 101825 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1088 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1092 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 22250 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 41299 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21988 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 544 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40874 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205516 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 205822 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 96146898 # ITB inst accesses -system.cpu1.itb.hits 96043604 # DTB hits -system.cpu1.itb.misses 103294 # DTB misses -system.cpu1.itb.accesses 96146898 # DTB accesses -system.cpu1.numCycles 675301208 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 95387318 # ITB inst accesses +system.cpu1.itb.hits 95285493 # DTB hits +system.cpu1.itb.misses 101825 # DTB misses +system.cpu1.itb.accesses 95387318 # DTB accesses +system.cpu1.numCycles 677360427 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 248765293 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 593949498 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 133577738 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 82708586 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 386843919 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13545666 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2415137 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 21504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 4007 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5459319 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 169387 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 1822 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95816300 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3685759 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 39432 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 650452950 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.068285 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.315163 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 248549507 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 588684684 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 132595782 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 82134204 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 389145480 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13431349 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2335492 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 20294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 4597 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5447640 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 169416 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 1942 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 95058557 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3668998 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 40025 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 652389771 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.056521 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.304488 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 503682671 77.44% 77.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18498717 2.84% 80.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18563467 2.85% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13597541 2.09% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28733288 4.42% 89.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9099977 1.40% 91.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9814186 1.51% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8571904 1.32% 93.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39891199 6.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 506719262 77.67% 77.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18449281 2.83% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18323109 2.81% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13434339 2.06% 85.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28729534 4.40% 89.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 8986163 1.38% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9758970 1.50% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8450464 1.30% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 39538649 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 650452950 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.197805 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.879533 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 201647992 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 323236826 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 106239229 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13947017 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5379639 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19860273 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1413177 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 647237018 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4350385 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5379639 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 209424655 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 28067269 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 255930457 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 112228565 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 39419858 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 631550288 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 96632 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2287540 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1813390 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19429955 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 4996 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 604714007 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 972949887 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 746652224 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 816553 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 506435319 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 98278683 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15335388 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13342018 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 78452935 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 101901110 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 86377507 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13921613 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14837029 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 598946566 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15418828 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 598874973 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 821829 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 77129289 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53862821 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352968 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 650452950 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.920705 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.641335 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 652389771 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.195754 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.869086 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 201147393 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 326816283 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 105097642 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 14007460 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5318954 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19647868 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1416154 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 641757938 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4369017 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5318954 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 208911045 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 28047403 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 258823969 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 111174433 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 40111705 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 626286274 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 89729 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2292362 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1848085 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19940508 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 5105 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 599962292 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 966932024 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 740689310 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 881849 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 503173353 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 96788934 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15525446 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13560324 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 79127309 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 101049697 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 85573282 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13915572 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14825014 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 593826390 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15642550 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 594476204 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 818225 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 76136612 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53142905 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 356951 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 652389771 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.911229 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.632553 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 414330356 63.70% 63.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 100076970 15.39% 79.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43847279 6.74% 85.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31289942 4.81% 90.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23378361 3.59% 94.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16103120 2.48% 96.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10912961 1.68% 98.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6384879 0.98% 99.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4129082 0.63% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 416908971 63.90% 63.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 100667120 15.43% 79.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43571359 6.68% 86.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31041594 4.76% 90.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23116047 3.54% 94.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 15866958 2.43% 96.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10833871 1.66% 98.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6331428 0.97% 99.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4052423 0.62% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 650452950 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 652389771 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3013028 25.67% 25.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 23161 0.20% 25.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2816 0.02% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2996828 25.66% 25.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 24624 0.21% 25.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2734 0.02% 25.89% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.89% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.89% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.89% # attempts to use FU when none available @@ -1439,19 +1723,19 @@ system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.89% # at system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.89% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.89% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 2 0.00% 25.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 3 0.00% 25.89% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.89% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.89% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4848351 41.30% 67.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3852019 32.81% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4869636 41.69% 67.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3787065 32.42% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 405949153 67.79% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1474390 0.25% 68.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 66030 0.01% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 142 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 402964828 67.78% 67.78% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1445986 0.24% 68.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 66608 0.01% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 132 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued @@ -1464,7 +1748,7 @@ system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Ty system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued @@ -1473,156 +1757,156 @@ system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Ty system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 56962 0.01% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 61370 0.01% 68.05% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 108207982 18.07% 86.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 83120313 13.88% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 107585906 18.10% 86.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82351372 13.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 598874973 # Type of FU issued -system.cpu1.iq.rate 0.886826 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11739377 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019602 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1859775645 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 691731884 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 576296193 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 988457 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 469794 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 425393 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 610086136 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 528213 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4764786 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 594476204 # Type of FU issued +system.cpu1.iq.rate 0.877636 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11680890 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019649 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1852781725 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 685800777 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 571863197 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1059569 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 502092 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 457373 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 605590748 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 566345 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4749876 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16932520 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 21750 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 718636 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 9175857 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16757289 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 22108 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 708788 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 9117452 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3929336 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8527630 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3937125 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8714130 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5379639 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 15396107 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 10835641 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 614503705 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1815595 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 101901110 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 86377507 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13042378 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 259470 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 10465486 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 718636 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2720399 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2342418 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5062817 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 592014750 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 106053814 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5994040 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5318954 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 15381414 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 10835277 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 609605144 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1787029 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 101049697 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 85573282 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13260611 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 256865 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 10466220 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 708788 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2676587 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2314011 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4990598 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 587727574 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 105451218 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5872593 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 138311 # number of nop insts executed -system.cpu1.iew.exec_refs 188080635 # number of memory reference insts executed -system.cpu1.iew.exec_branches 109728675 # Number of branches executed -system.cpu1.iew.exec_stores 82026821 # Number of stores executed -system.cpu1.iew.exec_rate 0.876668 # Inst execution rate -system.cpu1.iew.wb_sent 577948748 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 576721586 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 284303568 # num instructions producing a value -system.cpu1.iew.wb_consumers 493660086 # num instructions consuming a value +system.cpu1.iew.exec_nop 136204 # number of nop insts executed +system.cpu1.iew.exec_refs 186716455 # number of memory reference insts executed +system.cpu1.iew.exec_branches 109034476 # Number of branches executed +system.cpu1.iew.exec_stores 81265237 # Number of stores executed +system.cpu1.iew.exec_rate 0.867673 # Inst execution rate +system.cpu1.iew.wb_sent 573536970 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 572320570 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 281697554 # num instructions producing a value +system.cpu1.iew.wb_consumers 489376492 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.854021 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575910 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.844928 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575625 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 82926260 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15065860 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4556436 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 636355753 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.835207 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.827690 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 81905872 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15285599 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4497270 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 638458448 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.826393 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.816586 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 440359254 69.20% 69.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 97084176 15.26% 84.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33726039 5.30% 89.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15156809 2.38% 92.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10762314 1.69% 93.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6601636 1.04% 94.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5939289 0.93% 95.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 4020807 0.63% 96.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22705429 3.57% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 442788562 69.35% 69.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 97620349 15.29% 84.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33589881 5.26% 89.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 14950626 2.34% 92.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10704317 1.68% 93.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6546690 1.03% 94.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5838446 0.91% 95.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3972340 0.62% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22447237 3.52% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 636355753 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 452434315 # Number of instructions committed -system.cpu1.commit.committedOps 531488932 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 638458448 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 448865132 # Number of instructions committed +system.cpu1.commit.committedOps 527617659 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 162170239 # Number of memory references committed -system.cpu1.commit.loads 84968589 # Number of loads committed -system.cpu1.commit.membars 3740598 # Number of memory barriers committed -system.cpu1.commit.branches 101032588 # Number of branches committed -system.cpu1.commit.fp_insts 407528 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 487762142 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13294479 # Number of function calls committed. +system.cpu1.commit.refs 160748237 # Number of memory references committed +system.cpu1.commit.loads 84292407 # Number of loads committed +system.cpu1.commit.membars 3769330 # Number of memory barriers committed +system.cpu1.commit.branches 100442689 # Number of branches committed +system.cpu1.commit.fp_insts 439800 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 484228202 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13335340 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 368091914 69.26% 69.26% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1129647 0.21% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49240 0.01% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 47892 0.01% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84968589 15.99% 85.47% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 77201650 14.53% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 365655543 69.30% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1112211 0.21% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 49677 0.01% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 51991 0.01% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84292407 15.98% 85.51% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 76455830 14.49% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 531488932 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22705429 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 527617659 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22447237 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1224024924 # The number of ROB reads -system.cpu1.rob.rob_writes 1242947045 # The number of ROB writes -system.cpu1.timesIdled 4091922 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 24848258 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 54236174505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 452434315 # Number of Instructions Simulated -system.cpu1.committedOps 531488932 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.492595 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.492595 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.669974 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.669974 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 697864723 # number of integer regfile reads -system.cpu1.int_regfile_writes 411651158 # number of integer regfile writes -system.cpu1.fp_regfile_reads 767907 # number of floating regfile reads -system.cpu1.fp_regfile_writes 473740 # number of floating regfile writes -system.cpu1.cc_regfile_reads 126991866 # number of cc regfile reads -system.cpu1.cc_regfile_writes 128085324 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2338745159 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15183498 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40379 # Transaction distribution -system.iobus.trans_dist::ReadResp 40379 # Transaction distribution +system.cpu1.rob.rob_reads 1221498833 # The number of ROB reads +system.cpu1.rob.rob_writes 1232997569 # The number of ROB writes +system.cpu1.timesIdled 4096806 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 24970656 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 52437515063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 448865132 # Number of Instructions Simulated +system.cpu1.committedOps 527617659 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.509051 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.509051 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.662668 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.662668 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 693047790 # number of integer regfile reads +system.cpu1.int_regfile_writes 408438474 # number of integer regfile writes +system.cpu1.fp_regfile_reads 823112 # number of floating regfile reads +system.cpu1.fp_regfile_writes 494780 # number of floating regfile writes +system.cpu1.cc_regfile_reads 126134775 # number of cc regfile reads +system.cpu1.cc_regfile_writes 127188255 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2330176021 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15424448 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40375 # Transaction distribution +system.iobus.trans_dist::ReadResp 40375 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1642,11 +1926,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354216 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1663,11 +1947,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492622 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1696,71 +1980,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042420321 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042399628 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 178996533 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 178994733 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.429567 # Cycle average of tags in use +system.iocache.tags.replacements 115455 # number of replacements +system.iocache.tags.tagsinuse 10.429644 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13090570223000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.541524 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.888043 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221345 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430503 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651848 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13090563453000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.541528 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.888116 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221346 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430507 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651853 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.tags.tag_accesses 1039614 # Number of tag accesses +system.iocache.tags.data_accesses 1039614 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses -system.iocache.demand_misses::total 8853 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8809 # number of demand (read+write) misses +system.iocache.demand_misses::total 8849 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8813 # number of overall misses -system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.overall_misses::realview.ide 8809 # number of overall misses +system.iocache.overall_misses::total 8849 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1921756799 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1927241799 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1920259350 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1925744350 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28951102989 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28951102989 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28938987545 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28938987545 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1921756799 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1927580799 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1920259350 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1926083350 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1921756799 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1927580799 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1920259350 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1926083350 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8809 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8849 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8809 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8849 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1775,54 +2059,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218059.321343 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217767.434915 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 217988.347145 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217696.625593 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271423.376106 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271423.376106 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271309.790979 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271309.790979 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 218059.321343 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217731.932565 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 217988.347145 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217661.131201 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 218059.321343 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217731.932565 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 227766 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 217988.347145 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217661.131201 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 227974 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27719 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27752 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.216963 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.214687 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8809 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8809 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8849 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8809 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8849 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1463357813 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1466918813 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1462065868 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1465626868 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23404023041 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23404023041 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23392010493 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23392010493 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1463357813 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1467101813 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1462065868 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1465809868 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1463357813 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1467101813 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1462065868 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1465809868 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1837,291 +2121,291 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166045.366277 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165753.538192 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165974.102395 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165682.440425 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219418.201464 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219418.201464 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219305.581011 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219305.581011 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 166045.366277 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165718.040551 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 165974.102395 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165646.950842 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 166045.366277 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165718.040551 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 165974.102395 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165646.950842 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1389484 # number of replacements -system.l2c.tags.tagsinuse 65352.106394 # Cycle average of tags in use -system.l2c.tags.total_refs 31455593 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1452181 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.660931 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2484843000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35806.671040 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 143.176301 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 245.153324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3359.514416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11467.907347 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 184.237244 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 273.594467 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3844.520884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10027.331371 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.546366 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002185 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003741 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.051262 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.174986 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002811 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004175 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.058663 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.153005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997194 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 343 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62354 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 341 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 538 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2779 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5047 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53889 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005234 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 295633480 # Number of tag accesses -system.l2c.tags.data_accesses 295633480 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 538849 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 186240 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7977279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3458474 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 540473 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 189439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 8047769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3485516 # number of ReadReq hits -system.l2c.ReadReq_hits::total 24424039 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8137324 # number of Writeback hits -system.l2c.Writeback_hits::total 8137324 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 356242 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 359953 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 716195 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4893 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5150 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10043 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 790931 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 806807 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1597738 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 538849 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 186240 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7977279 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4249405 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 540473 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 189439 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8047769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4292323 # number of demand (read+write) hits -system.l2c.demand_hits::total 26021777 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 538849 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 186240 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7977279 # number of overall hits -system.l2c.overall_hits::cpu0.data 4249405 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 540473 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 189439 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8047769 # number of overall hits -system.l2c.overall_hits::cpu1.data 4292323 # number of overall hits -system.l2c.overall_hits::total 26021777 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2272 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2136 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 49402 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 157936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2713 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2545 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 44633 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 153451 # number of ReadReq misses -system.l2c.ReadReq_misses::total 415088 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 274017 # number of WriteInvalidateReq misses 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49402 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 442095 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2713 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2545 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 44633 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 421210 # number of demand (read+write) misses -system.l2c.demand_misses::total 967006 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2272 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2136 # number of overall misses -system.l2c.overall_misses::cpu0.inst 49402 # number of overall misses -system.l2c.overall_misses::cpu0.data 442095 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2713 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2545 # number of overall misses -system.l2c.overall_misses::cpu1.inst 44633 # number of overall misses -system.l2c.overall_misses::cpu1.data 421210 # number of overall misses -system.l2c.overall_misses::total 967006 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 184273245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 176430743 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 3875377998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 13368382174 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 220451240 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 205887741 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3497850741 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 13033563402 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 34562217284 # number of ReadReq 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of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1234414 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 22630 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 23726 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 46356 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 10 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1075090 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1074566 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2149656 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 541121 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 188376 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 8026681 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4691500 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 543186 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 191984 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8092402 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 4713533 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 26988783 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 541121 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 188376 # number of overall (read+write) accesses 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82598.662453 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 78445.771386 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 93158.836596 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81257.368227 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80898.915914 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78369.160509 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 92358.688243 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 91258.720885 # average overall miss latency +system.l2c.tags.replacements 1414814 # number of replacements +system.l2c.tags.tagsinuse 65356.208679 # Cycle average of tags in use +system.l2c.tags.total_refs 31586438 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1477430 # Sample count of references to valid blocks. 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+system.l2c.demand_mshr_miss_rate::total 0.036489 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004728 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006111 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.095054 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004621 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012098 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005833 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.091685 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036489 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 71586.782929 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72316.823373 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 70470.064489 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 37932.216105 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 39412.539959 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38618.518168 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.220688 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.286547 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10013.737194 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83846.404002 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 83507.798698 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 83680.233686 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79456.172080 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79414.965722 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 77994.234960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79456.172080 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79414.965722 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 77994.234960 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2338,57 +2619,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 478201 # Transaction distribution -system.membus.trans_dist::ReadResp 478201 # Transaction distribution +system.membus.trans_dist::ReadReq 489224 # Transaction distribution +system.membus.trans_dist::ReadResp 489224 # Transaction distribution system.membus.trans_dist::WriteReq 33860 # Transaction distribution system.membus.trans_dist::WriteResp 33860 # Transaction distribution -system.membus.trans_dist::Writeback 1282324 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 624745 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 624745 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37074 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 37077 # Transaction distribution -system.membus.trans_dist::ReadExReq 551298 # Transaction distribution -system.membus.trans_dist::ReadExResp 551298 # Transaction distribution +system.membus.trans_dist::Writeback 1299265 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 627170 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 627170 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37411 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 37412 # Transaction distribution +system.membus.trans_dist::ReadExReq 563054 # Transaction distribution +system.membus.trans_dist::ReadExResp 563054 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4264222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4394358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4729779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4332246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4462384 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335088 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335088 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4797472 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 171538732 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 171711000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14073856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14073856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185784856 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2907 # Total snoops (count) -system.membus.snoop_fanout::samples 2919339 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174236076 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 174408348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14052800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14052800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 188461148 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3233 # Total snoops (count) +system.membus.snoop_fanout::samples 2961771 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2919339 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2961771 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2919339 # Request fanout histogram -system.membus.reqLayer0.occupancy 99723000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2961771 # Request fanout histogram +system.membus.reqLayer0.occupancy 99708500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5540499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5504999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18597273982 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 18802986477 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9904783124 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10120184001 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186654467 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186568267 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2432,58 +2713,58 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 25451799 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25443711 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 25574289 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25566182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33860 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33860 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8137324 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1341081 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1234414 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46359 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46371 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2149656 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2149656 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32279635 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29644963 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 905204 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2573359 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 65403161 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1032942144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1201952920 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3042880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8674456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2246612400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 665707 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 37265900 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003100 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.055590 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 8181117 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1340428 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1233761 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46747 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46754 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2162441 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2162441 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32390529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29801361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 923404 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2600212 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 65715506 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1036485248 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1208333724 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3115152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8777312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2256711436 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 667123 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 37442651 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003085 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.055458 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 37150380 99.69% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115520 0.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 37327135 99.69% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115516 0.31% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 37265900 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 56232033216 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 37442651 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 56492183787 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 3430500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 3327000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 72693447528 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 72944134855 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 43148678653 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 43405971950 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 527770675 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 537017212 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1503131700 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1517407654 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16411 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16420 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 549c3e2c6..b93c1aabd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.781932 # Number of seconds simulated -sim_ticks 51781931516000 # Number of ticks simulated -final_tick 51781931516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.861398 # Number of seconds simulated +sim_ticks 51861397612000 # Number of ticks simulated +final_tick 51861397612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 513884 # Simulator instruction rate (inst/s) -host_op_rate 603881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31103019215 # Simulator tick rate (ticks/s) -host_mem_usage 672564 # Number of bytes of host memory used -host_seconds 1664.85 # Real time elapsed on the host -sim_insts 855540358 # Number of instructions simulated -sim_ops 1005371984 # Number of ops (including micro ops) simulated +host_inst_rate 682840 # Simulator instruction rate (inst/s) +host_op_rate 802417 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40752483757 # Simulator tick rate (ticks/s) +host_mem_usage 728928 # Number of bytes of host memory used +host_seconds 1272.59 # Real time elapsed on the host +sim_insts 868978236 # Number of instructions simulated +sim_ops 1021151568 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 107200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 102528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2434152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20994800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 96832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 103680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2545804 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 20458904 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 379200 # Number of bytes read from this memory -system.physmem.bytes_read::total 47223100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2434152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2545804 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4979956 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68447104 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 110912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 113344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2519016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 22396080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 118144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 113984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2612108 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 22226264 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 390656 # Number of bytes read from this memory +system.physmem.bytes_read::total 50600508 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2519016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2612108 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5131124 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71823424 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 68467684 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1602 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 65448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 328047 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1513 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1620 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 52771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 319680 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 5925 # Number of read requests responded to by this memory -system.physmem.num_reads::total 778281 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1069486 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 71844004 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 66774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 349942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 53807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 347295 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6104 # Number of read requests responded to by this memory +system.physmem.num_reads::total 831053 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1122241 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1072059 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 47008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 405446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 395097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 911961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 47008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 96172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1321834 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1124814 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 48572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 431845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 428570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 975687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 48572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 98939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1384911 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1322231 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1321834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 47008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 405447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 395495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2234192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 778281 # Number of read requests accepted -system.physmem.writeReqs 1672780 # Number of write requests accepted -system.physmem.readBursts 778281 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1672780 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49778368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31616 # Total number of bytes read from write queue -system.physmem.bytesWritten 106609920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 47223100 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 106913828 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 494 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6998 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 34417 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 49121 # Per bank write bursts -system.physmem.perBankRdBursts::1 48968 # Per bank write bursts -system.physmem.perBankRdBursts::2 43998 # Per bank write bursts -system.physmem.perBankRdBursts::3 44044 # Per bank write bursts -system.physmem.perBankRdBursts::4 46923 # Per bank write bursts -system.physmem.perBankRdBursts::5 50978 # Per bank write bursts -system.physmem.perBankRdBursts::6 43709 # Per bank write bursts -system.physmem.perBankRdBursts::7 43367 # Per bank write bursts -system.physmem.perBankRdBursts::8 43043 # Per bank write bursts -system.physmem.perBankRdBursts::9 89491 # Per bank write bursts -system.physmem.perBankRdBursts::10 47224 # Per bank write bursts -system.physmem.perBankRdBursts::11 49584 # Per bank write bursts -system.physmem.perBankRdBursts::12 42821 # Per bank write bursts -system.physmem.perBankRdBursts::13 45810 # Per bank write bursts -system.physmem.perBankRdBursts::14 42383 # Per bank write bursts -system.physmem.perBankRdBursts::15 46323 # Per bank write bursts -system.physmem.perBankWrBursts::0 104557 # Per bank write bursts -system.physmem.perBankWrBursts::1 105414 # Per bank write bursts -system.physmem.perBankWrBursts::2 105583 # Per bank write bursts -system.physmem.perBankWrBursts::3 103819 # Per bank write bursts -system.physmem.perBankWrBursts::4 104348 # Per bank write bursts -system.physmem.perBankWrBursts::5 108141 # Per bank write bursts -system.physmem.perBankWrBursts::6 101114 # Per bank write bursts -system.physmem.perBankWrBursts::7 100245 # Per bank write bursts -system.physmem.perBankWrBursts::8 99850 # Per bank write bursts -system.physmem.perBankWrBursts::9 106510 # Per bank write bursts -system.physmem.perBankWrBursts::10 102540 # Per bank write bursts -system.physmem.perBankWrBursts::11 107777 # Per bank write bursts -system.physmem.perBankWrBursts::12 103459 # Per bank write bursts -system.physmem.perBankWrBursts::13 105336 # Per bank write bursts -system.physmem.perBankWrBursts::14 101779 # Per bank write bursts -system.physmem.perBankWrBursts::15 105308 # Per bank write bursts +system.physmem.bw_write::total 1385308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1384911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 48572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 431845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 428967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2360995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 831053 # Number of read requests accepted +system.physmem.writeReqs 1733697 # Number of write requests accepted +system.physmem.readBursts 831053 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1733697 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 53155264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 32128 # Total number of bytes read from write queue +system.physmem.bytesWritten 110517504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 50600508 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 110812516 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 502 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6857 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35215 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 52772 # Per bank write bursts +system.physmem.perBankRdBursts::1 58055 # Per bank write bursts +system.physmem.perBankRdBursts::2 48746 # Per bank write bursts +system.physmem.perBankRdBursts::3 51625 # Per bank write bursts +system.physmem.perBankRdBursts::4 50901 # Per bank write bursts +system.physmem.perBankRdBursts::5 53731 # Per bank write bursts +system.physmem.perBankRdBursts::6 47545 # Per bank write bursts +system.physmem.perBankRdBursts::7 46576 # Per bank write bursts +system.physmem.perBankRdBursts::8 47759 # Per bank write bursts +system.physmem.perBankRdBursts::9 90120 # Per bank write bursts +system.physmem.perBankRdBursts::10 47452 # Per bank write bursts +system.physmem.perBankRdBursts::11 51057 # Per bank write bursts +system.physmem.perBankRdBursts::12 47939 # Per bank write bursts +system.physmem.perBankRdBursts::13 45720 # Per bank write bursts +system.physmem.perBankRdBursts::14 43868 # Per bank write bursts +system.physmem.perBankRdBursts::15 46685 # Per bank write bursts +system.physmem.perBankWrBursts::0 110572 # Per bank write bursts +system.physmem.perBankWrBursts::1 116599 # Per bank write bursts +system.physmem.perBankWrBursts::2 110707 # Per bank write bursts +system.physmem.perBankWrBursts::3 112437 # Per bank write bursts +system.physmem.perBankWrBursts::4 109828 # Per bank write bursts +system.physmem.perBankWrBursts::5 113045 # Per bank write bursts +system.physmem.perBankWrBursts::6 105073 # Per bank write bursts +system.physmem.perBankWrBursts::7 102356 # Per bank write bursts +system.physmem.perBankWrBursts::8 103784 # Per bank write bursts +system.physmem.perBankWrBursts::9 107644 # Per bank write bursts +system.physmem.perBankWrBursts::10 104570 # Per bank write bursts +system.physmem.perBankWrBursts::11 108123 # Per bank write bursts +system.physmem.perBankWrBursts::12 106842 # Per bank write bursts +system.physmem.perBankWrBursts::13 106503 # Per bank write bursts +system.physmem.perBankWrBursts::14 103411 # Per bank write bursts +system.physmem.perBankWrBursts::15 105342 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 51781928959500 # Total gap between requests +system.physmem.totGap 51861395055500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 735165 # Read request sizes (log2) +system.physmem.readPktSize::6 787937 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1670207 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 745946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 26414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 204 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1731124 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 797504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 363 # What read queue length does an incoming req see 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1.37% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 69894 13.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 531423 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 80476 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 9.664621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 89.984802 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 80471 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 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length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 563789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 290.307984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.321614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.078407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 235457 41.76% 41.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 139953 24.82% 66.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 46694 8.28% 74.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25357 4.50% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16838 2.99% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11479 2.04% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8496 1.51% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7843 1.39% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71672 12.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 563789 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 84234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 9.859653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 88.079162 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 84229 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 80476 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 80476 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.699090 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.496721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.527834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 200 0.25% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 177 0.22% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 72247 89.77% 90.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 4200 5.22% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1327 1.65% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 446 0.55% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 582 0.72% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 137 0.17% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 223 0.28% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 119 0.15% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 159 0.20% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 60 0.07% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 172 0.21% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 43 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 70 0.09% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 53 0.07% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 161 0.20% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 11 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 23 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 15 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 80476 # Writes before turning the bus around for reads -system.physmem.totQLat 9983720499 # Total ticks spent queuing -system.physmem.totMemAccLat 24567226749 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3888935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12836.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 84234 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 84234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.500463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.372295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.059087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 108 0.13% 0.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 80 0.09% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 54 0.06% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 121 0.14% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 46153 54.79% 55.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 30225 35.88% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2462 2.92% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1364 1.62% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 933 1.11% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 416 0.49% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 269 0.32% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 164 0.19% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 538 0.64% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 68 0.08% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 77 0.09% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 53 0.06% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 0.19% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 54 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 29 0.03% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 79 0.09% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 145 0.17% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 43 0.05% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 17 0.02% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 33 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 176 0.21% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 15 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 19 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 61 0.07% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 20 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 40 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 24 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 103 0.12% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 13 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 10 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 9 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 10 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 84234 # Writes before turning the bus around for reads +system.physmem.totQLat 10578626250 # Total ticks spent queuing +system.physmem.totMemAccLat 26151457500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4152755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12736.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31586.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31486.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.17 # Average write queue length when enqueuing -system.physmem.readRowHits 580589 # Number of row buffer hits during reads -system.physmem.writeRowHits 1331554 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes -system.physmem.avgGap 21126332.21 # Average gap between requests -system.physmem.pageHitRate 78.25 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49696712332000 # Time in different power states -system.physmem.memoryStateTime::REF 1729112320000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 356106481500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2031447600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1986110280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1108428750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1083691125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2894642400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3172057200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5399272080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5394982320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3382143697920 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3382143697920 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1286313063165 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1285469654400 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29940811051500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29941550883750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34620701603415 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34620801076995 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.586590 # Core power per rank (mW) -system.physmem.averagePower::1 668.588511 # Core power per rank (mW) +system.physmem.avgWrQLen 12.05 # Average write queue length when enqueuing +system.physmem.readRowHits 620179 # Number of row buffer hits during reads +system.physmem.writeRowHits 1373418 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.53 # Row buffer hit rate for writes +system.physmem.avgGap 20220838.31 # Average gap between requests +system.physmem.pageHitRate 77.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2224749240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1213900875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3197578800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5706398160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3387334061280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1303736226660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29973207455250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34676620370265 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.640359 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49862520204500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1731765880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 267111145000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2037495600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1111728750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3280680000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5483499120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3387334061280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1287848520900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29987144039250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34674240024900 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.594461 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49885777301500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1731765880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243849706000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -360,6 +389,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -381,27 +418,76 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 125209 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 125209 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 19669 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90325 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 125193 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 125193 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 125193 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 110010 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22089.371421 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18317.414501 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13164.465309 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 107059 97.32% 97.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2114 1.92% 99.24% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 606 0.55% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 110 0.10% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 25 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 28 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 110010 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 3295703864 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.071233 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -234762296 -7.12% -7.12% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 3530466160 107.12% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 3295703864 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90326 82.12% 82.12% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 19669 17.88% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 109995 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125209 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125209 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109995 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109995 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 235204 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 80391901 # DTB read hits -system.cpu0.dtb.read_misses 93388 # DTB read misses -system.cpu0.dtb.write_hits 73043030 # DTB write hits -system.cpu0.dtb.write_misses 28813 # DTB write misses -system.cpu0.dtb.flush_tlb 51784 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 81853035 # DTB read hits +system.cpu0.dtb.read_misses 95759 # DTB read misses +system.cpu0.dtb.write_hits 74321037 # DTB write hits +system.cpu0.dtb.write_misses 29450 # DTB write misses +system.cpu0.dtb.flush_tlb 51862 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 20238 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 70641 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 20132 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 528 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 71205 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4105 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4306 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9619 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 80485289 # DTB read accesses -system.cpu0.dtb.write_accesses 73071843 # DTB write accesses +system.cpu0.dtb.perms_faults 9531 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81948794 # DTB read accesses +system.cpu0.dtb.write_accesses 74350487 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 153434931 # DTB hits -system.cpu0.dtb.misses 122201 # DTB misses -system.cpu0.dtb.accesses 153557132 # DTB accesses +system.cpu0.dtb.hits 156174072 # DTB hits +system.cpu0.dtb.misses 125209 # DTB misses +system.cpu0.dtb.accesses 156299281 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -423,242 +509,284 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 427471663 # ITB inst hits -system.cpu0.itb.inst_misses 76376 # ITB inst misses +system.cpu0.itb.walker.walks 77027 # Table walker walks requested +system.cpu0.itb.walker.walksLong 77027 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4349 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67368 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 77027 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 77027 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 77027 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 71717 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25312.366663 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21958.347721 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 14763.140629 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 66172 92.27% 92.27% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 4523 6.31% 98.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 706 0.98% 99.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 175 0.24% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 37 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 34 0.05% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 34 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 71717 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -294463796 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -294463796 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -294463796 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 67368 93.94% 93.94% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4349 6.06% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 71717 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 77027 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 77027 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71717 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71717 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 148744 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 434570813 # ITB inst hits +system.cpu0.itb.inst_misses 77027 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51784 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51862 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 20238 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 52019 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 20132 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 528 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 52030 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 427548039 # ITB inst accesses -system.cpu0.itb.hits 427471663 # DTB hits -system.cpu0.itb.misses 76376 # DTB misses -system.cpu0.itb.accesses 427548039 # DTB accesses -system.cpu0.numCycles 51782412762 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 434647840 # ITB inst accesses +system.cpu0.itb.hits 434570813 # DTB hits +system.cpu0.itb.misses 77027 # DTB misses +system.cpu0.itb.accesses 434647840 # DTB accesses +system.cpu0.numCycles 51862348340 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 427217866 # Number of instructions committed -system.cpu0.committedOps 502133426 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 461356318 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 442453 # Number of float alu accesses -system.cpu0.num_func_calls 25480565 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64997329 # number of instructions that are conditional controls -system.cpu0.num_int_insts 461356318 # number of integer instructions -system.cpu0.num_fp_insts 442453 # number of float instructions -system.cpu0.num_int_register_reads 669433821 # number of times the integer registers were read -system.cpu0.num_int_register_writes 365789159 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 711452 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 379824 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 111391626 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 111077654 # number of times the CC registers were written -system.cpu0.num_mem_refs 153423964 # number of memory refs -system.cpu0.num_load_insts 80387324 # Number of load instructions -system.cpu0.num_store_insts 73036640 # Number of store instructions -system.cpu0.num_idle_cycles 50249111943.842865 # Number of idle cycles -system.cpu0.num_busy_cycles 1533300818.157139 # Number of busy cycles -system.cpu0.not_idle_fraction 0.029610 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.970390 # Percentage of idle cycles -system.cpu0.Branches 95379703 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 347836061 69.23% 69.23% # Class of executed instruction -system.cpu0.op_class::IntMult 1052847 0.21% 69.44% # Class of executed instruction -system.cpu0.op_class::IntDiv 47944 0.01% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 6 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 5 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 9 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 55653 0.01% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::MemRead 80387324 16.00% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 73036640 14.54% 100.00% # Class of executed instruction +system.cpu0.committedInsts 434316413 # Number of instructions committed +system.cpu0.committedOps 510251172 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 468762245 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 455279 # Number of float alu accesses +system.cpu0.num_func_calls 25833192 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 66107864 # number of instructions that are conditional controls +system.cpu0.num_int_insts 468762245 # number of integer instructions +system.cpu0.num_fp_insts 455279 # number of float instructions +system.cpu0.num_int_register_reads 680505745 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371520195 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 735714 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 382992 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113236512 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 112912982 # number of times the CC registers were written +system.cpu0.num_mem_refs 156164016 # number of memory refs +system.cpu0.num_load_insts 81849666 # Number of load instructions +system.cpu0.num_store_insts 74314350 # Number of store instructions +system.cpu0.num_idle_cycles 50300563806.190483 # Number of idle cycles +system.cpu0.num_busy_cycles 1561784533.809517 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030114 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969886 # Percentage of idle cycles +system.cpu0.Branches 96959859 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 353181248 69.18% 69.18% # Class of executed instruction +system.cpu0.op_class::IntMult 1084077 0.21% 69.39% # Class of executed instruction +system.cpu0.op_class::IntDiv 49491 0.01% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 6 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 8 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 12 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 55978 0.01% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::MemRead 81849666 16.03% 85.44% # Class of executed instruction +system.cpu0.op_class::MemWrite 74314350 14.56% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 502416489 # Class of executed instruction +system.cpu0.op_class::total 510534837 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16160 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 9666641 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.969685 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 297154926 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9667153 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.738618 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 16221 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 9866178 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.969728 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 301750178 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9866690 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.582716 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 3092948250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 283.466253 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 228.503431 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.553645 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.446296 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 290.086465 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 221.883263 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.566575 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.433366 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1237347722 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1237347722 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75260834 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 75246301 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 150507135 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69349664 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 69346777 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 138696441 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190562 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191577 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 382139 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171619 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 160816 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 332435 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1711920 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1739353 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3451273 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1857030 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1885244 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3742274 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 144610498 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 144593078 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 289203576 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 144801060 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 144784655 # number of overall hits -system.cpu0.dcache.overall_hits::total 289585715 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2479823 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2539735 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 5019558 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1027548 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1051512 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2079060 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 586953 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 604316 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1191269 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 612872 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 613029 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1225901 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145963 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 146688 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 292651 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1256728908 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1256728908 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 76588751 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 76163346 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 152752097 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 70555546 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 70327464 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 140883010 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190561 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 196148 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 386709 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 172423 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 161036 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 333459 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1750003 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1777885 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3527888 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1897893 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1924897 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3822790 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 147144297 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 146490810 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 293635107 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147334858 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 146686958 # number of overall hits +system.cpu0.dcache.overall_hits::total 294021816 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2557843 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2571612 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 5129455 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1050273 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1078042 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2128315 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 601274 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 625393 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1226667 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 620770 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 607819 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1228589 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148787 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 147781 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 296568 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3507371 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 3591247 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7098618 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4094324 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 4195563 # number of overall misses -system.cpu0.dcache.overall_misses::total 8289887 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38409075253 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 39279047002 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 77688122255 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27659575882 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 27687644531 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 55347220413 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 13571753508 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13540403000 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27112156508 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2071723750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2095160250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4166884000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 75000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 75000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66068651135 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66966691533 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 133035342668 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66068651135 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66966691533 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 133035342668 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 77740657 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 77786036 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 155526693 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 70377212 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 70398289 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 140775501 # number of WriteReq accesses(hits+misses) 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-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 8922621248 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 8744886500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17667507748 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 12346009492 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12314345000 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24660354492 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1340334000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1349733250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2690067250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 73000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 73000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58362188615 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 59194025467 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 117556214082 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 67284809863 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 67938911967 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 135223721830 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2674522248 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3054322749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5728844997 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2557892750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3016153500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5574046250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5232414998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6070476249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11302891247 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031850 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032613 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032232 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014456 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014780 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014618 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754722 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759054 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756914 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.781235 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.792186 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786673 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059900 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059093 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059494 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3594428 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3635550 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7229978 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4195560 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4260757 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 8456317 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34255815748 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 34669168995 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 68924984743 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26736974445 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 26668792594 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 53405767039 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 8942698000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9200320250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18143018250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 12615089500 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12247899494 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24862988994 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1372094500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1380082250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2752176750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 24499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 73000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 97499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60992790193 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 61337961589 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 122330751782 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 69935488193 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 70538281839 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 140473770032 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2674956999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3053270500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5728227499 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2550639000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3023463750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5574102750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5225595999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6076734250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11302330249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032274 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032622 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032448 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014524 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014943 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014734 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759163 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.761017 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760107 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.782622 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.790551 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786524 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060022 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058193 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059101 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023586 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024141 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023864 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028067 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027736 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13394.918697 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13394.866508 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13394.892286 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24765.081360 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24231.470524 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24495.276732 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15205.350384 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14475.269232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14835.001560 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20144.515481 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20087.703844 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20116.106025 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12043.832219 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12110.444407 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12077.162836 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16706.170665 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16546.772122 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16625.525428 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16490.328154 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16247.490009 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16367.421162 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023843 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024214 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024028 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027685 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028224 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027954 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13410.508275 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13497.816624 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13454.282609 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25707.961856 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24993.058039 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25345.926006 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14876.429802 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14715.638581 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.455897 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20321.680332 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20150.570308 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20237.027186 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12039.190482 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12315.565322 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12176.210796 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24499 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 48749.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16968.705506 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16871.714483 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16919.934166 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16668.928151 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16555.340246 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16611.696325 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -795,79 +927,79 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13477112 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.892486 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 842591946 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13477624 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 62.517840 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 32076200250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.322157 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 270.570329 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471332 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.528458 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 13777264 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.892662 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 855737357 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13777776 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 62.109977 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 32072682250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.033427 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.859235 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535222 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.464569 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999790 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 197 # Occupied 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overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11408.881139 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11398.841529 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11388.745063 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11408.881139 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11398.841529 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -925,6 +1057,14 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -946,27 +1086,81 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 127972 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 127972 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 19780 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92740 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 127956 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.265716 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 71.272998 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 127954 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 127956 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 112536 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22019.187193 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18129.081838 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13444.450617 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 109487 97.29% 97.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2144 1.91% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 659 0.59% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 117 0.10% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 32 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 27 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 112536 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 6637919892 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.174468 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1158102796 -17.45% -17.45% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 7796022688 117.45% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 6637919892 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92740 82.42% 82.42% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 19780 17.58% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 112520 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 127972 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 127972 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 112520 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 112520 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 240492 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80485889 # DTB read hits -system.cpu1.dtb.read_misses 94650 # DTB read misses -system.cpu1.dtb.write_hits 73083689 # DTB write hits -system.cpu1.dtb.write_misses 28922 # DTB write misses -system.cpu1.dtb.flush_tlb 51788 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 81500118 # DTB read hits +system.cpu1.dtb.read_misses 97955 # DTB read misses +system.cpu1.dtb.write_hits 74126007 # DTB write hits +system.cpu1.dtb.write_misses 30017 # DTB write misses +system.cpu1.dtb.flush_tlb 51868 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 19698 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 69957 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 20724 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 72099 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4240 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4473 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9564 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80580539 # DTB read accesses -system.cpu1.dtb.write_accesses 73112611 # DTB write accesses +system.cpu1.dtb.perms_faults 9907 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 81598073 # DTB read accesses +system.cpu1.dtb.write_accesses 74156024 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 153569578 # DTB hits -system.cpu1.dtb.misses 123572 # DTB misses -system.cpu1.dtb.accesses 153693150 # DTB accesses +system.cpu1.dtb.hits 155626125 # DTB hits +system.cpu1.dtb.misses 127972 # DTB misses +system.cpu1.dtb.accesses 155754097 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -988,91 +1182,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 428597912 # ITB inst hits -system.cpu1.itb.inst_misses 76336 # ITB inst misses +system.cpu1.itb.walker.walks 77421 # Table walker walks requested +system.cpu1.itb.walker.walksLong 77421 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4271 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67596 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 77421 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 77421 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 77421 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71867 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24990.746796 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21538.641816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14943.355403 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 66410 92.41% 92.41% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 4449 6.19% 98.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 690 0.96% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 184 0.26% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 29 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 30 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 19 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71867 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1257793296 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1257793296 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1257793296 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 67596 94.06% 94.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4271 5.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71867 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71867 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71867 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 149288 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 434944325 # ITB inst hits +system.cpu1.itb.inst_misses 77421 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51788 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51868 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 19698 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 51781 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 20724 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 53256 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 428674248 # ITB inst accesses -system.cpu1.itb.hits 428597912 # DTB hits -system.cpu1.itb.misses 76336 # DTB misses -system.cpu1.itb.accesses 428674248 # DTB accesses -system.cpu1.numCycles 51781450270 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 435021746 # ITB inst accesses +system.cpu1.itb.hits 434944325 # DTB hits +system.cpu1.itb.misses 77421 # DTB misses +system.cpu1.itb.accesses 435021746 # DTB accesses +system.cpu1.numCycles 51860446884 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 428322492 # Number of instructions committed -system.cpu1.committedOps 503238558 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 462373470 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 457847 # Number of float alu accesses -system.cpu1.num_func_calls 25589000 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 65138542 # number of instructions that are conditional controls -system.cpu1.num_int_insts 462373470 # number of integer instructions -system.cpu1.num_fp_insts 457847 # number of float instructions -system.cpu1.num_int_register_reads 672243876 # number of times the integer registers were read -system.cpu1.num_int_register_writes 366665103 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 741025 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 381476 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 111687570 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 111401234 # number of times the CC registers were written -system.cpu1.num_mem_refs 153562143 # number of memory refs -system.cpu1.num_load_insts 80482788 # Number of load instructions -system.cpu1.num_store_insts 73079355 # Number of store instructions -system.cpu1.num_idle_cycles 50246687172.676186 # Number of idle cycles -system.cpu1.num_busy_cycles 1534763097.323812 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029639 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970361 # Percentage of idle cycles -system.cpu1.Branches 95580848 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 348749586 69.26% 69.26% # Class of executed instruction -system.cpu1.op_class::IntMult 1110324 0.22% 69.48% # Class of executed instruction -system.cpu1.op_class::IntDiv 49704 0.01% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 2 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 8 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 12 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 56056 0.01% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::MemRead 80482788 15.98% 85.49% # Class of executed instruction -system.cpu1.op_class::MemWrite 73079355 14.51% 100.00% # Class of executed instruction +system.cpu1.committedInsts 434661823 # Number of instructions committed +system.cpu1.committedOps 510900396 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 469262912 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 444776 # Number of float alu accesses +system.cpu1.num_func_calls 25944068 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66238146 # number of instructions that are conditional controls +system.cpu1.num_int_insts 469262912 # number of integer instructions +system.cpu1.num_fp_insts 444776 # number of float instructions +system.cpu1.num_int_register_reads 683773696 # number of times the integer registers were read +system.cpu1.num_int_register_writes 372368162 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 716331 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 377944 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113908068 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113630972 # number of times the CC registers were written +system.cpu1.num_mem_refs 155618629 # number of memory refs +system.cpu1.num_load_insts 81496317 # Number of load instructions +system.cpu1.num_store_insts 74122312 # Number of store instructions +system.cpu1.num_idle_cycles 50297346072.144875 # Number of idle cycles +system.cpu1.num_busy_cycles 1563100811.855124 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030141 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969859 # Percentage of idle cycles +system.cpu1.Branches 97056682 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 354376144 69.32% 69.32% # Class of executed instruction +system.cpu1.op_class::IntMult 1097996 0.21% 69.54% # Class of executed instruction +system.cpu1.op_class::IntDiv 48675 0.01% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 2 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 5 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 9 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 55297 0.01% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::MemRead 81496317 15.94% 85.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 74122312 14.50% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 503527836 # Class of executed instruction +system.cpu1.op_class::total 511196757 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40424 # Transaction distribution -system.iobus.trans_dist::ReadResp 40424 # Transaction distribution +system.iobus.trans_dist::ReadReq 40404 # Transaction distribution +system.iobus.trans_dist::ReadResp 40404 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1092,11 +1326,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1113,11 +1347,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7493014 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1146,71 +1380,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042410724 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042408857 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179081273 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179045538 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115504 # number of replacements -system.iocache.tags.tagsinuse 10.454717 # Cycle average of tags in use +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.461673 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115520 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13154373196000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.509635 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.945082 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219352 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434068 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653420 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13154364038000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.508099 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.953575 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219256 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434598 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653855 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040055 # Number of tag accesses -system.iocache.tags.data_accesses 1040055 # Number of data accesses +system.iocache.tags.tag_accesses 1039875 # Number of tag accesses +system.iocache.tags.data_accesses 1039875 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8858 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8895 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8858 # number of demand (read+write) misses -system.iocache.demand_misses::total 8898 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses +system.iocache.demand_misses::total 8878 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8858 # number of overall misses -system.iocache.overall_misses::total 8898 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1913667012 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1919146012 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8838 # number of overall misses +system.iocache.overall_misses::total 8878 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1903038512 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1908523512 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28832566439 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28832566439 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1913667012 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1919485012 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1913667012 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1919485012 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28811758807 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28811758807 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1903038512 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1908862512 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1903038512 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1908862512 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8858 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8895 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8858 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8898 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8858 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8898 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1224,55 +1458,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 216038.271845 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 215755.594379 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 215324.565739 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 215044.902761 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270312.068167 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270312.068167 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 216038.271845 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 215720.949876 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 216038.271845 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 215720.949876 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223529 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270116.991740 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270116.991740 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 215324.565739 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 215010.420365 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 215324.565739 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 215010.420365 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 222004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27514 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27403 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.124191 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.101449 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8858 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8895 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8858 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8898 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8858 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8898 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1452961512 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1456516512 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1443371512 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1446932512 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR 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WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23265154883 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1443371512 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1447115512 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1443371512 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1447115512 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 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latency +system.iocache.overall_avg_mshr_miss_latency::total 163000.170309 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1132290 # number of replacements -system.l2c.tags.tagsinuse 65332.905134 # Cycle average of tags in use -system.l2c.tags.total_refs 26887895 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1194294 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 22.513631 # Average number of references to valid blocks. +system.l2c.tags.replacements 1193420 # number of replacements +system.l2c.tags.tagsinuse 65274.322363 # Cycle average of tags in use +system.l2c.tags.total_refs 27445630 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1256045 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.850833 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 6379783000 # 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(read+write) hits -system.l2c.demand_hits::total 21959810 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 218363 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 160178 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6707988 # number of overall hits -system.l2c.overall_hits::cpu0.data 3840973 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 224681 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 161726 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6694510 # number of overall hits -system.l2c.overall_hits::cpu1.data 3951391 # number of overall hits -system.l2c.overall_hits::total 21959810 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1675 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1602 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 36219 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 126965 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1513 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1620 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 38912 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 123410 # number of ReadReq misses -system.l2c.ReadReq_misses::total 331916 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 247597 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 246465 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 494062 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17085 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16773 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 33858 # number of UpgradeReq misses +system.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id 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latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61075.907990 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60985.278209 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61031.289289 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61909.009377 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61919.698834 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61930.149616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61909.009377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61919.698834 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61930.149616 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1755,57 +1997,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 417721 # Transaction distribution -system.membus.trans_dist::ReadResp 417721 # Transaction distribution -system.membus.trans_dist::WriteReq 33871 # Transaction distribution -system.membus.trans_dist::WriteResp 33871 # Transaction distribution -system.membus.trans_dist::Writeback 1069486 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 600721 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 600721 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34423 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34424 # Transaction distribution -system.membus.trans_dist::ReadExReq 397977 # Transaction distribution -system.membus.trans_dist::ReadExResp 397977 # Transaction distribution +system.membus.trans_dist::ReadReq 431429 # Transaction distribution +system.membus.trans_dist::ReadResp 431429 # Transaction distribution +system.membus.trans_dist::WriteReq 33873 # Transaction distribution +system.membus.trans_dist::WriteResp 33873 # Transaction distribution +system.membus.trans_dist::Writeback 1122241 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 608883 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 608883 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35220 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35222 # Transaction distribution +system.membus.trans_dist::ReadExReq 436846 # Transaction distribution +system.membus.trans_dist::ReadExResp 436846 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3570318 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3700502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 334782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4035284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3746179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3876375 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 334941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4211316 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 140106848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 140277172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14030080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14030080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 154307252 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3630 # Total snoops (count) -system.membus.snoop_fanout::samples 2443419 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147371488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 147541836 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14041536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14041536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 161583372 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3431 # Total snoops (count) +system.membus.snoop_fanout::samples 2557707 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2443419 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2557707 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2443419 # Request fanout histogram -system.membus.reqLayer0.occupancy 107392500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2557707 # Request fanout histogram +system.membus.reqLayer0.occupancy 107352000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5575997 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5560499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16318205493 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 16960886493 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7697194309 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8211852015 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186789727 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186625462 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1849,55 +2091,55 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 21137473 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21129474 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33871 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33871 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7479557 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1332565 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1225901 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43231 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43232 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2014651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2014651 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27041508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27036574 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 774452 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1144323 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 55996857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 862740756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1097639072 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2601008 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3569856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 1966550692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 492520 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 31930568 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003619 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.060051 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 21612149 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21604161 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33873 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33873 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7621991 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1335253 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1228589 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 44226 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44228 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2062852 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2062852 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27641812 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27580079 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 784917 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1183820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 57190628 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 881950484 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1119524728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2643752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3719680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2007838644 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 494311 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 32599559 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003544 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.059428 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 31815006 99.64% 99.64% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115562 0.36% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 32484017 99.65% 99.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 31930568 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 50801737999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 32599559 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 51716744749 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 4033500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 3993000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 60715950506 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 62067119757 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 38798201181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 39696027226 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 449711000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 454863250 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 698488000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 719296500 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index d01497065..0f19127f8 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125918 # Number of seconds simulated -sim_ticks 5125917808500 # Number of ticks simulated -final_tick 5125917808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.125948 # Number of seconds simulated +sim_ticks 5125948496500 # Number of ticks simulated +final_tick 5125948496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163224 # Simulator instruction rate (inst/s) -host_op_rate 322646 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2051147218 # Simulator tick rate (ticks/s) -host_mem_usage 753920 # Number of bytes of host memory used -host_seconds 2499.05 # Real time elapsed on the host -sim_insts 407905794 # Number of instructions simulated -sim_ops 806307064 # Number of ops (including micro ops) simulated +host_inst_rate 181287 # Simulator instruction rate (inst/s) +host_op_rate 358347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2277524092 # Simulator tick rate (ticks/s) +host_mem_usage 808864 # Number of bytes of host memory used +host_seconds 2250.67 # Real time elapsed on the host +sim_insts 408017153 # Number of instructions simulated +sim_ops 806519171 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1044736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10779456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1048640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10814912 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11857920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1044736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1044736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9592896 # Number of bytes written to this memory -system.physmem.bytes_written::total 9592896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 78 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11896448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1048640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1048640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9598912 # Number of bytes written to this memory +system.physmem.bytes_written::total 9598912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16385 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168983 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185280 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149889 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149889 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 974 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 185882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149983 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149983 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 203814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2102932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 204575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2109836 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2313326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1871449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1871449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1871449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2320829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 204575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 204575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1872612 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1872612 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1872612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2102932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 204575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2109836 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4184776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185280 # Number of read requests accepted -system.physmem.writeReqs 196609 # Number of write requests accepted -system.physmem.readBursts 185280 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196609 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11848512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 12427072 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11857920 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12582976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2411 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1705 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11356 # Per bank write bursts -system.physmem.perBankRdBursts::1 10792 # Per bank write bursts -system.physmem.perBankRdBursts::2 11765 # Per bank write bursts -system.physmem.perBankRdBursts::3 11427 # Per bank write bursts -system.physmem.perBankRdBursts::4 11775 # Per bank write bursts -system.physmem.perBankRdBursts::5 11293 # Per bank write bursts -system.physmem.perBankRdBursts::6 11205 # Per bank write bursts -system.physmem.perBankRdBursts::7 11692 # Per bank write bursts -system.physmem.perBankRdBursts::8 11087 # Per bank write bursts -system.physmem.perBankRdBursts::9 11285 # Per bank write bursts -system.physmem.perBankRdBursts::10 11605 # Per bank write bursts -system.physmem.perBankRdBursts::11 12031 # Per bank write bursts -system.physmem.perBankRdBursts::12 11880 # Per bank write bursts -system.physmem.perBankRdBursts::13 12674 # Per bank write bursts -system.physmem.perBankRdBursts::14 11994 # Per bank write bursts -system.physmem.perBankRdBursts::15 11272 # Per bank write bursts -system.physmem.perBankWrBursts::0 13000 # Per bank write bursts -system.physmem.perBankWrBursts::1 12435 # Per bank write bursts -system.physmem.perBankWrBursts::2 11147 # Per bank write bursts -system.physmem.perBankWrBursts::3 11517 # Per bank write bursts -system.physmem.perBankWrBursts::4 12452 # Per bank write bursts -system.physmem.perBankWrBursts::5 12346 # Per bank write bursts -system.physmem.perBankWrBursts::6 11719 # Per bank write bursts -system.physmem.perBankWrBursts::7 11239 # Per bank write bursts -system.physmem.perBankWrBursts::8 12215 # Per bank write bursts -system.physmem.perBankWrBursts::9 12097 # Per bank write bursts -system.physmem.perBankWrBursts::10 12764 # Per bank write bursts -system.physmem.perBankWrBursts::11 12134 # Per bank write bursts -system.physmem.perBankWrBursts::12 12379 # Per bank write bursts -system.physmem.perBankWrBursts::13 12264 # Per bank write bursts -system.physmem.perBankWrBursts::14 12219 # Per bank write bursts -system.physmem.perBankWrBursts::15 12246 # Per bank write bursts +system.physmem.bw_total::total 4193440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185882 # Number of read requests accepted +system.physmem.writeReqs 196703 # Number of write requests accepted +system.physmem.readBursts 185882 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196703 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11884864 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue +system.physmem.bytesWritten 12459008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11896448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12588992 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2006 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1725 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11442 # Per bank write bursts +system.physmem.perBankRdBursts::1 11010 # Per bank write bursts +system.physmem.perBankRdBursts::2 11990 # Per bank write bursts +system.physmem.perBankRdBursts::3 11673 # Per bank write bursts +system.physmem.perBankRdBursts::4 12100 # Per bank write bursts +system.physmem.perBankRdBursts::5 11243 # Per bank write bursts +system.physmem.perBankRdBursts::6 11527 # Per bank write bursts +system.physmem.perBankRdBursts::7 11544 # Per bank write bursts +system.physmem.perBankRdBursts::8 11275 # Per bank write bursts +system.physmem.perBankRdBursts::9 11901 # Per bank write bursts +system.physmem.perBankRdBursts::10 11758 # Per bank write bursts +system.physmem.perBankRdBursts::11 11788 # Per bank write bursts +system.physmem.perBankRdBursts::12 11617 # Per bank write bursts +system.physmem.perBankRdBursts::13 12244 # Per bank write bursts +system.physmem.perBankRdBursts::14 11799 # Per bank write bursts +system.physmem.perBankRdBursts::15 10790 # Per bank write bursts +system.physmem.perBankWrBursts::0 14290 # Per bank write bursts +system.physmem.perBankWrBursts::1 13466 # Per bank write bursts +system.physmem.perBankWrBursts::2 12356 # Per bank write bursts +system.physmem.perBankWrBursts::3 11306 # Per bank write bursts +system.physmem.perBankWrBursts::4 11781 # Per bank write bursts +system.physmem.perBankWrBursts::5 11472 # Per bank write bursts +system.physmem.perBankWrBursts::6 11444 # Per bank write bursts +system.physmem.perBankWrBursts::7 11849 # Per bank write bursts +system.physmem.perBankWrBursts::8 11105 # Per bank write bursts +system.physmem.perBankWrBursts::9 11337 # Per bank write bursts +system.physmem.perBankWrBursts::10 12902 # Per bank write bursts +system.physmem.perBankWrBursts::11 12297 # Per bank write bursts +system.physmem.perBankWrBursts::12 12359 # Per bank write bursts +system.physmem.perBankWrBursts::13 12104 # Per bank write bursts +system.physmem.perBankWrBursts::14 12504 # Per bank write bursts +system.physmem.perBankWrBursts::15 12100 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5125917756500 # Total gap between requests +system.physmem.totGap 5125948445000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185280 # Read request sizes (log2) +system.physmem.readPktSize::6 185882 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196609 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196703 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,435 +156,440 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 11003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 11503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 14022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 13789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10718 # What write queue length does an incoming req see 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write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.738348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.730188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.091209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27875 37.17% 37.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17344 23.13% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7346 9.80% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4205 5.61% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3044 4.06% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1991 2.66% 82.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1466 1.96% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1106 1.47% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10608 14.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74985 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7802 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.727634 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.765031 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7801 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 75254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.488559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.903299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.428888 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27891 37.06% 37.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17298 22.99% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7596 10.09% 70.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4208 5.59% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3159 4.20% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2000 2.66% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1345 1.79% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1163 1.55% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10594 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75254 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7808 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.780866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 544.702276 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7807 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7802 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.887593 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.377135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.103132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6364 81.57% 81.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 53 0.68% 82.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 22 0.28% 82.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 275 3.52% 86.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 179 2.29% 88.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 0.68% 89.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 27 0.35% 89.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 51 0.65% 90.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 164 2.10% 92.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.22% 92.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.17% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.18% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 32 0.41% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 25 0.32% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.09% 93.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 50 0.64% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 101 1.29% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 9 0.12% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 29 0.37% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 150 1.92% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 8 0.10% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.09% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 28 0.36% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.05% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.14% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.05% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 23 0.29% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.09% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.04% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 14 0.18% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 10 0.13% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.12% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7802 # Writes before turning the bus around for reads -system.physmem.totQLat 2011030750 # Total ticks spent queuing -system.physmem.totMemAccLat 5482274500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 925665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10862.63 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7808 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.932377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.361157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.539970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6379 81.70% 81.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 49 0.63% 82.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 9 0.12% 82.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 259 3.32% 85.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 187 2.39% 88.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 53 0.68% 88.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 34 0.44% 89.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 61 0.78% 90.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 178 2.28% 92.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.24% 92.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 13 0.17% 92.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.18% 92.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 27 0.35% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.24% 93.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 50 0.64% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 97 1.24% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.10% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 20 0.26% 95.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 156 2.00% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 7 0.09% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 10 0.13% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 29 0.37% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 11 0.14% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.05% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.20% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 10 0.13% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.08% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.09% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.14% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 10 0.13% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 7 0.09% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 4 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7808 # Writes before turning the bus around for reads +system.physmem.totQLat 1993300749 # Total ticks spent queuing +system.physmem.totMemAccLat 5475194499 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 928505000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10733.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29612.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29483.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.38 # Average write queue length when enqueuing -system.physmem.readRowHits 151985 # Number of row buffer hits during reads -system.physmem.writeRowHits 152335 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.44 # Row buffer hit rate for writes -system.physmem.avgGap 13422533.14 # Average gap between requests -system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4919402035500 # Time in different power states -system.physmem.memoryStateTime::REF 171165540000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 35350129500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 274957200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 291929400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 150026250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 159286875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 712179000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 731850600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 621140400 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 637100640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 334799796240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 334799796240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 129444240060 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 129652397505 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 2962001074500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2961818480250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3428003413650 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3428090841510 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.759392 # Core power per rank (mW) -system.physmem.averagePower::1 668.776448 # Core power per rank (mW) -system.cpu.branchPred.lookups 86891854 # Number of BP lookups -system.cpu.branchPred.condPredicted 86891854 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 902474 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80057154 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78172464 # Number of BTB hits +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.04 # Average write queue length when enqueuing +system.physmem.readRowHits 152642 # Number of row buffer hits during reads +system.physmem.writeRowHits 152476 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.31 # Row buffer hit rate for writes +system.physmem.avgGap 13398195.03 # Average gap between requests +system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 279704880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 152616750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 721718400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 634806720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129444104115 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2962019880750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3428054662095 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.765327 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4927513863750 # Time in different power states +system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27267949750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 289215360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 157806000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726741600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 626667840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129734124390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2961765477000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3428101862670 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.774535 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4927089550750 # Time in different power states +system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27689450500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 86963954 # Number of BP lookups +system.cpu.branchPred.condPredicted 86963954 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 905408 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80060833 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78220075 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.645819 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1556145 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178539 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.700801 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1554669 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179026 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449528542 # number of cpu cycles simulated +system.cpu.numCycles 449722784 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27579139 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429063602 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86891854 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79728609 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417924990 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1892404 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 141641 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 49747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 210937 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 127048 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 749 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9185584 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 447344 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4767 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 446980453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051866 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27725020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429300438 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86963954 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79774744 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417978242 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1899598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 143976 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 49214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 212054 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 124897 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 365 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9198894 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 449574 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4910 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 447183567 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894463 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051838 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281454432 62.97% 62.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2285018 0.51% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72162718 16.14% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1595292 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2151182 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2328836 0.52% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1532887 0.34% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1872269 0.42% 81.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81597819 18.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281562684 62.96% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2296710 0.51% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72185404 16.14% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1608090 0.36% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2152491 0.48% 80.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2328628 0.52% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1534045 0.34% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1900420 0.42% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81615095 18.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 446980453 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193296 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954475 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23006879 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264875775 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150713064 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7438533 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 946202 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838427175 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 946202 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25861517 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223289477 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13277674 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154607234 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 28998349 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834936902 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 476513 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12412504 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 177326 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13726812 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997336716 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1813473834 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114859292 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964283425 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33053286 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468997 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473016 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39075310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17327574 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10191135 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1313699 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1076527 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829405798 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1211413 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824144334 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 238741 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23374016 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36157635 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 155810 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 446980453 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843804 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418028 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 447183567 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193372 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954589 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23075597 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264910108 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150816162 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7431901 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 949799 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838865197 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 949799 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25926245 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223342995 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13219671 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154710115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29034742 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 835373495 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 478818 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12412845 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 182552 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13765619 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997850152 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1814454577 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1115386152 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 142 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964539686 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33310464 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 468855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 472576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 39019315 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17353635 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10197147 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1310615 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1095058 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829813890 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1210662 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824509848 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 239912 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23585262 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36379120 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 154680 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 447183567 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418075 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262751782 58.78% 58.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13860127 3.10% 61.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10088289 2.26% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6929216 1.55% 65.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74323701 16.63% 82.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4464363 1.00% 83.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72802131 16.29% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1196176 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 564668 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262867260 58.78% 58.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13875410 3.10% 61.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10102524 2.26% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6917845 1.55% 65.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74366987 16.63% 82.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4460507 1.00% 83.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72819289 16.28% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1200322 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 573423 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 446980453 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 447183567 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1984017 71.87% 71.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 212 0.01% 71.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1649 0.06% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 613790 22.24% 94.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160788 5.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1986412 71.97% 71.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 252 0.01% 71.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1233 0.04% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 612541 22.19% 94.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159591 5.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 292283 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795766200 96.56% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150572 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125282 0.02% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 8 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18411850 2.23% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9398139 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 292966 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796097417 96.55% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150721 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125468 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18437939 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9405337 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824144334 # Type of FU issued -system.cpu.iq.rate 1.833353 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2760456 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2098268090 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854003641 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819590055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 270 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 824509848 # Type of FU issued +system.cpu.iq.rate 1.833374 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2760029 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2099202980 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854622338 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819935754 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826612402 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 105 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1877597 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 826976810 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1879265 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3329866 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14364 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14470 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1763076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3349902 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15405 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14537 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1763571 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224552 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 71468 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 72078 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 946202 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205595274 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9411486 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 830617211 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 184433 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17327584 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10191135 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 714161 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 416193 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8093117 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14470 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 516905 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 536436 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1053341 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822534076 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18016449 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1476395 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 949799 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205606066 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9444034 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831024552 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 186671 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17353635 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10197147 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 713788 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 414805 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8129418 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14537 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 518368 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 539118 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1057486 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822883825 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18037381 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1492626 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27187129 # number of memory reference insts executed -system.cpu.iew.exec_branches 83286990 # Number of branches executed -system.cpu.iew.exec_stores 9170680 # Number of stores executed -system.cpu.iew.exec_rate 1.829771 # Inst execution rate -system.cpu.iew.wb_sent 822027813 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819590117 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640953314 # num instructions producing a value -system.cpu.iew.wb_consumers 1050450596 # num instructions consuming a value +system.cpu.iew.exec_refs 27216272 # number of memory reference insts executed +system.cpu.iew.exec_branches 83330623 # Number of branches executed +system.cpu.iew.exec_stores 9178891 # Number of stores executed +system.cpu.iew.exec_rate 1.829758 # Inst execution rate +system.cpu.iew.wb_sent 822374066 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819935816 # cumulative count of insts written-back +system.cpu.iew.wb_producers 641195588 # num instructions producing a value +system.cpu.iew.wb_consumers 1050795800 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823222 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610170 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823203 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610200 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24215626 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1055602 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443339838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818711 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675515 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24410170 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1055982 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 917776 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443513895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675053 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272569121 61.48% 61.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11207092 2.53% 64.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3543073 0.80% 64.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74545535 16.81% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2433206 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1610406 0.36% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 913346 0.21% 82.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71032181 16.02% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5485878 1.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272662791 61.48% 61.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11205596 2.53% 64.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3584252 0.81% 64.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74566158 16.81% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2433850 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1609395 0.36% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 952580 0.21% 82.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71045442 16.02% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5453831 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443339838 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407905794 # Number of instructions committed -system.cpu.commit.committedOps 806307064 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443513895 # Number of insts commited each cycle +system.cpu.commit.committedInsts 408017153 # Number of instructions committed +system.cpu.commit.committedOps 806519171 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22425775 # Number of memory references committed -system.cpu.commit.loads 13997716 # Number of loads committed -system.cpu.commit.membars 475203 # Number of memory barriers committed -system.cpu.commit.branches 82185787 # Number of branches committed +system.cpu.commit.refs 22437308 # Number of memory references committed +system.cpu.commit.loads 14003732 # Number of loads committed +system.cpu.commit.membars 475345 # Number of memory barriers committed +system.cpu.commit.branches 82208289 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735131032 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155610 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174231 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783440615 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144913 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121530 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735327062 # Number of committed integer instructions. +system.cpu.commit.function_calls 1156001 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174296 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783640915 97.16% 97.18% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 145051 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121601 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -611,167 +616,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13997716 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8428059 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14003732 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8433576 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806307064 # Class of committed instruction -system.cpu.commit.bw_lim_events 5485878 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806519171 # Class of committed instruction +system.cpu.commit.bw_lim_events 5453831 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1268298437 # The number of ROB reads -system.cpu.rob.rob_writes 1664703185 # The number of ROB writes -system.cpu.timesIdled 295137 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2548089 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9802307300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407905794 # Number of Instructions Simulated -system.cpu.committedOps 806307064 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.102040 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.102040 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907408 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907408 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092406866 # number of integer regfile reads -system.cpu.int_regfile_writes 656005719 # number of integer regfile writes +system.cpu.rob.rob_reads 1268911189 # The number of ROB reads +system.cpu.rob.rob_writes 1665544826 # The number of ROB writes +system.cpu.timesIdled 297395 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2539217 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9802174458 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 408017153 # Number of Instructions Simulated +system.cpu.committedOps 806519171 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.102215 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.102215 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907264 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907264 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092796597 # number of integer regfile reads +system.cpu.int_regfile_writes 656284247 # number of integer regfile writes system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.cc_regfile_reads 416194474 # number of cc regfile reads -system.cpu.cc_regfile_writes 322040205 # number of cc regfile writes -system.cpu.misc_regfile_reads 265569258 # number of misc regfile reads -system.cpu.misc_regfile_writes 402671 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1659070 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.990007 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19130419 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659582 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.527251 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 416355955 # number of cc regfile reads +system.cpu.cc_regfile_writes 322152728 # number of cc regfile writes +system.cpu.misc_regfile_reads 265715662 # number of misc regfile reads +system.cpu.misc_regfile_writes 402877 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1660514 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996956 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19150908 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1661026 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.529565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.990007 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999980 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999980 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996956 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88317394 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88317394 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10978879 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10978879 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8084521 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8084521 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 64338 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 64338 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19063400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19063400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19127738 # number of overall hits -system.cpu.dcache.overall_hits::total 19127738 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1796470 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1796470 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 333911 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 333911 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406328 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406328 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2130381 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2130381 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2536709 # number of overall misses -system.cpu.dcache.overall_misses::total 2536709 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26526077953 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26526077953 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12856931699 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12856931699 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39383009652 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39383009652 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39383009652 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39383009652 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12775349 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12775349 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8418432 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8418432 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 470666 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 470666 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21193781 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21193781 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21664447 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21664447 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140620 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.140620 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039664 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039664 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863304 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.863304 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100519 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100519 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117091 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117091 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.667088 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.667088 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38504.067548 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38504.067548 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18486.369176 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18486.369176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15525.237484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15525.237484 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 375690 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88414778 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88414778 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10992291 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10992291 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8090245 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8090245 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 65628 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 65628 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19082536 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19082536 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19148164 # number of overall hits +system.cpu.dcache.overall_hits::total 19148164 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1800200 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1800200 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 333674 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 333674 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406398 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406398 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2133874 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2133874 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2540272 # number of overall misses +system.cpu.dcache.overall_misses::total 2540272 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26575138519 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26575138519 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12884484816 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12884484816 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39459623335 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39459623335 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39459623335 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39459623335 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12792491 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12792491 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8423919 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8423919 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 472026 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 472026 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21216410 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21216410 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21688436 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21688436 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140723 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.140723 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039610 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039610 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.860965 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.860965 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.100577 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100577 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117126 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117126 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14762.325585 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14762.325585 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38613.990949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38613.990949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18492.011869 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18492.011869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15533.621335 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15533.621335 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 372367 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39932 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 40008 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.408244 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.307314 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560667 # number of writebacks -system.cpu.dcache.writebacks::total 1560667 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827312 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 827312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44114 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44114 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 871426 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 871426 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 871426 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 871426 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969158 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 969158 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289797 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289797 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402869 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402869 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1258955 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1258955 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1661824 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1661824 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12253110515 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12253110515 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11193391556 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11193391556 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5590029250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5590029250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23446502071 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23446502071 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29036531321 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29036531321 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97386643000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97386643000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2557063000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2557063000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99943706000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99943706000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075862 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075862 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855955 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855955 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.writebacks::writebacks 1561114 # number of writebacks +system.cpu.dcache.writebacks::total 1561114 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829484 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 829484 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44098 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44098 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 873582 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 873582 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 873582 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 873582 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970716 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 970716 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289576 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289576 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402937 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402937 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1260292 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1260292 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1663229 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1663229 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12259067013 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12259067013 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11217533642 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11217533642 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5591612757 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5591612757 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23476600655 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23476600655 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29068213412 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29068213412 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390347000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390347000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564142000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564142000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954489000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954489000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.853633 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.853633 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059402 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.059402 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076707 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076707 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12643.047382 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12643.047382 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38624.939375 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38624.939375 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13875.550737 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13875.550737 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18623.780891 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18623.780891 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.687433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.687433 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076687 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076687 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12628.891471 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12628.891471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38737.787807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38737.787807 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.138999 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.138999 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18627.905799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18627.905799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17476.976058 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17476.976058 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -779,58 +784,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 73854 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.812426 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 117340 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 73869 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.588488 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812426 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988277 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988277 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 73235 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.785723 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 116281 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 73250 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.587454 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785723 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986608 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986608 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 459584 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 459584 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117385 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 117385 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117385 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 117385 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117385 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 117385 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74938 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 74938 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74938 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 74938 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74938 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 74938 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 912423463 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 912423463 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 912423463 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 912423463 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 912423463 # number of overall miss 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-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389647 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389647 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389647 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389647 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12175.711428 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12175.711428 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12175.711428 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12175.711428 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12175.711428 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12175.711428 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 455451 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 455451 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116283 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 116283 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116283 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 116283 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116283 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 116283 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74295 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 74295 # number of ReadReq misses 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overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190578 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 190578 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190578 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 190578 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 190578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389840 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389840 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389840 # miss rate for demand accesses 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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,180 +844,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 19615 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 19615 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74938 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74938 # number of ReadReq MSHR misses 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mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10174.099829 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10174.099829 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20236 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20236 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74295 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74295 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74295 # number of demand (read+write) MSHR misses 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cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389840 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389840 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389840 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389840 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10323.769810 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10323.769810 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10323.769810 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10323.769810 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 996223 # number of replacements -system.cpu.icache.tags.tagsinuse 510.034964 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8125334 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 996735 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.151950 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit. 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-system.cpu.icache.ReadReq_miss_latency::total 14710988702 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14710988702 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14710988702 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14710988702 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14710988702 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9185580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9185580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9185580 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9185580 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9185580 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9185580 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13875.071165 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13875.071165 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13875.071165 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13875.071165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13875.071165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13875.071165 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8852 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10200177 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10200177 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8133580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8133580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8133580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8133580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8133580 # number of overall hits +system.cpu.icache.overall_hits::total 8133580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1065313 # number of ReadReq misses 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12075236643 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12075236643 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12075236643 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108516 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108516 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108516 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108516 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12114.195897 # average ReadReq mshr miss latency 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12122903243 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12122903243 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12122903243 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108848 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108848 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108848 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108848 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12107.357396 # average ReadReq mshr miss latency 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-system.cpu.itb_walker_cache.tags.avg_refs 1.900886 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104067070500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017843 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376115 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376115 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 14176 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.015804 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 26673 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 14191 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.879572 # Average number of references to valid blocks. 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number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26180 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26180 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26180 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26180 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14640 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14640 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14640 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14640 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14640 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14640 # number of overall misses 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ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174774993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 174774993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174774993 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 174774993 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41734 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41734 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40820 # number of demand (read+write) accesses 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average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11537.636407 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11537.636407 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11537.636407 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11537.636407 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11537.636407 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41736 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41736 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41736 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41736 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.360857 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.360857 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.360840 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.360840 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.360840 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.360840 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11605.245219 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11605.245219 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11605.245219 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11605.245219 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11605.245219 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11605.245219 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1021,177 +1026,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 3000 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 3000 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14640 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14640 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14640 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14640 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14640 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14640 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 139618019 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 139618019 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 139618019 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 139618019 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 139618019 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 139618019 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358665 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358665 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358648 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358648 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358648 # mshr miss rate for overall accesses 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3266.844648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11101.886147 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769445 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50385.421591 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.865695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.131540 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3266.822655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11149.599847 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768821 # 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number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 65 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16326 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169384 # number of overall misses -system.cpu.l2cache.overall_misses::total 185794 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6504500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 472000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1249428250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2850151495 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4106556245 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17517303 # number of UpgradeReq miss cycles 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cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1043304250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10060190034 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11109197784 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89275614000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89275614000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2397124500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2397124500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91672738500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91672738500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000478 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.831154 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.831154 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.466352 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.466352 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000478 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102338 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067972 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000478 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102338 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067972 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67833.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63674.351541 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66724.071393 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65787.351416 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10634.365937 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10634.365937 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57191.006802 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57191.006802 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67833.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63674.351541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59202.662504 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59603.816765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81484.615385 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67833.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63674.351541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59202.662504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59603.816765 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1300,63 +1305,63 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3068576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3068035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1583282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3074514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3073974 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1584244 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2219 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2219 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 12 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1993478 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130100 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 29738 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 161735 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8315051 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63788416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207873825 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 966272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5555008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278183521 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 59487 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4379111 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010877 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103722 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6133560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30509 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162399 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8328931 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64075456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207996475 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 988736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5638656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278699323 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 58087 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4385762 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103651 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4331481 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47630 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4338126 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47636 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4379111 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4067623882 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4385762 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4071958893 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 571500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1499268850 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1506070002 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141964932 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3144166318 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 21966489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 22600980 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 112467385 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 111516357 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225657 # Transaction distribution -system.iobus.trans_dist::ReadResp 225657 # Transaction distribution -system.iobus.trans_dist::WriteReq 57676 # Transaction distribution -system.iobus.trans_dist::WriteResp 10956 # Transaction distribution +system.iobus.trans_dist::ReadReq 225687 # Transaction distribution +system.iobus.trans_dist::ReadResp 225687 # Transaction distribution +system.iobus.trans_dist::WriteReq 57721 # Transaction distribution +system.iobus.trans_dist::WriteResp 11001 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1641 # Transaction distribution -system.iobus.trans_dist::MessageResp 1641 # Transaction distribution +system.iobus.trans_dist::MessageReq 1644 # Transaction distribution +system.iobus.trans_dist::MessageResp 1644 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -1372,15 +1377,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471406 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 570104 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -1396,19 +1401,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 241980 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276506 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1438,54 +1443,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448438152 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448361200 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460450000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52358513 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52371753 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.091509 # Cycle average of tags in use +system.iocache.tags.replacements 47581 # number of replacements +system.iocache.tags.tagsinuse 0.091546 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47597 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992976927000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091509 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005719 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005719 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992992715000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091546 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005722 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005722 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428670 # Number of tag accesses -system.iocache.tags.data_accesses 428670 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.tags.tag_accesses 428724 # Number of tag accesses +system.iocache.tags.data_accesses 428724 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses +system.iocache.ReadReq_misses::total 916 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses -system.iocache.demand_misses::total 910 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses -system.iocache.overall_misses::total 910 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151600663 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 151600663 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12348426976 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12348426976 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 151600663 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 151600663 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 151600663 # number of overall miss cycles -system.iocache.overall_miss_latency::total 151600663 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses +system.iocache.demand_misses::total 916 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses +system.iocache.overall_misses::total 916 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149161446 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149161446 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12345702001 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12345702001 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 149161446 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 149161446 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 149161446 # number of overall miss cycles +system.iocache.overall_miss_latency::total 149161446 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1494,40 +1499,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 166594.135165 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264307.084247 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264307.084247 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 166594.135165 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166594.135165 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 166594.135165 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70653 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162840.006550 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264248.758583 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264248.758583 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 162840.006550 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 162840.006550 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70237 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9154 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9120 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.718265 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.701425 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104259663 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918961002 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918961002 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 104259663 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104259663 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 104259663 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 101504946 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9916256007 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9916256007 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 101504946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 101504946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1536,79 +1541,79 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 114571.058242 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212306.528296 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212306.528296 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 114571.058242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 114571.058242 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110813.259825 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212248.630287 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212248.630287 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662598 # Transaction distribution -system.membus.trans_dist::ReadResp 662586 # Transaction distribution -system.membus.trans_dist::WriteReq 13841 # Transaction distribution -system.membus.trans_dist::WriteResp 13841 # Transaction distribution -system.membus.trans_dist::Writeback 149889 # Transaction distribution +system.membus.trans_dist::ReadReq 662646 # Transaction distribution +system.membus.trans_dist::ReadResp 662640 # Transaction distribution +system.membus.trans_dist::WriteReq 13889 # Transaction distribution +system.membus.trans_dist::WriteResp 13889 # Transaction distribution +system.membus.trans_dist::Writeback 149983 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2184 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1723 # Transaction distribution -system.membus.trans_dist::ReadExReq 133213 # Transaction distribution -system.membus.trans_dist::ReadExResp 133211 # Transaction distribution -system.membus.trans_dist::MessageReq 1641 # Transaction distribution -system.membus.trans_dist::MessageResp 1641 # Transaction distribution -system.membus.trans_dist::BadAddressError 12 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471406 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775060 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723935 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141460 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141460 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1868677 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550117 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18435776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20227873 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2187 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1743 # Transaction distribution +system.membus.trans_dist::ReadExReq 133791 # Transaction distribution +system.membus.trans_dist::ReadExResp 133789 # Transaction distribution +system.membus.trans_dist::MessageReq 1644 # Transaction distribution +system.membus.trans_dist::MessageResp 1644 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1725388 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1870142 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18480320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20272507 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26239557 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1606 # Total snoops (count) -system.membus.snoop_fanout::samples 385212 # Request fanout histogram +system.membus.pkt_size::total 26284203 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1595 # Total snoops (count) +system.membus.snoop_fanout::samples 385911 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 385212 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 385911 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 385212 # Request fanout histogram -system.membus.reqLayer0.occupancy 251510000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 385911 # Request fanout histogram +system.membus.reqLayer0.occupancy 251714500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583228000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583067000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1995467500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1996777999 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3158524545 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3163999272 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54933487 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54979247 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index b728ac0c9..92c4535bc 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.300742 # Number of seconds simulated -sim_ticks 5300741898500 # Number of ticks simulated -final_tick 5300741898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305804 # Number of seconds simulated +sim_ticks 5305803886500 # Number of ticks simulated +final_tick 5305803886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 268181 # Simulator instruction rate (inst/s) -host_op_rate 514172 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13311463323 # Simulator tick rate (ticks/s) -host_mem_usage 800056 # Number of bytes of host memory used -host_seconds 398.21 # Real time elapsed on the host -sim_insts 106792132 # Number of instructions simulated -sim_ops 204747982 # Number of ops (including micro ops) simulated +host_inst_rate 199055 # Simulator instruction rate (inst/s) +host_op_rate 381625 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9885187347 # Simulator tick rate (ticks/s) +host_mem_usage 854320 # Number of bytes of host memory used +host_seconds 536.74 # Real time elapsed on the host +sim_insts 106841423 # Number of instructions simulated +sim_ops 204834575 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11447360 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11447360 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9142976 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9142976 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 178865 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 178865 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 142859 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 142859 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2159577 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2159577 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1724848 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1724848 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3884425 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3884425 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 178865 # Number of read requests accepted -system.mem_ctrls.writeReqs 142859 # Number of write requests accepted -system.mem_ctrls.readBursts 178865 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 142859 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11390720 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 56640 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9134848 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11447360 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9142976 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 885 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 106 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11434048 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11434048 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9128256 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9128256 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 178657 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 178657 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 142629 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 142629 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2155008 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2155008 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1720428 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1720428 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3875436 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3875436 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 178657 # Number of read requests accepted +system.mem_ctrls.writeReqs 142629 # Number of write requests accepted +system.mem_ctrls.readBursts 178657 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 142629 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11379712 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 54336 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9119680 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11434048 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9128256 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 849 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 11083 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 10466 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 10673 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 10751 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11479 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 11934 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 10746 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10510 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 10984 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 10978 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 10728 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 13966 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 10998 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10695 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11146 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10843 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 9192 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 8887 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 8721 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8884 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9584 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9646 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 8803 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8544 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8749 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 8837 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 8942 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 8982 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 8616 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 8535 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 8942 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8868 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 10773 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10609 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10875 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11019 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11847 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 12404 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 11308 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10254 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10790 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 10382 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10431 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 13895 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 11043 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10450 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 11056 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10672 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8646 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8740 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8909 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9072 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9699 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9645 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8889 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8365 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 8684 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 8653 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 8512 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9107 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 8716 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8645 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9206 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 9007 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5300741764000 # Total gap between requests +system.mem_ctrls.totGap 5305803752000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 178865 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 178657 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 142859 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 177944 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 36 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 142629 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 177742 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 66 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,38 +135,38 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2042 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2762 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8528 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9126 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8582 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9159 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9214 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8343 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9016 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9104 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8438 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8502 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8352 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8474 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8065 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8107 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8180 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 7958 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 136 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 116 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 100 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 96 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 84 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 72 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 32 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 21 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 11 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2048 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2805 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8516 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9095 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8606 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9164 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9192 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8373 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9017 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9032 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8415 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8498 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8325 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8422 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8038 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8077 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8151 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 7943 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 129 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 121 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 110 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 90 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 88 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 71 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 51 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 13 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -184,74 +184,73 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60353 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 340.090865 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 200.552614 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 345.449556 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20341 33.70% 33.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14451 23.94% 57.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6322 10.48% 68.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3381 5.60% 73.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2729 4.52% 78.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1822 3.02% 81.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1379 2.28% 83.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1383 2.29% 85.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8545 14.16% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60353 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7902 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.522399 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 318.068462 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7896 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60600 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.272739 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 199.847297 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.861949 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20364 33.60% 33.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14670 24.21% 57.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6315 10.42% 68.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3448 5.69% 73.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2734 4.51% 78.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1855 3.06% 81.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1401 2.31% 83.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1433 2.36% 86.17% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8380 13.83% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60600 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7887 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.539115 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 318.374099 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7881 99.92% 99.92% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 2 0.03% 99.95% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 2 0.03% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7902 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7902 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.062769 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.701265 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 4.160598 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5817 73.61% 73.61% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.73% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 164 2.08% 75.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 13 0.16% 75.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 44 0.56% 76.52% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 510 6.45% 82.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 151 1.91% 84.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 32 0.40% 85.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 635 8.04% 93.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 115 1.46% 94.79% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 6 0.08% 94.86% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 14 0.18% 95.04% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 297 3.76% 98.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 8 0.10% 98.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 4 0.05% 98.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 6 0.08% 99.03% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 6 0.08% 99.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 2 0.03% 99.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 4 0.05% 99.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 1 0.01% 99.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.28% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 5 0.06% 99.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 6 0.08% 99.46% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 9 0.11% 99.57% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.65% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 4 0.05% 99.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 5 0.06% 99.76% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 3 0.04% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::46 2 0.03% 99.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 5 0.06% 99.89% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 9 0.11% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7902 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1958460749 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5295585749 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 889900000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11003.82 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 7887 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7887 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.067072 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.711824 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 4.086646 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5792 73.44% 73.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 155 1.97% 75.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 18 0.23% 75.81% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 48 0.61% 76.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 474 6.01% 82.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 162 2.05% 84.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 48 0.61% 85.09% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 632 8.01% 93.10% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 129 1.64% 94.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 11 0.14% 94.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 12 0.15% 95.03% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 299 3.79% 98.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 7 0.09% 98.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 7 0.09% 99.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 8 0.10% 99.10% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.19% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 6 0.08% 99.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::36 1 0.01% 99.38% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 4 0.05% 99.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 1 0.01% 99.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 11 0.14% 99.62% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 6 0.08% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 3 0.04% 99.73% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 1 0.01% 99.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 8 0.10% 99.85% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 3 0.04% 99.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 7 0.09% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 7887 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1946379497 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5280279497 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 889040000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10946.52 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29753.82 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 2.15 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 29696.52 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 2.14 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s @@ -260,270 +259,275 @@ system.mem_ctrls.busUtil 0.03 # Da system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 27.88 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 142054 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 118304 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.81 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 82.87 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 16476053.28 # Average gap between requests -system.mem_ctrls.pageHitRate 81.18 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 5045112796500 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 177003320000 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 78625657500 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 223791120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 232477560 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 122108250 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 126847875 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 683599800 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 704636400 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 468251280 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 456652080 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 346218493920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 346218493920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 148888594485 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 149563929060 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 3049839426000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 3049247027250 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 3546444264855 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 3546550064145 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 669.047128 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 669.067087 # Core power per rank (mW) +system.mem_ctrls.avgWrQLen 25.29 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 141783 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 117919 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.74 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.74 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 16514270.00 # Average gap between requests +system.mem_ctrls.pageHitRate 81.07 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 229566960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 125259750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 694894200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 466333200 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 346549057920 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 149180699250 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052619831250 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549865642530 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.053779 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5078135564501 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 177172320000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 50492285499 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 228569040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 124715250 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 692000400 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 457034400 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 346549057920 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 149006937600 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3052772253750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549830568360 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.047168 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5078398943499 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 177172320000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 50232498501 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10600620667 # number of cpu cycles simulated +system.cpu0.numCycles 10611607773 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 58326751 # Number of instructions committed -system.cpu0.committedOps 112208544 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 105142610 # Number of integer alu accesses +system.cpu0.committedInsts 58312369 # Number of instructions committed +system.cpu0.committedOps 112077158 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 105052932 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 999393 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9968022 # number of instructions that are conditional controls -system.cpu0.num_int_insts 105142610 # number of integer instructions +system.cpu0.num_func_calls 985826 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9959513 # number of instructions that are conditional controls +system.cpu0.num_int_insts 105052932 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 198014063 # number of times the integer registers were read -system.cpu0.num_int_register_writes 89363011 # number of times the integer registers were written +system.cpu0.num_int_register_reads 198024346 # number of times the integer registers were read +system.cpu0.num_int_register_writes 89262745 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 60260543 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43624365 # number of times the CC registers were written -system.cpu0.num_mem_refs 12030075 # number of memory refs -system.cpu0.num_load_insts 7288332 # Number of load instructions -system.cpu0.num_store_insts 4741743 # Number of store instructions -system.cpu0.num_idle_cycles 10084773874.270475 # Number of idle cycles -system.cpu0.num_busy_cycles 515846792.729524 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048662 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951338 # Percentage of idle cycles -system.cpu0.Branches 11302630 # Number of branches fetched -system.cpu0.op_class::No_OpClass 132692 0.12% 0.12% # Class of executed instruction -system.cpu0.op_class::IntAlu 99906926 89.04% 89.15% # Class of executed instruction -system.cpu0.op_class::IntMult 87661 0.08% 89.23% # Class of executed instruction -system.cpu0.op_class::IntDiv 51849 0.05% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::MemRead 7288332 6.50% 95.77% # Class of executed instruction -system.cpu0.op_class::MemWrite 4741743 4.23% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 60301130 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43624803 # number of times the CC registers were written +system.cpu0.num_mem_refs 12143482 # number of memory refs +system.cpu0.num_load_insts 7354533 # Number of load instructions +system.cpu0.num_store_insts 4788949 # Number of store instructions +system.cpu0.num_idle_cycles 10094720432.678099 # Number of idle cycles +system.cpu0.num_busy_cycles 516887340.321903 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048710 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951290 # Percentage of idle cycles +system.cpu0.Branches 11277737 # Number of branches fetched +system.cpu0.op_class::No_OpClass 133660 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 99659673 88.92% 89.04% # Class of executed instruction +system.cpu0.op_class::IntMult 84103 0.08% 89.11% # Class of executed instruction +system.cpu0.op_class::IntDiv 57076 0.05% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.17% # Class of executed instruction +system.cpu0.op_class::MemRead 7354533 6.56% 95.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 4788949 4.27% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 112209203 # Class of executed instruction +system.cpu0.op_class::total 112077994 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10601483797 # number of cpu cycles simulated +system.cpu1.numCycles 10608678164 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48465381 # Number of instructions committed -system.cpu1.committedOps 92539438 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88910462 # Number of integer alu accesses +system.cpu1.committedInsts 48529054 # Number of instructions committed +system.cpu1.committedOps 92757417 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 89083939 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1744945 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8275238 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88910462 # number of integer instructions +system.cpu1.num_func_calls 1759211 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8292881 # number of instructions that are conditional controls +system.cpu1.num_int_insts 89083939 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 172623141 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73500216 # number of times the integer registers were written +system.cpu1.num_int_register_reads 172769101 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73668949 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 51257305 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 33029139 # number of times the CC registers were written -system.cpu1.num_mem_refs 14403882 # number of memory refs -system.cpu1.num_load_insts 9271822 # Number of load instructions -system.cpu1.num_store_insts 5132060 # Number of store instructions -system.cpu1.num_idle_cycles 10262330670.974064 # Number of idle cycles -system.cpu1.num_busy_cycles 339153126.025936 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031991 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968009 # Percentage of idle cycles -system.cpu1.Branches 10623766 # Number of branches fetched -system.cpu1.op_class::No_OpClass 173936 0.19% 0.19% # Class of executed instruction -system.cpu1.op_class::IntAlu 77788975 84.06% 84.25% # Class of executed instruction -system.cpu1.op_class::IntMult 96916 0.10% 84.35% # Class of executed instruction -system.cpu1.op_class::IntDiv 76680 0.08% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::MemRead 9271822 10.02% 94.45% # Class of executed instruction -system.cpu1.op_class::MemWrite 5132060 5.55% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 51289512 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 33065409 # number of times the CC registers were written +system.cpu1.num_mem_refs 14308473 # number of memory refs +system.cpu1.num_load_insts 9217545 # Number of load instructions +system.cpu1.num_store_insts 5090928 # Number of store instructions +system.cpu1.num_idle_cycles 10270312186.995054 # Number of idle cycles +system.cpu1.num_busy_cycles 338365977.004946 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031895 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968105 # Percentage of idle cycles +system.cpu1.Branches 10658677 # Number of branches fetched +system.cpu1.op_class::No_OpClass 173276 0.19% 0.19% # Class of executed instruction +system.cpu1.op_class::IntAlu 78104057 84.20% 84.39% # Class of executed instruction +system.cpu1.op_class::IntMult 100669 0.11% 84.50% # Class of executed instruction +system.cpu1.op_class::IntDiv 71662 0.08% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.57% # Class of executed instruction +system.cpu1.op_class::MemRead 9217545 9.94% 94.51% # Class of executed instruction +system.cpu1.op_class::MemWrite 5090928 5.49% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92540389 # Class of executed instruction +system.cpu1.op_class::total 92758137 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 857926 # Transaction distribution -system.iobus.trans_dist::ReadResp 857926 # Transaction distribution -system.iobus.trans_dist::WriteReq 36569 # Transaction distribution -system.iobus.trans_dist::WriteResp 36569 # Transaction distribution -system.iobus.trans_dist::MessageReq 1919 # Transaction distribution -system.iobus.trans_dist::MessageResp 1919 # Transaction distribution +system.iobus.trans_dist::ReadReq 857916 # Transaction distribution +system.iobus.trans_dist::ReadResp 857916 # Transaction distribution +system.iobus.trans_dist::WriteReq 36558 # Transaction distribution +system.iobus.trans_dist::WriteResp 36558 # Transaction distribution +system.iobus.trans_dist::MessageReq 1920 # Transaction distribution +system.iobus.trans_dist::MessageResp 1920 # Transaction distribution system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4780 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5802 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 1048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 82 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 42 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 964 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 966 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 16892 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743276 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 296 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 238 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1704360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703174 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5240 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 316 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 400 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 348 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 10236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12178 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 200 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1792828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 86270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1792788 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3284 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6684 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3294 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 524 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 41 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 21 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 482 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1980 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1932 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 8446 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486546 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7471 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 476 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972617 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971862 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3964 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3366 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 158 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15582 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 728 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 696 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15626 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 5118 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6089 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10293 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51987 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2031288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 51000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10473 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52670 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2031220 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10161500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10107000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 145000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1080000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1059500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 94000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 96000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 59500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 55000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 20808000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 28599000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1385500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1327000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 31365000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 39157000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 23203000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 23099500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -531,19 +535,19 @@ system.iobus.reqLayer15.occupancy 9000 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 469007612 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 469010624 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8240496 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 8240920 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 1330000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2404108 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2415044 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2025089500 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 2023919000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 59993000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 76513000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -560,48 +564,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10900696 # delay histogram for all message -system.ruby.delayHist::mean 0.442840 # delay histogram for all message -system.ruby.delayHist::stdev 1.830682 # delay histogram for all message -system.ruby.delayHist | 10297724 94.47% 94.47% | 1479 0.01% 94.48% | 601064 5.51% 100.00% | 150 0.00% 100.00% | 222 0.00% 100.00% | 14 0.00% 100.00% | 41 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10900696 # delay histogram for all message +system.ruby.delayHist::samples 10911216 # delay histogram for all message +system.ruby.delayHist::mean 0.442136 # delay histogram for all message +system.ruby.delayHist::stdev 1.829254 # delay histogram for all message +system.ruby.delayHist | 10308626 94.48% 94.48% | 1272 0.01% 94.49% | 600907 5.51% 100.00% | 150 0.00% 100.00% | 203 0.00% 100.00% | 20 0.00% 100.00% | 38 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10911216 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152128630 +system.ruby.outstanding_req_hist::samples 152209035 system.ruby.outstanding_req_hist::mean 1.000112 system.ruby.outstanding_req_hist::gmean 1.000078 -system.ruby.outstanding_req_hist::stdev 0.010605 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152111520 99.99% 99.99% | 17110 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152128630 +system.ruby.outstanding_req_hist::stdev 0.010600 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152191931 99.99% 99.99% | 17104 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152209035 system.ruby.latency_hist::bucket_size 256 system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 152128629 -system.ruby.latency_hist::mean 3.436815 -system.ruby.latency_hist::gmean 3.107877 -system.ruby.latency_hist::stdev 5.781267 -system.ruby.latency_hist | 152119575 99.99% 99.99% | 6193 0.00% 100.00% | 2797 0.00% 100.00% | 28 0.00% 100.00% | 34 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152128629 +system.ruby.latency_hist::samples 152209034 +system.ruby.latency_hist::mean 3.436503 +system.ruby.latency_hist::gmean 3.107893 +system.ruby.latency_hist::stdev 5.762527 +system.ruby.latency_hist | 152200028 99.99% 99.99% | 6260 0.00% 100.00% | 2677 0.00% 100.00% | 43 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 152209034 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 149464039 +system.ruby.hit_latency_hist::samples 149542283 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149464039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 149464039 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149542283 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 149542283 system.ruby.miss_latency_hist::bucket_size 256 system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 2664590 -system.ruby.miss_latency_hist::mean 27.938944 -system.ruby.miss_latency_hist::gmean 22.546119 -system.ruby.miss_latency_hist::stdev 36.016044 -system.ruby.miss_latency_hist | 2655536 99.66% 99.66% | 6193 0.23% 99.89% | 2797 0.10% 100.00% | 28 0.00% 100.00% | 34 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2664590 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 10684802 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 518536 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11203338 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 67461431 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 317291 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 67778722 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2666751 +system.ruby.miss_latency_hist::mean 27.914090 +system.ruby.miss_latency_hist::gmean 22.539704 +system.ruby.miss_latency_hist::stdev 35.853723 +system.ruby.miss_latency_hist | 2657745 99.66% 99.66% | 6260 0.23% 99.90% | 2677 0.10% 100.00% | 43 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 2666751 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 10785659 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 531574 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11317233 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 67530179 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 328872 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 67859051 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -611,13 +615,13 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 13058053 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1328322 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14386375 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 58259753 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 500441 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58760194 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 15 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12972395 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1316773 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14289168 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 58254050 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 489532 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58743582 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -627,601 +631,613 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2436707 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227883 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2664590 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 10 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2439158 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 227593 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2666751 # Number of cache demand accesses +system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.029331 -system.ruby.network.routers0.msg_count.Control::0 835827 -system.ruby.network.routers0.msg_count.Request_Control::2 42905 -system.ruby.network.routers0.msg_count.Response_Data::1 863889 -system.ruby.network.routers0.msg_count.Response_Control::1 496114 -system.ruby.network.routers0.msg_count.Response_Control::2 492544 -system.ruby.network.routers0.msg_count.Writeback_Data::0 292440 -system.ruby.network.routers0.msg_count.Writeback_Data::1 167 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-system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 814 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 815 system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58680 system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle1.link_utilization 0.000224 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47550 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47551 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380408 system.ruby.network.routers5.throttle0.link_utilization 0 system.ruby.network.routers5.throttle1.link_utilization 0 -system.ruby.network.routers6.throttle0.link_utilization 0.037422 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42905 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 823544 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 479708 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 343240 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 59295168 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3837664 -system.ruby.network.routers6.throttle1.link_utilization 0.083305 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40586 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1818878 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1252654 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 324688 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 130959216 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 10021232 -system.ruby.network.routers6.throttle2.link_utilization 0.059790 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2664590 -system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 203618 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 125324 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1762230 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 575354 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 375 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1110930 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21316720 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14660496 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 1002592 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14097840 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41425488 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 27000 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8887440 -system.ruby.network.routers6.throttle3.link_utilization 0.005288 -system.ruby.network.routers6.throttle3.msg_count.Control::0 178413 -system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97701 -system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15947 -system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47550 -system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1427304 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7034472 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 127576 -system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers6.throttle0.link_utilization 0.038501 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42982 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 848348 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 493076 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 343856 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 61081056 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3944608 +system.ruby.network.routers6.throttle1.link_utilization 0.082209 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40219 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1796151 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1241782 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 321752 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129322872 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9934256 +system.ruby.network.routers6.throttle2.link_utilization 0.059751 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2666751 +system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 203534 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 124997 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1764444 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 575124 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 402 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1113406 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21334008 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14654448 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 999976 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14115552 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41408928 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 28944 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8907248 +system.ruby.network.routers6.throttle3.link_utilization 0.005283 +system.ruby.network.routers6.throttle3.msg_count.Control::0 178187 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97745 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15738 +system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47551 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1425496 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7037640 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 125904 +system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380408 system.ruby.network.routers6.throttle4.link_utilization 0.000255 -system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 814 +system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 815 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58680 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6113104 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754972 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.341149 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5536836 90.57% 90.57% | 424 0.01% 90.58% | 575424 9.41% 99.99% | 146 0.00% 100.00% | 217 0.00% 100.00% | 14 0.00% 100.00% | 41 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6113104 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6119725 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.753707 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.339234 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5543761 90.59% 90.59% | 388 0.01% 90.59% | 575170 9.40% 99.99% | 147 0.00% 100.00% | 201 0.00% 100.00% | 20 0.00% 100.00% | 38 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6119725 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4704101 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.045072 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.595912 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4676918 99.42% 99.42% | 479 0.01% 99.43% | 405 0.01% 99.44% | 650 0.01% 99.45% | 25495 0.54% 100.00% | 145 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4704101 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4708290 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.044976 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.595659 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4681222 99.43% 99.43% | 442 0.01% 99.43% | 339 0.01% 99.44% | 545 0.01% 99.45% | 25596 0.54% 100.00% | 141 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4708290 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 83491 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000264 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.022955 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 83480 99.99% 99.99% | 0 0.00% 99.99% | 11 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 83491 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 256 -system.ruby.LD.latency_hist::max_bucket 2559 -system.ruby.LD.latency_hist::samples 14918164 -system.ruby.LD.latency_hist::mean 4.885826 -system.ruby.LD.latency_hist::gmean 3.596048 -system.ruby.LD.latency_hist::stdev 9.349489 -system.ruby.LD.latency_hist | 14916026 99.99% 99.99% | 1637 0.01% 100.00% | 485 0.00% 100.00% | 10 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 14918164 +system.ruby.delayVCHist.vnet_2::samples 83201 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000120 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.015504 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 83196 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 83201 # delay histogram for vnet_2 +system.ruby.LD.latency_hist::bucket_size 128 +system.ruby.LD.latency_hist::max_bucket 1279 +system.ruby.LD.latency_hist::samples 14928118 +system.ruby.LD.latency_hist::mean 4.887199 +system.ruby.LD.latency_hist::gmean 3.596426 +system.ruby.LD.latency_hist::stdev 9.328249 +system.ruby.LD.latency_hist | 14912021 99.89% 99.89% | 13966 0.09% 99.99% | 828 0.01% 99.99% | 820 0.01% 100.00% | 357 0.00% 100.00% | 111 0.00% 100.00% | 2 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 14928118 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13527451 +system.ruby.LD.hit_latency_hist::samples 13535758 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13527451 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13527451 -system.ruby.LD.miss_latency_hist::bucket_size 256 -system.ruby.LD.miss_latency_hist::max_bucket 2559 -system.ruby.LD.miss_latency_hist::samples 1390713 -system.ruby.LD.miss_latency_hist::mean 23.229241 -system.ruby.LD.miss_latency_hist::gmean 20.959487 -system.ruby.LD.miss_latency_hist::stdev 23.803463 -system.ruby.LD.miss_latency_hist | 1388575 99.85% 99.85% | 1637 0.12% 99.96% | 485 0.03% 100.00% | 10 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1390713 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535758 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13535758 +system.ruby.LD.miss_latency_hist::bucket_size 128 +system.ruby.LD.miss_latency_hist::max_bucket 1279 +system.ruby.LD.miss_latency_hist::samples 1392360 +system.ruby.LD.miss_latency_hist::mean 23.233506 +system.ruby.LD.miss_latency_hist::gmean 20.962083 +system.ruby.LD.miss_latency_hist::stdev 23.700852 +system.ruby.LD.miss_latency_hist | 1376263 98.84% 98.84% | 13966 1.00% 99.85% | 828 0.06% 99.91% | 820 0.06% 99.97% | 357 0.03% 99.99% | 111 0.01% 100.00% | 2 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1392360 system.ruby.ST.latency_hist::bucket_size 256 system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 9498200 -system.ruby.ST.latency_hist::mean 5.193739 -system.ruby.ST.latency_hist::gmean 3.303046 -system.ruby.ST.latency_hist::stdev 17.710522 -system.ruby.ST.latency_hist | 9492386 99.94% 99.94% | 3703 0.04% 99.98% | 2069 0.02% 100.00% | 12 0.00% 100.00% | 29 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9498200 +system.ruby.ST.latency_hist::samples 9504180 +system.ruby.ST.latency_hist::mean 5.187204 +system.ruby.ST.latency_hist::gmean 3.302390 +system.ruby.ST.latency_hist::stdev 17.665644 +system.ruby.ST.latency_hist | 9498362 99.94% 99.94% | 3775 0.04% 99.98% | 1993 0.02% 100.00% | 29 0.00% 100.00% | 20 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 9504180 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9146403 +system.ruby.ST.hit_latency_hist::samples 9152723 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9146403 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9146403 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9152723 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9152723 system.ruby.ST.miss_latency_hist::bucket_size 256 system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 351797 -system.ruby.ST.miss_latency_hist::mean 62.228953 -system.ruby.ST.miss_latency_hist::gmean 40.318436 -system.ruby.ST.miss_latency_hist::stdev 71.347621 -system.ruby.ST.miss_latency_hist | 345983 98.35% 98.35% | 3703 1.05% 99.40% | 2069 0.59% 99.99% | 12 0.00% 99.99% | 29 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 351797 +system.ruby.ST.miss_latency_hist::samples 351457 +system.ruby.ST.miss_latency_hist::mean 62.146880 +system.ruby.ST.miss_latency_hist::gmean 40.269218 +system.ruby.ST.miss_latency_hist::stdev 71.205537 +system.ruby.ST.miss_latency_hist | 345639 98.34% 98.34% | 3775 1.07% 99.42% | 1993 0.57% 99.99% | 29 0.01% 99.99% | 20 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 351457 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 126538916 -system.ruby.IFETCH.latency_hist::mean 3.120095 -system.ruby.IFETCH.latency_hist::gmean 3.036786 -system.ruby.IFETCH.latency_hist::stdev 2.265582 -system.ruby.IFETCH.latency_hist | 126532168 99.99% 99.99% | 5703 0.00% 100.00% | 492 0.00% 100.00% | 323 0.00% 100.00% | 160 0.00% 100.00% | 64 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 126538916 +system.ruby.IFETCH.latency_hist::samples 126602633 +system.ruby.IFETCH.latency_hist::mean 3.119985 +system.ruby.IFETCH.latency_hist::gmean 3.036795 +system.ruby.IFETCH.latency_hist::stdev 2.244898 +system.ruby.IFETCH.latency_hist | 126595894 99.99% 99.99% | 5742 0.00% 100.00% | 458 0.00% 100.00% | 336 0.00% 100.00% | 141 0.00% 100.00% | 58 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126602633 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 125721184 +system.ruby.IFETCH.hit_latency_hist::samples 125784229 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125721184 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 125721184 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125784229 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 125784229 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 817732 -system.ruby.IFETCH.miss_latency_hist::mean 21.583892 -system.ruby.IFETCH.miss_latency_hist::gmean 19.777346 -system.ruby.IFETCH.miss_latency_hist::stdev 21.240290 -system.ruby.IFETCH.miss_latency_hist | 810984 99.17% 99.17% | 5703 0.70% 99.87% | 492 0.06% 99.93% | 323 0.04% 99.97% | 160 0.02% 99.99% | 64 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 817732 +system.ruby.IFETCH.miss_latency_hist::samples 818404 +system.ruby.IFETCH.miss_latency_hist::mean 21.561079 +system.ruby.IFETCH.miss_latency_hist::gmean 19.774643 +system.ruby.IFETCH.miss_latency_hist::stdev 20.911893 +system.ruby.IFETCH.miss_latency_hist | 811665 99.18% 99.18% | 5742 0.70% 99.88% | 458 0.06% 99.93% | 336 0.04% 99.98% | 141 0.02% 99.99% | 58 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 818404 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 494265 -system.ruby.RMW_Read.latency_hist::mean 6.023605 -system.ruby.RMW_Read.latency_hist::gmean 3.954302 -system.ruby.RMW_Read.latency_hist::stdev 10.239189 -system.ruby.RMW_Read.latency_hist | 494082 99.96% 99.96% | 137 0.03% 99.99% | 14 0.00% 99.99% | 17 0.00% 100.00% | 10 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 494265 +system.ruby.RMW_Read.latency_hist::samples 494795 +system.ruby.RMW_Read.latency_hist::mean 6.019475 +system.ruby.RMW_Read.latency_hist::gmean 3.954538 +system.ruby.RMW_Read.latency_hist::stdev 10.125129 +system.ruby.RMW_Read.latency_hist | 494623 99.97% 99.97% | 131 0.03% 99.99% | 11 0.00% 99.99% | 18 0.00% 100.00% | 7 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 494795 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 428815 +system.ruby.RMW_Read.hit_latency_hist::samples 429248 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428815 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 428815 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 429248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 429248 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 65450 -system.ruby.RMW_Read.miss_latency_hist::mean 25.833644 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.151736 -system.ruby.RMW_Read.miss_latency_hist::stdev 18.422970 -system.ruby.RMW_Read.miss_latency_hist | 65267 99.72% 99.72% | 137 0.21% 99.93% | 14 0.02% 99.95% | 17 0.03% 99.98% | 10 0.02% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65450 -system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 -system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.latency_hist::samples 339542 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.330551 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.775845 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.064390 -system.ruby.Locked_RMW_Read.latency_hist | 339293 99.93% 99.93% | 238 0.07% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339542 +system.ruby.RMW_Read.miss_latency_hist::samples 65547 +system.ruby.RMW_Read.miss_latency_hist::mean 25.793126 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.141988 +system.ruby.RMW_Read.miss_latency_hist::stdev 17.977211 +system.ruby.RMW_Read.miss_latency_hist | 65375 99.74% 99.74% | 131 0.20% 99.94% | 11 0.02% 99.95% | 18 0.03% 99.98% | 7 0.01% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65547 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639 +system.ruby.Locked_RMW_Read.latency_hist::samples 339654 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.341447 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.777860 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.189753 +system.ruby.Locked_RMW_Read.latency_hist | 339308 99.90% 99.90% | 89 0.03% 99.92% | 236 0.07% 99.99% | 2 0.00% 99.99% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339654 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300644 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300671 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300644 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 300644 -system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 -system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38898 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.343462 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.340350 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.186116 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38649 99.36% 99.36% | 238 0.61% 99.97% | 4 0.01% 99.98% | 3 0.01% 99.99% | 1 0.00% 99.99% | 3 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 38898 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300671 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 300671 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38983 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.400739 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.361163 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.695962 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38637 99.11% 99.11% | 89 0.23% 99.34% | 236 0.61% 99.95% | 2 0.01% 99.95% | 6 0.02% 99.97% | 3 0.01% 99.97% | 2 0.01% 99.98% | 3 0.01% 99.99% | 2 0.01% 99.99% | 3 0.01% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 38983 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339542 +system.ruby.Locked_RMW_Write.latency_hist::samples 339654 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339542 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339542 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339542 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339654 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339542 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339542 -system.ruby.Directory_Controller.Fetch 178413 0.00% 0.00% -system.ruby.Directory_Controller.Data 97701 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 178865 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 142859 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339654 +system.ruby.Directory_Controller.Fetch 178187 0.00% 0.00% +system.ruby.Directory_Controller.Data 97745 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 178657 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142629 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 815 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 15947 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 178413 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 452 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 45158 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 452 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 45158 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 95761 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1578 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 15947 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 178413 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 95761 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1578 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1578 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.ReadRequest::total 814 +system.ruby.Directory_Controller.CleanReplacement 15738 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 178187 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 470 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 44884 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 470 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 44884 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95548 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 345 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1852 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 15738 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 178187 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95548 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 345 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 345 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1852 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1852 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest | 815 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.ReadRequest::total 815 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.WriteRequest::total 46736 -system.ruby.DMA_Controller.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Data::total 814 +system.ruby.DMA_Controller.Data | 815 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Data::total 815 system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.Ack::total 46736 -system.ruby.DMA_Controller.READY.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.ReadRequest::total 814 +system.ruby.DMA_Controller.READY.ReadRequest | 815 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.ReadRequest::total 815 system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.READY.WriteRequest::total 46736 -system.ruby.DMA_Controller.BUSY_RD.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_RD.Data::total 814 +system.ruby.DMA_Controller.BUSY_RD.Data | 815 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_RD.Data::total 815 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6037097 40.47% 40.47% | 8881067 59.53% 100.00% -system.ruby.L1Cache_Controller.Load::total 14918164 -system.ruby.L1Cache_Controller.Ifetch | 67778726 53.56% 53.56% | 58760197 46.44% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 126538923 -system.ruby.L1Cache_Controller.Store | 5166241 48.41% 48.41% | 5505308 51.59% 100.00% -system.ruby.L1Cache_Controller.Store::total 10671549 -system.ruby.L1Cache_Controller.Inv | 16573 48.71% 48.71% | 17448 51.29% 100.00% -system.ruby.L1Cache_Controller.Inv::total 34021 -system.ruby.L1Cache_Controller.L1_Replacement | 807951 30.97% 30.97% | 1801234 69.03% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2609185 -system.ruby.L1Cache_Controller.Fwd_GETX | 12319 50.77% 50.77% | 11946 49.23% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 24265 -system.ruby.L1Cache_Controller.Fwd_GETS | 14009 55.59% 55.59% | 11192 44.41% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25201 +system.ruby.L1Cache_Controller.Load | 6103954 40.89% 40.89% | 8824164 59.11% 100.00% +system.ruby.L1Cache_Controller.Load::total 14928118 +system.ruby.L1Cache_Controller.Ifetch | 67859054 53.60% 53.60% | 58743585 46.40% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126602639 +system.ruby.L1Cache_Controller.Store | 5213279 48.82% 48.82% | 5465004 51.18% 100.00% +system.ruby.L1Cache_Controller.Store::total 10678283 +system.ruby.L1Cache_Controller.Inv | 16394 48.51% 48.51% | 17401 51.49% 100.00% +system.ruby.L1Cache_Controller.Inv::total 33795 +system.ruby.L1Cache_Controller.L1_Replacement | 832783 31.89% 31.89% | 1778531 68.11% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2611314 +system.ruby.L1Cache_Controller.Fwd_GETX | 12220 50.79% 50.79% | 11839 49.21% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 24059 +system.ruby.L1Cache_Controller.Fwd_GETS | 14364 56.68% 56.68% | 10979 43.32% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 25343 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 658 37.77% 37.77% | 1084 62.23% 100.00% -system.ruby.L1Cache_Controller.Data::total 1742 -system.ruby.L1Cache_Controller.Data_Exclusive | 243874 19.04% 19.04% | 1037006 80.96% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1280880 -system.ruby.L1Cache_Controller.DataS_fromL1 | 11192 44.40% 44.40% | 14013 55.60% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25205 -system.ruby.L1Cache_Controller.Data_all_Acks | 567820 42.55% 42.55% | 766775 57.45% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1334595 -system.ruby.L1Cache_Controller.Ack | 12283 55.41% 55.41% | 9885 44.59% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22168 -system.ruby.L1Cache_Controller.Ack_all | 12941 54.12% 54.12% | 10969 45.88% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 23910 -system.ruby.L1Cache_Controller.WB_Ack | 454484 26.95% 26.95% | 1231800 73.05% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1686284 -system.ruby.L1Cache_Controller.NP.Load | 272421 19.86% 19.86% | 1099369 80.14% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1371790 -system.ruby.L1Cache_Controller.NP.Ifetch | 317175 38.82% 38.82% | 499890 61.18% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 817065 -system.ruby.L1Cache_Controller.NP.Store | 219379 51.94% 51.94% | 202999 48.06% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 422378 -system.ruby.L1Cache_Controller.NP.Inv | 5530 57.31% 57.31% | 4119 42.69% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 9649 -system.ruby.L1Cache_Controller.I.Load | 8637 45.64% 45.64% | 10286 54.36% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18923 -system.ruby.L1Cache_Controller.I.Ifetch | 116 17.39% 17.39% | 551 82.61% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 667 -system.ruby.L1Cache_Controller.I.Store | 5816 50.14% 50.14% | 5783 49.86% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11599 -system.ruby.L1Cache_Controller.I.L1_Replacement | 8686 50.09% 50.09% | 8655 49.91% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 17341 -system.ruby.L1Cache_Controller.S.Load | 551952 52.35% 52.35% | 502332 47.65% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1054284 -system.ruby.L1Cache_Controller.S.Ifetch | 67461431 53.66% 53.66% | 58259753 46.34% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 125721184 -system.ruby.L1Cache_Controller.S.Store | 12283 55.41% 55.41% | 9885 44.59% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22168 -system.ruby.L1Cache_Controller.S.Inv | 10821 45.28% 45.28% | 13078 54.72% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23899 -system.ruby.L1Cache_Controller.S.L1_Replacement | 344781 38.07% 38.07% | 560779 61.93% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 905560 -system.ruby.L1Cache_Controller.E.Load | 1077334 27.76% 27.76% | 2803511 72.24% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3880845 -system.ruby.L1Cache_Controller.E.Store | 80360 48.21% 48.21% | 86332 51.79% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166692 -system.ruby.L1Cache_Controller.E.Inv | 55 56.12% 56.12% | 43 43.88% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 98 -system.ruby.L1Cache_Controller.E.L1_Replacement | 162044 14.59% 14.59% | 948886 85.41% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1110930 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 433 65.81% 65.81% | 225 34.19% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 658 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 907 40.65% 40.65% | 1324 59.35% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2231 -system.ruby.L1Cache_Controller.M.Load | 4126753 48.03% 48.03% | 4465569 51.97% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8592322 -system.ruby.L1Cache_Controller.M.Store | 4848403 48.25% 48.25% | 5200309 51.75% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10048712 -system.ruby.L1Cache_Controller.M.Inv | 167 44.53% 44.53% | 208 55.47% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 375 -system.ruby.L1Cache_Controller.M.L1_Replacement | 292440 50.83% 50.83% | 282914 49.17% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 575354 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11886 50.35% 50.35% | 11721 49.65% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23607 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13102 57.04% 57.04% | 9868 42.96% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 22970 +system.ruby.L1Cache_Controller.Data | 793 43.48% 43.48% | 1031 56.52% 100.00% +system.ruby.L1Cache_Controller.Data::total 1824 +system.ruby.L1Cache_Controller.Data_Exclusive | 253693 19.77% 19.77% | 1029417 80.23% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1283110 +system.ruby.L1Cache_Controller.DataS_fromL1 | 10979 43.31% 43.31% | 14368 56.69% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 25347 +system.ruby.L1Cache_Controller.Data_all_Acks | 582883 43.69% 43.69% | 751335 56.31% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1334218 +system.ruby.L1Cache_Controller.Ack | 12098 54.37% 54.37% | 10154 45.63% 100.00% +system.ruby.L1Cache_Controller.Ack::total 22252 +system.ruby.L1Cache_Controller.Ack_all | 12891 53.54% 53.54% | 11185 46.46% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 24076 +system.ruby.L1Cache_Controller.WB_Ack | 468087 27.72% 27.72% | 1220443 72.28% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1688530 +system.ruby.L1Cache_Controller.NP.Load | 281209 20.47% 20.47% | 1092251 79.53% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1373460 +system.ruby.L1Cache_Controller.NP.Ifetch | 328766 40.20% 40.20% | 488985 59.80% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 817751 +system.ruby.L1Cache_Controller.NP.Store | 223831 53.02% 53.02% | 198319 46.98% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 422150 +system.ruby.L1Cache_Controller.NP.Inv | 5086 54.54% 54.54% | 4239 45.46% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 9325 +system.ruby.L1Cache_Controller.I.Load | 8631 45.67% 45.67% | 10269 54.33% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 18900 +system.ruby.L1Cache_Controller.I.Ifetch | 106 16.23% 16.23% | 547 83.77% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 653 +system.ruby.L1Cache_Controller.I.Store | 5805 50.11% 50.11% | 5779 49.89% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11584 +system.ruby.L1Cache_Controller.I.L1_Replacement | 8985 51.90% 51.90% | 8328 48.10% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17313 +system.ruby.L1Cache_Controller.S.Load | 530372 50.22% 50.22% | 525759 49.78% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1056131 +system.ruby.L1Cache_Controller.S.Ifetch | 67530179 53.69% 53.69% | 58254050 46.31% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 125784229 +system.ruby.L1Cache_Controller.S.Store | 12098 54.37% 54.37% | 10155 45.63% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22253 +system.ruby.L1Cache_Controller.S.Inv | 11044 46.05% 46.05% | 12940 53.95% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 23984 +system.ruby.L1Cache_Controller.S.L1_Replacement | 355711 39.28% 39.28% | 549760 60.72% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 905471 +system.ruby.L1Cache_Controller.E.Load | 1138534 29.37% 29.37% | 2737774 70.63% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3876308 +system.ruby.L1Cache_Controller.E.Store | 81127 48.65% 48.65% | 85645 51.35% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166772 +system.ruby.L1Cache_Controller.E.Inv | 48 57.83% 57.83% | 35 42.17% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 83 +system.ruby.L1Cache_Controller.E.L1_Replacement | 171015 15.36% 15.36% | 942391 84.64% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1113406 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 278 59.40% 59.40% | 190 40.60% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 468 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 1045 48.60% 48.60% | 1105 51.40% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2150 +system.ruby.L1Cache_Controller.M.Load | 4145208 48.18% 48.18% | 4458111 51.82% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8603319 +system.ruby.L1Cache_Controller.M.Store | 4890418 48.63% 48.63% | 5165106 51.37% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10055524 +system.ruby.L1Cache_Controller.M.Inv | 216 53.73% 53.73% | 186 46.27% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 402 +system.ruby.L1Cache_Controller.M.L1_Replacement | 297072 51.65% 51.65% | 278052 48.35% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 575124 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11941 50.62% 50.62% | 11649 49.38% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23590 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13319 57.43% 57.43% | 9874 42.57% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23193 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 243874 19.04% 19.04% | 1037006 80.96% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280880 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11192 44.40% 44.40% | 14013 55.60% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25205 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 343283 38.04% 38.04% | 559077 61.96% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 902360 -system.ruby.L1Cache_Controller.IM.Data | 658 37.77% 37.77% | 1084 62.23% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1742 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 224537 51.95% 51.95% | 207698 48.05% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 432235 -system.ruby.L1Cache_Controller.SM.Ack | 12283 55.41% 55.41% | 9885 44.59% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22168 -system.ruby.L1Cache_Controller.SM.Ack_all | 12941 54.12% 54.12% | 10969 45.88% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 23910 -system.ruby.L1Cache_Controller.M_I.Ifetch | 4 57.14% 57.14% | 3 42.86% 100.00% -system.ruby.L1Cache_Controller.M_I.Ifetch::total 7 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 454484 26.95% 26.95% | 1231800 73.05% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1686284 -system.ruby.L2Cache_Controller.L1_GET_INSTR 817732 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1390884 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 433978 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22168 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1686284 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 95716 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 15992 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 178413 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 113648 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23349 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2231 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1814 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7922 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25205 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1737025 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 3880 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16558 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 34140 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127715 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 801143 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 84632 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1919 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22168 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 243 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7577 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.MEM_Inv 4 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GET_INSTR 27 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1246740 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 280078 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 95328 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8315 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1708 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 253693 19.77% 19.77% | 1029417 80.23% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1283110 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10979 43.31% 43.31% | 14368 56.69% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25347 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 354040 39.24% 39.24% | 548267 60.76% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 902307 +system.ruby.L1Cache_Controller.IM.Data | 793 43.48% 43.48% | 1031 56.52% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1824 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 228843 52.98% 52.98% | 203068 47.02% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431911 +system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.SM.Inv::total 1 +system.ruby.L1Cache_Controller.SM.Ack | 12098 54.37% 54.37% | 10154 45.63% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 22252 +system.ruby.L1Cache_Controller.SM.Ack_all | 12891 53.54% 53.54% | 11185 46.46% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 24076 +system.ruby.L1Cache_Controller.M_I.Ifetch | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 +system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 468086 27.72% 27.72% | 1220443 72.28% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1688529 +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 1 +system.ruby.L2Cache_Controller.L1_GET_INSTR 818404 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1392538 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 433736 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 22253 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1688530 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 1 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95493 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 15793 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 178187 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 113483 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23599 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2150 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1627 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7690 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 25347 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1739097 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 4394 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16549 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 34274 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 127364 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 801825 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 83907 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1933 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22252 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 275 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7330 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 2 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1248836 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 280379 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 95073 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8368 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1950 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25201 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 24265 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1686284 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 25343 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 24059 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1688529 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX_old 1 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L2_Replacement 145 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 100 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.MEM_Inv 228 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 113648 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1708 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 330 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 95 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 245 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 113483 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1950 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 347 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.Ack_all 43 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.MEM_Inv 228 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 45 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 55 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1567 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7577 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 247 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 247 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.MEM_Inv 4 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 34140 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 16558 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127715 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 125 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24087 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 46 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1712938 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22969 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2231 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25200 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 245 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 55 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 40 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1351 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 7330 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 276 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 277 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 2 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 34274 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 16549 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 127364 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 131 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24185 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 47 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1714912 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23196 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2149 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25345 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 1dbb00ab9..039ebcc95 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,148 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133759 # Number of seconds simulated -sim_ticks 5133759356500 # Number of ticks simulated -final_tick 5133759356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136081 # Number of seconds simulated +sim_ticks 5136081138000 # Number of ticks simulated +final_tick 5136081138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 270712 # Simulator instruction rate (inst/s) -host_op_rate 538208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5706161187 # Simulator tick rate (ticks/s) -host_mem_usage 956212 # Number of bytes of host memory used -host_seconds 899.69 # Real time elapsed on the host -sim_insts 243556000 # Number of instructions simulated -sim_ops 484219202 # Number of ops (including micro ops) simulated +host_inst_rate 275445 # Simulator instruction rate (inst/s) +host_op_rate 547622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5813086840 # Simulator tick rate (ticks/s) +host_mem_usage 1006240 # Number of bytes of host memory used +host_seconds 883.54 # Real time elapsed on the host +sim_insts 243366027 # Number of instructions simulated +sim_ops 483844707 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 473664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5506752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1916928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 343744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2959424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 488576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5525632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 145728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1937472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 336128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2922880 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11383040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 473664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 343744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9167488 # Number of bytes written to this memory -system.physmem.bytes_written::total 9167488 # Number of bytes written to this memory +system.physmem.bytes_read::total 11386880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 488576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 145728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 336128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 970432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9156352 # Number of bytes written to this memory +system.physmem.bytes_written::total 9156352 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 86043 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2364 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 29952 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 40 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 46241 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 86338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 30273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5252 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 45670 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177860 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143242 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143242 # Number of write requests responded to by this memory +system.physmem.num_reads::total 177920 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143068 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143068 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 92265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1072655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 373397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 66958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 576463 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2217291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 92265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 66958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1785726 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1785726 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1785726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 95126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1075846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 377228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 65444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 569088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2217037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 95126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 65444 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1782751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1782751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1782751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 92265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1072655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 373397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 66958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 576463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4003017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 84411 # Number of read requests accepted -system.physmem.writeReqs 105225 # Number of write requests accepted -system.physmem.readBursts 84411 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 105225 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5391616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10688 # Total number of bytes read from write queue -system.physmem.bytesWritten 6646720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5402304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6734400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1370 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 877 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5556 # Per bank write bursts -system.physmem.perBankRdBursts::1 4342 # Per bank write bursts -system.physmem.perBankRdBursts::2 4498 # Per bank write bursts -system.physmem.perBankRdBursts::3 5943 # Per bank write bursts -system.physmem.perBankRdBursts::4 5610 # Per bank write bursts -system.physmem.perBankRdBursts::5 4878 # Per bank write bursts -system.physmem.perBankRdBursts::6 4789 # Per bank write bursts -system.physmem.perBankRdBursts::7 4605 # Per bank write bursts -system.physmem.perBankRdBursts::8 5348 # Per bank write bursts -system.physmem.perBankRdBursts::9 5424 # Per bank write bursts -system.physmem.perBankRdBursts::10 4968 # Per bank write bursts -system.physmem.perBankRdBursts::11 5291 # Per bank write bursts -system.physmem.perBankRdBursts::12 5168 # Per bank write bursts -system.physmem.perBankRdBursts::13 6289 # Per bank write bursts -system.physmem.perBankRdBursts::14 5888 # Per bank write bursts -system.physmem.perBankRdBursts::15 5647 # Per bank write bursts -system.physmem.perBankWrBursts::0 6974 # Per bank write bursts -system.physmem.perBankWrBursts::1 5943 # Per bank write bursts -system.physmem.perBankWrBursts::2 5537 # Per bank write bursts -system.physmem.perBankWrBursts::3 6451 # Per bank write bursts -system.physmem.perBankWrBursts::4 6503 # Per bank write bursts -system.physmem.perBankWrBursts::5 5766 # Per bank write bursts -system.physmem.perBankWrBursts::6 6233 # Per bank write bursts -system.physmem.perBankWrBursts::7 6363 # Per bank write bursts -system.physmem.perBankWrBursts::8 6662 # Per bank write bursts -system.physmem.perBankWrBursts::9 6738 # Per bank write bursts -system.physmem.perBankWrBursts::10 7192 # Per bank write bursts -system.physmem.perBankWrBursts::11 7225 # Per bank write bursts -system.physmem.perBankWrBursts::12 6202 # Per bank write bursts -system.physmem.perBankWrBursts::13 7261 # Per bank write bursts -system.physmem.perBankWrBursts::14 6520 # Per bank write bursts -system.physmem.perBankWrBursts::15 6285 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 95126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1075846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 377228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 65444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 569088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3999787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 83943 # Number of read requests accepted +system.physmem.writeReqs 110041 # Number of write requests accepted +system.physmem.readBursts 83943 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 110041 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5367872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4480 # Total number of bytes read from write queue +system.physmem.bytesWritten 6959552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5372352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7042624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 70 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1298 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 825 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5657 # Per bank write bursts +system.physmem.perBankRdBursts::1 4325 # Per bank write bursts +system.physmem.perBankRdBursts::2 4452 # Per bank write bursts +system.physmem.perBankRdBursts::3 6002 # Per bank write bursts +system.physmem.perBankRdBursts::4 5499 # Per bank write bursts +system.physmem.perBankRdBursts::5 4854 # Per bank write bursts +system.physmem.perBankRdBursts::6 4847 # Per bank write bursts +system.physmem.perBankRdBursts::7 4597 # Per bank write bursts +system.physmem.perBankRdBursts::8 5338 # Per bank write bursts +system.physmem.perBankRdBursts::9 5444 # Per bank write bursts +system.physmem.perBankRdBursts::10 5075 # Per bank write bursts +system.physmem.perBankRdBursts::11 5197 # Per bank write bursts +system.physmem.perBankRdBursts::12 5244 # Per bank write bursts +system.physmem.perBankRdBursts::13 6205 # Per bank write bursts +system.physmem.perBankRdBursts::14 5705 # Per bank write bursts +system.physmem.perBankRdBursts::15 5432 # Per bank write bursts +system.physmem.perBankWrBursts::0 8070 # Per bank write bursts +system.physmem.perBankWrBursts::1 6584 # Per bank write bursts +system.physmem.perBankWrBursts::2 6149 # Per bank write bursts +system.physmem.perBankWrBursts::3 7200 # Per bank write bursts +system.physmem.perBankWrBursts::4 7057 # Per bank write bursts +system.physmem.perBankWrBursts::5 6223 # Per bank write bursts +system.physmem.perBankWrBursts::6 6693 # Per bank write bursts +system.physmem.perBankWrBursts::7 6492 # Per bank write bursts +system.physmem.perBankWrBursts::8 6300 # Per bank write bursts +system.physmem.perBankWrBursts::9 6374 # Per bank write bursts +system.physmem.perBankWrBursts::10 7150 # Per bank write bursts +system.physmem.perBankWrBursts::11 7064 # Per bank write bursts +system.physmem.perBankWrBursts::12 7000 # Per bank write bursts +system.physmem.perBankWrBursts::13 7706 # Per bank write bursts +system.physmem.perBankWrBursts::14 6569 # Per bank write bursts +system.physmem.perBankWrBursts::15 6112 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5132576110500 # Total gap between requests +system.physmem.totGap 5132269646500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 84411 # Read request sizes (log2) +system.physmem.readPktSize::6 83943 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 105225 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 78589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 775 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.writePktSize::6 110041 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 78296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see @@ -161,450 +161,457 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 123 # What 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queue length does an incoming req see -system.physmem.wrQLenPdf::9 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4284 # What write queue length does an incoming req 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write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6097 # What write queue length does an incoming req see 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does an incoming req see +system.physmem.wrQLenPdf::40 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.093112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.896548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.057147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15327 38.97% 38.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9261 23.55% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3835 9.75% 72.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2116 5.38% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1579 4.01% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 961 2.44% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 670 1.70% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 553 1.41% 87.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5027 12.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39329 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4061 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.744644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.795472 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4058 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 39516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.960320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.025881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 337.744102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15369 38.89% 38.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9220 23.33% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3764 9.53% 71.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2091 5.29% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1514 3.83% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 970 2.45% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 639 1.62% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 601 1.52% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5348 13.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39516 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4123 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.342712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 185.525630 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4120 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4061 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.573750 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.065998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 25.155630 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 71 1.75% 1.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 7 0.17% 1.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 3181 78.33% 80.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 170 4.19% 84.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 129 3.18% 87.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 48 1.18% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 114 2.81% 91.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 18 0.44% 92.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 31 0.76% 92.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 38 0.94% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 54 1.33% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 16 0.39% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 98 2.41% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 9 0.22% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 19 0.47% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.12% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.37% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.07% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 11 0.27% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.10% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.10% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.07% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4061 # Writes before turning the bus around for reads -system.physmem.totQLat 954764500 # Total ticks spent queuing -system.physmem.totMemAccLat 2534339500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 421220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11333.32 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4123 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.374727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.353037 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 26.922743 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 71 1.72% 1.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 7 0.17% 1.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 3190 77.37% 79.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 194 4.71% 83.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 131 3.18% 87.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 35 0.85% 87.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 132 3.20% 91.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 15 0.36% 91.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 23 0.56% 92.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 42 1.02% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 60 1.46% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 20 0.49% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 93 2.26% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.19% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 26 0.63% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 5 0.12% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 22 0.53% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 8 0.19% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 11 0.27% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 5 0.12% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.07% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.12% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4123 # Writes before turning the bus around for reads +system.physmem.totQLat 931934250 # Total ticks spent queuing +system.physmem.totMemAccLat 2504553000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 419365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11111.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30083.32 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29861.25 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.29 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.74 # Average write queue length when enqueuing -system.physmem.readRowHits 67051 # Number of row buffer hits during reads -system.physmem.writeRowHits 81719 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.69 # Row buffer hit rate for writes -system.physmem.avgGap 27065410.10 # Average gap between requests -system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4938610465000 # Time in different power states -system.physmem.memoryStateTime::REF 171427360000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23717365000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 143949960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 153377280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 78544125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 83688000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 313723800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 343379400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 322509600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 350470800 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 335311916160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 335311916160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 122830725285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 123321765465 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 2972506855500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2972076118500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3431508224430 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3431640715605 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.420699 # Core power per rank (mW) -system.physmem.averagePower::1 668.446507 # Core power per rank (mW) +system.physmem.avgWrQLen 12.18 # Average write queue length when enqueuing +system.physmem.readRowHits 66618 # Number of row buffer hits during reads +system.physmem.writeRowHits 86482 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.53 # Row buffer hit rate for writes +system.physmem.avgGap 26457180.21 # Average gap between requests +system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 145862640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 79389750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 313817400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 352952640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250172869440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94379716215 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2235135422250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2580580030335 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.988936 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3685687946000 # Time in different power states +system.physmem_0.memoryStateTime::REF 127900240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17077044750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 152878320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 83263125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 340392000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 351702000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250172869440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95036922225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2235169487250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2581307514360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.001289 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3684742447500 # Time in different power states +system.physmem_1.memoryStateTime::REF 127900240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18039817250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 816782821 # number of cpu cycles simulated +system.cpu0.numCycles 818737889 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71499658 # Number of instructions committed -system.cpu0.committedOps 145804776 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 133691400 # Number of integer alu accesses +system.cpu0.committedInsts 71815441 # Number of instructions committed +system.cpu0.committedOps 146372002 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134241940 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 937441 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14175274 # number of instructions that are conditional controls -system.cpu0.num_int_insts 133691400 # number of integer instructions +system.cpu0.num_func_calls 946109 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14229680 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134241940 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 245252400 # number of times the integer registers were read -system.cpu0.num_int_register_writes 114908320 # number of times the integer registers were written +system.cpu0.num_int_register_reads 246318200 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115340862 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83238542 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55564556 # number of times the CC registers were written -system.cpu0.num_mem_refs 13632532 # number of memory refs -system.cpu0.num_load_insts 10074437 # Number of load instructions -system.cpu0.num_store_insts 3558095 # Number of store instructions -system.cpu0.num_idle_cycles 775198881.273652 # Number of idle cycles -system.cpu0.num_busy_cycles 41583939.726348 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050912 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949088 # Percentage of idle cycles -system.cpu0.Branches 15460140 # Number of branches fetched -system.cpu0.op_class::No_OpClass 93742 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 131973601 90.51% 90.58% # Class of executed instruction -system.cpu0.op_class::IntMult 57512 0.04% 90.62% # Class of executed instruction -system.cpu0.op_class::IntDiv 47972 0.03% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.65% # Class of executed instruction -system.cpu0.op_class::MemRead 10074437 6.91% 97.56% # Class of executed instruction -system.cpu0.op_class::MemWrite 3558095 2.44% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83590760 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55777582 # number of times the CC registers were written +system.cpu0.num_mem_refs 13734986 # number of memory refs +system.cpu0.num_load_insts 10122778 # Number of load instructions +system.cpu0.num_store_insts 3612208 # Number of store instructions +system.cpu0.num_idle_cycles 777021055.677311 # Number of idle cycles +system.cpu0.num_busy_cycles 41716833.322689 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050953 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949047 # Percentage of idle cycles +system.cpu0.Branches 15525387 # Number of branches fetched +system.cpu0.op_class::No_OpClass 95218 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 132436366 90.48% 90.54% # Class of executed instruction +system.cpu0.op_class::IntMult 58371 0.04% 90.58% # Class of executed instruction +system.cpu0.op_class::IntDiv 47638 0.03% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction +system.cpu0.op_class::MemRead 10122778 6.92% 97.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 3612208 2.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 145805359 # Class of executed instruction +system.cpu0.op_class::total 146372579 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1638252 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999461 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 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miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10461.106053 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 134433 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 28093 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 27793 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.809205 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.836937 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33731276500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64767852500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059393 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086728 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045599 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032871 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032140 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018702 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.859382 # mshr miss rate for SoftPFReq accesses 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mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13391.509559 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35877.349273 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32531.537494 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33797.424800 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13773.825439 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15036.881330 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14720.366774 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18412.347743 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17413.099364 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17710.506091 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17385.389624 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16783.661148 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16955.608411 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1546924 # number of writebacks +system.cpu0.dcache.writebacks::total 1546924 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 56 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 365946 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 366002 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1557 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30874 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 32431 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1613 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 396820 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 398433 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1613 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 396820 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 398433 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 162143 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 418897 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 581040 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 59649 # number of WriteReq MSHR misses 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overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1966861250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5809520082 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7776381332 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2132969160 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3102124491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5235093651 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 862802000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2814001254 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3676803254 # number of SoftPFReq MSHR miss cycles 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uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 580448000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 654820000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1235268000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31033289000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33636595500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64669884500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059443 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087070 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045336 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032920 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031131 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018150 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.860552 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850612 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.536618 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048857 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065662 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034570 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061717 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087219 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045361 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12130.411119 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13868.612289 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13383.555920 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35758.674244 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33408.985073 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34328.032754 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13719.224042 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15031.576199 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14701.567614 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18485.023851 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17414.058765 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17737.873200 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17432.195959 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16775.942730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16965.873865 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -615,515 +622,516 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 869855 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.839263 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129296965 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 870367 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 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4555263703 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6460927203 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1905663500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4555263703 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6460927203 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1905663500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4555263703 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6460927203 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004073 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004073 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004073 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.629641 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.629641 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.629641 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604022160 # number of cpu cycles simulated +system.cpu1.numCycles 2604019962 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35714054 # Number of instructions committed -system.cpu1.committedOps 69387825 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64459883 # Number of integer alu accesses +system.cpu1.committedInsts 35730684 # Number of instructions committed +system.cpu1.committedOps 69408718 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64481893 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 492416 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6558216 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64459883 # number of integer instructions +system.cpu1.num_func_calls 491880 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6558534 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64481893 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119340959 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55539831 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119402180 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55560948 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36447320 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27215061 # number of times the CC registers were written -system.cpu1.num_mem_refs 4790084 # number of memory refs -system.cpu1.num_load_insts 2979771 # Number of load instructions -system.cpu1.num_store_insts 1810313 # Number of store instructions -system.cpu1.num_idle_cycles 2477161896.436619 # Number of idle cycles -system.cpu1.num_busy_cycles 126860263.563381 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048717 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951283 # Percentage of idle cycles -system.cpu1.Branches 7226981 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35150 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64505894 92.96% 93.01% # Class of executed instruction -system.cpu1.op_class::IntMult 31723 0.05% 93.06% # Class of executed instruction -system.cpu1.op_class::IntDiv 25263 0.04% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.10% # Class of executed instruction -system.cpu1.op_class::MemRead 2979771 4.29% 97.39% # Class of executed instruction -system.cpu1.op_class::MemWrite 1810313 2.61% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36459460 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27231683 # number of times the CC registers were written +system.cpu1.num_mem_refs 4801643 # number of memory refs +system.cpu1.num_load_insts 2988079 # Number of load instructions +system.cpu1.num_store_insts 1813564 # Number of store instructions +system.cpu1.num_idle_cycles 2476018804.880995 # Number of idle cycles +system.cpu1.num_busy_cycles 128001157.119005 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049155 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950845 # Percentage of idle cycles +system.cpu1.Branches 7226738 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34859 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64514544 92.95% 93.00% # Class of executed instruction +system.cpu1.op_class::IntMult 31705 0.05% 93.04% # Class of executed instruction +system.cpu1.op_class::IntDiv 26275 0.04% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.08% # Class of executed instruction +system.cpu1.op_class::MemRead 2988079 4.31% 97.39% # Class of executed instruction +system.cpu1.op_class::MemWrite 1813564 2.61% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69388114 # Class of executed instruction +system.cpu1.op_class::total 69409026 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29235559 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29235559 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 325219 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26520697 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25831839 # Number of BTB hits +system.cpu2.branchPred.lookups 29092929 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29092929 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 315476 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26409431 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25746575 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.402564 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 591824 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 65511 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154416401 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.490078 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 584007 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63229 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153281353 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10884284 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 144162908 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29235559 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26423663 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 142028644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 680270 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 102603 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9165 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 58663 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 3537 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 505 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3520608 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 170393 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3486 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 153432274 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.849912 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.030749 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10494646 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 143459530 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29092929 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26330582 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 141345595 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 659748 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 97189 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 4757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7888 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 55541 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 2125 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3459376 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 164097 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3515 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 152337401 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.854593 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.033085 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98146892 63.97% 63.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 849455 0.55% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23639563 15.41% 79.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 596355 0.39% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 820460 0.53% 80.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 843182 0.55% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 578600 0.38% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 712944 0.46% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27244823 17.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 97296263 63.87% 63.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 832536 0.55% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23575408 15.48% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 586344 0.38% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 814239 0.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 832677 0.55% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 567105 0.37% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 704147 0.46% 82.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27128682 17.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 153432274 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189329 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.933598 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10016257 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93700057 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23552939 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5059225 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 340786 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 280915475 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 340786 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12183481 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76207577 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4633489 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26208589 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13095410 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 279683437 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 223314 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5946104 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 66230 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4950669 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 334110880 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 610223912 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 374707495 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321802825 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12308055 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 159496 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 160992 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24728287 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6624186 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3707561 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 399799 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 335575 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 277732310 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 423659 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 275640781 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 103956 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8785176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13632215 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64646 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 153432274 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.796498 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.396081 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 152337401 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189801 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.935923 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9688238 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 93124886 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23395204 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5013369 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 330525 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 279674043 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 330525 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11836052 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76001562 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4488572 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 26027497 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12868079 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278471354 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 223428 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5927671 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 64367 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4764004 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 332707542 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 607302278 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 372965322 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 116 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320669422 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12038120 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 154906 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 156494 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24500450 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6532282 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3632430 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 395237 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 325236 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276569941 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 416887 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274532538 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 100855 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8584816 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13350787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 62925 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 152337401 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.802135 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.398465 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90704132 59.12% 59.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5447937 3.55% 62.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3973753 2.59% 65.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3694975 2.41% 67.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22399331 14.60% 82.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2621812 1.71% 83.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23895005 15.57% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 478633 0.31% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 216696 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 89943207 59.04% 59.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5345468 3.51% 62.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3937636 2.58% 65.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3657575 2.40% 67.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22350485 14.67% 82.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2587133 1.70% 83.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23826816 15.64% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 472076 0.31% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 217005 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 153432274 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 152337401 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1775129 86.29% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 6 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 95 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 220574 10.72% 97.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 61430 2.99% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1755222 86.36% 86.36% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 86.36% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 168 0.01% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.37% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 216539 10.65% 97.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 60595 2.98% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 78003 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 265083835 96.17% 96.20% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56667 0.02% 96.22% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50646 0.02% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6950861 2.52% 98.76% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3420769 1.24% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 75570 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264135020 96.21% 96.24% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 55664 0.02% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49906 0.02% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6866354 2.50% 98.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3350024 1.22% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 275640781 # Type of FU issued -system.cpu2.iq.rate 1.785049 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2057234 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007463 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 706874938 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 286945707 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 274032875 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 88 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 277619970 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 42 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 720639 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274532538 # Type of FU issued +system.cpu2.iq.rate 1.791037 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2032524 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007404 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 703535734 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 285575754 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272952384 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 276489433 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 59 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 719306 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1236107 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6357 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5250 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 663784 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1204229 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6084 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4820 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 645551 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 755898 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23011 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 756143 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 21686 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 340786 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 71022096 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1766284 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 278155969 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 42225 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6624208 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3707561 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 245817 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 196681 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1270617 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5250 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 184655 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 193373 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 378028 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 275054919 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6809103 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 532643 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 330525 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70849508 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1741832 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 276986828 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 38338 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6532282 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3632430 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 240586 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 193301 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1249611 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4820 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 179927 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 186201 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 366128 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273965652 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6730604 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 516589 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10142277 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27929616 # Number of branches executed -system.cpu2.iew.exec_stores 3333174 # Number of stores executed -system.cpu2.iew.exec_rate 1.781255 # Inst execution rate -system.cpu2.iew.wb_sent 274858802 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 274032897 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213637344 # num instructions producing a value -system.cpu2.iew.wb_consumers 350353641 # num instructions consuming a value +system.cpu2.iew.exec_refs 9996676 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27816636 # Number of branches executed +system.cpu2.iew.exec_stores 3266072 # Number of stores executed +system.cpu2.iew.exec_rate 1.787338 # Inst execution rate +system.cpu2.iew.wb_sent 273775485 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272952416 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212880444 # num instructions producing a value +system.cpu2.iew.wb_consumers 349125324 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.774636 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609776 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.780728 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609754 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9127323 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 359013 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 328005 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152066658 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.769136 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.649747 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8921992 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 353962 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 318190 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 151004847 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.775201 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.653055 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94590362 62.20% 62.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4261266 2.80% 65.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1284145 0.84% 65.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24598382 16.18% 82.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1032712 0.68% 82.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 681511 0.45% 83.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 477761 0.31% 83.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23127222 15.21% 98.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2013297 1.32% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 93801921 62.12% 62.12% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4186228 2.77% 64.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1259762 0.83% 65.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24518557 16.24% 81.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1012800 0.67% 82.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 677237 0.45% 83.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 473264 0.31% 83.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23075029 15.28% 98.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2000049 1.32% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152066658 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136342288 # Number of instructions committed -system.cpu2.commit.committedOps 269026601 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 151004847 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135819902 # Number of instructions committed +system.cpu2.commit.committedOps 268063987 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8431878 # Number of memory references committed -system.cpu2.commit.loads 5388101 # Number of loads committed -system.cpu2.commit.membars 162694 # Number of memory barriers committed -system.cpu2.commit.branches 27513301 # Number of branches committed +system.cpu2.commit.refs 8314932 # Number of memory references committed +system.cpu2.commit.loads 5328053 # Number of loads committed +system.cpu2.commit.membars 161474 # Number of memory barriers committed +system.cpu2.commit.branches 27411077 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245807321 # Number of committed integer instructions. -system.cpu2.commit.function_calls 438928 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 45809 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 260445608 96.81% 96.83% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 54412 0.02% 96.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 48894 0.02% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5388101 2.00% 98.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3043777 1.13% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244897516 # Number of committed integer instructions. +system.cpu2.commit.function_calls 434912 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 44620 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 259602696 96.84% 96.86% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 53542 0.02% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48197 0.02% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5328053 1.99% 98.89% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2986879 1.11% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 269026601 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2013297 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 268063987 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2000049 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 428179753 # The number of ROB reads -system.cpu2.rob.rob_writes 557679634 # The number of ROB writes -system.cpu2.timesIdled 117886 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 984127 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4904701568 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136342288 # Number of Instructions Simulated -system.cpu2.committedOps 269026601 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.132564 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.132564 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882952 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882952 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 366241285 # number of integer regfile reads -system.cpu2.int_regfile_writes 219634896 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads +system.cpu2.rob.rob_reads 425964171 # The number of ROB reads +system.cpu2.rob.rob_writes 555310468 # The number of ROB writes +system.cpu2.timesIdled 112460 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 943952 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4909839532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135819902 # Number of Instructions Simulated +system.cpu2.committedOps 268063987 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.128563 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.128563 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.886082 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.886082 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364708409 # number of integer regfile reads +system.cpu2.int_regfile_writes 218787106 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72944 # number of floating regfile reads system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139741848 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107405291 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89464185 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137179 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3554524 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554524 # Transaction distribution +system.cpu2.cc_regfile_reads 139159619 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107004309 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89032423 # number of misc regfile reads +system.cpu2.misc_regfile_writes 133306 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3554527 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554527 # Transaction distribution system.iobus.trans_dist::WriteReq 57693 # Transaction distribution system.iobus.trans_dist::WriteResp 10973 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution @@ -1148,11 +1156,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 7129192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227766 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7227772 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -1172,24 +1180,24 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 3570795 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605211 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2723904 # Layer occupancy (ticks) +system.iobus.pkt_size::total 6605235 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2673040 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 5226000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4313000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1197,64 +1205,64 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 355000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 345000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10403000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10349000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 252354975 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 277910069 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303598000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 302790000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31582004 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 34215251 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1142000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1117000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47566 # number of replacements -system.iocache.tags.tagsinuse 0.080066 # Cycle average of tags in use +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.087266 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47582 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.080066 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005004 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005004 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000571413009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.087266 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005454 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005454 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428589 # Number of tag accesses -system.iocache.tags.data_accesses 428589 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 901 # number of ReadReq misses -system.iocache.ReadReq_misses::total 901 # number of ReadReq misses +system.iocache.tags.tag_accesses 428616 # Number of tag accesses +system.iocache.tags.data_accesses 428616 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 901 # number of demand (read+write) misses -system.iocache.demand_misses::total 901 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 901 # number of overall misses -system.iocache.overall_misses::total 901 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129757279 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129757279 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 6940731692 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6940731692 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 129757279 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 129757279 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 129757279 # number of overall miss cycles -system.iocache.overall_miss_latency::total 129757279 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 901 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 901 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses +system.iocache.demand_misses::total 904 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses +system.iocache.overall_misses::total 904 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131125053 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 131125053 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 7701347765 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 7701347765 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 131125053 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 131125053 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 131125053 # number of overall miss cycles +system.iocache.overall_miss_latency::total 131125053 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 901 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 901 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 901 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 901 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1263,311 +1271,311 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144014.738069 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 144014.738069 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 148560.181764 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 148560.181764 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 144014.738069 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 144014.738069 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 144014.738069 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 144014.738069 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 39427 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145049.837389 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 164840.491545 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 164840.491545 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145049.837389 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145049.837389 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 44239 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5130 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5740 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.685575 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.707143 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 749 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 26264 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 26264 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 749 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 749 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 749 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 749 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90783279 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 90783279 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 5574995700 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 5574995700 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 90783279 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 90783279 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 90783279 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 90783279 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.831299 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.831299 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.562158 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.562158 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.831299 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.831299 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.831299 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.831299 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 121205.979973 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212267.579196 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212267.579196 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 121205.979973 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 121205.979973 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 121205.979973 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 737 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28920 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 28920 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 737 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 737 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 737 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92773553 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6197505767 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6197505767 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 92773553 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 92773553 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.815265 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.619007 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.619007 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.815265 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.815265 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 125879.990502 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 214298.263036 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214298.263036 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 125879.990502 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 125879.990502 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104681 # number of replacements -system.l2c.tags.tagsinuse 64826.811839 # Cycle average of tags in use -system.l2c.tags.total_refs 3703362 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168901 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.926229 # Average number of references to valid blocks. +system.l2c.tags.replacements 104557 # number of replacements +system.l2c.tags.tagsinuse 64826.146133 # Cycle average of tags in use +system.l2c.tags.total_refs 3692284 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168716 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.884611 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51337.140952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1734.424462 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4936.447431 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 379.153025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1982.017983 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.155297 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 876.173345 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3570.165084 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.783343 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51357.956330 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134652 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1732.560753 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4954.090850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 380.669805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1966.640889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.273350 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 862.228039 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3565.591465 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.783660 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026465 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075324 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005785 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030243 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.013369 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.054476 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989179 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3804 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7293 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52804 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33932949 # Number of tag accesses -system.l2c.tags.data_accesses 33932949 # Number of data accesses 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-system.l2c.demand_avg_mshr_miss_latency::total 60010.173814 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61210.236887 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56656.145348 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72356.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66154.300875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61406.688131 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60010.173814 # average overall mshr miss latency +system.l2c.writebacks::writebacks 96401 # number of writebacks +system.l2c.writebacks::total 96401 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 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58227327500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 540082000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 615936000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1156018000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28538038000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30845307500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59383345500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014291 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023125 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000486 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014103 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010973 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.857143 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.837891 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.409255 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.426617 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.357477 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.200283 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014291 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.107352 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014103 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.065666 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.032003 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014291 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.107352 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014103 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.065666 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.032003 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61254.281950 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63972.280938 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 72330.357143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65476.056740 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66393.809450 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 65262.056904 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12383.888889 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10382.109557 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11122.856094 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55177.106921 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59121.672710 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57409.961621 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61254.281950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56676.241754 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72330.357143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65476.056740 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61155.346743 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59803.133457 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61254.281950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56676.241754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72330.357143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65476.056740 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61155.346743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59803.133457 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1693,66 +1707,62 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5119623 # Transaction distribution -system.membus.trans_dist::ReadResp 5119621 # Transaction distribution -system.membus.trans_dist::WriteReq 13885 # Transaction distribution -system.membus.trans_dist::WriteResp 13885 # Transaction distribution -system.membus.trans_dist::Writeback 143242 # Transaction distribution +system.membus.trans_dist::ReadReq 5119668 # Transaction distribution +system.membus.trans_dist::ReadResp 5119668 # Transaction distribution +system.membus.trans_dist::WriteReq 13886 # Transaction distribution +system.membus.trans_dist::WriteResp 13886 # Transaction distribution +system.membus.trans_dist::Writeback 143068 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1670 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1670 # Transaction distribution -system.membus.trans_dist::ReadExReq 130030 # Transaction distribution -system.membus.trans_dist::ReadExResp 130030 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1653 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1653 # Transaction distribution +system.membus.trans_dist::ReadExReq 130108 # Transaction distribution +system.membus.trans_dist::ReadExResp 130108 # Transaction distribution system.membus.trans_dist::MessageReq 1666 # Transaction distribution system.membus.trans_dist::MessageResp 1666 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039944 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455611 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10624751 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141603 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141603 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10769686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3040070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10624915 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141621 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141621 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10769868 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570795 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079885 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17550016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27200696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6014848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6014848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33222208 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 744 # Total snoops (count) -system.membus.snoop_fanout::samples 370602 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6080137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17551104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27202036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6015808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33224508 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 602 # Total snoops (count) +system.membus.snoop_fanout::samples 370472 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 370602 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 370472 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 370602 # Request fanout histogram -system.membus.reqLayer0.occupancy 163555999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 370472 # Request fanout histogram +system.membus.reqLayer0.occupancy 162446500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314970500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 314906500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2284000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2234000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1078528499 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1120775500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1142000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1117000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1669525375 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1662967675 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 33021996 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 35567749 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1766,52 +1776,51 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7445520 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7444981 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13887 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13887 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1547770 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 26264 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1672 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291256 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291256 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740744 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14998032 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 215574 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17027929 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55702976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213603640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 275304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 788512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270370432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 71210 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4262409 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011172 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105107 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7434879 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7434349 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1546924 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 28920 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291412 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291412 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1730144 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14995223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73480 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207718 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17006565 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55364032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213483380 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 273608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 760144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 269881164 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 70776 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4251023 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011203 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105249 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4214788 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47621 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4203399 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4262409 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5252515580 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4251023 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5194614325 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 954000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 931500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2476922699 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2395792281 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4880781676 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4837647628 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 25221399 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 25185912 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 92014088 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 87831597 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index a4eaa28e3..52746e018 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061494 # Nu sim_ticks 61493732000 # Number of ticks simulated final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 280016 # Simulator instruction rate (inst/s) -host_op_rate 281410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 190051649 # Simulator tick rate (ticks/s) -host_mem_usage 385752 # Number of bytes of host memory used -host_seconds 323.56 # Real time elapsed on the host +host_inst_rate 271090 # Simulator instruction rate (inst/s) +host_op_rate 272440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 183993432 # Simulator tick rate (ticks/s) +host_mem_usage 445016 # Number of bytes of host memory used +host_seconds 334.22 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # By system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation -system.physmem.totQLat 73246500 # Total ticks spent queuing -system.physmem.totMemAccLat 365277750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 73247750 # Total ticks spent queuing +system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.83 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.83 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 90.09 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 3948227.51 # Average gap between requests system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 56242943250 # Time in different power states -system.physmem.memoryStateTime::REF 2053220000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 3193793750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6320160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 5261760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3448500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2871000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 63663600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 57462600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2490497865 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2514078765 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34708310250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 34687625250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41288338695 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41283397695 # Total energy per rank (pJ) -system.physmem.averagePower::0 671.483256 # Core power per rank (mW) -system.physmem.averagePower::1 671.402899 # Core power per rank (mW) +system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.483541 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.402933 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20789429 # Number of BP lookups system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 98.812096 # BT system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -383,14 +420,14 @@ system.cpu.dcache.demand_misses::cpu.inst 988866 # n system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 988866 # number of overall misses system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910311744 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11910311744 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345697500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2345697500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 14256009244 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14256009244 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 14256009244 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14256009244 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 14256024494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) @@ -411,14 +448,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14416.522809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14416.522809 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.315542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.478920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.538231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,14 +482,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 950203 system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958869756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958869756 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333434750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333434750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292304506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11292304506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292304506 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11292304506 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009877 # mshr miss rate for WriteReq accesses @@ -461,22 +498,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034871 system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.097668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.411179 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.411179 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id @@ -556,13 +593,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10247.121792 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236502 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.885294 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027188 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy @@ -593,14 +630,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 15583 # system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 15583 # number of overall misses system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71718500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71718500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958069250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 958069250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1029787750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1029787750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1029787750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1029787750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71704250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958084250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1029788500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1029788500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 904238 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses) @@ -619,14 +656,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,14 +686,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 15575 system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 15575 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58344750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58344750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774500250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774500250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832845000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 832845000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832845000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 832845000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310982 # mshr miss rate for ReadExReq accesses @@ -665,14 +702,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution @@ -705,7 +742,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # La system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428672494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1031 # Transaction distribution @@ -728,7 +765,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 15575 # Request fanout histogram system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 146202000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 3f4662e45..ea993d96c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057713 # Number of seconds simulated -sim_ticks 57712782000 # Number of ticks simulated -final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057719 # Number of seconds simulated +sim_ticks 57719377000 # Number of ticks simulated +final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133110 # Simulator instruction rate (inst/s) -host_op_rate 133773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84801314 # Simulator tick rate (ticks/s) -host_mem_usage 388280 # Number of bytes of host memory used -host_seconds 680.56 # Real time elapsed on the host +host_inst_rate 125223 # Simulator instruction rate (inst/s) +host_op_rate 125847 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79786059 # Simulator tick rate (ticks/s) +host_mem_usage 443544 # Number of bytes of host memory used +host_seconds 723.43 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory -system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory -system.physmem.bytes_written::total 73600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory -system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 17490 # Number of read requests accepted -system.physmem.writeReqs 1150 # Number of write requests accepted -system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory +system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory +system.physmem.bytes_written::total 19776 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory +system.physmem.num_writes::total 309 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15872 # Number of read requests accepted +system.physmem.writeReqs 309 # Number of write requests accepted +system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue +system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1094 # Per bank write bursts -system.physmem.perBankRdBursts::1 953 # Per bank write bursts -system.physmem.perBankRdBursts::2 1083 # Per bank write bursts -system.physmem.perBankRdBursts::3 1113 # Per bank write bursts -system.physmem.perBankRdBursts::4 1125 # Per bank write bursts -system.physmem.perBankRdBursts::5 1235 # Per bank write bursts -system.physmem.perBankRdBursts::6 1314 # Per bank write bursts -system.physmem.perBankRdBursts::7 1243 # Per bank write bursts -system.physmem.perBankRdBursts::8 1060 # Per bank write bursts +system.physmem.perBankRdBursts::0 999 # Per bank write bursts +system.physmem.perBankRdBursts::1 876 # Per bank write bursts +system.physmem.perBankRdBursts::2 956 # Per bank write bursts +system.physmem.perBankRdBursts::3 1023 # Per bank write bursts +system.physmem.perBankRdBursts::4 1064 # Per bank write bursts +system.physmem.perBankRdBursts::5 1127 # Per bank write bursts +system.physmem.perBankRdBursts::6 1115 # Per bank write bursts +system.physmem.perBankRdBursts::7 1101 # Per bank write bursts +system.physmem.perBankRdBursts::8 1033 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 1021 # Per bank write bursts -system.physmem.perBankRdBursts::11 923 # Per bank write bursts -system.physmem.perBankRdBursts::12 921 # Per bank write bursts -system.physmem.perBankRdBursts::13 987 # Per bank write bursts -system.physmem.perBankRdBursts::14 1105 # Per bank write bursts -system.physmem.perBankRdBursts::15 1049 # Per bank write bursts -system.physmem.perBankWrBursts::0 72 # Per bank write bursts +system.physmem.perBankRdBursts::10 937 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 910 # Per bank write bursts +system.physmem.perBankRdBursts::13 886 # Per bank write bursts +system.physmem.perBankRdBursts::14 919 # Per bank write bursts +system.physmem.perBankRdBursts::15 912 # Per bank write bursts +system.physmem.perBankWrBursts::0 23 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 62 # Per bank write bursts -system.physmem.perBankWrBursts::3 19 # Per bank write bursts -system.physmem.perBankWrBursts::4 14 # Per bank write bursts -system.physmem.perBankWrBursts::5 111 # Per bank write bursts -system.physmem.perBankWrBursts::6 193 # Per bank write bursts -system.physmem.perBankWrBursts::7 122 # Per bank write bursts -system.physmem.perBankWrBursts::8 49 # Per bank write bursts +system.physmem.perBankWrBursts::2 4 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 9 # Per bank write bursts +system.physmem.perBankWrBursts::5 29 # Per bank write bursts +system.physmem.perBankWrBursts::6 62 # Per bank write bursts +system.physmem.perBankWrBursts::7 30 # Per bank write bursts +system.physmem.perBankWrBursts::8 15 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 68 # Per bank write bursts -system.physmem.perBankWrBursts::11 20 # Per bank write bursts -system.physmem.perBankWrBursts::12 15 # Per bank write bursts -system.physmem.perBankWrBursts::13 94 # Per bank write bursts -system.physmem.perBankWrBursts::14 168 # Per bank write bursts -system.physmem.perBankWrBursts::15 110 # Per bank write bursts +system.physmem.perBankWrBursts::10 10 # Per bank write bursts +system.physmem.perBankWrBursts::11 1 # Per bank write bursts +system.physmem.perBankWrBursts::12 9 # Per bank write bursts +system.physmem.perBankWrBursts::13 27 # Per bank write bursts +system.physmem.perBankWrBursts::14 48 # Per bank write bursts +system.physmem.perBankWrBursts::15 21 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57712604500 # Total gap between requests +system.physmem.totGap 57719226000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 17490 # Read request sizes (log2) +system.physmem.readPktSize::6 15872 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1150 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,118 +197,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads -system.physmem.totQLat 228948216 # Total ticks spent queuing -system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads +system.physmem.totQLat 179464908 # Total ticks spent queuing +system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.16 # Data bus utilization in percentage -system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing -system.physmem.readRowHits 14950 # Number of row buffer hits during reads -system.physmem.writeRowHits 375 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes -system.physmem.avgGap 3096169.77 # Average gap between requests -system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states -system.physmem.memoryStateTime::REF 1927120000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 11854080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 10636920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 6468000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 5803875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 71299800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 62602800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3842640 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3395520 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2993861160 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3031288785 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 32001000000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 31968168750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 38857772400 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 38851343370 # Total energy per rank (pJ) -system.physmem.averagePower::0 673.305017 # Core power per rank (mW) -system.physmem.averagePower::1 673.193618 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 17158 # Transaction distribution -system.membus.trans_dist::ReadResp 17158 # Transaction distribution -system.membus.trans_dist::Writeback 1150 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 332 # Transaction distribution -system.membus.trans_dist::ReadExResp 332 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 18642 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18642 # Request fanout histogram -system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 28272297 # Number of BP lookups -system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing +system.physmem.readRowHits 14166 # Number of row buffer hits during reads +system.physmem.writeRowHits 92 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes +system.physmem.avgGap 3567098.82 # Average gap between requests +system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.607894 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states +system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.433104 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states +system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 28271166 # Number of BP lookups +system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -330,6 +316,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -351,6 +345,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -372,6 +374,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -394,83 +404,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 115425565 # number of cpu cycles simulated +system.cpu.numCycles 115438755 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679445 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -478,9 +488,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available @@ -509,12 +519,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued @@ -537,90 +547,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued -system.cpu.iq.rate 0.878733 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued +system.cpu.iq.rate 0.878644 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12666 # number of nop insts executed -system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed -system.cpu.iew.exec_branches 20629033 # Number of branches executed -system.cpu.iew.exec_stores 4918889 # Number of stores executed -system.cpu.iew.exec_rate 0.867621 # Inst execution rate -system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59710820 # num instructions producing a value -system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value +system.cpu.iew.exec_nop 12667 # number of nop insts executed +system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed +system.cpu.iew.exec_branches 20629236 # Number of branches executed +system.cpu.iew.exec_stores 4918943 # Number of stores executed +system.cpu.iew.exec_rate 0.867532 # Inst execution rate +system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59706662 # num instructions producing a value +system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back +system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -666,396 +676,79 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction -system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 217038076 # The number of ROB reads -system.cpu.rob.rob_writes 219583065 # The number of ROB writes -system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 217026090 # The number of ROB reads +system.cpu.rob.rob_writes 219584249 # The number of ROB writes +system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads -system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108123923 # number of integer regfile reads -system.cpu.int_regfile_writes 58738896 # number of integer regfile writes +system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads +system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108125012 # number of integer regfile reads +system.cpu.int_regfile_writes 58739124 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 100 # number of floating regfile writes -system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads -system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes -system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads +system.cpu.fp_regfile_writes 99 # number of floating regfile writes +system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads +system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes +system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 28370 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 456 # number of replacements -system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits -system.cpu.icache.overall_hits::total 32315555 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses -system.cpu.icache.overall_misses::total 1024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 1672 # number of replacements -system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10807.797190 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 104.008842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 299.224972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1347.657528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.659656 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006348 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.018263 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082254 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.766522 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1557 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1370 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 12200 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.095032 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.872864 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 174560305 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 174560305 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 753 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5260483 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5261236 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 5407164 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 5407164 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224791 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224791 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 753 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5485274 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5486027 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 753 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5485274 # number of overall hits -system.cpu.l2cache.overall_hits::total 5486027 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 993 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1156 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 496 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 496 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1489 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1652 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1489 # number of overall misses -system.cpu.l2cache.overall_misses::total 1652 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12439500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59393247 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71832747 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31513998 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 31513998 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12439500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 90907245 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 103346745 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12439500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 90907245 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 103346745 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 916 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 5261476 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5262392 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 5407164 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 5407164 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 225287 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 225287 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 916 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5486763 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5487679 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 916 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5486763 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5487679 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177948 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000189 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000220 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002202 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002202 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177948 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000271 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000301 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177948 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000271 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000301 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76315.950920 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59811.930514 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62139.054498 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63536.286290 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63536.286290 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62558.562349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62558.562349 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 50 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16.400000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1150 # number of writebacks -system.cpu.l2cache.writebacks::total 1150 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 256 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 418 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 442 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 418 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 442 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 139 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26554 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10286000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 72273751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 5486251 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5486247 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits -system.cpu.dcache.overall_hits::total 18263549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits +system.cpu.dcache.overall_hits::total 18263472 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses -system.cpu.dcache.overall_misses::total 9970085 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses +system.cpu.dcache.overall_misses::total 9970594 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) @@ -1064,92 +757,452 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks -system.cpu.dcache.writebacks::total 5407164 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks +system.cpu.dcache.writebacks::total 5460017 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154868 # 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misses system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194331 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.194331 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7256.749186 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7256.749186 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9715.487663 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9715.487663 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50100 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50100 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7356.585936 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7356.585936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 447 # number of replacements +system.cpu.icache.tags.tagsinuse 428.924531 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32314402 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35667.110375 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1144 # number of overall misses +system.cpu.icache.overall_misses::total 1144 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55657984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55657984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55657984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55657984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55657984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55657984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32315546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32315546 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32315546 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32315546 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32315546 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32315546 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48652.083916 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48652.083916 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48652.083916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48652.083916 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17056 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 223 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 76.484305 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 238 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 238 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 238 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 238 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 906 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 906 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 906 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 906 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 906 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44276742 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 44276742 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44276742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 44276742 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44276742 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 44276742 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48870.576159 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48870.576159 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.prefetcher.num_hwpf_issued 4494242 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296949 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 693182 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 14114027 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 432 # number of replacements +system.cpu.l2cache.tags.tagsinuse 12071.451375 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10694296 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15874 # Sample count of references to valid blocks. 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 175404109 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 175404109 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 211 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5261084 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5261295 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 5460017 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 5460017 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224780 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224780 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5485864 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5486075 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5485864 # number of overall hits +system.cpu.l2cache.overall_hits::total 5486075 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 695 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 386 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 509 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 509 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1590 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 895 # number of overall misses +system.cpu.l2cache.overall_misses::total 1590 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42529250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21068985 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 63598235 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30498 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 30498 # number of UpgradeReq miss cycles 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67775.029470 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 61695.424528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 61695.424528 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks +system.cpu.l2cache.writebacks::total 309 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 168 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 168 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 694 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20230 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 20230 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 682 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1376 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 682 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20230 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 21606 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36534500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16113750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52648250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 777111161 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 22591778 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 22591778 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36534500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 38705528 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 75240028 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36534500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 38705528 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 852351189 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 22341 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 15531 # Transaction distribution +system.membus.trans_dist::ReadResp 15531 # Transaction distribution +system.membus.trans_dist::Writeback 309 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 341 # Transaction distribution +system.membus.trans_dist::ReadExResp 341 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 16183 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 16183 # Request fanout histogram +system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 0aa02b40d..16d507b60 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000000 # Number of ticks simulated final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2068738 # Simulator instruction rate (inst/s) -host_op_rate 2079040 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1236208278 # Simulator tick rate (ticks/s) -host_mem_usage 428768 # Number of bytes of host memory used -host_seconds 43.80 # Real time elapsed on the host +host_inst_rate 1669323 # Simulator instruction rate (inst/s) +host_op_rate 1677636 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 997531404 # Simulator tick rate (ticks/s) +host_mem_usage 433488 # Number of bytes of host memory used +host_seconds 54.28 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 349238802 # Wr system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 130287905 # Transaction distribution -system.membus.trans_dist::ReadResp 130291792 # Transaction distribution -system.membus.trans_dist::WriteReq 4734981 # Transaction distribution -system.membus.trans_dist::WriteResp 4734981 # Transaction distribution -system.membus.trans_dist::SoftPFReq 510 # Transaction distribution -system.membus.trans_dist::SoftPFResp 510 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 135031170 # Request fanout histogram -system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 135031170 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction +system.membus.trans_dist::ReadReq 130287905 # Transaction distribution +system.membus.trans_dist::ReadResp 130291792 # Transaction distribution +system.membus.trans_dist::WriteReq 4734981 # Transaction distribution +system.membus.trans_dist::WriteResp 4734981 # Transaction distribution +system.membus.trans_dist::SoftPFReq 510 # Transaction distribution +system.membus.trans_dist::SoftPFResp 510 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 135031170 # Request fanout histogram +system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 135031170 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index b163f38c3..3f9742fb4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147041 # Nu sim_ticks 147041218000 # Number of ticks simulated final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130471 # Simulator instruction rate (inst/s) -host_op_rate 1136089 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1835190843 # Simulator tick rate (ticks/s) -host_mem_usage 438268 # Number of bytes of host memory used -host_seconds 80.12 # Real time elapsed on the host +host_inst_rate 1114927 # Simulator instruction rate (inst/s) +host_op_rate 1120467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1809956176 # Simulator tick rate (ticks/s) +host_mem_usage 442716 # Number of bytes of host memory used +host_seconds 81.24 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 251576 # In system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 792 # Transaction distribution -system.membus.trans_dist::ReadResp 792 # Transaction distribution -system.membus.trans_dist::ReadExReq 14548 # Transaction distribution -system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15340 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,144 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits +system.cpu.dcache.overall_hits::total 26245827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses +system.cpu.dcache.overall_misses::total 946799 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks +system.cpu.dcache.writebacks::total 942334 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. @@ -429,144 +576,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits -system.cpu.dcache.overall_hits::total 26245827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses -system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks -system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution @@ -600,5 +609,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 898500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 792 # Transaction distribution +system.membus.trans_dist::ReadResp 792 # Transaction distribution +system.membus.trans_dist::ReadExReq 14548 # Transaction distribution +system.membus.trans_dist::ReadExResp 14548 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15340 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15340 # Request fanout histogram +system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index afe4ad98b..a20619a99 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061857 # Nu sim_ticks 61857343500 # Number of ticks simulated final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117254 # Simulator instruction rate (inst/s) -host_op_rate 206466 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45908562 # Simulator tick rate (ticks/s) -host_mem_usage 395064 # Number of bytes of host memory used -host_seconds 1347.40 # Real time elapsed on the host +host_inst_rate 113051 # Simulator instruction rate (inst/s) +host_op_rate 199065 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44263102 # Simulator tick rate (ticks/s) +host_mem_usage 453712 # Number of bytes of host memory used +host_seconds 1397.49 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Wr system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads -system.physmem.totQLat 131010750 # Total ticks spent queuing -system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 130999000 # Total ticks spent queuing +system.physmem.totMemAccLat 700455250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4313.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23063.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s @@ -244,56 +244,34 @@ system.physmem.readRowHitRate 91.19 # Ro system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes system.physmem.avgGap 2017525.41 # Average gap between requests system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 55617527500 # Time in different power states -system.physmem.memoryStateTime::REF 2065440000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 10939320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 9623880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 5968875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 5251125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 122226000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 114246600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 1095120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 51840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2776037940 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2977033050 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34677417000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 34501105500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41633684895 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41647312635 # Total energy per rank (pJ) -system.physmem.averagePower::0 673.093577 # Core power per rank (mW) -system.physmem.averagePower::1 673.313897 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1465 # Transaction distribution -system.membus.trans_dist::ReadResp 1462 # Transaction distribution -system.membus.trans_dist::Writeback 197 # Transaction distribution -system.membus.trans_dist::ReadExReq 28998 # Transaction distribution -system.membus.trans_dist::ReadExResp 28998 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30660 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30660 # Request fanout histogram -system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 10939320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5968875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1095120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2776043070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34677412500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41633685525 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.093587 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57673269750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2115534000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 9623880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5251125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114246600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2977027920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34501101750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41647303755 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.313903 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57380456750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2409426750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 37414357 # Number of BP lookups system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect @@ -303,16 +281,17 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 123714688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28240184 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 28240185 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94568947 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 94568946 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1664995 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps @@ -339,22 +318,22 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13285380 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63221157 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 13285381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63221156 # Number of cycles decode is blocked system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18592313 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 18592314 # Number of cycles rename is idle system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54481539 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 54481538 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48119118 # Number of times rename has blocked due to LQ full +system.cpu.rename.LQFullEvents 48119117 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made @@ -380,21 +359,21 @@ system.cpu.iq.issued_per_cycle::samples 123656373 # Nu system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30107103 24.35% 24.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30107102 24.35% 24.35% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16727631 13.53% 53.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16727632 13.53% 53.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16031842 12.96% 80.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12684149 10.26% 90.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5762402 4.66% 95.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4173790 3.38% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1554838 1.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16031841 12.96% 80.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12684150 10.26% 90.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5762404 4.66% 95.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4173789 3.38% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1554837 1.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 316998 7.53% 7.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 316999 7.53% 7.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available @@ -463,17 +442,17 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued system.cpu.iq.rate 2.489411 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4211171 # FU busy when requested +system.cpu.iq.fu_busy_cnt 4211172 # FU busy when requested system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 743874544 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 743874545 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 312154273 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 312154274 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58255906 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 58255905 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed @@ -509,8 +488,8 @@ system.cpu.iew.exec_stores 33824606 # Nu system.cpu.iew.exec_rate 2.480687 # Inst execution rate system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231632885 # num instructions producing a value -system.cpu.iew.wb_consumers 336126878 # num instructions consuming a value +system.cpu.iew.wb_producers 231632886 # num instructions producing a value +system.cpu.iew.wb_consumers 336126880 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back @@ -522,12 +501,12 @@ system.cpu.commit.committed_per_cycle::samples 117208008 system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52857680 45.10% 45.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52857679 45.10% 45.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10970810 9.36% 68.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8748486 7.46% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10970811 9.36% 68.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8748487 7.46% 75.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1731777 1.48% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1731776 1.48% 78.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle @@ -600,37 +579,121 @@ system.cpu.cc_regfile_reads 107699117 # nu system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121417500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 2072433 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68459745 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.968355 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 144502465 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 144502465 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37113882 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37113882 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68459745 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68459745 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68459745 # number of overall hits +system.cpu.dcache.overall_hits::total 68459745 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses +system.cpu.dcache.overall_misses::total 2753223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861027000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31861027000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2765155494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34626182494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34626182494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34626182494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34626182494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39773216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39773216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 71212968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 71212968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 71212968 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 71212968 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.829411 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.829411 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.325437 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.325437 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12576.599314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12576.599314 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks +system.cpu.dcache.writebacks::total 2066654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524097244 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24524097244 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524097244 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24524097244 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.913780 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.913780 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.061317 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.061317 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 62 # number of replacements system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. @@ -660,12 +723,12 @@ system.cpu.icache.demand_misses::cpu.inst 1347 # n system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses system.cpu.icache.overall_misses::total 1347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 92883749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 92883749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 92883749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 92883749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 92883749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 92883749 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 92877749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 92877749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 92877749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 92877749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 92877749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 92877749 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses @@ -678,12 +741,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68956.012621 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68956.012621 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68951.558278 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68951.558278 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68951.558278 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68951.558278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68951.558278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68951.558278 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -704,32 +767,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1026 system.cpu.icache.demand_mshr_misses::total 1026 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1026 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72336999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 72336999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72336999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 72336999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72336999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 72336999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72330999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 72330999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72330999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 72330999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72330999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 72330999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70503.897661 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70503.897661 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70498.049708 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70498.049708 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70498.049708 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70498.049708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70498.049708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70498.049708 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 515 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20693.420536 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20693.420547 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4029533 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30444 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.358856 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319871 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319882 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.987127 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 249.113538 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.603098 # Average percentage of cache occupancy @@ -769,17 +832,17 @@ system.cpu.l2cache.demand_misses::total 30463 # nu system.cpu.l2cache.overall_misses::cpu.inst 1010 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29453 # number of overall misses system.cpu.l2cache.overall_misses::total 30463 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71141750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31680000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 102821750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1901914500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 71141750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1933594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2004736250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 71141750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1933594500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2004736250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71135750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31674000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 102809750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1901914750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 71135750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1933588750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2004724500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 71135750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1933588750 # number of overall miss cycles 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latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.781916 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.781916 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65808.891114 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65808.891114 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70431.435644 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69613.186813 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70177.303754 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.790537 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.790537 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70431.435644 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65649.976233 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65808.505400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70431.435644 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65649.976233 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65808.505400 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -836,17 +899,17 @@ system.cpu.l2cache.demand_mshr_misses::total 30463 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58482750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26096500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84579250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58482750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556138500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1614621250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58482750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556138500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1614621250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58476750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26090500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84567250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58476750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556132750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1614609500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58476750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556132750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1614609500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses @@ -858,132 +921,74 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57897.772277 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57341.758242 # average ReadReq mshr miss latency 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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072433 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68459744 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.968354 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144502463 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144502463 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37113881 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37113881 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68459744 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68459744 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68459744 # number of overall hits -system.cpu.dcache.overall_hits::total 68459744 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses -system.cpu.dcache.overall_misses::total 2753223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861058000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31861058000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155744 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2765155744 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34626213744 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34626213744 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34626213744 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34626213744 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39773215 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39773215 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71212967 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71212967 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71212967 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71212967 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12576.610665 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12576.610665 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks -system.cpu.dcache.writebacks::total 2066654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009130500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009130500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524102994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24524102994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524102994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24524102994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3121417250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1465 # Transaction distribution +system.membus.trans_dist::ReadResp 1462 # Transaction distribution +system.membus.trans_dist::Writeback 197 # Transaction distribution +system.membus.trans_dist::ReadExReq 28998 # Transaction distribution +system.membus.trans_dist::ReadExResp 28998 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30660 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30660 # Request fanout histogram +system.membus.reqLayer0.occupancy 43499500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 291787500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index f1692fa7b..93f93a6a3 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.411003 # Number of seconds simulated -sim_ticks 411003011000 # Number of ticks simulated -final_tick 411003011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410940 # Number of seconds simulated +sim_ticks 410940483000 # Number of ticks simulated +final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279515 # Simulator instruction rate (inst/s) -host_op_rate 279515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187744969 # Simulator tick rate (ticks/s) -host_mem_usage 239248 # Number of bytes of host memory used -host_seconds 2189.16 # Real time elapsed on the host +host_inst_rate 339016 # Simulator instruction rate (inst/s) +host_op_rate 339016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 227676015 # Simulator tick rate (ticks/s) +host_mem_usage 297088 # Number of bytes of host memory used +host_seconds 1804.94 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24320320 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724480 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380005 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292570 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59173094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59173094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 415919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 415919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45558012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45558012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45558012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59173094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104731106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380005 # Number of read requests accepted -system.physmem.writeReqs 292570 # Number of write requests accepted -system.physmem.readBursts 380005 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292570 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24297088 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23232 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 363 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59182721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59182721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380009 # Number of read requests accepted +system.physmem.writeReqs 292569 # Number of write requests accepted +system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292569 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24297024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23737 # Per bank write bursts -system.physmem.perBankRdBursts::1 23219 # Per bank write bursts -system.physmem.perBankRdBursts::2 23515 # Per bank write bursts -system.physmem.perBankRdBursts::3 24536 # Per bank write bursts -system.physmem.perBankRdBursts::4 25458 # Per bank write bursts -system.physmem.perBankRdBursts::5 23589 # Per bank write bursts -system.physmem.perBankRdBursts::6 23674 # Per bank write bursts -system.physmem.perBankRdBursts::7 23973 # Per bank write bursts -system.physmem.perBankRdBursts::8 23176 # Per bank write bursts -system.physmem.perBankRdBursts::9 23944 # Per bank write bursts -system.physmem.perBankRdBursts::10 24674 # Per bank write bursts -system.physmem.perBankRdBursts::11 22747 # Per bank write bursts -system.physmem.perBankRdBursts::12 23719 # Per bank write bursts -system.physmem.perBankRdBursts::13 24413 # Per bank write bursts -system.physmem.perBankRdBursts::14 22804 # Per bank write bursts -system.physmem.perBankRdBursts::15 22464 # Per bank write bursts +system.physmem.perBankRdBursts::0 23736 # Per bank write bursts +system.physmem.perBankRdBursts::1 23216 # Per bank write bursts +system.physmem.perBankRdBursts::2 23510 # Per bank write bursts +system.physmem.perBankRdBursts::3 24529 # Per bank write bursts +system.physmem.perBankRdBursts::4 25457 # Per bank write bursts +system.physmem.perBankRdBursts::5 23594 # Per bank write bursts +system.physmem.perBankRdBursts::6 23677 # Per bank write bursts +system.physmem.perBankRdBursts::7 23981 # Per bank write bursts +system.physmem.perBankRdBursts::8 23173 # Per bank write bursts +system.physmem.perBankRdBursts::9 23945 # Per bank write bursts +system.physmem.perBankRdBursts::10 24675 # Per bank write bursts +system.physmem.perBankRdBursts::11 22741 # Per bank write bursts +system.physmem.perBankRdBursts::12 23723 # Per bank write bursts +system.physmem.perBankRdBursts::13 24409 # Per bank write bursts +system.physmem.perBankRdBursts::14 22807 # Per bank write bursts +system.physmem.perBankRdBursts::15 22468 # Per bank write bursts system.physmem.perBankWrBursts::0 17754 # Per bank write bursts system.physmem.perBankWrBursts::1 17431 # Per bank write bursts -system.physmem.perBankWrBursts::2 17902 # Per bank write bursts +system.physmem.perBankWrBursts::2 17901 # Per bank write bursts system.physmem.perBankWrBursts::3 18773 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18543 # Per bank write bursts -system.physmem.perBankWrBursts::6 18682 # Per bank write bursts -system.physmem.perBankWrBursts::7 18577 # Per bank write bursts -system.physmem.perBankWrBursts::8 18349 # Per bank write bursts +system.physmem.perBankWrBursts::6 18677 # Per bank write bursts +system.physmem.perBankWrBursts::7 18574 # Per bank write bursts +system.physmem.perBankWrBursts::8 18352 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts system.physmem.perBankWrBursts::10 19127 # Per bank write bursts -system.physmem.perBankWrBursts::11 17965 # Per bank write bursts +system.physmem.perBankWrBursts::11 17966 # Per bank write bursts system.physmem.perBankWrBursts::12 18224 # Per bank write bursts -system.physmem.perBankWrBursts::13 18693 # Per bank write bursts +system.physmem.perBankWrBursts::13 18695 # Per bank write bursts system.physmem.perBankWrBursts::14 17148 # Per bank write bursts system.physmem.perBankWrBursts::15 17103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 411002929500 # Total gap between requests +system.physmem.totGap 410940401000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380005 # Read request sizes (log2) +system.physmem.readPktSize::6 380009 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292570 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292569 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,42 +140,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -189,123 +189,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 141657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.679790 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.908631 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.510648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50805 35.86% 35.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38362 27.08% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12861 9.08% 72.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8208 5.79% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5905 4.17% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3832 2.71% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2875 2.03% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2523 1.78% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16286 11.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141657 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17265 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.988184 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 229.046433 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17255 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142331 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.240383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.797095 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.472154 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51326 36.06% 36.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38738 27.22% 63.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13057 9.17% 72.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7891 5.54% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5698 4.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3672 2.58% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3107 2.18% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2648 1.86% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16194 11.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142331 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17261 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.992932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.052387 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17249 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17265 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17265 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.944454 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.865388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.133478 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17065 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 148 0.86% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.16% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 9 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17265 # Writes before turning the bus around for reads -system.physmem.totQLat 4080991250 # Total ticks spent queuing -system.physmem.totMemAccLat 11199278750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10749.58 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17261 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17261 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.948207 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.879580 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.601828 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17058 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 154 0.89% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17261 # Writes before turning the bus around for reads +system.physmem.totQLat 4019056000 # Total ticks spent queuing +system.physmem.totMemAccLat 11137324750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10586.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29499.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.17 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29336.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.64 # Average write queue length when enqueuing -system.physmem.readRowHits 314689 # Number of row buffer hits during reads -system.physmem.writeRowHits 215833 # Number of row buffer hits during writes +system.physmem.avgWrQLen 20.74 # Average write queue length when enqueuing +system.physmem.readRowHits 314673 # Number of row buffer hits during reads +system.physmem.writeRowHits 215171 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.77 # Row buffer hit rate for writes -system.physmem.avgGap 611088.62 # Average gap between requests -system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 276203849000 # Time in different power states -system.physmem.memoryStateTime::REF 13724100000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 121069531000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 545847120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 524837880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 297833250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 286369875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1495111800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1465471800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 953117280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 942373440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 26844339600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 26844339600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 61600136265 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 58531832820 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 192563272500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 195254766750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 284299657815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 283849992165 # Total energy per rank (pJ) -system.physmem.averagePower::0 691.730926 # Core power per rank (mW) -system.physmem.averagePower::1 690.636842 # Core power per rank (mW) -system.cpu.branchPred.lookups 124266527 # Number of BP lookups -system.cpu.branchPred.condPredicted 87927203 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6406168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71920312 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67440384 # Number of BTB hits +system.physmem.writeRowHitRate 73.55 # Row buffer hit rate for writes +system.physmem.avgGap 610992.93 # Average gap between requests +system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 547495200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 298732500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1495119600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 953078400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61546767165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 192572713500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 284254177485 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.725104 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 319820574750 # Time in different power states +system.physmem_0.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77392866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 528262560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 288238500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465495200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 942392880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 58539586815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195210595500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 283814842575 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.655981 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 324225356250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 72987820500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 124267347 # Number of BP lookups +system.cpu.branchPred.condPredicted 87926966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6405633 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71910290 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67438494 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.770984 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15061672 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126459 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.781424 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15062581 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126311 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149394307 # DTB read hits -system.cpu.dtb.read_misses 568771 # DTB read misses +system.cpu.dtb.read_hits 149395037 # DTB read hits +system.cpu.dtb.read_misses 569044 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149963078 # DTB read accesses -system.cpu.dtb.write_hits 57322555 # DTB write hits -system.cpu.dtb.write_misses 67010 # DTB write misses +system.cpu.dtb.read_accesses 149964081 # DTB read accesses +system.cpu.dtb.write_hits 57322306 # DTB write hits +system.cpu.dtb.write_misses 67257 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57389565 # DTB write accesses -system.cpu.dtb.data_hits 206716862 # DTB hits -system.cpu.dtb.data_misses 635781 # DTB misses +system.cpu.dtb.write_accesses 57389563 # DTB write accesses +system.cpu.dtb.data_hits 206717343 # DTB hits +system.cpu.dtb.data_misses 636301 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207352643 # DTB accesses -system.cpu.itb.fetch_hits 226799477 # ITB hits +system.cpu.dtb.data_accesses 207353644 # DTB accesses +system.cpu.itb.fetch_hits 226796884 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226799525 # ITB accesses +system.cpu.itb.fetch_accesses 226796932 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -319,66 +322,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 822006022 # number of cpu cycles simulated +system.cpu.numCycles 821880966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12977706 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12979255 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.343363 # CPI: cycles per instruction -system.cpu.ipc 0.744400 # IPC: instructions per cycle -system.cpu.tickCycles 741717254 # Number of cycles that the object actually ticked -system.cpu.idleCycles 80288768 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535461 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.779511 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202630719 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539557 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.789790 # Average number of references to valid blocks. +system.cpu.cpi 1.343159 # CPI: cycles per instruction +system.cpu.ipc 0.744514 # IPC: instructions per cycle +system.cpu.tickCycles 741712966 # Number of cycles that the object actually ticked +system.cpu.idleCycles 80168000 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535450 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.778260 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202631199 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.779511 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.778260 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414705281 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414705281 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 146964513 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146964513 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 55666206 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666206 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 202630719 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202630719 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 202630719 # number of overall hits -system.cpu.dcache.overall_hits::total 202630719 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1908315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543828 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543828 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3452143 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452143 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3452143 # number of overall misses -system.cpu.dcache.overall_misses::total 3452143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36427451000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36427451000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45003472500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45003472500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 81430923500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81430923500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 81430923500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81430923500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 148872828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148872828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 146964985 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 55666214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 202631199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 202631199 # number of overall hits +system.cpu.dcache.overall_hits::total 202631199 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1908330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 1543820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3452150 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3452150 # number of overall misses +system.cpu.dcache.overall_misses::total 3452150 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36414832750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 44905898000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 81320730750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 81320730750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 148873315 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 206082862 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206082862 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 206082862 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206082862 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 206083349 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 206083349 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses @@ -387,14 +390,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.016751 system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.016751 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19088.803997 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19088.803997 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29150.574092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29150.574092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23588.514004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23588.514004 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19082.041759 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29087.521861 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,32 +406,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340066 # number of writebacks -system.cpu.dcache.writebacks::total 2340066 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143549 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143549 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769037 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769037 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 912586 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912586 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 912586 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912586 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774791 # 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(read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51453271000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51453271000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51453271000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2340060 # number of writebacks +system.cpu.dcache.writebacks::total 2340060 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143560 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769044 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769044 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 912604 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912604 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 912604 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912604 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764770 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764770 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774776 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774776 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2539546 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539546 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2539546 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539546 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222614500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222614500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21167535500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21167535500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51390150000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51390150000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51390150000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51390150000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses @@ -437,69 +440,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012323 system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17133.104049 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17133.104049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27384.612754 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27384.612754 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20260.726969 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20260.726969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20260.726969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20260.726969 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17125.525989 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17125.525989 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27320.845638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27320.845638 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3180 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.063523 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226794468 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5009 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45277.394290 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3192 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.017357 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226791863 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5021 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45168.664210 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.063523 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545441 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.017357 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545419 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545419 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453603963 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453603963 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226794468 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226794468 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226794468 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226794468 # number of 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demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228135750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228135750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 226799477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 226799477 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 226799477 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 226799477 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 226799477 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 226799477 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 453598789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 453598789 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 226791863 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 226791863 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 226791863 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 226791863 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226791863 # number of overall hits +system.cpu.icache.overall_hits::total 226791863 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5021 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5021 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5021 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5021 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5021 # number of overall misses +system.cpu.icache.overall_misses::total 5021 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 229227250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 229227250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 229227250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 229227250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 229227250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 229227250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226796884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226796884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226796884 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226796884 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226796884 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226796884 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45545.168696 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45545.168696 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45545.168696 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45545.168696 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45545.168696 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45545.168696 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45653.704441 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45653.704441 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45653.704441 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45653.704441 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,103 +511,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5009 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5009 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5009 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5009 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5009 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5009 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 217013250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 217013250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 217013250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 217013250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 217013250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 217013250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5021 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5021 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5021 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5021 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5021 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5021 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218087750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 218087750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218087750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 218087750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218087750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 218087750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 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-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10018 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 320576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312295872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312616448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778132 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 321344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312616128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884632 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4884627 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884632 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884627 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884632 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782382000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4884627 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782373500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8065750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8080250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891629500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173378 # Transaction distribution -system.membus.trans_dist::ReadResp 173378 # Transaction distribution -system.membus.trans_dist::Writeback 292570 # Transaction distribution -system.membus.trans_dist::ReadExReq 206627 # Transaction distribution -system.membus.trans_dist::ReadExResp 206627 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052580 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052580 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43044800 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 173383 # Transaction distribution +system.membus.trans_dist::ReadResp 173383 # Transaction distribution +system.membus.trans_dist::Writeback 292569 # Transaction distribution +system.membus.trans_dist::ReadExReq 206626 # Transaction distribution +system.membus.trans_dist::ReadExResp 206626 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 672575 # Request fanout histogram +system.membus.snoop_fanout::samples 672578 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 672575 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 672578 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 672575 # Request fanout histogram -system.membus.reqLayer0.occupancy 3222733000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 672578 # Request fanout histogram +system.membus.reqLayer0.occupancy 3222626500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3617871750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3617752750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 940b25691..a1fa65b86 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365348 # Number of seconds simulated -sim_ticks 365347511000 # Number of ticks simulated -final_tick 365347511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365317 # Number of seconds simulated +sim_ticks 365317233000 # Number of ticks simulated +final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 224796 # Simulator instruction rate (inst/s) -host_op_rate 243484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162123009 # Simulator tick rate (ticks/s) -host_mem_usage 256924 # Number of bytes of host memory used -host_seconds 2253.52 # Real time elapsed on the host +host_inst_rate 241300 # Simulator instruction rate (inst/s) +host_op_rate 261360 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174011250 # Simulator tick rate (ticks/s) +host_mem_usage 315696 # Number of bytes of host memory used +host_seconds 2099.39 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9224896 # Number of bytes read from this memory -system.physmem.bytes_read::total 9224896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6179008 # Number of bytes written to this memory -system.physmem.bytes_written::total 6179008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144139 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96547 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96547 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25249648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25249648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 605758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16912687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16912687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16912687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25249648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42162335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144139 # Number of read requests accepted -system.physmem.writeReqs 96547 # Number of write requests accepted -system.physmem.readBursts 144139 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96547 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9218048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 6177856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9224896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6179008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 9226048 # Number of bytes read from this memory +system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory +system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25254894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25254894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144157 # Number of read requests accepted +system.physmem.writeReqs 96561 # Number of write requests accepted +system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9344 # Per bank write bursts -system.physmem.perBankRdBursts::1 8969 # Per bank write bursts +system.physmem.perBankRdBursts::0 9347 # Per bank write bursts +system.physmem.perBankRdBursts::1 8970 # Per bank write bursts system.physmem.perBankRdBursts::2 8998 # Per bank write bursts -system.physmem.perBankRdBursts::3 8704 # Per bank write bursts -system.physmem.perBankRdBursts::4 9453 # Per bank write bursts -system.physmem.perBankRdBursts::5 9341 # Per bank write bursts -system.physmem.perBankRdBursts::6 8940 # Per bank write bursts +system.physmem.perBankRdBursts::3 8695 # Per bank write bursts +system.physmem.perBankRdBursts::4 9455 # Per bank write bursts +system.physmem.perBankRdBursts::5 9342 # Per bank write bursts +system.physmem.perBankRdBursts::6 8947 # Per bank write bursts system.physmem.perBankRdBursts::7 8101 # Per bank write bursts -system.physmem.perBankRdBursts::8 8571 # Per bank write bursts -system.physmem.perBankRdBursts::9 8677 # Per bank write bursts -system.physmem.perBankRdBursts::10 8772 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 9379 # Per bank write bursts -system.physmem.perBankRdBursts::13 9523 # Per bank write bursts -system.physmem.perBankRdBursts::14 8710 # Per bank write bursts -system.physmem.perBankRdBursts::15 9074 # Per bank write bursts -system.physmem.perBankWrBursts::0 6191 # Per bank write bursts -system.physmem.perBankWrBursts::1 6093 # Per bank write bursts +system.physmem.perBankRdBursts::8 8578 # Per bank write bursts +system.physmem.perBankRdBursts::9 8679 # Per bank write bursts +system.physmem.perBankRdBursts::10 8774 # Per bank write bursts +system.physmem.perBankRdBursts::11 9477 # Per bank write bursts +system.physmem.perBankRdBursts::12 9374 # Per bank write bursts +system.physmem.perBankRdBursts::13 9525 # Per bank write bursts +system.physmem.perBankRdBursts::14 8712 # Per bank write bursts +system.physmem.perBankRdBursts::15 9087 # Per bank write bursts +system.physmem.perBankWrBursts::0 6196 # Per bank write bursts +system.physmem.perBankWrBursts::1 6092 # Per bank write bursts system.physmem.perBankWrBursts::2 6006 # Per bank write bursts -system.physmem.perBankWrBursts::3 5817 # Per bank write bursts -system.physmem.perBankWrBursts::4 6161 # Per bank write bursts -system.physmem.perBankWrBursts::5 6171 # Per bank write bursts -system.physmem.perBankWrBursts::6 6013 # Per bank write bursts -system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::3 5813 # Per bank write bursts +system.physmem.perBankWrBursts::4 6163 # Per bank write bursts +system.physmem.perBankWrBursts::5 6172 # Per bank write bursts +system.physmem.perBankWrBursts::6 6014 # Per bank write bursts +system.physmem.perBankWrBursts::7 5493 # Per bank write bursts system.physmem.perBankWrBursts::8 5728 # Per bank write bursts -system.physmem.perBankWrBursts::9 5821 # Per bank write bursts -system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6446 # Per bank write bursts +system.physmem.perBankWrBursts::9 5823 # Per bank write bursts +system.physmem.perBankWrBursts::10 5962 # Per bank write bursts +system.physmem.perBankWrBursts::11 6445 # Per bank write bursts system.physmem.perBankWrBursts::12 6308 # Per bank write bursts -system.physmem.perBankWrBursts::13 6280 # Per bank write bursts -system.physmem.perBankWrBursts::14 5994 # Per bank write bursts -system.physmem.perBankWrBursts::15 6045 # Per bank write bursts +system.physmem.perBankWrBursts::13 6282 # Per bank write bursts +system.physmem.perBankWrBursts::14 5997 # Per bank write bursts +system.physmem.perBankWrBursts::15 6048 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 365347483000 # Total gap between requests +system.physmem.totGap 365317203500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144139 # Read request sizes (log2) +system.physmem.readPktSize::6 144157 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96547 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96561 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,37 +140,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -189,98 +189,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.344433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.101707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.291878 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24488 37.75% 37.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18300 28.21% 65.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6859 10.57% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7791 12.01% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2064 3.18% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1161 1.79% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 764 1.18% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 681 1.05% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2758 4.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5569 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.862992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.285392 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5565 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5569 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.333273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.210704 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.188900 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5418 97.29% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 79 1.42% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 23 0.41% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 20 0.36% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 9 0.16% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 7 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 5 0.09% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5569 # Writes before turning the bus around for reads -system.physmem.totQLat 1570268250 # Total ticks spent queuing -system.physmem.totMemAccLat 4270868250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10902.22 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads +system.physmem.totQLat 1534207250 # Total ticks spent queuing +system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29652.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.86 # Average write queue length when enqueuing -system.physmem.readRowHits 110988 # Number of row buffer hits during reads -system.physmem.writeRowHits 64704 # Number of row buffer hits during writes +system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing +system.physmem.readRowHits 111019 # Number of row buffer hits during reads +system.physmem.writeRowHits 64498 # Number of row buffer hits during writes system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.02 # Row buffer hit rate for writes -system.physmem.avgGap 1517942.39 # Average gap between requests -system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 256543365500 # Time in different power states -system.physmem.memoryStateTime::REF 12199720000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 96603610750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 246584520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 243719280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134545125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132981750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 560422200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 562972800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 310625280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 314778960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 23862652320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 23862652320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 47112370740 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 46678345380 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 177881368500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 178262092500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 250108568685 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 250057542990 # Total energy per rank (pJ) -system.physmem.averagePower::0 684.578732 # Core power per rank (mW) -system.physmem.averagePower::1 684.439068 # Core power per rank (mW) -system.cpu.branchPred.lookups 132580026 # Number of BP lookups -system.cpu.branchPred.condPredicted 98506360 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6554090 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 69003825 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64853184 # Number of BTB hits +system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes +system.physmem.avgGap 1517614.82 # Average gap between requests +system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.594758 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.461067 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 132578917 # Number of BP lookups +system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.984912 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10016062 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17737 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -302,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -323,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -344,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -366,90 +411,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 730695022 # number of cpu cycles simulated +system.cpu.numCycles 730634466 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13461717 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.442402 # CPI: cycles per instruction -system.cpu.ipc 0.693288 # IPC: instructions per cycle -system.cpu.tickCycles 695775254 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34919768 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139848 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.076883 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171283127 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143944 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.730343 # Average number of references to valid blocks. +system.cpu.cpi 1.442282 # CPI: cycles per instruction +system.cpu.ipc 0.693346 # IPC: instructions per cycle +system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139812 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.076883 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.074819 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346820764 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346820764 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 114767369 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114767369 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538676 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538676 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 114766084 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 53538710 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 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of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169861328 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007392 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 169860145 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 169860145 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007393 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 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average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,103 +503,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068569 # number of writebacks -system.cpu.dcache.writebacks::total 1068569 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66869 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66869 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787784 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787784 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356160 # number of WriteReq MSHR misses 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ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28284.555545 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18642.586436 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18642.586436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17642 # number of replacements -system.cpu.icache.tags.tagsinuse 1190.521713 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200940130 # Total number of references to valid blocks. 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-system.cpu.l2cache.writebacks::writebacks 96547 # number of writebacks -system.cpu.l2cache.writebacks::total 96547 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96561 # number of writebacks +system.cpu.l2cache.writebacks::total 96561 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43270 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43270 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100869 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100869 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144139 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144139 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2682518500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2682518500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5916082000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5916082000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8598600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8598600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8598600500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8598600500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053615 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283012 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283012 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123888 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123888 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100868 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 144157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 144157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2680290500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5883442250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8563732750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8563732750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61916.202730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58328.134294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356413 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1248896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141600832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142849728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2232027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -729,41 +774,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2232027 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2232027 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184582500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29960995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744681985 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43270 # Transaction distribution -system.membus.trans_dist::ReadResp 43270 # Transaction distribution -system.membus.trans_dist::Writeback 96547 # Transaction distribution -system.membus.trans_dist::ReadExReq 100869 # Transaction distribution -system.membus.trans_dist::ReadExResp 100869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384825 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384825 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15403904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15403904 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43289 # Transaction distribution +system.membus.trans_dist::ReadResp 43289 # Transaction distribution +system.membus.trans_dist::Writeback 96561 # Transaction distribution +system.membus.trans_dist::ReadExReq 100868 # Transaction distribution +system.membus.trans_dist::ReadExResp 100868 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240686 # Request fanout histogram +system.membus.snoop_fanout::samples 240718 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240686 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240686 # Request fanout histogram -system.membus.reqLayer0.occupancy 1081853000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 240718 # Request fanout histogram +system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1366563500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e3aeba90b..e36a9b419 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.231519 # Number of seconds simulated -sim_ticks 231518815500 # Number of ticks simulated -final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.232212 # Number of seconds simulated +sim_ticks 232211555000 # Number of ticks simulated +final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137569 # Simulator instruction rate (inst/s) -host_op_rate 149036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63039200 # Simulator tick rate (ticks/s) -host_mem_usage 324016 # Number of bytes of host memory used -host_seconds 3672.62 # Real time elapsed on the host +host_inst_rate 135087 # Simulator instruction rate (inst/s) +host_op_rate 146347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62087234 # Simulator tick rate (ticks/s) +host_mem_usage 317808 # Number of bytes of host memory used +host_seconds 3740.09 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory -system.physmem.bytes_read::total 28711552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory -system.physmem.bytes_written::total 19446336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448618 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory -system.physmem.num_writes::total 303849 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448618 # Number of read requests accepted -system.physmem.writeReqs 303849 # Number of write requests accepted -system.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue -system.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory +system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory +system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory +system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412658 # Number of read requests accepted +system.physmem.writeReqs 292638 # Number of write requests accepted +system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue +system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28534 # Per bank write bursts -system.physmem.perBankRdBursts::1 27313 # Per bank write bursts -system.physmem.perBankRdBursts::2 27956 # Per bank write bursts -system.physmem.perBankRdBursts::3 26702 # Per bank write bursts -system.physmem.perBankRdBursts::4 30075 # Per bank write bursts -system.physmem.perBankRdBursts::5 29207 # Per bank write bursts -system.physmem.perBankRdBursts::6 27700 # Per bank write bursts -system.physmem.perBankRdBursts::7 26438 # Per bank write bursts -system.physmem.perBankRdBursts::8 28442 # Per bank write bursts -system.physmem.perBankRdBursts::9 26796 # Per bank write bursts -system.physmem.perBankRdBursts::10 28037 # Per bank write bursts -system.physmem.perBankRdBursts::11 28667 # Per bank write bursts -system.physmem.perBankRdBursts::12 28663 # Per bank write bursts -system.physmem.perBankRdBursts::13 27984 # Per bank write bursts -system.physmem.perBankRdBursts::14 26659 # Per bank write bursts -system.physmem.perBankRdBursts::15 27067 # Per bank write bursts -system.physmem.perBankWrBursts::0 19504 # Per bank write bursts -system.physmem.perBankWrBursts::1 19011 # Per bank write bursts -system.physmem.perBankWrBursts::2 18881 # Per bank write bursts -system.physmem.perBankWrBursts::3 18629 # Per bank write bursts -system.physmem.perBankWrBursts::4 19556 # Per bank write bursts -system.physmem.perBankWrBursts::5 19014 # Per bank write bursts -system.physmem.perBankWrBursts::6 18738 # Per bank write bursts -system.physmem.perBankWrBursts::7 18227 # Per bank write bursts -system.physmem.perBankWrBursts::8 18808 # Per bank write bursts -system.physmem.perBankWrBursts::9 18381 # Per bank write bursts -system.physmem.perBankWrBursts::10 19036 # Per bank write bursts -system.physmem.perBankWrBursts::11 19525 # Per bank write bursts -system.physmem.perBankWrBursts::12 19578 # Per bank write bursts -system.physmem.perBankWrBursts::13 19080 # Per bank write bursts -system.physmem.perBankWrBursts::14 18969 # Per bank write bursts -system.physmem.perBankWrBursts::15 18884 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26576 # Per bank write bursts +system.physmem.perBankRdBursts::1 25575 # Per bank write bursts +system.physmem.perBankRdBursts::2 25174 # Per bank write bursts +system.physmem.perBankRdBursts::3 24876 # Per bank write bursts +system.physmem.perBankRdBursts::4 27202 # Per bank write bursts +system.physmem.perBankRdBursts::5 26589 # Per bank write bursts +system.physmem.perBankRdBursts::6 25428 # Per bank write bursts +system.physmem.perBankRdBursts::7 24234 # Per bank write bursts +system.physmem.perBankRdBursts::8 25846 # Per bank write bursts +system.physmem.perBankRdBursts::9 24812 # Per bank write bursts +system.physmem.perBankRdBursts::10 25055 # Per bank write bursts +system.physmem.perBankRdBursts::11 26081 # Per bank write bursts +system.physmem.perBankRdBursts::12 26502 # Per bank write bursts +system.physmem.perBankRdBursts::13 25872 # Per bank write bursts +system.physmem.perBankRdBursts::14 25198 # Per bank write bursts +system.physmem.perBankRdBursts::15 25467 # Per bank write bursts +system.physmem.perBankWrBursts::0 18795 # Per bank write bursts +system.physmem.perBankWrBursts::1 18343 # Per bank write bursts +system.physmem.perBankWrBursts::2 17877 # Per bank write bursts +system.physmem.perBankWrBursts::3 18076 # Per bank write bursts +system.physmem.perBankWrBursts::4 18802 # Per bank write bursts +system.physmem.perBankWrBursts::5 18306 # Per bank write bursts +system.physmem.perBankWrBursts::6 18071 # Per bank write bursts +system.physmem.perBankWrBursts::7 17638 # Per bank write bursts +system.physmem.perBankWrBursts::8 18138 # Per bank write bursts +system.physmem.perBankWrBursts::9 17849 # Per bank write bursts +system.physmem.perBankWrBursts::10 18079 # Per bank write bursts +system.physmem.perBankWrBursts::11 18708 # Per bank write bursts +system.physmem.perBankWrBursts::12 18879 # Per bank write bursts +system.physmem.perBankWrBursts::13 18261 # Per bank write bursts +system.physmem.perBankWrBursts::14 18465 # Per bank write bursts +system.physmem.perBankWrBursts::15 18329 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 231518762500 # Total gap between requests +system.physmem.totGap 232211534500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 448618 # Read request sizes (log2) +system.physmem.readPktSize::6 412658 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 303849 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,125 +197,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads -system.physmem.totQLat 10651839911 # Total ticks spent queuing -system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads +system.physmem.totQLat 9526506707 # Total ticks spent queuing +system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.62 # Data bus utilization in percentage -system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing -system.physmem.readRowHits 331076 # Number of row buffer hits during reads -system.physmem.writeRowHits 99609 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes -system.physmem.avgGap 307679.62 # Average gap between requests -system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states -system.physmem.memoryStateTime::REF 7730840000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 1204270200 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1209705840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 657091875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 660057750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1746123600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1733674800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 981894960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 986450400 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 15121523040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 15121523040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 75885673770 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 75815795475 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 72343590000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 72404886750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 167940167445 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 167932094055 # Total energy per rank (pJ) -system.physmem.averagePower::0 725.391418 # Core power per rank (mW) -system.physmem.averagePower::1 725.356546 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 445006 # Transaction distribution -system.membus.trans_dist::ReadResp 445005 # Transaction distribution -system.membus.trans_dist::Writeback 303849 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 3612 # Transaction distribution -system.membus.trans_dist::ReadExResp 3612 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 752471 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 752471 # Request fanout histogram -system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 175071152 # Number of BP lookups -system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits +system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing +system.physmem.readRowHits 299737 # Number of row buffer hits during reads +system.physmem.writeRowHits 95481 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes +system.physmem.avgGap 329239.83 # Average gap between requests +system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.427350 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states +system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.098525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states +system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 175052211 # Number of BP lookups +system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -358,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -379,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -401,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 463037632 # number of cpu cycles simulated +system.cpu.numCycles 464423111 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14941835 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -551,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued -system.cpu.iq.rate 1.317880 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued +system.cpu.iq.rate 1.313932 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1486621 # number of nop insts executed -system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed -system.cpu.iew.exec_branches 131372634 # Number of branches executed -system.cpu.iew.exec_stores 60949141 # Number of stores executed -system.cpu.iew.exec_rate 1.294450 # Inst execution rate -system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349881958 # num instructions producing a value -system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value +system.cpu.iew.exec_nop 1486524 # number of nop insts executed +system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed +system.cpu.iew.exec_branches 131371292 # Number of branches executed +system.cpu.iew.exec_stores 60952468 # Number of stores executed +system.cpu.iew.exec_rate 1.290583 # Inst execution rate +system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349870966 # num instructions producing a value +system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back +system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -674,513 +684,527 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1090469902 # The number of ROB reads -system.cpu.rob.rob_writes 1334452492 # The number of ROB writes -system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1091332417 # The number of ROB reads +system.cpu.rob.rob_writes 1334357175 # The number of ROB writes +system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611059162 # number of integer regfile reads -system.cpu.int_regfile_writes 328109228 # number of integer regfile writes +system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads +system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611063177 # number of integer regfile reads +system.cpu.int_regfile_writes 328106532 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads -system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes -system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads +system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes +system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 453214 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 73538 # number of replacements -system.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2823114 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits +system.cpu.dcache.overall_hits::total 166674811 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses +system.cpu.dcache.overall_misses::total 7050523 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173725334 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173725334 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040189 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041456 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041456 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.040585 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.040585 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.040584 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.040584 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11141.158297 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11141.158297 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7634.237152 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7634.237152 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15189.393939 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15189.393939 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10022.729159 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10022.729159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10022.713522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10022.713522 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 454984 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10035 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45.339711 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2354028 # number of writebacks +system.cpu.dcache.writebacks::total 2354028 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2498261 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2498261 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728610 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1728610 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4226871 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4226871 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4226871 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4226871 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303698 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2303698 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519943 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519943 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2823641 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2823641 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2823651 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2823651 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25499562714 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25499562714 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4017408221 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4017408221 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 706750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 706750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29516970935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29516970935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29517677685 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29517677685 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019281 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019281 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016254 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11068.969420 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11068.969420 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7726.631998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7726.631998 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70675 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70675 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10453.514075 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10453.514075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10453.727350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10453.727350 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 73454 # number of replacements +system.cpu.icache.tags.tagsinuse 465.665769 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236580046 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.497228 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114499459250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 465.665769 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.909503 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.909503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473451718 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473451718 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236609871 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236609871 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236609871 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236609871 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236609871 # number of overall hits -system.cpu.icache.overall_hits::total 236609871 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 78950 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 78950 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 78950 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 78950 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 78950 # number of overall misses -system.cpu.icache.overall_misses::total 78950 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 870914265 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 870914265 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 870914265 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 870914265 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 870914265 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 870914265 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236688821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236688821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236688821 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236688821 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236688821 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236688821 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000334 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000334 # 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14 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5209 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10.836821 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 14 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 473397028 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473397028 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236580046 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236580046 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236580046 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236580046 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236580046 # number of overall hits +system.cpu.icache.overall_hits::total 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ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62300.872022 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2823064 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.644481 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169655503 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2823576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.085333 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 487301500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.644481 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits -system.cpu.dcache.overall_hits::total 166678355 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses -system.cpu.dcache.overall_misses::total 7049008 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks -system.cpu.dcache.writebacks::total 2348838 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 335729 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 408974 # Transaction distribution +system.membus.trans_dist::ReadResp 408974 # Transaction distribution +system.membus.trans_dist::Writeback 292638 # Transaction distribution +system.membus.trans_dist::UpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 3684 # Transaction distribution +system.membus.trans_dist::ReadExResp 3684 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 705299 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 705299 # Request fanout histogram +system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index aa1528255..29aebf258 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362297500 # Number of ticks simulated final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2087081 # Simulator instruction rate (inst/s) -host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1150953174 # Simulator tick rate (ticks/s) -host_mem_usage 299952 # Number of bytes of host memory used -host_seconds 242.72 # Real time elapsed on the host +host_inst_rate 1700410 # Simulator instruction rate (inst/s) +host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 937717572 # Simulator tick rate (ticks/s) +host_mem_usage 304668 # Number of bytes of host memory used +host_seconds 297.92 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 773431583 # Wr system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 630711790 # Transaction distribution -system.membus.trans_dist::ReadResp 632200331 # Transaction distribution -system.membus.trans_dist::WriteReq 54239306 # Transaction distribution -system.membus.trans_dist::WriteResp 54239306 # Transaction distribution -system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution -system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 687930749 # Request fanout histogram -system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 687930749 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction +system.membus.trans_dist::ReadReq 630711790 # Transaction distribution +system.membus.trans_dist::ReadResp 632200331 # Transaction distribution +system.membus.trans_dist::WriteReq 54239306 # Transaction distribution +system.membus.trans_dist::WriteResp 54239306 # Transaction distribution +system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution +system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 687930749 # Request fanout histogram +system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 687930749 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index a70fb0c6b..efad42105 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.707539 # Nu sim_ticks 707539023000 # Number of ticks simulated final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1199909 # Simulator instruction rate (inst/s) -host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1681197618 # Simulator tick rate (ticks/s) -host_mem_usage 309428 # Number of bytes of host memory used -host_seconds 420.85 # Real time elapsed on the host +host_inst_rate 1166033 # Simulator instruction rate (inst/s) +host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1633733414 # Simulator tick rate (ticks/s) +host_mem_usage 312880 # Number of bytes of host memory used +host_seconds 433.08 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 8679369 # To system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 41855 # Transaction distribution -system.membus.trans_dist::ReadResp 41855 # Transaction distribution -system.membus.trans_dist::Writeback 95953 # Transaction distribution -system.membus.trans_dist::ReadExReq 100794 # Transaction distribution -system.membus.trans_dist::ReadExResp 100794 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 238603 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 238603 # Request fanout histogram -system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,139 @@ system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction +system.cpu.dcache.tags.replacements 1134822 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits +system.cpu.dcache.overall_hits::total 167203374 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses +system.cpu.dcache.overall_misses::total 1138918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks +system.cpu.dcache.writebacks::total 1064905 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. @@ -439,139 +580,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits -system.cpu.dcache.overall_hits::total 167203374 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses -system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks -system.cpu.dcache.writebacks::total 1064905 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution @@ -605,5 +613,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 17281500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 41855 # Transaction distribution +system.membus.trans_dist::ReadResp 41855 # Transaction distribution +system.membus.trans_dist::Writeback 95953 # Transaction distribution +system.membus.trans_dist::ReadExReq 100794 # Transaction distribution +system.membus.trans_dist::ReadExResp 100794 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 238603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 238603 # Request fanout histogram +system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 666f127d9..be422e790 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451764 # Number of seconds simulated -sim_ticks 451764406000 # Number of ticks simulated -final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.451526 # Number of seconds simulated +sim_ticks 451526391500 # Number of ticks simulated +final_tick 451526391500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112231 # Simulator instruction rate (inst/s) -host_op_rate 207527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61317335 # Simulator tick rate (ticks/s) -host_mem_usage 367016 # Number of bytes of host memory used -host_seconds 7367.65 # Real time elapsed on the host +host_inst_rate 97078 # Simulator instruction rate (inst/s) +host_op_rate 179507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53010367 # Simulator tick rate (ticks/s) +host_mem_usage 427448 # Number of bytes of host memory used +host_seconds 8517.70 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24540544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24764608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18820736 # Number of bytes written to this memory -system.physmem.bytes_written::total 18820736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3501 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383446 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386947 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294074 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294074 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 495975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54321553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54817528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 495975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 495975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41660511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41660511 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41660511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 495975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54321553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96478039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386948 # Number of read requests accepted -system.physmem.writeReqs 294074 # Number of write requests accepted -system.physmem.readBursts 386948 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294074 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24743168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21504 # Total number of bytes read from write queue -system.physmem.bytesWritten 18819072 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24764672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18820736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 336 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 224960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24535168 # Number of bytes read from this memory +system.physmem.bytes_read::total 24760128 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18817920 # Number of bytes written to this memory +system.physmem.bytes_written::total 18817920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383362 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386877 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294030 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294030 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 498221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54338281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54836502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 498221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41676235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41676235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41676235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 498221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54338281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 96512737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386877 # Number of read requests accepted +system.physmem.writeReqs 294030 # Number of write requests accepted +system.physmem.readBursts 386877 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294030 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24738496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue +system.physmem.bytesWritten 18816576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24760128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18817920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 179060 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24122 # Per bank write bursts -system.physmem.perBankRdBursts::1 26505 # Per bank write bursts -system.physmem.perBankRdBursts::2 24681 # Per bank write bursts -system.physmem.perBankRdBursts::3 24611 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 180174 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24137 # Per bank write bursts +system.physmem.perBankRdBursts::1 26529 # Per bank write bursts +system.physmem.perBankRdBursts::2 24699 # Per bank write bursts +system.physmem.perBankRdBursts::3 24593 # Per bank write bursts system.physmem.perBankRdBursts::4 23302 # Per bank write bursts -system.physmem.perBankRdBursts::5 23732 # Per bank write bursts -system.physmem.perBankRdBursts::6 24448 # Per bank write bursts -system.physmem.perBankRdBursts::7 24311 # Per bank write bursts -system.physmem.perBankRdBursts::8 23620 # Per bank write bursts -system.physmem.perBankRdBursts::9 23937 # Per bank write bursts -system.physmem.perBankRdBursts::10 24812 # Per bank write bursts -system.physmem.perBankRdBursts::11 24076 # Per bank write bursts -system.physmem.perBankRdBursts::12 23393 # Per bank write bursts -system.physmem.perBankRdBursts::13 22985 # Per bank write bursts -system.physmem.perBankRdBursts::14 24096 # Per bank write bursts -system.physmem.perBankRdBursts::15 23981 # Per bank write bursts +system.physmem.perBankRdBursts::5 23749 # Per bank write bursts +system.physmem.perBankRdBursts::6 24449 # Per bank write bursts +system.physmem.perBankRdBursts::7 24297 # Per bank write bursts +system.physmem.perBankRdBursts::8 23610 # Per bank write bursts +system.physmem.perBankRdBursts::9 23919 # Per bank write bursts +system.physmem.perBankRdBursts::10 24817 # Per bank write bursts +system.physmem.perBankRdBursts::11 24050 # Per bank write bursts +system.physmem.perBankRdBursts::12 23346 # Per bank write bursts +system.physmem.perBankRdBursts::13 22971 # Per bank write bursts +system.physmem.perBankRdBursts::14 24088 # Per bank write bursts +system.physmem.perBankRdBursts::15 23983 # Per bank write bursts system.physmem.perBankWrBursts::0 18558 # Per bank write bursts -system.physmem.perBankWrBursts::1 19850 # Per bank write bursts -system.physmem.perBankWrBursts::2 18948 # Per bank write bursts -system.physmem.perBankWrBursts::3 18946 # Per bank write bursts +system.physmem.perBankWrBursts::1 19844 # Per bank write bursts +system.physmem.perBankWrBursts::2 18955 # Per bank write bursts +system.physmem.perBankWrBursts::3 18948 # Per bank write bursts system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18437 # Per bank write bursts -system.physmem.perBankWrBursts::6 18993 # Per bank write bursts -system.physmem.perBankWrBursts::7 18991 # Per bank write bursts -system.physmem.perBankWrBursts::8 18543 # Per bank write bursts -system.physmem.perBankWrBursts::9 18160 # Per bank write bursts -system.physmem.perBankWrBursts::10 18841 # Per bank write bursts -system.physmem.perBankWrBursts::11 17736 # Per bank write bursts -system.physmem.perBankWrBursts::12 17380 # Per bank write bursts -system.physmem.perBankWrBursts::13 16967 # Per bank write bursts -system.physmem.perBankWrBursts::14 17832 # Per bank write bursts -system.physmem.perBankWrBursts::15 17826 # Per bank write bursts +system.physmem.perBankWrBursts::5 18446 # Per bank write bursts +system.physmem.perBankWrBursts::6 18985 # Per bank write bursts +system.physmem.perBankWrBursts::7 18975 # Per bank write bursts +system.physmem.perBankWrBursts::8 18547 # Per bank write bursts +system.physmem.perBankWrBursts::9 18155 # Per bank write bursts +system.physmem.perBankWrBursts::10 18842 # Per bank write bursts +system.physmem.perBankWrBursts::11 17721 # Per bank write bursts +system.physmem.perBankWrBursts::12 17374 # Per bank write bursts +system.physmem.perBankWrBursts::13 16974 # Per bank write bursts +system.physmem.perBankWrBursts::14 17821 # Per bank write bursts +system.physmem.perBankWrBursts::15 17824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 451764392500 # Total gap between requests +system.physmem.totGap 451526286000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386948 # Read request sizes (log2) +system.physmem.readPktSize::6 386877 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294074 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294030 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,418 +144,395 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17467 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17580 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.521852 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.115334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.715133 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54829 37.20% 37.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40372 27.39% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13383 9.08% 73.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7515 5.10% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5234 3.55% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3732 2.53% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3157 2.14% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2805 1.90% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16375 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147402 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17447 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.158537 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.201153 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17434 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.912829 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.000830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.915309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54902 37.17% 37.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40417 27.37% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13633 9.23% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7488 5.07% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5349 3.62% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3749 2.54% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3045 2.06% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2781 1.88% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16322 11.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147686 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17443 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.159892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.587687 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17430 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17447 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.853786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.774474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.995315 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17244 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 149 0.85% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17443 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17443 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.855415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.780849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.647023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17241 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 150 0.86% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17447 # Writes before turning the bus around for reads -system.physmem.totQLat 4338654000 # Total ticks spent queuing -system.physmem.totMemAccLat 11587629000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1933060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11222.24 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17443 # Writes before turning the bus around for reads +system.physmem.totQLat 4244351250 # Total ticks spent queuing +system.physmem.totMemAccLat 11491957500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932695000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10980.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29972.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29730.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.75 # Data bus utilization in percentage system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.93 # Average write queue length when enqueuing -system.physmem.readRowHits 317693 # Number of row buffer hits during reads -system.physmem.writeRowHits 215552 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes -system.physmem.avgGap 663362.41 # Average gap between requests -system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 312439483250 # Time in different power states -system.physmem.memoryStateTime::REF 15085200000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 567642600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 546300720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 309725625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 298080750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1526397600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1488559800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 976736880 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 928272960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 29506651200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 29506651200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 64826566830 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 62404533090 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 214189673250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 216314264250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 311903393985 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 311486662770 # Total energy per rank (pJ) -system.physmem.averagePower::0 690.420687 # Core power per rank (mW) -system.physmem.averagePower::1 689.498222 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 179971 # Transaction distribution -system.membus.trans_dist::ReadResp 179970 # Transaction distribution -system.membus.trans_dist::Writeback 294074 # Transaction distribution -system.membus.trans_dist::UpgradeReq 179060 # Transaction distribution -system.membus.trans_dist::UpgradeResp 179060 # Transaction distribution -system.membus.trans_dist::ReadExReq 206977 # Transaction distribution -system.membus.trans_dist::ReadExResp 206977 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1426089 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43585344 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 860082 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 860082 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 860082 # Request fanout histogram -system.membus.reqLayer0.occupancy 3467694500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3995364517 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 231811700 # Number of BP lookups -system.cpu.branchPred.condPredicted 231811700 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9749774 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132043202 # Number of BTB lookups -system.cpu.branchPred.BTBHits 129334985 # Number of BTB hits +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.42 # Average write queue length when enqueuing +system.physmem.readRowHits 317756 # Number of row buffer hits during reads +system.physmem.writeRowHits 215101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes +system.physmem.avgGap 663124.75 # Average gap between requests +system.physmem.pageHitRate 78.30 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 569336040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310649625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1526881200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 976788720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64757369970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 214110228000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 311742647955 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.421834 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 355630472000 # Time in different power states +system.physmem_0.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80817135000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 547049160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 298489125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1487951400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928182240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62071035210 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 216466682250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 311290783785 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.421031 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 359566067000 # Time in different power states +system.physmem_1.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 76881477500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 231910847 # Number of BP lookups +system.cpu.branchPred.condPredicted 231910847 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9746486 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132027793 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129309443 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.948992 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28034260 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1466603 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.941077 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28045741 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1465755 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903528833 # number of cpu cycles simulated +system.cpu.numCycles 903052797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 186193866 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1278658073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20239877 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1885 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 180561661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2733230 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 903347128 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.632355 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.341099 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186172753 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278263981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231910847 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157355184 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 705668368 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20227891 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1132 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 96729 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 811106 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1664 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180547715 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2736967 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 902865746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.633456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.342016 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492680103 54.54% 54.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 34123521 3.78% 58.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33275891 3.68% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33627770 3.72% 65.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27182272 3.01% 68.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27855831 3.08% 71.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37310737 4.13% 75.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33828820 3.74% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183462183 20.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 492504429 54.55% 54.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33980590 3.76% 58.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33251729 3.68% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33383912 3.70% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27248388 3.02% 68.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27817475 3.08% 71.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37350305 4.14% 75.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33792757 3.74% 79.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183536161 20.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 903347128 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.256563 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.415182 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127724228 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 442644539 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240143304 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82715119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10119938 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2233772257 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10119938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159908050 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 227395701 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285948747 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219943139 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183809979 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 169165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 140088736 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 23988102 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 45039827 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2289176453 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5526365527 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3514194402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 52054 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 902865746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.256808 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.415492 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127621918 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 442269855 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240334233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82525795 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10113945 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2233625829 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10113945 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159854620 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 227411371 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31769 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285878914 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219575127 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2183611721 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 177740 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 139597859 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24038652 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44983183 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2288587317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5525861457 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3514141602 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 52752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 675135599 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2312 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2290 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 426537147 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 530783294 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210410050 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 240827707 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72173678 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112785390 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25204 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1829110925 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 437516 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 579120624 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1007560279 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24652 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 903347128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.024815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.069613 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 674546463 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2421 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2405 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 426714045 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530721549 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210389629 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240824950 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72195473 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112352245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24995 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1828962616 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 418654 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 578669571 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1006826210 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24443 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 902865746 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.025730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070839 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 319005991 35.31% 35.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 130297139 14.42% 49.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 120325805 13.32% 63.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111338872 12.33% 75.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91295017 10.11% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61401299 6.80% 92.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43188488 4.78% 97.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19128067 2.12% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7366450 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 318904182 35.32% 35.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130514441 14.46% 49.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119555800 13.24% 63.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 110903587 12.28% 75.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91967934 10.19% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61336498 6.79% 92.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43115692 4.78% 97.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19163460 2.12% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7404152 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 903347128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 902865746 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11298417 42.44% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12271176 46.10% 88.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3050228 11.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11303507 42.48% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12206863 45.87% 88.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3099868 11.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719541 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212963557 66.31% 66.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 389902 0.02% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881002 0.21% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435438564 23.81% 90.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173718237 9.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2714574 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212750239 66.31% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 388692 0.02% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881011 0.21% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435509272 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173718712 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1829110925 # Type of FU issued -system.cpu.iq.rate 2.024408 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26619821 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014553 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4588595925 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2692200263 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1799476115 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 30390 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 66120 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6655 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1852997149 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185108157 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1828962616 # Type of FU issued +system.cpu.iq.rate 2.025311 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26610238 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014549 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4587788532 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2691313007 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799275575 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31338 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 67501 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6790 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852843768 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14512 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185242573 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 146685050 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 212835 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 388917 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61249864 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146624129 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213999 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 388901 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61229443 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18586 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 815 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19562 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 956 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10119938 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166724787 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10164048 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112810594 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401170 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 530787207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210410050 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7737 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4462758 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3568650 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 388917 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5751622 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4609702 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10361324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1807989007 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 429368726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21121918 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10113945 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 166739883 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10207354 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112377240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 401313 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530726286 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210389629 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7530 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4519493 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3556436 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 388901 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5749904 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4643271 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10393175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1807883955 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429428539 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21078661 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599512830 # number of memory reference insts executed -system.cpu.iew.exec_branches 171944433 # Number of branches executed -system.cpu.iew.exec_stores 170144104 # Number of stores executed -system.cpu.iew.exec_rate 2.001031 # Inst execution rate -system.cpu.iew.wb_sent 1804759601 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1799482770 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1369602342 # num instructions producing a value -system.cpu.iew.wb_consumers 2093301343 # num instructions consuming a value +system.cpu.iew.exec_refs 599547832 # number of memory reference insts executed +system.cpu.iew.exec_branches 171967250 # Number of branches executed +system.cpu.iew.exec_stores 170119293 # Number of stores executed +system.cpu.iew.exec_rate 2.001969 # Inst execution rate +system.cpu.iew.wb_sent 1804612346 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799282365 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369352269 # num instructions producing a value +system.cpu.iew.wb_consumers 2092896532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.991616 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654279 # average fanout of values written-back +system.cpu.iew.wb_rate 1.992444 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 583616621 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 824173638 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9832190 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823756093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.505218 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 355774644 43.17% 43.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174944190 21.23% 64.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57267566 6.95% 71.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27168668 3.30% 85.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27065091 3.28% 88.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9878369 1.20% 89.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8803957 1.07% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76959576 9.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 355425849 43.15% 43.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174994405 21.24% 64.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57317339 6.96% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86207861 10.47% 81.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27016335 3.28% 85.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27048633 3.28% 88.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9853927 1.20% 89.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8829984 1.07% 90.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 77061760 9.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 824173638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823756093 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,256 +578,338 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76959576 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 77061760 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2860250696 # The number of ROB reads -system.cpu.rob.rob_writes 4305432556 # The number of ROB writes -system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2859299655 # The number of ROB reads +system.cpu.rob.rob_writes 4304507020 # The number of ROB writes +system.cpu.timesIdled 2587 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 187051 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.092700 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.092700 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.915164 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2763452214 # number of integer regfile reads -system.cpu.int_regfile_writes 1467518123 # number of integer regfile writes -system.cpu.fp_regfile_reads 6756 # number of floating regfile reads -system.cpu.fp_regfile_writes 202 # number of floating regfile writes -system.cpu.cc_regfile_reads 600952146 # number of cc regfile reads -system.cpu.cc_regfile_writes 409697644 # number of cc regfile writes -system.cpu.misc_regfile_reads 991728878 # number of misc regfile reads +system.cpu.cpi 1.092125 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.092125 # CPI: Total CPI of All Threads +system.cpu.ipc 0.915646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.915646 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763619398 # number of integer regfile reads +system.cpu.int_regfile_writes 1467382261 # number of integer regfile writes +system.cpu.fp_regfile_reads 6855 # number of floating regfile reads +system.cpu.fp_regfile_writes 205 # number of floating regfile writes +system.cpu.cc_regfile_reads 600921704 # number of cc regfile reads +system.cpu.cc_regfile_writes 409683570 # number of cc regfile writes +system.cpu.misc_regfile_reads 991700936 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 1956687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1956686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2333034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 180860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 180860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771518 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 198212 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7771975 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7970187 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311785216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312336768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 180976 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5242099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5242099 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5242099 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4970549506 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 284884490 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3981162622 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 7001 # number of replacements -system.cpu.icache.tags.tagsinuse 1081.953602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 180366705 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8614 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20938.786278 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2534340 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.717392 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 388713882 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538436 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.131252 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.717392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 872 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 786546356 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 786546356 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 240120715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 240120715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148188548 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148188548 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 388309263 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 388309263 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 388309263 # number of overall hits +system.cpu.dcache.overall_hits::total 388309263 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2723043 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2723043 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 971654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 971654 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3694697 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3694697 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3694697 # number of overall misses +system.cpu.dcache.overall_misses::total 3694697 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55426039088 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55426039088 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27751124058 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27751124058 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83177163146 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83177163146 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83177163146 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83177163146 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 392003960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 392003960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 392003960 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 392003960 # number of overall (read+write) accesses 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ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6179.793379 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6179.793379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6179.793379 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1413 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.133333 # average number of cycles each access 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189594 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 189594 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 189594 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 189594 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 189594 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702034010 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 702034010 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702034010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 702034010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702034010 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 702034010 # 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# average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3702.828201 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3702.828201 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2457 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2457 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2457 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2457 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2457 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2457 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 190723 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 190723 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 190723 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 190723 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 190723 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 190723 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 707574010 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 707574010 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 707574010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 707574010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 707574010 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 707574010 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for 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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989854 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268318 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268318 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406243 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151060 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151923 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406243 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151060 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151923 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61524.064553 # average ReadReq mshr miss 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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61524.064553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59982.423527 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59996.370613 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 294030 # number of writebacks +system.cpu.l2cache.writebacks::total 294030 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3515 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176333 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179848 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 180136 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 180136 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207067 # number of ReadExReq MSHR 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accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151908 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151038 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151908 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.160740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.864002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60469.925760 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10093.523049 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10093.523049 # average UpgradeReq mshr miss latency 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number of replacements -system.cpu.dcache.tags.tagsinuse 4088.721227 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 388791403 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538610 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.151293 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.721227 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998223 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998223 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 861 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3187 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 786699916 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 786699916 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 240205034 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 240205034 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148189734 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148189734 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 388394768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 388394768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 388394768 # number of overall hits -system.cpu.dcache.overall_hits::total 388394768 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2715417 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2715417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 970468 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 970468 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3685885 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3685885 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3685885 # number of overall misses -system.cpu.dcache.overall_misses::total 3685885 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55284847940 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55284847940 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27786671624 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27786671624 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83071519564 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83071519564 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83071519564 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83071519564 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242920451 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242920451 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 392080653 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 392080653 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 392080653 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 392080653 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011178 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011178 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006506 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009401 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009401 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009401 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009401 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20359.616199 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20359.616199 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28632.238903 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28632.238903 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22537.740479 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22537.740479 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8578 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 914 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.385120 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.400000 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2333034 # number of writebacks -system.cpu.dcache.writebacks::total 2333034 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 948123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 948123 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 966414 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 966414 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 966414 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 966414 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767294 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767294 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 952177 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 952177 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2719471 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2719471 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2719471 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2719471 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30652377753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30652377753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25560484625 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25560484625 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56212862378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56212862378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56212862378 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56212862378 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007275 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006936 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006936 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 1957626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1957626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2333101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 182005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 182005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771533 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 199325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7773983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7973308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311778368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312328896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182121 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5244265 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5244265 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5244265 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4971600701 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 286576989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3981486557 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 179848 # Transaction distribution +system.membus.trans_dist::ReadResp 179848 # Transaction distribution +system.membus.trans_dist::Writeback 294030 # Transaction distribution +system.membus.trans_dist::UpgradeReq 180174 # Transaction distribution +system.membus.trans_dist::UpgradeResp 180174 # Transaction distribution +system.membus.trans_dist::ReadExReq 207029 # Transaction distribution +system.membus.trans_dist::ReadExResp 207029 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1428132 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 861081 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 861081 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 861081 # Request fanout histogram +system.membus.reqLayer0.occupancy 3467092000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3996161130 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index ca5c08420..fd544a1a5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.226819 # Nu sim_ticks 226818771000 # Number of ticks simulated final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 285609 # Simulator instruction rate (inst/s) -host_op_rate 285609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162496290 # Simulator tick rate (ticks/s) -host_mem_usage 242892 # Number of bytes of host memory used -host_seconds 1395.84 # Real time elapsed on the host +host_inst_rate 333141 # Simulator instruction rate (inst/s) +host_op_rate 333141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189539219 # Simulator tick rate (ticks/s) +host_mem_usage 300760 # Number of bytes of host memory used +host_seconds 1196.69 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # By system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 50615750 # Total ticks spent queuing -system.physmem.totMemAccLat 198234500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 50610250 # Total ticks spent queuing +system.physmem.totMemAccLat 198229000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6429.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6428.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25179.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25178.33 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s @@ -218,36 +218,41 @@ system.physmem.readRowHitRate 80.54 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28809690.02 # Average gap between requests system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 217525128250 # Time in different power states -system.physmem.memoryStateTime::REF 7573800000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1714919250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6698160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4808160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3654750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2623500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 34164000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 26910000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5823022815 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5572463355 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 130980318750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 131200107750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 151662211275 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 151621265565 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.664178 # Core power per rank (mW) -system.physmem.averagePower::1 668.483652 # Core power per rank (mW) -system.cpu.branchPred.lookups 46273762 # Number of BP lookups +system.physmem_0.actEnergy 6698160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3654750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5823127980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130980226500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151662224190 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.664235 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217898379000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1344256000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4808160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2623500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5572496700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 131200078500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151621269660 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.483670 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 218263346500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 976701000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 46273761 # Number of BP lookups system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25595417 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25595416 # Number of BTB lookups system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.452221 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 83.452224 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -293,15 +298,15 @@ system.cpu.discardedOps 4467797 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.137893 # CPI: cycles per instruction system.cpu.ipc 0.878818 # IPC: instructions per cycle -system.cpu.tickCycles 450174331 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3463211 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 450174327 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3463215 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.955317 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3291.955330 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955317 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955330 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id @@ -329,14 +334,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7119 # n system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81052500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81052500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391543250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 391543250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 472595750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 472595750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 472595750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 472595750 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81009750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 391587500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 472597250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 472597250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) @@ -353,14 +358,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68630.397968 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68630.397968 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65938.573594 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65938.573594 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66385.131339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.131339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66385.131339 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68594.199831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65946.025598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.342042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,14 +392,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64327500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64327500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214316000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 214316000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278643500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278643500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278643500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278643500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64296000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 214342750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 278638750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 278638750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses @@ -403,22 +408,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66317.010309 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66317.010309 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67078.560250 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67078.560250 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66901.200480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66901.200480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66901.200480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66901.200480 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66284.536082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67086.932707 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66900.060024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.781810 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1918.781818 # Cycle average of tags in use system.cpu.icache.tags.total_refs 98776054 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19090.849246 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781810 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781818 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.936905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.936905 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id @@ -441,12 +446,12 @@ system.cpu.icache.demand_misses::cpu.inst 5174 # n system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses system.cpu.icache.overall_misses::total 5174 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293010500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293010500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293010500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293010500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293010500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293010500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293011250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293011250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293011250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293011250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293011250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293011250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 98781228 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 98781228 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 98781228 # number of demand (read+write) accesses @@ -459,12 +464,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.329726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56631.329726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.329726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56631.329726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.329726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56631.329726 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.474681 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56631.474681 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56631.474681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56631.474681 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,33 +484,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5174 system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281053500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281053500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281053500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281053750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281053750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281053750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.351759 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.351759 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.351759 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.351759 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.351759 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.351759 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.400077 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.400077 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.924710 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4426.924727 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.138333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786377 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4053.786392 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123712 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy @@ -535,14 +540,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7873 # system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7873 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324986750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 324986750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210671750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 210671750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 535658500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 535658500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 535658500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 535658500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 324955500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 210698500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 535654000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 535654000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) @@ -561,14 +566,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843024 system.cpu.l2cache.demand_miss_rate::total 0.843024 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843024 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68620.513091 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68620.513091 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67157.076825 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67157.076825 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68037.406325 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68037.406325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68037.406325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68037.406325 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.914696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67165.604080 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68036.834752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,14 +590,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7873 system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7873 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265636250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265636250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 170998250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 170998250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436634500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 436634500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436634500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 436634500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 171025500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 436627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 436627500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980926 # mshr miss rate for ReadExReq accesses @@ -601,14 +606,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843024 system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843024 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56088.735220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56088.735220 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54510.121135 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54510.121135 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55459.735806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55459.735806 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56081.503378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54518.807778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution @@ -635,9 +640,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8565750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6972750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4736 # Transaction distribution system.membus.trans_dist::ReadResp 4736 # Transaction distribution @@ -660,7 +665,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 7873 # Request fanout histogram system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73875500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 73877500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 52c9c0408..90aeffe97 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.069652 # Nu sim_ticks 69651704000 # Number of ticks simulated final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274902 # Simulator instruction rate (inst/s) -host_op_rate 274902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50981523 # Simulator tick rate (ticks/s) -host_mem_usage 244336 # Number of bytes of host memory used -host_seconds 1366.21 # Real time elapsed on the host +host_inst_rate 253977 # Simulator instruction rate (inst/s) +host_op_rate 253977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47101012 # Simulator tick rate (ticks/s) +host_mem_usage 302288 # Number of bytes of host memory used +host_seconds 1478.77 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 915 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see @@ -188,24 +188,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.823320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.868335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 424 31.34% 31.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 330 24.39% 55.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 151 11.16% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 84 6.21% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.99% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 42 3.10% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 39 2.88% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.904608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.764111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 423 31.26% 31.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 330 24.39% 55.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 152 11.23% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 83 6.13% 73.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 55 4.07% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 3.18% 80.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 38 2.81% 83.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation -system.physmem.totQLat 66704750 # Total ticks spent queuing -system.physmem.totMemAccLat 206542250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 67034750 # Total ticks spent queuing +system.physmem.totMemAccLat 206872250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8944.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8988.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27694.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27738.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s @@ -222,82 +222,64 @@ system.physmem.readRowHitRate 81.74 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9339181.35 # Average gap between requests system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 66207575500 # Time in different power states -system.physmem.memoryStateTime::REF 2325700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 5843880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4362120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3188625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2380125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 32385600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 25373400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2090120175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1977791130 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 39955521000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 40054055250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 46636128480 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 46613031225 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.594966 # Core power per rank (mW) -system.physmem.averagePower::1 669.263339 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4328 # Transaction distribution -system.membus.trans_dist::ReadResp 4328 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7458 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7458 # Request fanout histogram -system.membus.reqLayer0.occupancy 9424000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69710500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 51167476 # Number of BP lookups +system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32385600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2090226195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 39955428000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46636141500 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.595153 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66468117000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 855864000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25373400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1978191270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40053704250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46613080365 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.264045 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66630949750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 691630250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 51167471 # Number of BP lookups system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25804997 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25804996 # Number of BTB lookups system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.459026 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9351095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.459030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9351091 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103696201 # DTB read hits +system.cpu.dtb.read_hits 103696202 # DTB read hits system.cpu.dtb.read_misses 91462 # DTB read misses system.cpu.dtb.read_acv 49407 # DTB read access violations -system.cpu.dtb.read_accesses 103787663 # DTB read accesses +system.cpu.dtb.read_accesses 103787664 # DTB read accesses system.cpu.dtb.write_hits 79414480 # DTB write hits system.cpu.dtb.write_misses 1579 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations system.cpu.dtb.write_accesses 79416059 # DTB write accesses -system.cpu.dtb.data_hits 183110681 # DTB hits +system.cpu.dtb.data_hits 183110682 # DTB hits system.cpu.dtb.data_misses 93041 # DTB misses system.cpu.dtb.data_acv 49409 # DTB access violations -system.cpu.dtb.data_accesses 183203722 # DTB accesses -system.cpu.itb.fetch_hits 51277823 # ITB hits +system.cpu.dtb.data_accesses 183203723 # DTB accesses +system.cpu.itb.fetch_hits 51277820 # ITB hits system.cpu.itb.fetch_misses 422 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51278245 # ITB accesses +system.cpu.itb.fetch_accesses 51278242 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -314,57 +296,57 @@ system.cpu.workload.num_syscalls 215 # Nu system.cpu.numCycles 139303411 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52063861 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85692225 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 52063926 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 457094521 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51167471 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32952090 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85692281 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139036455 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287588 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 51277820 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 545278 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139036576 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58307210 41.94% 41.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58307337 41.94% 41.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4519216 3.25% 45.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11970287 8.61% 63.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11970286 8.61% 63.02% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5933035 4.27% 73.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5933032 4.27% 73.06% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35575530 25.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139036455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 139036576 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45112319 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16348091 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking +system.cpu.fetch.rate 3.281287 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45112383 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16348146 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71787003 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4526860 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode +system.cpu.decode.SquashedInsts 14196 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47010962 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5663544 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 518995 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10271556 # Number of cycles rename is unblocking +system.cpu.rename.IdleCycles 47011024 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5663526 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74309218 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10271511 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3600572 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 3600527 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups @@ -373,35 +355,35 @@ system.cpu.rename.CommittedMaps 259532329 # Nu system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 16173803 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 16173797 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 406915916 # Number of instructions issued +system.cpu.iq.iqInstsIssued 406915918 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 18208107 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139036455 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.926685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.221928 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 139036576 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.926683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891375 17.18% 17.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19616672 14.11% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22677489 16.31% 47.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23891494 17.18% 17.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19616678 14.11% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22677483 16.31% 47.60% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14153870 10.18% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9626407 6.92% 92.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14153871 10.18% 85.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9626410 6.92% 92.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6209797 4.47% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4351187 3.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139036455 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139036576 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available @@ -437,7 +419,7 @@ system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153207489 37.65% 37.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153207490 37.65% 37.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued @@ -466,21 +448,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105367867 25.89% 80.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105367868 25.89% 80.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 406915916 # Type of FU issued +system.cpu.iq.FU_type_0::total 406915918 # Type of FU issued system.cpu.iq.rate 2.921076 # Inst issue rate system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 625896924 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 625897049 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 237228631 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246150912 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 246150914 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -491,35 +473,35 @@ system.cpu.iew.lsq.thread0.squashedStores 8146657 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 139208 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 131709 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 131691 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403157734 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103837101 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 403157736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103837102 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 24979489 # number of nop insts executed -system.cpu.iew.exec_refs 183253197 # number of memory reference insts executed -system.cpu.iew.exec_branches 46959988 # Number of branches executed +system.cpu.iew.exec_refs 183253198 # number of memory reference insts executed +system.cpu.iew.exec_branches 46959989 # Number of branches executed system.cpu.iew.exec_stores 79416096 # Number of stores executed system.cpu.iew.exec_rate 2.894098 # Inst execution rate -system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198000445 # num instructions producing a value -system.cpu.iew.wb_consumers 283955599 # num instructions consuming a value +system.cpu.iew.wb_sent 401401507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400567896 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198000452 # num instructions producing a value +system.cpu.iew.wb_consumers 283955606 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back @@ -527,23 +509,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133310602 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.990494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 133310723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.990491 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48555591 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18055922 13.54% 49.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9630864 7.22% 57.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48555712 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18055923 13.54% 49.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8737322 6.55% 63.75% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2616133 1.96% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29895302 22.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4404759 3.30% 71.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4988493 3.74% 75.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2616131 1.96% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133310602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133310723 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -589,60 +571,152 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29895302 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 542988978 # The number of ROB reads +system.cpu.rob.rob_reads 542989097 # The number of ROB reads system.cpu.rob.rob_writes 884890973 # The number of ROB writes -system.cpu.timesIdled 3472 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 266956 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 3476 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 266835 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403240144 # number of integer regfile reads -system.cpu.int_regfile_writes 171897287 # number of integer regfile writes +system.cpu.int_regfile_reads 403240146 # number of integer regfile reads +system.cpu.int_regfile_writes 171897288 # number of integer regfile writes system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6787000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6700000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 798 # number of replacements +system.cpu.dcache.tags.tagsinuse 3297.113166 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113166 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits +system.cpu.dcache.overall_hits::total 156873469 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses +system.cpu.dcache.overall_misses::total 21715 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114608500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114608500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125293584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1125293584 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239902084 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239902084 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239902084 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239902084 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62902.579583 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62902.579583 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56567.314332 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56567.314332 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57098.875616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57098.875616 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 46396 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.044397 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 674 # number of writebacks +system.cpu.dcache.writebacks::total 674 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67693000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 67693000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235962750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 235962750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303655750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 303655750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67828.657315 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67828.657315 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73669.294411 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73669.294411 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2164 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.364308 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1832.364532 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51272141 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12532.911513 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364308 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364532 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id @@ -651,44 +725,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 167 system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 102559737 # Number of tag accesses -system.cpu.icache.tags.data_accesses 102559737 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 51272145 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 51272145 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 51272145 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 51272145 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 51272145 # number of overall hits -system.cpu.icache.overall_hits::total 51272145 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5678 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5678 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5678 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses -system.cpu.icache.overall_misses::total 5678 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 340036249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 340036249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 340036249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 340036249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 340036249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 340036249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 51277823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 51277823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 51277823 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 102559731 # Number of tag accesses +system.cpu.icache.tags.data_accesses 102559731 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 51272141 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 51272141 # number of ReadReq hits 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0.000111 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000111 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59886.623635 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59886.623635 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59886.623635 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59886.623635 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60061.718436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60061.718436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60061.718436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60061.718436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked @@ -697,46 +771,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1587 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1587 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1587 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1587 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1587 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1587 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1588 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1588 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1588 # number of demand (read+write) MSHR hits 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-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249962500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249962500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249962500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249962500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250258250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 250258250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250258250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 250258250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250258250 # number of overall MSHR miss cycles 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-system.cpu.icache.demand_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61172.879492 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61172.879492 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4021.632026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4021.632512 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.133812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.662944 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835269 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.133834 # Average occupied blocks per requestor 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system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses) @@ -808,17 +882,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.899421 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69200.173310 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75349.595843 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70430.626155 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74092.252396 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74092.252396 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71967.350496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71967.350496 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69285.600809 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75383.371824 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70505.718577 # average ReadReq miss latency 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number of cycles access was blocked @@ -838,17 +912,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7458 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195687500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54580750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250268250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193330750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193330750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195687500 # number of demand (read+write) MSHR miss cycles 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193350250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195982250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247960750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 443943000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195982250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247960750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 443943000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses @@ -860,138 +934,69 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56524.407857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63026.270208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57825.381238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61767.012780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61767.012780 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56609.546505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63060.623557 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.358133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61773.242812 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61773.242812 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 798 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.113011 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113011 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits -system.cpu.dcache.overall_hits::total 156873469 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses -system.cpu.dcache.overall_misses::total 21715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114579750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114579750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125182835 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1125182835 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239762585 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239762585 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239762585 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239762585 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62886.800220 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62886.800220 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56561.747097 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56561.747097 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57092.451531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57092.451531 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46428 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 947 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.026399 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 674 # number of writebacks -system.cpu.dcache.writebacks::total 674 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67663750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67663750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235941750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 235941750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303605500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 303605500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303605500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 303605500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67799.348697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67799.348697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73662.738058 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73662.738058 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6700250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4328 # Transaction distribution +system.membus.trans_dist::ReadResp 4328 # Transaction distribution +system.membus.trans_dist::ReadExReq 3130 # Transaction distribution +system.membus.trans_dist::ReadExResp 3130 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7458 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7458 # Request fanout histogram +system.membus.reqLayer0.occupancy 9422500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 69712000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index a544f3c3c..d0b9d8c3b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.216828 # Nu sim_ticks 216828260500 # Number of ticks simulated final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172164 # Simulator instruction rate (inst/s) -host_op_rate 206702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136721287 # Simulator tick rate (ticks/s) -host_mem_usage 262128 # Number of bytes of host memory used -host_seconds 1585.91 # Real time elapsed on the host +host_inst_rate 175239 # Simulator instruction rate (inst/s) +host_op_rate 210394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139163086 # Simulator tick rate (ticks/s) +host_mem_usage 320864 # Number of bytes of host memory used +host_seconds 1558.09 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -184,24 +184,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.317321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.826076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 548 36.41% 36.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 349 23.19% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 163 10.83% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.58% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 60 3.99% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.19% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 50683250 # Total ticks spent queuing -system.physmem.totMemAccLat 192902000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 50845500 # Total ticks spent queuing +system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6682.04 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25432.04 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 80.07 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 28586424.65 # Average gap between requests system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 207228229000 # Time in different power states -system.physmem.memoryStateTime::REF 7240220000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 2356912000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 5012280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 6342840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2734875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3460875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 29905200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 29000400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5651949285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5745162240 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 125136528000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 125054762250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 144987999960 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 145000598925 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.689925 # Core power per rank (mW) -system.physmem.averagePower::1 668.748031 # Core power per rank (mW) +system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.690273 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.748242 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 33221230 # Number of BP lookups system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 87.059638 # BT system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -345,15 +382,15 @@ system.cpu.discardedOps 4064410 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.588265 # CPI: cycles per instruction system.cpu.ipc 0.629618 # IPC: instructions per cycle -system.cpu.tickCycles 430211091 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3445430 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.009332 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009332 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 3086.009488 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -385,14 +422,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7290 # n system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 7290 # number of overall misses system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126122956 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 126122956 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360338500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 360338500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 486461456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486461456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 486461456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486461456 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 126489706 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 360451750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 486941456 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 486941456 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) @@ -413,14 +450,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66729.966529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66729.966529 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61313.478429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68959.584848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66795.810151 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,14 +484,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4511 system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 99847542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 99847542 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197786250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197786250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297633792 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 297633792 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297633792 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 297633792 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100259792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197855250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 298115042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses @@ -463,22 +500,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61096.765387 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68939.111498 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66086.242962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 36927 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.993605 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73270396 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1885.302491 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993605 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -488,44 +525,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34 system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146657386 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146657386 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73270396 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73270396 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73270396 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73270396 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73270396 # number of overall hits -system.cpu.icache.overall_hits::total 73270396 # number of overall hits +system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits +system.cpu.icache.overall_hits::total 73270394 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses system.cpu.icache.overall_misses::total 38865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 703294747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 703294747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 703294747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 703294747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 703294747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 703294747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73309261 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73309261 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73309261 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73309261 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73309261 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73309261 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18095.838081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18095.838081 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,33 +577,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38865 system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624165253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 624165253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624165253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 624165253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624165253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 624165253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624088753 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 624088753 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624088753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 624088753 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624088753 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 624088753 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4198.559652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4198.559801 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.760812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798840 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.798959 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117334 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy @@ -597,14 +634,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7630 # system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 7630 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326194750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 326194750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194720750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 194720750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 520915500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 520915500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 520915500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 520915500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 326530500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194789750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 521320250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 521320250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 40506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) @@ -623,14 +660,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175904 system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175904 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68369.032663 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68251.489138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,14 +690,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7585 system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 7585 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264387500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264387500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158755250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158755250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423142750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 423142750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423142750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 423142750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 264479250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158825750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 423305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 423305000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116798 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994425 # mshr miss rate for ReadExReq accesses @@ -669,14 +706,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174866 system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174866 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55903.455929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55650.227751 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution @@ -709,7 +746,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7500208 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4731 # Transaction distribution system.membus.trans_dist::ReadResp 4731 # Transaction distribution @@ -730,9 +767,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8963500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71030250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 784b1e77a..2e0077bb1 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112541 # Number of seconds simulated -sim_ticks 112540655000 # Number of ticks simulated -final_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112624 # Number of seconds simulated +sim_ticks 112623767500 # Number of ticks simulated +final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132153 # Simulator instruction rate (inst/s) -host_op_rate 158665 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54470958 # Simulator tick rate (ticks/s) -host_mem_usage 270904 # Number of bytes of host memory used -host_seconds 2066.07 # Real time elapsed on the host +host_inst_rate 123996 # Simulator instruction rate (inst/s) +host_op_rate 148871 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51146556 # Simulator tick rate (ticks/s) +host_mem_usage 325020 # Number of bytes of host memory used +host_seconds 2201.98 # Real time elapsed on the host sim_insts 273037219 # Number of instructions simulated sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory -system.physmem.bytes_read::total 623680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 9745 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 9745 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory +system.physmem.bytes_read::total 469120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7330 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 623680 # Total read bytes from the system interface side +system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 803 # Per bank write bursts -system.physmem.perBankRdBursts::1 999 # Per bank write bursts -system.physmem.perBankRdBursts::2 769 # Per bank write bursts -system.physmem.perBankRdBursts::3 645 # Per bank write bursts -system.physmem.perBankRdBursts::4 618 # Per bank write bursts -system.physmem.perBankRdBursts::5 484 # Per bank write bursts -system.physmem.perBankRdBursts::6 251 # Per bank write bursts -system.physmem.perBankRdBursts::7 363 # Per bank write bursts -system.physmem.perBankRdBursts::8 300 # Per bank write bursts -system.physmem.perBankRdBursts::9 432 # Per bank write bursts -system.physmem.perBankRdBursts::10 486 # Per bank write bursts -system.physmem.perBankRdBursts::11 534 # Per bank write bursts -system.physmem.perBankRdBursts::12 696 # Per bank write bursts -system.physmem.perBankRdBursts::13 850 # Per bank write bursts -system.physmem.perBankRdBursts::14 782 # Per bank write bursts -system.physmem.perBankRdBursts::15 733 # Per bank write bursts +system.physmem.perBankRdBursts::0 589 # Per bank write bursts +system.physmem.perBankRdBursts::1 789 # Per bank write bursts +system.physmem.perBankRdBursts::2 601 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::4 444 # Per bank write bursts +system.physmem.perBankRdBursts::5 346 # Per bank write bursts +system.physmem.perBankRdBursts::6 153 # Per bank write bursts +system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::8 219 # Per bank write bursts +system.physmem.perBankRdBursts::9 291 # Per bank write bursts +system.physmem.perBankRdBursts::10 316 # Per bank write bursts +system.physmem.perBankRdBursts::11 411 # Per bank write bursts +system.physmem.perBankRdBursts::12 547 # Per bank write bursts +system.physmem.perBankRdBursts::13 678 # Per bank write bursts +system.physmem.perBankRdBursts::14 615 # Per bank write bursts +system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112540488500 # Total gap between requests +system.physmem.totGap 112623613500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 9745 # Read request sizes (log2) +system.physmem.readPktSize::6 7330 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,100 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation -system.physmem.totQLat 248191131 # Total ticks spent queuing -system.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 48725000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation +system.physmem.totQLat 100359280 # Total ticks spent queuing +system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 8500 # Number of row buffer hits during reads +system.physmem.readRowHits 5950 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 11548536.53 # Average gap between requests -system.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states -system.physmem.memoryStateTime::REF 3757780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1567991501 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 4460400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 4845960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2433750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2644125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 38220000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 37221600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 7350217680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 7350217680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 3071428470 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3094710975 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 64826723250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 64806300000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 75293483550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 75295940340 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.067664 # Core power per rank (mW) -system.physmem.averagePower::1 669.089495 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 9170 # Transaction distribution -system.membus.trans_dist::ReadResp 9170 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 575 # Transaction distribution -system.membus.trans_dist::ReadExResp 575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9746 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9746 # Request fanout histogram -system.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 37763717 # Number of BP lookups -system.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17302092 # Number of BTB hits +system.physmem.avgGap 15364749.45 # Average gap between requests +system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.161673 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states +system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.228880 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states +system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 37762202 # Number of BP lookups +system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -305,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -326,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -347,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -369,96 +381,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225081311 # number of cpu cycles simulated +system.cpu.numCycles 225247536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3511517 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108311612 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113472399 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17017 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available @@ -477,22 +488,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued @@ -511,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346267862 # Type of FU issued -system.cpu.iq.rate 1.538412 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued +system.cpu.iq.rate 1.537271 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 864 # number of nop insts executed -system.cpu.iew.exec_refs 175168098 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752179 # Number of branches executed -system.cpu.iew.exec_stores 84582729 # Number of stores executed -system.cpu.iew.exec_rate 1.520806 # Inst execution rate -system.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340645195 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153543382 # num instructions producing a value -system.cpu.iew.wb_consumers 265817565 # num instructions consuming a value +system.cpu.iew.exec_nop 868 # number of nop insts executed +system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752029 # Number of branches executed +system.cpu.iew.exec_stores 84582492 # Number of stores executed +system.cpu.iew.exec_rate 1.519678 # Inst execution rate +system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153542130 # num instructions producing a value +system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.513432 # insts written-back per cycle +system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037831 # Number of instructions committed system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -643,489 +654,155 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction -system.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 561656707 # The number of ROB reads -system.cpu.rob.rob_writes 705358339 # The number of ROB writes -system.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 561683936 # The number of ROB reads +system.cpu.rob.rob_writes 705354391 # The number of ROB writes +system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037219 # Number of Instructions Simulated system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824361 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads -system.cpu.ipc 1.213060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331187240 # number of integer regfile reads -system.cpu.int_regfile_writes 136909181 # number of integer regfile writes -system.cpu.fp_regfile_reads 187100304 # number of floating regfile reads -system.cpu.fp_regfile_writes 132166714 # number of floating regfile writes -system.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads -system.cpu.cc_regfile_writes 80246596 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads +system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads +system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331186150 # number of integer regfile reads +system.cpu.int_regfile_writes 136908474 # number of integer regfile writes +system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads +system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes +system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads +system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 50213 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 715368 # number of replacements -system.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178939093 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits -system.cpu.icache.overall_hits::total 88391816 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses -system.cpu.icache.overall_misses::total 719790 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 44298 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 135685 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf 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-system.cpu.l2cache.tags.occ_percent::writebacks 0.157120 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026924 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.022425 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.301379 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.507848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 5676 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4042 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 572 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4961 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3234 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.346436 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.246704 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51678510 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51678510 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 714431 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1313042 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2027473 # number 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# number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38998499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50021748 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 89020247 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41954499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41954499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 38998499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 91976247 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 130974746 # number of demand (read+write) miss cycles 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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003125 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003125 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000764 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000874 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000764 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000874 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71425.822344 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68522.942466 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69765.083856 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60891.870827 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60891.870827 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66653.814758 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66653.814758 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 6173 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 209 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.535885 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 114 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 114 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 157 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 157 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 225 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 478 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 687 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1165 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 44298 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 44298 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 575 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 478 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1262 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 478 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1262 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 44298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 46038 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32592250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42691498 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75283748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 669707182 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34465750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34465750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32592250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77157248 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 109749498 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32592250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77157248 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 779456680 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.002608 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.002608 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000774 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.020468 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1533746 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533739 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits -system.cpu.dcache.overall_hits::total 163781573 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits +system.cpu.dcache.overall_hits::total 163782096 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses -system.cpu.dcache.overall_misses::total 3771680 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses +system.cpu.dcache.overall_misses::total 3771380 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966282 # number of writebacks -system.cpu.dcache.writebacks::total 966282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks +system.cpu.dcache.writebacks::total 966281 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses 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miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 62388.691988 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 62388.691988 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 98 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 98 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 131 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 131 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 142 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2923 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1026 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3949 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30530 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 30530 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 727 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 727 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4676 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30530 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35206 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 153898250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59960500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 213858750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 204942291 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41351500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41351500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 153898250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101312000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 255210250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 153898250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101312000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 460152541 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001947 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003297 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003297 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002079 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015653 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52650.786863 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58441.033138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54155.165865 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6712.816607 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56879.642366 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56879.642366 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 33002 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 6603 # Transaction distribution +system.membus.trans_dist::ReadResp 6603 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 727 # Transaction distribution +system.membus.trans_dist::ReadExResp 727 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7331 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7331 # Request fanout histogram +system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 607680a6d..8e74d72ee 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717313500 # Number of ticks simulated final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1306299 # Simulator instruction rate (inst/s) -host_op_rate 1568357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 965080142 # Simulator tick rate (ticks/s) -host_mem_usage 305108 # Number of bytes of host memory used -host_seconds 209.02 # Real time elapsed on the host +host_inst_rate 1117455 # Simulator instruction rate (inst/s) +host_op_rate 1341629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 825564009 # Simulator tick rate (ticks/s) +host_mem_usage 308812 # Number of bytes of host memory used +host_seconds 244.34 # Real time elapsed on the host sim_insts 273037594 # Number of instructions simulated sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1983209850 # Wr system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 434895827 # Transaction distribution -system.membus.trans_dist::ReadResp 434906722 # Transaction distribution -system.membus.trans_dist::WriteReq 82052672 # Transaction distribution -system.membus.trans_dist::WriteResp 82052672 # Transaction distribution -system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution -system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution -system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution -system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 517024351 # Request fanout histogram -system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 517024351 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812144 # Class of executed instruction +system.membus.trans_dist::ReadReq 434895827 # Transaction distribution +system.membus.trans_dist::ReadResp 434906722 # Transaction distribution +system.membus.trans_dist::WriteReq 82052672 # Transaction distribution +system.membus.trans_dist::WriteResp 82052672 # Transaction distribution +system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution +system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 517024351 # Request fanout histogram +system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 517024351 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 09b69e575..c39fe9424 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517235 # Nu sim_ticks 517235411000 # Number of ticks simulated final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 795879 # Simulator instruction rate (inst/s) -host_op_rate 955482 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1509341441 # Simulator tick rate (ticks/s) -host_mem_usage 314596 # Number of bytes of host memory used -host_seconds 342.69 # Real time elapsed on the host +host_inst_rate 761441 # Simulator instruction rate (inst/s) +host_op_rate 914138 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1444030997 # Simulator tick rate (ticks/s) +host_mem_usage 318052 # Number of bytes of host memory used +host_seconds 358.19 # Real time elapsed on the host sim_insts 272739285 # Number of instructions simulated sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 322824 # In system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3976 # Transaction distribution -system.membus.trans_dist::ReadResp 3976 # Transaction distribution -system.membus.trans_dist::ReadExReq 2856 # Transaction distribution -system.membus.trans_dist::ReadExResp 2856 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6833 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,145 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812213 # Class of executed instruction +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 998 # number of writebacks +system.cpu.dcache.writebacks::total 998 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. @@ -430,145 +578,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits -system.cpu.dcache.overall_hits::total 168337827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses -system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 998 # number of writebacks -system.cpu.dcache.writebacks::total 998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution @@ -602,5 +611,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3976 # Transaction distribution +system.membus.trans_dist::ReadResp 3976 # Transaction distribution +system.membus.trans_dist::ReadExReq 2856 # Transaction distribution +system.membus.trans_dist::ReadExResp 2856 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6833 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6833 # Request fanout histogram +system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 3373b2092..896e43907 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.559967 # Number of seconds simulated -sim_ticks 559966999500 # Number of ticks simulated -final_tick 559966999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.559962 # Number of seconds simulated +sim_ticks 559961514500 # Number of ticks simulated +final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 393705 # Simulator instruction rate (inst/s) -host_op_rate 393705 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237364888 # Simulator tick rate (ticks/s) -host_mem_usage 245892 # Number of bytes of host memory used -host_seconds 2359.10 # Real time elapsed on the host +host_inst_rate 343254 # Simulator instruction rate (inst/s) +host_op_rate 343254 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206945650 # Simulator tick rate (ticks/s) +host_mem_usage 305268 # Number of bytes of host memory used +host_seconds 2705.84 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,33 +23,33 @@ system.physmem.num_reads::cpu.inst 291519 # Nu system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33318421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33318421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7621363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7621363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7621363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33318421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40939784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33318747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17280 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 270 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 17935 # Per bank write bursts system.physmem.perBankRdBursts::1 18289 # Per bank write bursts system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18248 # Per bank write bursts -system.physmem.perBankRdBursts::4 18163 # Per bank write bursts -system.physmem.perBankRdBursts::5 18239 # Per bank write bursts +system.physmem.perBankRdBursts::3 18250 # Per bank write bursts +system.physmem.perBankRdBursts::4 18167 # Per bank write bursts +system.physmem.perBankRdBursts::5 18240 # Per bank write bursts system.physmem.perBankRdBursts::6 18320 # Per bank write bursts system.physmem.perBankRdBursts::7 18299 # Per bank write bursts system.physmem.perBankRdBursts::8 18230 # Per bank write bursts @@ -59,7 +59,7 @@ system.physmem.perBankRdBursts::11 18391 # Pe system.physmem.perBankRdBursts::12 18259 # Per bank write bursts system.physmem.perBankRdBursts::13 18042 # Per bank write bursts system.physmem.perBankRdBursts::14 17977 # Per bank write bursts -system.physmem.perBankRdBursts::15 18106 # Per bank write bursts +system.physmem.perBankRdBursts::15 18101 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 559966923500 # Total gap between requests +system.physmem.totGap 559961438500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.912664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.833166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 269.609760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39535 37.79% 37.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43904 41.96% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8672 8.29% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 695 0.66% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 728 0.70% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 763 0.73% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1332 1.27% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 808 0.77% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8193 7.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.196437 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.192949 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.958027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes @@ -221,12 +221,12 @@ system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Wr system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2990654250 # Total ticks spent queuing -system.physmem.totMemAccLat 8451573000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10268.38 # Average queueing delay per DRAM burst +system.physmem.totQLat 2985206750 # Total ticks spent queuing +system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29018.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s @@ -237,35 +237,40 @@ system.physmem.busUtilRead 0.26 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 202814 # Number of row buffer hits during reads -system.physmem.writeRowHits 50461 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 1563271.35 # Average gap between requests -system.physmem.pageHitRate 70.76 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275670988500 # Time in different power states -system.physmem.memoryStateTime::REF 18698420000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 265594606500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 393989400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 396952920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 214974375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 216591375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136974800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1134400800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215550720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 36574109520 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 36574109520 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 108415975050 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 108760602465 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 240876668250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 240574363500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 387829129875 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 387872571300 # Total energy per rank (pJ) -system.physmem.averagePower::0 692.596540 # Core power per rank (mW) -system.physmem.averagePower::1 692.674119 # Core power per rank (mW) +system.physmem.readRowHits 202789 # Number of row buffer hits during reads +system.physmem.writeRowHits 50437 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgGap 1563256.04 # Average gap between requests +system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.597962 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states +system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.677886 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 125749069 # Number of BP lookups system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect @@ -309,24 +314,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1119933999 # number of cpu cycles simulated +system.cpu.numCycles 1119923029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.205800 # CPI: cycles per instruction -system.cpu.ipc 0.829325 # IPC: instructions per cycle -system.cpu.tickCycles 1060170405 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59763594 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.205788 # CPI: cycles per instruction +system.cpu.ipc 0.829333 # IPC: instructions per cycle +system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.890193 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890165 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -354,14 +359,14 @@ system.cpu.dcache.demand_misses::cpu.inst 849082 # n system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 849082 # number of overall misses system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23415653250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23415653250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9042894000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9042894000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32458547250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32458547250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32458547250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32458547250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32445902750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) @@ -378,14 +383,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002618 system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32890.433245 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32890.433245 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65932.892463 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65932.892463 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38227.812214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38227.812214 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32892.515616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65829.890706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,14 +417,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21914188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21914188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4452805750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4452805750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26366993750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26366993750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26366993750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26366993750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26361393250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses @@ -428,22 +433,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002407 system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30794.919177 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30794.919177 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64523.130371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64523.130371 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10606 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.447542 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447542 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id @@ -467,12 +472,12 @@ system.cpu.icache.demand_misses::cpu.inst 12350 # n system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses system.cpu.icache.overall_misses::total 12350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333735500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333735500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333735500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333735500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 333735500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 333735500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 333924000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 333924000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 333924000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses @@ -485,12 +490,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27023.117409 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27023.117409 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27023.117409 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27023.117409 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27038.380567 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27038.380567 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27038.380567 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27038.380567 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,41 +510,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12350 system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 307779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 307779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307779500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 307779500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307968000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 307968000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307968000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 307968000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307968000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 307968000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24921.417004 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24921.417004 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24936.680162 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24936.680162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 258740 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32601.453126 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32601.451844 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 523849 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2865.906217 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.546909 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2865.934205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.517639 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2657 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses @@ -562,14 +567,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 291520 # system.cpu.l2cache.demand_misses::total 291520 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 291520 # number of overall misses system.cpu.l2cache.overall_misses::total 291520 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16507068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16507068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4360106750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4360106750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20867174750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20867174750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20867174750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20867174750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20861762750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20861762750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) @@ -588,14 +593,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367627 system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367627 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73405.527515 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73405.527515 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65422.863681 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65422.863681 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71580.593956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71580.593956 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,14 +619,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 291520 system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 291520 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13668599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13668599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3526847250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3526847250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17195446750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17195446750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17195446750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17195446750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17190059750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965716 # mshr miss rate for ReadExReq accesses @@ -630,14 +635,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367627 system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60783.099500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60783.099500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52919.907720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52919.907720 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution @@ -666,7 +671,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # La system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222199250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution @@ -688,9 +693,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 975509000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2745284750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index ce136ba27..8cb1b2d37 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.278139 # Number of seconds simulated -sim_ticks 278139424500 # Number of ticks simulated -final_tick 278139424500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.278180 # Number of seconds simulated +sim_ticks 278180234500 # Number of ticks simulated +final_tick 278180234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197644 # Simulator instruction rate (inst/s) -host_op_rate 197644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65258345 # Simulator tick rate (ticks/s) -host_mem_usage 248388 # Number of bytes of host memory used -host_seconds 4262.13 # Real time elapsed on the host +host_inst_rate 185742 # Simulator instruction rate (inst/s) +host_op_rate 185742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61337566 # Simulator tick rate (ticks/s) +host_mem_usage 305284 # Number of bytes of host memory used +host_seconds 4535.23 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 175680 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18477184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18653120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18652864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 175680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 175680 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2745 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 288706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291451 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 632546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66431374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67063920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 632546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 632546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15343787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15343787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15343787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 632546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66431374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82407706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291455 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 631533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66421628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67053161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15341536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15341536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15341536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66421628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82394697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291451 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291451 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18634176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18944 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18653120 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18633536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652864 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 296 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17915 # Per bank write bursts -system.physmem.perBankRdBursts::1 18264 # Per bank write bursts -system.physmem.perBankRdBursts::2 18305 # Per bank write bursts -system.physmem.perBankRdBursts::3 18245 # Per bank write bursts -system.physmem.perBankRdBursts::4 18154 # Per bank write bursts -system.physmem.perBankRdBursts::5 18231 # Per bank write bursts -system.physmem.perBankRdBursts::6 18323 # Per bank write bursts -system.physmem.perBankRdBursts::7 18314 # Per bank write bursts -system.physmem.perBankRdBursts::8 18231 # Per bank write bursts -system.physmem.perBankRdBursts::9 18221 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18383 # Per bank write bursts -system.physmem.perBankRdBursts::12 18244 # Per bank write bursts -system.physmem.perBankRdBursts::13 18043 # Per bank write bursts -system.physmem.perBankRdBursts::14 17967 # Per bank write bursts -system.physmem.perBankRdBursts::15 18104 # Per bank write bursts +system.physmem.perBankRdBursts::0 17916 # Per bank write bursts +system.physmem.perBankRdBursts::1 18271 # Per bank write bursts +system.physmem.perBankRdBursts::2 18306 # Per bank write bursts +system.physmem.perBankRdBursts::3 18248 # Per bank write bursts +system.physmem.perBankRdBursts::4 18157 # Per bank write bursts +system.physmem.perBankRdBursts::5 18220 # Per bank write bursts +system.physmem.perBankRdBursts::6 18319 # Per bank write bursts +system.physmem.perBankRdBursts::7 18312 # Per bank write bursts +system.physmem.perBankRdBursts::8 18226 # Per bank write bursts +system.physmem.perBankRdBursts::9 18223 # Per bank write bursts +system.physmem.perBankRdBursts::10 18210 # Per bank write bursts +system.physmem.perBankRdBursts::11 18385 # Per bank write bursts +system.physmem.perBankRdBursts::12 18240 # Per bank write bursts +system.physmem.perBankRdBursts::13 18040 # Per bank write bursts +system.physmem.perBankRdBursts::14 17965 # Per bank write bursts +system.physmem.perBankRdBursts::15 18111 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::9 4187 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 278139341500 # Total gap between requests +system.physmem.totGap 278180151500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291455 # Read request sizes (log2) +system.physmem.readPktSize::6 291451 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 211494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 211637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,137 +193,118 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.952415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.081554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 279.010577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36030 35.87% 35.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42282 42.09% 77.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10217 10.17% 88.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 414 0.41% 88.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 384 0.38% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 317 0.32% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 757 0.75% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1270 1.26% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8780 8.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 100542 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.760100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.180809 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.034024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36066 35.87% 35.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42234 42.01% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10234 10.18% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 483 0.48% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 471 0.47% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 384 0.38% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 767 0.76% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1163 1.16% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8740 8.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100542 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.301854 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.144651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 769.722850 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.840049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.159268 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 778.757650 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.458498 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.856350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3077 76.07% 76.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 963 23.81% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.480346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.459004 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.856073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3075 76.02% 76.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 23.86% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 3340616250 # Total ticks spent queuing -system.physmem.totMemAccLat 8799847500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11473.51 # Average queueing delay per DRAM burst +system.physmem.totQLat 3369536750 # Total ticks spent queuing +system.physmem.totMemAccLat 8828580500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11573.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30223.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 67.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30323.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.98 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing -system.physmem.readRowHits 206977 # Number of row buffer hits during reads -system.physmem.writeRowHits 50379 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.55 # Row buffer hit rate for writes -system.physmem.avgGap 776626.17 # Average gap between requests -system.physmem.pageHitRate 71.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 74109656250 # Time in different power states -system.physmem.memoryStateTime::REF 9287460000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 194735825750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 377969760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 381175200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 206233500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 207982500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136124600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1133831400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215524800 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 18166271760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 18166271760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 79684218180 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79920417060 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 96981320250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 96774128250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 196768576530 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 196799330970 # Total energy per rank (pJ) -system.physmem.averagePower::0 707.462354 # Core power per rank (mW) -system.physmem.averagePower::1 707.572929 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 224829 # Transaction distribution -system.membus.trans_dist::ReadResp 224829 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66626 # Transaction distribution -system.membus.trans_dist::ReadExResp 66626 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649593 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649593 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22920832 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358138 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358138 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358138 # Request fanout histogram -system.membus.reqLayer0.occupancy 956225500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2708510750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 192497192 # Number of BP lookups -system.cpu.branchPred.condPredicted 125506208 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11891081 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 155386216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126898467 # Number of BTB hits +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 206912 # Number of row buffer hits during reads +system.physmem.writeRowHits 50353 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.51 # Row buffer hit rate for writes +system.physmem.avgGap 776748.79 # Average gap between requests +system.physmem.pageHitRate 71.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 378604800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 206580000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136756400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79832621385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96879153000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 196819477185 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.526603 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 160651755000 # Time in different power states +system.physmem_0.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108238852500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 381470040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 208143375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134088800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79968075615 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 96760333500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 196836972210 # Total energy per rank (pJ) +system.physmem_1.averagePower 707.589494 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 160452636750 # Time in different power states +system.physmem_1.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108437970750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 192516083 # Number of BP lookups +system.cpu.branchPred.condPredicted 125602202 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11889251 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 155393318 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126938973 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.666489 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 29014222 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.688823 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28938957 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244546246 # DTB read hits -system.cpu.dtb.read_misses 309763 # DTB read misses +system.cpu.dtb.read_hits 244535558 # DTB read hits +system.cpu.dtb.read_misses 309848 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244856009 # DTB read accesses -system.cpu.dtb.write_hits 135693142 # DTB write hits -system.cpu.dtb.write_misses 31331 # DTB write misses +system.cpu.dtb.read_accesses 244845406 # DTB read accesses +system.cpu.dtb.write_hits 135688740 # DTB write hits +system.cpu.dtb.write_misses 31438 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135724473 # DTB write accesses -system.cpu.dtb.data_hits 380239388 # DTB hits -system.cpu.dtb.data_misses 341094 # DTB misses +system.cpu.dtb.write_accesses 135720178 # DTB write accesses +system.cpu.dtb.data_hits 380224298 # DTB hits +system.cpu.dtb.data_misses 341286 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380580482 # DTB accesses -system.cpu.itb.fetch_hits 197059053 # ITB hits -system.cpu.itb.fetch_misses 278 # ITB misses +system.cpu.dtb.data_accesses 380565584 # DTB accesses +system.cpu.itb.fetch_hits 196974389 # ITB hits +system.cpu.itb.fetch_misses 282 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 197059331 # ITB accesses +system.cpu.itb.fetch_accesses 196974671 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -337,99 +318,99 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 556278850 # number of cpu cycles simulated +system.cpu.numCycles 556360470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202390061 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648021471 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192497192 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155912689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341534414 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24250324 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 202471372 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648161036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192516083 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155877930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341537101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24247434 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6722 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 6713 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 197059053 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6903560 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 556056617 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 196974389 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6735628 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 556139161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176192 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236849124 42.59% 42.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30318987 5.45% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22124224 3.98% 52.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36449383 6.55% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67846603 12.20% 70.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21659642 3.90% 74.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19297725 3.47% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3452517 0.62% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118058412 21.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236974879 42.61% 42.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30241040 5.44% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22122460 3.98% 52.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36446378 6.55% 58.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67887841 12.21% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21615986 3.89% 74.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19300231 3.47% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3499506 0.63% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118050840 21.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 556056617 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346044 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.962582 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168903349 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 88724490 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273566111 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12744273 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12118394 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15366279 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1583865955 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 556139161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346028 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.962398 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168673381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 88906441 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273702922 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12739464 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12116953 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15366288 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7026 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1584564231 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12118394 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176795678 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61743317 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13930 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278397423 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26987875 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1537838720 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7334 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2373790 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17873362 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6849052 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1027019192 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1768562187 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1728780266 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39781920 # Number of floating rename lookups +system.cpu.rename.SquashCycles 12116953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176662049 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61884123 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13864 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278433046 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27029126 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538057639 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6904 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2373775 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17934465 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6832008 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1026949046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1768413823 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1728631636 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39782186 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 388052034 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1374 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9574141 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372265088 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175432833 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40642740 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11166161 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304456084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 387981888 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1375 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 99 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9559876 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372392006 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175420299 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40717360 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11158065 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304772774 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015678873 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8790246 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462050270 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427374200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1015651643 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8789932 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462366805 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427709940 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 556056617 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.826575 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.903970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 556139161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.826254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.901646 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197073815 35.44% 35.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93100278 16.74% 52.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91275539 16.41% 68.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59807751 10.76% 79.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56767795 10.21% 89.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29817356 5.36% 94.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17038926 3.06% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7188508 1.29% 99.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3986649 0.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 196811929 35.39% 35.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93156725 16.75% 52.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91633615 16.48% 68.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59891442 10.77% 79.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56837976 10.22% 89.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29662833 5.33% 94.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17038989 3.06% 98.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7191857 1.29% 99.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3913795 0.70% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 556056617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 556139161 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2463855 10.47% 10.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2464081 10.47% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available @@ -458,118 +439,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15566694 66.15% 76.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5500530 23.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15568992 66.16% 76.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5500305 23.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579447507 57.05% 57.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579437623 57.05% 57.05% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7930 0.00% 57.05% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13181923 1.30% 58.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13181925 1.30% 58.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276926005 27.27% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138947884 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276912765 27.26% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138943776 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015678873 # Type of FU issued -system.cpu.iq.rate 1.825845 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23531079 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2548927232 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1725239923 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 940039301 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70808456 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41311588 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34425282 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002846638 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36362038 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50462240 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015651643 # Type of FU issued +system.cpu.iq.rate 1.825528 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23533378 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023171 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2548957351 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1725871307 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 940019268 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70808406 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41313833 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34425264 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002821720 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36362025 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50456367 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 134754491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1146539 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45582 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77131633 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 134881409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1145791 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45978 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77119099 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2126 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4422 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2647 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4470 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12118394 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60795579 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 183960 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1478937167 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16099 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372265088 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175432833 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 12116953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60932529 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 189663 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479247252 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16168 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372392006 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175420299 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 26971 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 168750 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45582 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11885427 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16182 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11901609 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976191371 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244856188 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39487502 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 26629 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 174749 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45978 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11882583 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16645 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11899228 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976172370 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244845576 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39479273 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174481002 # number of nop insts executed -system.cpu.iew.exec_refs 380581036 # number of memory reference insts executed -system.cpu.iew.exec_branches 129104728 # Number of branches executed -system.cpu.iew.exec_stores 135724848 # Number of stores executed -system.cpu.iew.exec_rate 1.754860 # Inst execution rate -system.cpu.iew.wb_sent 974983742 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974464583 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556223277 # num instructions producing a value -system.cpu.iew.wb_consumers 832224680 # num instructions consuming a value +system.cpu.iew.exec_nop 174474397 # number of nop insts executed +system.cpu.iew.exec_refs 380566182 # number of memory reference insts executed +system.cpu.iew.exec_branches 129102826 # Number of branches executed +system.cpu.iew.exec_stores 135720606 # Number of stores executed +system.cpu.iew.exec_rate 1.754568 # Inst execution rate +system.cpu.iew.wb_sent 974964146 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974444532 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556292557 # num instructions producing a value +system.cpu.iew.wb_consumers 832443785 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.751756 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668357 # average fanout of values written-back +system.cpu.iew.wb_rate 1.751463 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668264 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543106202 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543416365 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11884314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 483349873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.921150 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.600543 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11882488 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 483294798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.921369 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.600805 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 205286712 42.47% 42.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102225167 21.15% 63.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51816081 10.72% 74.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25666887 5.31% 79.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21541208 4.46% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9141976 1.89% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10432211 2.16% 88.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6655388 1.38% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50584243 10.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 205311965 42.48% 42.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102147195 21.14% 63.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51748026 10.71% 74.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25735966 5.33% 79.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21537447 4.46% 84.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9139527 1.89% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10425967 2.16% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6656382 1.38% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50592323 10.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 483349873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 483294798 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -615,238 +596,330 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50584243 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 50592323 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1901838322 # The number of ROB reads -system.cpu.rob.rob_writes 3016095658 # The number of ROB writes -system.cpu.timesIdled 3295 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 222233 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1902085330 # The number of ROB reads +system.cpu.rob.rob_writes 3016853590 # The number of ROB writes +system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 221309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.660364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.660364 # CPI: Total CPI of All Threads -system.cpu.ipc 1.514316 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.514316 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237260763 # number of integer regfile reads -system.cpu.int_regfile_writes 705832198 # number of integer regfile writes -system.cpu.fp_regfile_reads 36691509 # number of floating regfile reads -system.cpu.fp_regfile_writes 24411335 # number of floating regfile writes +system.cpu.cpi 0.660461 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.660461 # CPI: Total CPI of All Threads +system.cpu.ipc 1.514094 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.514094 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237238749 # number of integer regfile reads +system.cpu.int_regfile_writes 705818584 # number of integer regfile writes +system.cpu.fp_regfile_reads 36691517 # number of floating regfile reads +system.cpu.fp_regfile_writes 24411333 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 718899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68835 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1666955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 408320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56270144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 879222 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 879222 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 879222 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 531099000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10065500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1207435500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 4667 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.176031 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 197050731 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6380 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30885.694514 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 777239 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.040110 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289873961 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781335 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 370.998305 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354310000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.040110 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy 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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369495 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.369993 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369495 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.369993 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60064.636364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60647.849874 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60640.716319 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64699.749347 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64699.749347 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60064.636364 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61582.925190 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61568.599548 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60064.636364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61582.925190 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61568.599548 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 291452 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 165368000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13488499500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13653867500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4314074750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4314074750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17802574250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17967942250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17802574250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17967942250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312748 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.369999 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.369999 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60221.412964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60736.572527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60730.280481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64752.562890 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64752.562890 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 777257 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.039658 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 289884062 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781353 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 371.002686 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354263250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.039658 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2500 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 242 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585539447 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585539447 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192500682 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192500682 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97383359 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97383359 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 21 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 21 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289884041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289884041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289884041 # number of overall hits -system.cpu.dcache.overall_hits::total 289884041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1577144 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1577144 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 917841 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 917841 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2494985 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2494985 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2494985 # number of overall misses -system.cpu.dcache.overall_misses::total 2494985 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79985151750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79985151750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57294656713 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57294656713 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137279808463 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137279808463 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137279808463 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137279808463 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194077826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194077826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292379026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292379026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292379026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292379026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008126 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008126 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009337 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009337 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008533 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008533 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008533 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008533 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50715.186280 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50715.186280 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62423.291957 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62423.291957 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55022.298115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55022.298115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55022.298115 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21941 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 56666 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 465 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.184946 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 109.605416 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks -system.cpu.dcache.writebacks::total 91488 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864626 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 864626 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 849006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 849006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1713632 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1713632 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1713632 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1713632 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712518 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712518 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68835 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68835 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781353 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781353 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781353 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781353 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21854414000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21854414000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5217448748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5217448748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27071862748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27071862748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27071862748 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27071862748 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30672.086881 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30672.086881 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75796.451631 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75796.451631 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34647.416402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34647.416402 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 718879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68831 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1666907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 407936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55860672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56268608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 879198 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 879198 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 879198 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 531087000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 10054750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1207495250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224827 # Transaction distribution +system.membus.trans_dist::ReadResp 224827 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66624 # Transaction distribution +system.membus.trans_dist::ReadExResp 66624 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649585 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649585 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 358134 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 358134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 358134 # Request fanout histogram +system.membus.reqLayer0.occupancy 959207000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2708819750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 531c5ebad..11060cf95 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541781 # Number of seconds simulated -sim_ticks 541781076000 # Number of ticks simulated -final_tick 541781076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.541786 # Number of seconds simulated +sim_ticks 541786101000 # Number of ticks simulated +final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140173 # Simulator instruction rate (inst/s) -host_op_rate 172571 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118539448 # Simulator tick rate (ticks/s) -host_mem_usage 261676 # Number of bytes of host memory used -host_seconds 4570.47 # Real time elapsed on the host +host_inst_rate 183531 # Simulator instruction rate (inst/s) +host_op_rate 225950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155207340 # Simulator tick rate (ticks/s) +host_mem_usage 320704 # Number of bytes of host memory used +host_seconds 3490.72 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,43 +23,43 @@ system.physmem.num_reads::cpu.inst 290529 # Nu system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34319870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34319870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7808084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7808084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7808084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34319870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42127954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34319552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 290529 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18573248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18288 # Per bank write bursts -system.physmem.perBankRdBursts::1 18139 # Per bank write bursts -system.physmem.perBankRdBursts::2 18224 # Per bank write bursts -system.physmem.perBankRdBursts::3 18182 # Per bank write bursts -system.physmem.perBankRdBursts::4 18264 # Per bank write bursts -system.physmem.perBankRdBursts::5 18315 # Per bank write bursts -system.physmem.perBankRdBursts::6 18098 # Per bank write bursts +system.physmem.perBankRdBursts::0 18289 # Per bank write bursts +system.physmem.perBankRdBursts::1 18137 # Per bank write bursts +system.physmem.perBankRdBursts::2 18222 # Per bank write bursts +system.physmem.perBankRdBursts::3 18184 # Per bank write bursts +system.physmem.perBankRdBursts::4 18266 # Per bank write bursts +system.physmem.perBankRdBursts::5 18308 # Per bank write bursts +system.physmem.perBankRdBursts::6 18094 # Per bank write bursts system.physmem.perBankRdBursts::7 17914 # Per bank write bursts -system.physmem.perBankRdBursts::8 17936 # Per bank write bursts -system.physmem.perBankRdBursts::9 17963 # Per bank write bursts -system.physmem.perBankRdBursts::10 18015 # Per bank write bursts +system.physmem.perBankRdBursts::8 17939 # Per bank write bursts +system.physmem.perBankRdBursts::9 17962 # Per bank write bursts +system.physmem.perBankRdBursts::10 18018 # Per bank write bursts system.physmem.perBankRdBursts::11 18110 # Per bank write bursts -system.physmem.perBankRdBursts::12 18146 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts -system.physmem.perBankRdBursts::14 18075 # Per bank write bursts -system.physmem.perBankRdBursts::15 18267 # Per bank write bursts +system.physmem.perBankRdBursts::12 18143 # Per bank write bursts +system.physmem.perBankRdBursts::13 18270 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18266 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts system.physmem.perBankWrBursts::1 4101 # Per bank write bursts system.physmem.perBankWrBursts::2 4137 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541780987500 # Total gap between requests +system.physmem.totGap 541786012500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,9 +93,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -189,42 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.445337 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.546078 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.289579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46919 42.07% 42.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43694 39.18% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8696 7.80% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 722 0.65% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1258 1.13% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1255 1.13% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 576 0.52% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 502 0.45% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7898 7.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111520 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.543798 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.072613 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.664819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.488645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.467122 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3028 75.57% 75.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads -system.physmem.totQLat 2702187250 # Total ticks spent queuing -system.physmem.totMemAccLat 8143568500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1451035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9311.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads +system.physmem.totQLat 2707676000 # Total ticks spent queuing +system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28061.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s @@ -235,35 +237,40 @@ system.physmem.busUtilRead 0.27 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing -system.physmem.readRowHits 194639 # Number of row buffer hits during reads -system.physmem.writeRowHits 50105 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.80 # Row buffer hit rate for writes -system.physmem.avgGap 1519181.07 # Average gap between requests -system.physmem.pageHitRate 68.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 263887343000 # Time in different power states -system.physmem.memoryStateTime::REF 18091060000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 259796939500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 421530480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 421462440 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 230001750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 229964625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1134174600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1128987600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 215628480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 212505120 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 35386113360 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 35386113360 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 105979651695 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 105556941405 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 232100586000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 232471384500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 375467686365 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 375407359050 # Total energy per rank (pJ) -system.physmem.averagePower::0 693.032096 # Core power per rank (mW) -system.physmem.averagePower::1 692.920745 # Core power per rank (mW) +system.physmem.readRowHits 194608 # Number of row buffer hits during reads +system.physmem.writeRowHits 50098 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes +system.physmem.avgGap 1519195.16 # Average gap between requests +system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.117148 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.890615 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 156937341 # Number of BP lookups system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect @@ -274,6 +281,14 @@ system.cpu.branchPred.BTBHitPct 83.942615 # BT system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -295,6 +310,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -316,6 +339,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +368,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -359,24 +398,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1083562152 # number of cpu cycles simulated +system.cpu.numCycles 1083572202 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655084 # Number of instructions committed system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.691335 # CPI: cycles per instruction -system.cpu.ipc 0.591249 # IPC: instructions per cycle -system.cpu.tickCycles 1029140125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54422027 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.691350 # CPI: cycles per instruction +system.cpu.ipc 0.591244 # IPC: instructions per cycle +system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778221 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.644165 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 752182250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.644165 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.645412 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -408,14 +447,14 @@ system.cpu.dcache.demand_misses::cpu.inst 851460 # n system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 851460 # number of overall misses system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23050728217 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23050728217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9196889000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9196889000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32247617217 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32247617217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32247617217 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32247617217 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32255064217 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) @@ -436,14 +475,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32295.376677 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32295.376677 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66783.012497 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66783.012497 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37873.320199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37873.320199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37873.320199 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32302.557092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66799.873650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37882.066353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,14 +509,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 782317 system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 782317 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21540338778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21540338778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529678750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529678750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26070017528 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26070017528 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26070017528 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26070017528 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21545578028 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses @@ -486,22 +525,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30211.065685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30211.065685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65342.586048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65342.586048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33324.109700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33324.109700 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33332.600503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23590 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.180354 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289921724 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11440.816227 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180354 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -509,44 +548,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 57 system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579919473 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579919473 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289921724 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289921724 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289921724 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289921724 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289921724 # number of overall hits -system.cpu.icache.overall_hits::total 289921724 # number of overall hits +system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits +system.cpu.icache.overall_hits::total 289921723 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses system.cpu.icache.overall_misses::total 25342 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 481750746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 481750746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 481750746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 481750746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 481750746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 481750746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289947066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289947066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289947066 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289947066 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289947066 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289947066 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 480693746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 480693746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 480693746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 480693746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 480693746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 480693746 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289947065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289947065 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289947065 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289947065 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289947065 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19009.973404 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19009.973404 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19009.973404 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19009.973404 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19009.973404 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,36 +600,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25342 system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429966254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 429966254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429966254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 429966254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429966254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 429966254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16966.547786 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16966.547786 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16966.547786 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16966.547786 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32583.074549 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2860.585859 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.488690 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087298 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907058 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994357 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.446536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907057 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id @@ -618,14 +657,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 290562 # system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 290562 # number of overall misses system.cpu.l2cache.overall_misses::total 290562 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16093224000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16093224000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4428044750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4428044750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20521268750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20521268750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20521268750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20521268750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16097406250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4429448000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20526854250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20526854250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) @@ -644,14 +683,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359758 system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359758 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71694.000561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71694.000561 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66999.209423 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66999.209423 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70626.127126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70626.127126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70626.127126 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71712.632144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67020.441512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70645.350218 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,14 +715,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 290530 system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 290530 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13281416250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13281416250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3575940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3575940250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16857356500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16857356500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16857356500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16857356500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13285316750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3577310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16862626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16862626750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303979 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953391 # mshr miss rate for ReadExReq accesses @@ -692,14 +731,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359719 system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359719 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59176.062315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59176.062315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54106.311752 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54106.311752 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58022.773896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58022.773896 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59193.441202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54127.036964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution @@ -732,7 +771,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # La system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224341972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224438 # Transaction distribution system.membus.trans_dist::ReadResp 224438 # Transaction distribution @@ -754,9 +793,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 356627 # Request fanout histogram -system.membus.reqLayer0.occupancy 983533000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2738969000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 57de3b3e6..5cb40d175 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.407884 # Number of seconds simulated -sim_ticks 407883784500 # Number of ticks simulated -final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.408037 # Number of seconds simulated +sim_ticks 408037199500 # Number of ticks simulated +final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91246 # Simulator instruction rate (inst/s) -host_op_rate 112336 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58093586 # Simulator tick rate (ticks/s) -host_mem_usage 2566152 # Number of bytes of host memory used -host_seconds 7021.15 # Real time elapsed on the host +host_inst_rate 90640 # Simulator instruction rate (inst/s) +host_op_rate 111590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57729920 # Simulator tick rate (ticks/s) +host_mem_usage 318440 # Number of bytes of host memory used +host_seconds 7068.04 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 63360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6867584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 13490752 # Number of bytes read from this memory -system.physmem.bytes_read::total 20421696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4243968 # Number of bytes written to this memory -system.physmem.bytes_written::total 4243968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 107306 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 210793 # Number of read requests responded to by this memory -system.physmem.num_reads::total 319089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66312 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66312 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 155338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16837110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 33074990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50067438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10404846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10404846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10404846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16837110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 33074990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60472284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 319089 # Number of read requests accepted -system.physmem.writeReqs 66312 # Number of write requests accepted -system.physmem.readBursts 319089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66312 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20403200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20421696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4243968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 20089 # Per bank write bursts -system.physmem.perBankRdBursts::1 19545 # Per bank write bursts -system.physmem.perBankRdBursts::2 20086 # Per bank write bursts -system.physmem.perBankRdBursts::3 20646 # Per bank write bursts -system.physmem.perBankRdBursts::4 19933 # Per bank write bursts -system.physmem.perBankRdBursts::5 20704 # Per bank write bursts -system.physmem.perBankRdBursts::6 19571 # Per bank write bursts -system.physmem.perBankRdBursts::7 19471 # Per bank write bursts -system.physmem.perBankRdBursts::8 19556 # Per bank write bursts -system.physmem.perBankRdBursts::9 19505 # Per bank write bursts -system.physmem.perBankRdBursts::10 19502 # Per bank write bursts -system.physmem.perBankRdBursts::11 20173 # Per bank write bursts -system.physmem.perBankRdBursts::12 19634 # Per bank write bursts -system.physmem.perBankRdBursts::13 20280 # Per bank write bursts -system.physmem.perBankRdBursts::14 19577 # Per bank write bursts -system.physmem.perBankRdBursts::15 20528 # Per bank write bursts -system.physmem.perBankWrBursts::0 4247 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory +system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315254 # Number of read requests accepted +system.physmem.writeReqs 66324 # Number of write requests accepted +system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19893 # Per bank write bursts +system.physmem.perBankRdBursts::1 19507 # Per bank write bursts +system.physmem.perBankRdBursts::2 19696 # Per bank write bursts +system.physmem.perBankRdBursts::3 19811 # Per bank write bursts +system.physmem.perBankRdBursts::4 19755 # Per bank write bursts +system.physmem.perBankRdBursts::5 20266 # Per bank write bursts +system.physmem.perBankRdBursts::6 19606 # Per bank write bursts +system.physmem.perBankRdBursts::7 19431 # Per bank write bursts +system.physmem.perBankRdBursts::8 19468 # Per bank write bursts +system.physmem.perBankRdBursts::9 19384 # Per bank write bursts +system.physmem.perBankRdBursts::10 19414 # Per bank write bursts +system.physmem.perBankRdBursts::11 19672 # Per bank write bursts +system.physmem.perBankRdBursts::12 19624 # Per bank write bursts +system.physmem.perBankRdBursts::13 19992 # Per bank write bursts +system.physmem.perBankRdBursts::14 19481 # Per bank write bursts +system.physmem.perBankRdBursts::15 19957 # Per bank write bursts +system.physmem.perBankWrBursts::0 4278 # Per bank write bursts system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4151 # Per bank write bursts -system.physmem.perBankWrBursts::4 4245 # Per bank write bursts +system.physmem.perBankWrBursts::2 4141 # Per bank write bursts +system.physmem.perBankWrBursts::3 4152 # Per bank write bursts +system.physmem.perBankWrBursts::4 4250 # Per bank write bursts system.physmem.perBankWrBursts::5 4232 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4096 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4153 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 407883730500 # Total gap between requests +system.physmem.totGap 408037145000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 319089 # Read request sizes (log2) +system.physmem.readPktSize::6 315254 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66312 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 124916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 644 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66324 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,189 +148,171 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5220 # What write queue length does an incoming req see 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does an incoming req see -system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 138324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.138053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.082938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 199.804046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 55124 39.85% 39.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 58239 42.10% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14671 10.61% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 966 0.70% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1420 1.03% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1368 0.99% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1462 1.06% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1224 0.88% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3850 2.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 138324 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 67.829475 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.454654 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 482.917109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3981 99.10% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 5 0.12% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.10% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 3 0.07% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 2 0.05% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 2 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15872-16383 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.484690 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.435555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.421529 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3367 83.82% 83.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.22% 84.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 437 10.88% 94.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 79 1.97% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 37 0.92% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.45% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.37% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.55% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.32% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.07% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.15% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.07% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 9958454882 # Total ticks spent queuing -system.physmem.totMemAccLat 15935954882 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1594000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31237.31 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads +system.physmem.totQLat 9384520258 # Total ticks spent queuing +system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49987.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 50.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.07 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.47 # Data bus utilization in percentage system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing -system.physmem.readRowHits 219908 # Number of row buffer hits during reads -system.physmem.writeRowHits 26785 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.43 # Row buffer hit rate for writes -system.physmem.avgGap 1058335.94 # Average gap between requests -system.physmem.pageHitRate 64.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 155274651966 # Time in different power states -system.physmem.memoryStateTime::REF 13620100000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 238988228034 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 524928600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 520778160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 286419375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 284154750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1248351000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1238000400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216380160 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 212718960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 26640915600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 26640915600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 97043660235 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 97028348895 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 159603762000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 159617193000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 285564416970 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 285542109765 # Total energy per rank (pJ) -system.physmem.averagePower::0 700.113612 # Core power per rank (mW) -system.physmem.averagePower::1 700.058922 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 317731 # Transaction distribution -system.membus.trans_dist::ReadResp 317731 # Transaction distribution -system.membus.trans_dist::Writeback 66312 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19 # Transaction distribution -system.membus.trans_dist::UpgradeResp 19 # Transaction distribution -system.membus.trans_dist::ReadExReq 1358 # Transaction distribution -system.membus.trans_dist::ReadExResp 1358 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 704528 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 704528 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24665664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24665664 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 385420 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 385420 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 385420 # Request fanout histogram -system.membus.reqLayer0.occupancy 968060850 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2930140600 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 233961455 # Number of BP lookups -system.cpu.branchPred.condPredicted 161822903 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15515021 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121571694 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108258179 # Number of BTB hits +system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 218395 # Number of row buffer hits during reads +system.physmem.writeRowHits 26455 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes +system.physmem.avgGap 1069341.38 # Average gap between requests +system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.765171 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states +system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.696391 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states +system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 233958621 # Number of BP lookups +system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.048836 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25034450 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300530 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -352,6 +334,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -373,6 +363,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,6 +392,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -416,95 +422,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 815767570 # number of cpu cycles simulated +system.cpu.numCycles 816074400 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064711 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 216 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370072724 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652087 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 815611997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.839157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134572174 16.50% 16.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 222502254 27.28% 43.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98076609 12.02% 55.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360460960 44.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 815611997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286799 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.471100 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119967047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 156830594 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662032 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38633655 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518669 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25180757 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13832 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248142745 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39968083 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518669 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176978211 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77349013 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 209115 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464956606 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80600383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190653187 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25546667 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24946830 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267986 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40254462 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1692453 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225396135 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812466885 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358185264 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876472 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350617905 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7272 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 7264 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108149104 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366119032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236098756 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1753479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5371728 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168565166 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017100859 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18396242 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379746204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032205063 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 815611997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.247040 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 257903097 31.62% 31.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 228438073 28.01% 59.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 215325690 26.40% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97769150 11.99% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16175979 1.98% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 815611997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64512923 19.13% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18147 0.01% 19.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available @@ -532,13 +538,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155504488 46.10% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116641749 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456383765 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195693 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -560,90 +566,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550151 0.25% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478998 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322094029 31.67% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215573019 21.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017100859 # Type of FU issued -system.cpu.iq.rate 1.246802 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337314196 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331643 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3143647062 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504776491 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934274751 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877091 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565761 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152451 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320604680 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810375 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960281 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued +system.cpu.iq.rate 1.246337 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113878094 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1252 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107118260 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23979 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518669 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35328826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 675397 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168583078 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366119032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236098756 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 121 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 678981 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437712 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784771 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19222483 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974757504 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303300667 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42343355 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5552 # number of nop insts executed -system.cpu.iew.exec_refs 497757295 # number of memory reference insts executed -system.cpu.iew.exec_branches 150614518 # Number of branches executed -system.cpu.iew.exec_stores 194456628 # Number of stores executed -system.cpu.iew.exec_rate 1.194896 # Inst execution rate -system.cpu.iew.wb_sent 963726633 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960427202 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536683301 # num instructions producing a value -system.cpu.iew.wb_consumers 893293358 # num instructions consuming a value +system.cpu.iew.exec_nop 5556 # number of nop insts executed +system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed +system.cpu.iew.exec_branches 150614661 # Number of branches executed +system.cpu.iew.exec_stores 194464042 # Number of stores executed +system.cpu.iew.exec_rate 1.194456 # Inst execution rate +system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536684839 # num instructions producing a value +system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.177329 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600792 # average fanout of values written-back +system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357423726 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15501335 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 764789514 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.031303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.790973 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 428726988 56.06% 56.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 171833427 22.47% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566428 9.62% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31619643 4.13% 92.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 7902471 1.03% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14889027 1.95% 95.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7271717 0.95% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6618968 0.87% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360845 2.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 764789514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654410 # Number of instructions committed system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -689,507 +695,529 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1888573713 # The number of ROB reads -system.cpu.rob.rob_writes 2343133826 # The number of ROB writes -system.cpu.timesIdled 646395 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1888745890 # The number of ROB reads +system.cpu.rob.rob_writes 2343137518 # The number of ROB writes +system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649298 # Number of Instructions Simulated system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.273345 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.273345 # CPI: Total CPI of All Threads -system.cpu.ipc 0.785333 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.785333 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995802642 # number of integer regfile reads -system.cpu.int_regfile_writes 567917186 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889847 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959506 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794452598 # number of cc regfile reads -system.cpu.cc_regfile_writes 384905504 # number of cc regfile writes -system.cpu.misc_regfile_reads 715806131 # number of misc regfile reads +system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads +system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995816176 # number of integer regfile reads +system.cpu.int_regfile_writes 567918829 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads +system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes +system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 7205652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7205652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 9840757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339627 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248397 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16588024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330867456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223467584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554335040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 9840776 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18503299 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.531838 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.498985 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 8662542 46.82% 46.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 9840757 53.18% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18503299 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5066671498 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7754858551 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4142472532 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 5169293 # number of replacements -system.cpu.icache.tags.tagsinuse 510.870067 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 364901080 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.583169 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 199337500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.870067 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 325 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745315243 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745315243 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364901109 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364901109 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364901109 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364901109 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364901109 # number of overall hits -system.cpu.icache.overall_hits::total 364901109 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5171601 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5171601 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5171601 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5171601 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5171601 # number of overall misses -system.cpu.icache.overall_misses::total 5171601 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41478755019 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41478755019 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41478755019 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41478755019 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41478755019 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41478755019 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370072710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370072710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370072710 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370072710 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370072710 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370072710 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8020.486310 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8020.486310 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8020.486310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8020.486310 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8020.486310 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17792 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1782 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 9.984287 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1778 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1778 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1778 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1778 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1778 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1778 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169823 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5169823 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5169823 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5169823 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5169823 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5169823 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33703861415 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33703861415 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33703861415 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33703861415 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33703861415 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33703861415 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6519.345327 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6519.345327 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6519.345327 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6519.345327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6519.345327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6519.345327 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 42714534 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 332916 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 32636070 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 18709 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3827 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 9723012 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4810754 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 302773 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16364.911497 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7827990 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 319143 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.528158 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 12938833000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 727.090986 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.045333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8487.644412 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 7101.130766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.044378 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.518045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.433419 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998835 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 7180 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9190 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1499 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 5110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2000 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6801 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.438232 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.560913 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 139624071 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 139624071 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5168280 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1928699 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7096979 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 735005 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 735005 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718110 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718110 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5168280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2646809 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7815089 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5168280 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2646809 # number of overall hits -system.cpu.l2cache.overall_hits::total 7815089 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 107130 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 108654 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2737 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2737 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 109867 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 111391 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1524 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 109867 # number of overall misses -system.cpu.l2cache.overall_misses::total 111391 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 107432161 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7354763933 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 7462196094 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 174400348 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 174400348 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107432161 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7529164281 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7636596442 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107432161 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7529164281 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7636596442 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169804 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 2035829 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7205633 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 735005 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 735005 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5169804 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756676 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7926480 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5169804 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756676 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7926480 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.052622 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015079 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.950000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.950000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003797 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003797 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000295 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.039855 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014053 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000295 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.039855 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014053 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70493.543963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68652.701699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68678.521674 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63719.527950 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63719.527950 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70493.543963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68529.806775 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68556.673717 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70493.543963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68529.806775 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68556.673717 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 126545 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2364 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53.530034 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66312 # number of writebacks -system.cpu.l2cache.writebacks::total 66312 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 534 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1182 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1716 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1379 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1379 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 534 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2561 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3095 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 534 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2561 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3095 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 990 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 105948 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 106938 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 9723012 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 9723012 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1358 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1358 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 107306 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 108296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 107306 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 9723012 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 9831308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71873499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6404181248 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6476054747 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19431970184 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 143518 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 143518 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92793756 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92793756 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71873499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6496975004 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6568848503 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71873499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6496975004 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19431970184 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26000818687 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.052042 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.014841 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.950000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.950000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.013663 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000191 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.038926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.240312 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72599.493939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60446.457205 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60558.966382 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 1998.554582 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 7553.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 7553.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68331.189985 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68331.189985 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.427781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72599.493939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60546.241627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 1998.554582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 2644.695771 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2756164 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.948880 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414248795 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756676 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.271122 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 207459500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.948880 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999900 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999900 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756166 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347154 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347154 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286297439 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286297439 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127936631 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127936631 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414234070 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414234070 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414237227 # number of overall hits -system.cpu.dcache.overall_hits::total 414237227 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031039 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031039 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1014846 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1014846 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 648 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 648 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits +system.cpu.dcache.overall_hits::total 414238542 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4045885 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4045885 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4046533 # number of overall misses -system.cpu.dcache.overall_misses::total 4046533 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33719933619 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33719933619 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9704111685 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9704111685 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 169500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 169500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43424045304 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43424045304 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43424045304 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43424045304 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses +system.cpu.dcache.overall_misses::total 4045534 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3805 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3805 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279955 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279955 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283760 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283760 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010476 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007870 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.007870 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170302 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.170302 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009673 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009673 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009674 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009674 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11124.876196 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11124.876196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9562.151977 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9562.151977 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10732.891643 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10732.891643 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10731.172909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10731.172909 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 339239 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5513 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.534373 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735005 # number of writebacks -system.cpu.dcache.writebacks::total 735005 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995853 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 995853 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293979 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 293979 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks +system.cpu.dcache.writebacks::total 735128 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1289832 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1289832 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1289832 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1289832 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720867 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720867 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 643 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 643 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756053 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756053 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756696 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756696 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20990186992 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20990186992 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5237168826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5237168826 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5228000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5228000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26227355818 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26227355818 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26232583818 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26232583818 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1288834 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1288834 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1288834 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1288834 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035190 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035190 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2756054 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756054 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756695 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756695 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21052594116 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21052594116 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5256752100 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5256752100 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5684476 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5684476 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26309346216 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26309346216 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26315030692 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26315030692 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168988 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168988 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168595 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168595 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10313.645530 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10313.645530 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7265.097204 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7265.097204 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8130.637636 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8130.637636 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9516.274113 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9516.274113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9515.950913 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9515.950913 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10344.289288 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10344.289288 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7292.293831 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7292.293831 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8868.137285 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8868.137285 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9546.019859 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9546.019859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9545.862234 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9545.862234 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 5169210 # number of replacements +system.cpu.icache.tags.tagsinuse 510.721915 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 364899992 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169720 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.584092 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 237857250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.721915 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997504 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997504 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 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accesses +system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8045.894578 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8045.894578 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8045.894578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8045.894578 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 67339 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2239 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked 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5169737 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5169737 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5169737 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5169737 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5169737 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33819004202 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33819004202 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33819004202 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33819004202 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33819004202 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 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blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2092 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7253 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.398804 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.599976 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139620886 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139620886 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5166160 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1926359 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7092519 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 735128 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68079.864252 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78572.961768 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78572.961768 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68338.017414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68338.017414 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks +system.cpu.l2cache.writebacks::total 66324 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits 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demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency 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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 317003 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 313877 # Transaction distribution +system.membus.trans_dist::ReadResp 313877 # Transaction distribution +system.membus.trans_dist::Writeback 66324 # Transaction distribution +system.membus.trans_dist::UpgradeReq 14 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 381592 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 381592 # Request fanout histogram +system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index b5ba9b69f..4817ec8a9 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778000 # Number of ticks simulated final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1695212 # Simulator instruction rate (inst/s) -host_op_rate 2087030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1047118075 # Simulator tick rate (ticks/s) -host_mem_usage 304696 # Number of bytes of host memory used -host_seconds 377.92 # Real time elapsed on the host +host_inst_rate 1395078 # Simulator instruction rate (inst/s) +host_op_rate 1717525 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 861727739 # Simulator tick rate (ticks/s) +host_mem_usage 309420 # Number of bytes of host memory used +host_seconds 459.22 # Real time elapsed on the host sim_insts 640654410 # Number of instructions simulated sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1322421029 # Wr system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 893703777 # Transaction distribution -system.membus.trans_dist::ReadResp 893709516 # Transaction distribution -system.membus.trans_dist::WriteReq 128951477 # Transaction distribution -system.membus.trans_dist::WriteResp 128951477 # Transaction distribution -system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution -system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram -system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 1022670352 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction +system.membus.trans_dist::ReadReq 893703777 # Transaction distribution +system.membus.trans_dist::ReadResp 893709516 # Transaction distribution +system.membus.trans_dist::WriteReq 128951477 # Transaction distribution +system.membus.trans_dist::WriteResp 128951477 # Transaction distribution +system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution +system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram +system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 1022670352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index b1098c721..c5e3a18fc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.043695 # Nu sim_ticks 1043695084000 # Number of ticks simulated final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 974812 # Simulator instruction rate (inst/s) -host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1591272225 # Simulator tick rate (ticks/s) -host_mem_usage 314196 # Number of bytes of host memory used -host_seconds 655.89 # Real time elapsed on the host +host_inst_rate 894518 # Simulator instruction rate (inst/s) +host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1460200235 # Simulator tick rate (ticks/s) +host_mem_usage 317628 # Number of bytes of host memory used +host_seconds 714.76 # Real time elapsed on the host sim_insts 639366786 # Number of instructions simulated sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 4053168 # To system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 223619 # Transaction distribution -system.membus.trans_dist::ReadResp 223619 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::ReadExReq 66093 # Transaction distribution -system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 355811 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 355811 # Request fanout histogram -system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,145 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction +system.cpu.dcache.tags.replacements 778046 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits +system.cpu.dcache.overall_hits::total 378498833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses +system.cpu.dcache.overall_misses::total 782143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks +system.cpu.dcache.writebacks::total 91561 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. @@ -438,145 +585,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits -system.cpu.dcache.overall_hits::total 378498833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses -system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks -system.cpu.dcache.writebacks::total 91561 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution @@ -610,5 +618,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 15312000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 223619 # Transaction distribution +system.membus.trans_dist::ReadResp 223619 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::ReadExReq 66093 # Transaction distribution +system.membus.trans_dist::ReadExResp 66093 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 355811 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 355811 # Request fanout histogram +system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index a69375a69..1993a40dc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058648 # Number of seconds simulated -sim_ticks 58648243500 # Number of ticks simulated -final_tick 58648243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058585 # Number of seconds simulated +sim_ticks 58584661500 # Number of ticks simulated +final_tick 58584661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 296946 # Simulator instruction rate (inst/s) -host_op_rate 296946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 196921777 # Simulator tick rate (ticks/s) -host_mem_usage 246040 # Number of bytes of host memory used -host_seconds 297.83 # Real time elapsed on the host +host_inst_rate 346754 # Simulator instruction rate (inst/s) +host_op_rate 346754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 229702503 # Simulator tick rate (ticks/s) +host_mem_usage 303900 # Number of bytes of host memory used +host_seconds 255.05 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 10664704 # Number of bytes read from this memory -system.physmem.bytes_read::total 10664704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 516672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 516672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 166636 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114049 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114049 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 181841831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 181841831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8809676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8809676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 124456174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 124456174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 124456174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 181841831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 306298005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166636 # Number of read requests accepted -system.physmem.writeReqs 114049 # Number of write requests accepted -system.physmem.readBursts 166636 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114049 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10664320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10664704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 10664384 # Number of bytes read from this memory +system.physmem.bytes_read::total 10664384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 516608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 516608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 166631 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166631 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 182033722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 182033722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8818144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8818144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 124590154 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 124590154 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 124590154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 182033722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 306623876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166631 # Number of read requests accepted +system.physmem.writeReqs 114048 # Number of write requests accepted +system.physmem.readBursts 166631 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10663872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10664384 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10467 # Per bank write bursts -system.physmem.perBankRdBursts::1 10513 # Per bank write bursts +system.physmem.perBankRdBursts::0 10466 # Per bank write bursts +system.physmem.perBankRdBursts::1 10512 # Per bank write bursts system.physmem.perBankRdBursts::2 10315 # Per bank write bursts -system.physmem.perBankRdBursts::3 10094 # Per bank write bursts +system.physmem.perBankRdBursts::3 10093 # Per bank write bursts system.physmem.perBankRdBursts::4 10429 # Per bank write bursts system.physmem.perBankRdBursts::5 10431 # Per bank write bursts system.physmem.perBankRdBursts::6 9849 # Per bank write bursts -system.physmem.perBankRdBursts::7 10303 # Per bank write bursts +system.physmem.perBankRdBursts::7 10302 # Per bank write bursts system.physmem.perBankRdBursts::8 10595 # Per bank write bursts system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10600 # Per bank write bursts +system.physmem.perBankRdBursts::10 10598 # Per bank write bursts system.physmem.perBankRdBursts::11 10258 # Per bank write bursts system.physmem.perBankRdBursts::12 10302 # Per bank write bursts system.physmem.perBankRdBursts::13 10653 # Per bank write bursts -system.physmem.perBankRdBursts::14 10529 # Per bank write bursts +system.physmem.perBankRdBursts::14 10528 # Per bank write bursts system.physmem.perBankRdBursts::15 10648 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6999 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::5 7176 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7094 # Per bank write bursts -system.physmem.perBankWrBursts::8 7220 # Per bank write bursts +system.physmem.perBankWrBursts::7 7084 # Per bank write bursts +system.physmem.perBankWrBursts::8 7223 # Per bank write bursts system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7094 # Per bank write bursts +system.physmem.perBankWrBursts::10 7096 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6965 # Per bank write bursts +system.physmem.perBankWrBursts::12 6966 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts -system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58648216500 # Total gap between requests +system.physmem.totGap 58584634500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166636 # Read request sizes (log2) +system.physmem.readPktSize::6 166631 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114049 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1583 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114048 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165000 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1595 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7043 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -189,115 +189,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.476881 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.680943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.305827 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19373 35.65% 35.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11674 21.48% 57.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5602 10.31% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3597 6.62% 74.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2712 4.99% 79.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2058 3.79% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1657 3.05% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1528 2.81% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6148 11.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 54549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.259345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.795576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.998077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19535 35.81% 35.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11763 21.56% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5616 10.30% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3566 6.54% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2684 4.92% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2055 3.77% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1672 3.07% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1540 2.82% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6118 11.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54549 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 7016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.748575 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.190330 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7015 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.746152 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.264922 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7014 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 7016 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 7016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.251995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.236052 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.756108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6236 88.88% 88.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.21% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 602 8.58% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 126 1.80% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 27 0.38% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.250998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.234711 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.764594 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6252 89.11% 89.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 8 0.11% 89.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 591 8.42% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 125 1.78% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 23 0.33% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8 0.11% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 5 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 7016 # Writes before turning the bus around for reads -system.physmem.totQLat 2009240500 # Total ticks spent queuing -system.physmem.totMemAccLat 5133553000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12058.10 # Average queueing delay per DRAM burst +system.physmem.totQLat 1948128750 # Total ticks spent queuing +system.physmem.totMemAccLat 5072310000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11691.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30808.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 181.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 124.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 181.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 124.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30441.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 182.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 124.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 182.03 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 124.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.39 # Data bus utilization in percentage +system.physmem.busUtil 2.40 # Data bus utilization in percentage system.physmem.busUtilRead 1.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.97 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing -system.physmem.readRowHits 144828 # Number of row buffer hits during reads -system.physmem.writeRowHits 81470 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.92 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.43 # Row buffer hit rate for writes -system.physmem.avgGap 208946.74 # Average gap between requests -system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 32158270750 # Time in different power states -system.physmem.memoryStateTime::REF 1958320000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24529718750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 198298800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 212481360 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 108198750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 115937250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 642673200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 656838000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 367811280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 370960560 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3830473920 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3830473920 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 12291718545 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 12736700730 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 24405568500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 24015233250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 41844742995 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 41938625070 # Total energy per rank (pJ) -system.physmem.averagePower::0 713.510412 # Core power per rank (mW) -system.physmem.averagePower::1 715.111230 # Core power per rank (mW) -system.cpu.branchPred.lookups 14678284 # Number of BP lookups -system.cpu.branchPred.condPredicted 9497966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 389718 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9980180 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6390464 # Number of BTB hits +system.physmem.avgWrQLen 24.07 # Average write queue length when enqueuing +system.physmem.readRowHits 144841 # Number of row buffer hits during reads +system.physmem.writeRowHits 81248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.24 # Row buffer hit rate for writes +system.physmem.avgGap 208724.68 # Average gap between requests +system.physmem.pageHitRate 80.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199077480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108623625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 642681000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367791840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12184332255 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24462392250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41791303890 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.356895 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40549753500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16078529000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 213282720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116374500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 656908200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371038320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12703202685 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24007242750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41894454615 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.117627 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 39789307500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16838471250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 14678313 # Number of BP lookups +system.cpu.branchPred.condPredicted 9498021 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 389703 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9975544 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6390264 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.031551 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1709614 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85893 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.059303 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1709596 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85905 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20567325 # DTB read hits -system.cpu.dtb.read_misses 96876 # DTB read misses +system.cpu.dtb.read_hits 20567455 # DTB read hits +system.cpu.dtb.read_misses 96888 # DTB read misses system.cpu.dtb.read_acv 11 # DTB read access violations -system.cpu.dtb.read_accesses 20664201 # DTB read accesses -system.cpu.dtb.write_hits 14665780 # DTB write hits -system.cpu.dtb.write_misses 9406 # DTB write misses +system.cpu.dtb.read_accesses 20664343 # DTB read accesses +system.cpu.dtb.write_hits 14665775 # DTB write hits +system.cpu.dtb.write_misses 9411 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 14675186 # DTB write accesses -system.cpu.dtb.data_hits 35233105 # DTB hits -system.cpu.dtb.data_misses 106282 # DTB misses +system.cpu.dtb.data_hits 35233230 # DTB hits +system.cpu.dtb.data_misses 106299 # DTB misses system.cpu.dtb.data_acv 11 # DTB access violations -system.cpu.dtb.data_accesses 35339387 # DTB accesses -system.cpu.itb.fetch_hits 25627874 # ITB hits -system.cpu.itb.fetch_misses 5262 # ITB misses +system.cpu.dtb.data_accesses 35339529 # DTB accesses +system.cpu.itb.fetch_hits 25627333 # ITB hits +system.cpu.itb.fetch_misses 5261 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25633136 # ITB accesses +system.cpu.itb.fetch_accesses 25632594 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -311,81 +318,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 117296487 # number of cpu cycles simulated +system.cpu.numCycles 117169323 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1098513 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1098705 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.326312 # CPI: cycles per instruction -system.cpu.ipc 0.753970 # IPC: instructions per cycle -system.cpu.tickCycles 91572461 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25724026 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200783 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.549742 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616444 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204879 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.960430 # Average number of references to valid blocks. +system.cpu.cpi 1.324874 # CPI: cycles per instruction +system.cpu.ipc 0.754789 # IPC: instructions per cycle +system.cpu.tickCycles 91571156 # Number of cycles that the object actually ticked +system.cpu.idleCycles 25598167 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200776 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.523211 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616515 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204872 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.966550 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.549742 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994031 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994031 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.523211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.994024 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994024 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 740 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 745 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3298 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176773 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176773 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 20283132 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20283132 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 14333312 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333312 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 34616444 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616444 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 34616444 # number of overall hits -system.cpu.dcache.overall_hits::total 34616444 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 89438 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89438 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 280065 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280065 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 369503 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369503 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 369503 # number of overall misses -system.cpu.dcache.overall_misses::total 369503 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4420798500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4420798500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20106086500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20106086500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 24526885000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24526885000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 24526885000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24526885000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 20372570 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70176892 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176892 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20283193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20283193 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 14333322 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333322 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 34616515 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616515 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 34616515 # number of overall hits +system.cpu.dcache.overall_hits::total 34616515 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 89440 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89440 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 280055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280055 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 369495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 369495 # number of overall misses +system.cpu.dcache.overall_misses::total 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miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10124642750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10124642750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10124642750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.164634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.164634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461959 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.461959 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461959 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.461959 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60114.370629 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60114.370629 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60936.981403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60936.981403 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 217169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 217168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 217149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 217148 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143561 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 890005 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9974400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33873600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578290 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 889959 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9973376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33872128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 529276 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 529253 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 529276 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 529253 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 529276 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 433184000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 529253 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 433172500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 235328991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 235311991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343212750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35754 # Transaction distribution -system.membus.trans_dist::ReadResp 35754 # Transaction distribution -system.membus.trans_dist::Writeback 114049 # Transaction distribution +system.membus.trans_dist::ReadReq 35749 # Transaction distribution +system.membus.trans_dist::ReadResp 35749 # Transaction distribution +system.membus.trans_dist::Writeback 114048 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447321 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447321 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17963840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447310 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17963456 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280685 # Request fanout histogram +system.membus.snoop_fanout::samples 280679 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280685 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280679 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280685 # Request fanout histogram -system.membus.reqLayer0.occupancy 1304586000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 280679 # Request fanout histogram +system.membus.reqLayer0.occupancy 1304618000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602413250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1602414250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f3059ec0c..6d3efb0ae 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022330 # Number of seconds simulated -sim_ticks 22329989500 # Number of ticks simulated -final_tick 22329989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022282 # Number of seconds simulated +sim_ticks 22281815500 # Number of ticks simulated +final_tick 22281815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240121 # Simulator instruction rate (inst/s) -host_op_rate 240121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67367468 # Simulator tick rate (ticks/s) -host_mem_usage 247512 # Number of bytes of host memory used -host_seconds 331.47 # Real time elapsed on the host +host_inst_rate 227860 # Simulator instruction rate (inst/s) +host_op_rate 227860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63789654 # Simulator tick rate (ticks/s) +host_mem_usage 305428 # Number of bytes of host memory used +host_seconds 349.30 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10151616 # Number of bytes read from this memory -system.physmem.bytes_read::total 10639040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296896 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158619 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166235 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114014 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21828223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 454618037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 476446261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21828223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21828223 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 326775613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 326775613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 326775613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21828223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 454618037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 803221873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166235 # Number of read requests accepted -system.physmem.writeReqs 114014 # Number of write requests accepted -system.physmem.readBursts 166235 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114014 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10638592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10639040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7296896 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 487168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10151488 # Number of bytes read from this memory +system.physmem.bytes_read::total 10638656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 487168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 487168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296384 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158617 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166229 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114006 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114006 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21863928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455595192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 477459119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21863928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21863928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 327459134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 327459134 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 327459134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21863928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455595192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 804918253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166229 # Number of read requests accepted +system.physmem.writeReqs 114006 # Number of write requests accepted +system.physmem.readBursts 166229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114006 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294656 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10638656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7296384 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10441 # Per bank write bursts -system.physmem.perBankRdBursts::1 10459 # Per bank write bursts +system.physmem.perBankRdBursts::0 10438 # Per bank write bursts +system.physmem.perBankRdBursts::1 10454 # Per bank write bursts system.physmem.perBankRdBursts::2 10317 # Per bank write bursts system.physmem.perBankRdBursts::3 10059 # Per bank write bursts -system.physmem.perBankRdBursts::4 10419 # Per bank write bursts -system.physmem.perBankRdBursts::5 10394 # Per bank write bursts -system.physmem.perBankRdBursts::6 9840 # Per bank write bursts -system.physmem.perBankRdBursts::7 10309 # Per bank write bursts -system.physmem.perBankRdBursts::8 10592 # Per bank write bursts -system.physmem.perBankRdBursts::9 10641 # Per bank write bursts -system.physmem.perBankRdBursts::10 10546 # Per bank write bursts -system.physmem.perBankRdBursts::11 10221 # Per bank write bursts -system.physmem.perBankRdBursts::12 10273 # Per bank write bursts -system.physmem.perBankRdBursts::13 10617 # Per bank write bursts -system.physmem.perBankRdBursts::14 10480 # Per bank write bursts -system.physmem.perBankRdBursts::15 10620 # Per bank write bursts -system.physmem.perBankWrBursts::0 7082 # Per bank write bursts -system.physmem.perBankWrBursts::1 7259 # Per bank write bursts -system.physmem.perBankWrBursts::2 7256 # Per bank write bursts +system.physmem.perBankRdBursts::4 10417 # Per bank write bursts +system.physmem.perBankRdBursts::5 10393 # Per bank write bursts +system.physmem.perBankRdBursts::6 9837 # Per bank write bursts +system.physmem.perBankRdBursts::7 10310 # Per bank write bursts +system.physmem.perBankRdBursts::8 10606 # Per bank write bursts +system.physmem.perBankRdBursts::9 10643 # Per bank write bursts +system.physmem.perBankRdBursts::10 10543 # Per bank write bursts +system.physmem.perBankRdBursts::11 10224 # Per bank write bursts +system.physmem.perBankRdBursts::12 10268 # Per bank write bursts +system.physmem.perBankRdBursts::13 10616 # Per bank write bursts +system.physmem.perBankRdBursts::14 10478 # Per bank write bursts +system.physmem.perBankRdBursts::15 10618 # Per bank write bursts +system.physmem.perBankWrBursts::0 7083 # Per bank write bursts +system.physmem.perBankWrBursts::1 7253 # Per bank write bursts +system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7168 # Per bank write bursts -system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7079 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts -system.physmem.perBankWrBursts::9 6942 # Per bank write bursts -system.physmem.perBankWrBursts::10 7083 # Per bank write bursts -system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::5 7169 # Per bank write bursts +system.physmem.perBankWrBursts::6 6770 # Per bank write bursts +system.physmem.perBankWrBursts::7 7085 # Per bank write bursts +system.physmem.perBankWrBursts::8 7220 # Per bank write bursts +system.physmem.perBankWrBursts::9 6943 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6988 # Per bank write bursts +system.physmem.perBankWrBursts::12 6964 # Per bank write bursts system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts +system.physmem.perBankWrBursts::14 7283 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22329955500 # Total gap between requests +system.physmem.totGap 22281781500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166235 # Read request sizes (log2) +system.physmem.readPktSize::6 166229 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114014 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 53757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114006 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,142 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 51907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.459688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.593638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 345.239241 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18141 34.95% 34.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10684 20.58% 55.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5599 10.79% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2999 5.78% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2733 5.27% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1724 3.32% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1780 3.43% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1211 2.33% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7036 13.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 51907 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6971 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.843208 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.237754 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6969 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.580755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.430431 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.457165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18353 35.17% 35.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10742 20.58% 55.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5641 10.81% 66.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3092 5.92% 72.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2629 5.04% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1694 3.25% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1790 3.43% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1288 2.47% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6960 13.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52189 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6966 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.861757 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.246517 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6964 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6971 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6971 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.350882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.321302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.052955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6113 87.69% 87.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 29 0.42% 88.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 435 6.24% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 209 3.00% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 90 1.29% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 57 0.82% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 19 0.27% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 5 0.07% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 4 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6971 # Writes before turning the bus around for reads -system.physmem.totQLat 5659900500 # Total ticks spent queuing -system.physmem.totMemAccLat 8776675500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34049.02 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6966 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.363676 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.332802 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.079402 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6068 87.12% 87.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.43% 87.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 495 7.11% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 185 2.66% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 91 1.31% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.66% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.30% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.14% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6965 # Writes before turning the bus around for reads +system.physmem.totQLat 5436579750 # Total ticks spent queuing +system.physmem.totMemAccLat 8553223500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32706.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52799.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 476.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 326.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 476.45 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 326.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51456.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 477.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 327.38 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 477.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 327.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.72 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.55 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing -system.physmem.readRowHits 146045 # Number of row buffer hits during reads -system.physmem.writeRowHits 82245 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.14 # Row buffer hit rate for writes -system.physmem.avgGap 79678.98 # Average gap between requests -system.physmem.pageHitRate 81.46 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 9562649000 # Time in different power states -system.physmem.memoryStateTime::REF 745420000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 12015383500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 189642600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 202358520 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 103475625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 110413875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 641035200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 654732000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 367578000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 370610640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1458041520 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1458041520 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 6640293375 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 6800916240 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 7569244500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 7428347250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 16969310820 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 17025420045 # Total energy per rank (pJ) -system.physmem.averagePower::0 760.156668 # Core power per rank (mW) -system.physmem.averagePower::1 762.670135 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 35446 # Transaction distribution -system.membus.trans_dist::ReadResp 35446 # Transaction distribution -system.membus.trans_dist::Writeback 114014 # Transaction distribution -system.membus.trans_dist::ReadExReq 130789 # Transaction distribution -system.membus.trans_dist::ReadExResp 130789 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446484 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17935936 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280249 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280249 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280249 # Request fanout histogram -system.membus.reqLayer0.occupancy 1235861000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1525180500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16618969 # Number of BP lookups -system.cpu.branchPred.condPredicted 10749423 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 361100 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10742405 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7368684 # Number of BTB hits +system.physmem.busUtil 6.29 # Data bus utilization in percentage +system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 146012 # Number of row buffer hits during reads +system.physmem.writeRowHits 81986 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes +system.physmem.avgGap 79511.06 # Average gap between requests +system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190496880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103941750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 641043000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367539120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6553751985 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7617131250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16928894145 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.936312 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12590169250 # Time in different power states +system.physmem_0.memoryStateTime::REF 743860000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8942711000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 203779800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111189375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370694880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6762785805 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7433764500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 16992123720 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.774895 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12284853000 # Time in different power states +system.physmem_1.memoryStateTime::REF 743860000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9248437000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 16624924 # Number of BP lookups +system.cpu.branchPred.condPredicted 10755300 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 362268 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10924107 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7374828 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.594360 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1994688 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3025 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 67.509665 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1991560 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2903 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22640578 # DTB read hits -system.cpu.dtb.read_misses 225727 # DTB read misses -system.cpu.dtb.read_acv 15 # DTB read access violations -system.cpu.dtb.read_accesses 22866305 # DTB read accesses -system.cpu.dtb.write_hits 15860065 # DTB write hits -system.cpu.dtb.write_misses 44717 # DTB write misses -system.cpu.dtb.write_acv 7 # DTB write access violations -system.cpu.dtb.write_accesses 15904782 # DTB write accesses -system.cpu.dtb.data_hits 38500643 # DTB hits -system.cpu.dtb.data_misses 270444 # DTB misses -system.cpu.dtb.data_acv 22 # DTB access violations -system.cpu.dtb.data_accesses 38771087 # DTB accesses -system.cpu.itb.fetch_hits 13913295 # ITB hits -system.cpu.itb.fetch_misses 31383 # ITB misses +system.cpu.dtb.read_hits 22639897 # DTB read hits +system.cpu.dtb.read_misses 226363 # DTB read misses +system.cpu.dtb.read_acv 23 # DTB read access violations +system.cpu.dtb.read_accesses 22866260 # DTB read accesses +system.cpu.dtb.write_hits 15870343 # DTB write hits +system.cpu.dtb.write_misses 44837 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15915180 # DTB write accesses +system.cpu.dtb.data_hits 38510240 # DTB hits +system.cpu.dtb.data_misses 271200 # DTB misses +system.cpu.dtb.data_acv 24 # DTB access violations +system.cpu.dtb.data_accesses 38781440 # DTB accesses +system.cpu.itb.fetch_hits 13919462 # ITB hits +system.cpu.itb.fetch_misses 31654 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13944678 # ITB accesses +system.cpu.itb.fetch_accesses 13951116 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -342,141 +324,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44659983 # number of cpu cycles simulated +system.cpu.numCycles 44563634 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15776454 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106093576 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16618969 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9363372 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27339445 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 961528 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 166 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5126 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 335016 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13913295 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 207298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15791560 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106158478 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16624924 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9366388 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27217966 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 963396 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 137 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337279 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13919462 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206375 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43937055 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.414672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.131710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43833697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.421846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.133787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24208191 55.10% 55.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538198 3.50% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1405905 3.20% 61.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1524697 3.47% 65.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4231594 9.63% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1847884 4.21% 79.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 684699 1.56% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1071609 2.44% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7424278 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24095007 54.97% 54.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1538131 3.51% 58.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1406372 3.21% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1524721 3.48% 65.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4235690 9.66% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1846144 4.21% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685371 1.56% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070354 2.44% 83.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7431907 16.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43937055 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372122 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.375585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15090542 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9411892 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18462094 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 590748 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 381779 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3738870 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100752 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103984898 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 316746 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 381779 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15474298 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6446400 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97317 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18646914 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2890347 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102848317 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4603 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 150963 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 325598 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2361182 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61896036 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124089387 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123759844 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 329542 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43833697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.373060 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.382177 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15105656 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9282610 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18470395 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 592044 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 382992 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3741910 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100605 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104048931 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 315835 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 382992 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15490766 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6387964 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 95966 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18655378 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2820631 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102900646 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4493 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 152365 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 320462 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2296242 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61929819 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124171537 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123841536 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 330000 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9349155 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5813 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5869 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2465054 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23265818 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16448253 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1251433 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 545590 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91286622 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5695 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89090659 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79052 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11213817 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4716109 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1112 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43937055 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.027688 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.246728 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9382938 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5791 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5849 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2464589 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23265416 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16459353 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1262626 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 544604 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91320451 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5681 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89124415 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 80151 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11242959 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4725710 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1098 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43833697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.033240 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.247678 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17318675 39.42% 39.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5798510 13.20% 52.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5098508 11.60% 64.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4414835 10.05% 74.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4342383 9.88% 84.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2650303 6.03% 90.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1951252 4.44% 94.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1378643 3.14% 97.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 983946 2.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17209661 39.26% 39.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5800175 13.23% 52.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5098270 11.63% 64.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4410681 10.06% 74.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4347575 9.92% 84.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649961 6.05% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1950790 4.45% 94.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1381860 3.15% 97.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 984724 2.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43937055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43833697 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243742 9.63% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1177038 46.48% 56.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1111319 43.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 244354 9.65% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1175209 46.41% 56.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1112799 43.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49642313 55.72% 55.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44169 0.05% 55.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49663354 55.72% 55.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44187 0.05% 55.77% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122147 0.14% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121699 0.14% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39048 0.04% 56.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 122171 0.14% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 55.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121874 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39065 0.04% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued @@ -498,84 +480,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23057514 25.88% 81.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16063627 18.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23057459 25.87% 81.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16076160 18.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89090659 # Type of FU issued -system.cpu.iq.rate 1.994865 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2532099 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224114042 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102090455 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87155295 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 615482 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 436927 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 301089 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91314862 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307896 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1660010 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89124415 # Type of FU issued +system.cpu.iq.rate 1.999936 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2532362 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028414 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224079080 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102152200 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87178162 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615960 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 437940 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 301333 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91348643 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 308134 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1658507 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2989180 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6359 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21743 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1834876 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2988778 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6943 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21591 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1845976 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2985 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 325715 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3051 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 325532 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 381779 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1212086 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4898049 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100815278 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 146031 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23265818 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16448253 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5611 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3372 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4875472 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21743 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 149411 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 157245 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 306656 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88317091 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22866843 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 773568 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 382992 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1216204 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4841557 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100851766 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 147146 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23265416 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16459353 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5598 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3356 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4819285 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21591 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 151679 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 156559 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 308238 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88344034 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22866899 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 780381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9522961 # number of nop insts executed -system.cpu.iew.exec_refs 38771937 # number of memory reference insts executed -system.cpu.iew.exec_branches 15172750 # Number of branches executed -system.cpu.iew.exec_stores 15905094 # Number of stores executed -system.cpu.iew.exec_rate 1.977544 # Inst execution rate -system.cpu.iew.wb_sent 87870804 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87456384 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33898733 # num instructions producing a value -system.cpu.iew.wb_consumers 44340261 # num instructions consuming a value +system.cpu.iew.exec_nop 9525634 # number of nop insts executed +system.cpu.iew.exec_refs 38782381 # number of memory reference insts executed +system.cpu.iew.exec_branches 15172546 # Number of branches executed +system.cpu.iew.exec_stores 15915482 # Number of stores executed +system.cpu.iew.exec_rate 1.982424 # Inst execution rate +system.cpu.iew.wb_sent 87895909 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87479495 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33899568 # num instructions producing a value +system.cpu.iew.wb_consumers 44349597 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.958272 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764514 # average fanout of values written-back +system.cpu.iew.wb_rate 1.963024 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764372 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9275726 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9308985 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 262115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42571128 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.075131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.882631 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 263562 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42463328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.080399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.884681 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21025343 49.39% 49.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6328820 14.87% 64.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2946361 6.92% 71.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1760662 4.14% 75.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1654958 3.89% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1139679 2.68% 81.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1203795 2.83% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795933 1.87% 86.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5715577 13.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20917493 49.26% 49.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6333939 14.92% 64.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2944595 6.93% 71.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1757333 4.14% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1653620 3.89% 79.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1138333 2.68% 81.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1205391 2.84% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 793939 1.87% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5718685 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42571128 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42463328 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -621,238 +603,344 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5715577 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5718685 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133154607 # The number of ROB reads -system.cpu.rob.rob_writes 196602232 # The number of ROB writes -system.cpu.timesIdled 47762 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 722928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133076958 # The number of ROB reads +system.cpu.rob.rob_writes 196673244 # The number of ROB writes +system.cpu.timesIdled 48172 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 729937 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.561113 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561113 # CPI: Total CPI of All Threads -system.cpu.ipc 1.782172 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.782172 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116877675 # number of integer regfile reads -system.cpu.int_regfile_writes 57921110 # number of integer regfile writes -system.cpu.fp_regfile_reads 255696 # number of floating regfile reads -system.cpu.fp_regfile_writes 241715 # number of floating regfile writes -system.cpu.misc_regfile_reads 38130 # number of misc regfile reads +system.cpu.cpi 0.559903 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.559903 # CPI: Total CPI of All Threads +system.cpu.ipc 1.786025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.786025 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116925772 # number of integer regfile reads +system.cpu.int_regfile_writes 57936362 # number of integer regfile writes +system.cpu.fp_regfile_reads 255891 # number of floating regfile reads +system.cpu.fp_regfile_writes 241873 # number of floating regfile writes +system.cpu.misc_regfile_reads 38152 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 157630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157629 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143405 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143405 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191099 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579901 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 771000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6115136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23962624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30077760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 469974 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 469974 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 469974 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 403921992 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 144682208 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 321839246 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 93501 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.858110 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13804656 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 95549 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 144.477242 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18832337250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.858110 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936942 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936942 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201381 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.852002 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34090259 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205477 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.907907 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4071.852002 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994104 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994104 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2773 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 71020605 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71020605 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20525911 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20525911 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13564288 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13564288 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34090199 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34090199 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34090199 # number of overall hits +system.cpu.dcache.overall_hits::total 34090199 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 268215 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 268215 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1049089 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1049089 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1317304 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1317304 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1317304 # number of overall misses +system.cpu.dcache.overall_misses::total 1317304 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16911598996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16911598996 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85714857886 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85714857886 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102626456882 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102626456882 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102626456882 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102626456882 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20794126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20794126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35407503 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35407503 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35407503 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35407503 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012899 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012899 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071790 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071790 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016393 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037204 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63052.398248 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63052.398248 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81704.086008 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81704.086008 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77906.433809 # average overall miss latency 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number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206147 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 206147 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905681 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 905681 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1111828 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1111828 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1111828 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1111828 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62068 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62068 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143408 # number of WriteReq MSHR misses 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latency -system.cpu.icache.overall_avg_miss_latency::total 18482.779552 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27934642 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27934642 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13810732 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13810732 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13810732 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13810732 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13810732 # number of overall hits +system.cpu.icache.overall_hits::total 13810732 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 108728 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 108728 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 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13919460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13919460 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13919460 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13919460 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13919460 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007811 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007811 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007811 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007811 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007811 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007811 # miss rate for overall accesses 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of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 95723 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 95723 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 95723 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 95723 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 95723 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1546277535 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1546277535 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1546277535 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1546277535 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1546277535 # number of overall MSHR miss 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of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472609250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13760659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14233268250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448386 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.224621 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.551892 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.551892 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62079.239459 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81423.230327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77268.226448 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87888.326057 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87888.326057 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201389 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.903515 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34089462 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205485 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.897569 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.903515 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994117 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994117 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2789 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1230 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71018847 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71018847 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20525187 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20525187 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13564218 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13564218 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34089405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34089405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34089405 # number of overall hits -system.cpu.dcache.overall_hits::total 34089405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268059 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1049159 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1049159 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1317218 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1317218 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1317218 # number of overall misses -system.cpu.dcache.overall_misses::total 1317218 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17086669746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17086669746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 86915323054 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 86915323054 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104001992800 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104001992800 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104001992800 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104001992800 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20793246 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20793246 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35406623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35406623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35406623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35406623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012892 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071794 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071794 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017241 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017241 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037203 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037203 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63742.197598 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63742.197598 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82842.851326 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82842.851326 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78955.793802 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78955.793802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78955.793802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78955.793802 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6406656 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146327 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.783143 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168931 # number of writebacks -system.cpu.dcache.writebacks::total 168931 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205979 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205979 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905755 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 905755 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1111734 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1111734 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1111734 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1111734 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62080 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62080 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143404 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143404 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205484 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205484 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205484 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205484 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3049561754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3049561754 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13566762195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13566762195 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16616323949 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16616323949 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16616323949 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16616323949 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002986 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002986 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017241 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017241 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005804 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005804 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005804 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49123.095264 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49123.095264 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94605.186710 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94605.186710 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80864.320088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80864.320088 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 157790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157789 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191445 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579874 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 771319 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6126208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23961408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30087616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 470120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 470120 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 470120 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403980000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 144944965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 321950247 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 35442 # Transaction distribution +system.membus.trans_dist::ReadResp 35442 # Transaction distribution +system.membus.trans_dist::Writeback 114006 # Transaction distribution +system.membus.trans_dist::ReadExReq 130787 # Transaction distribution +system.membus.trans_dist::ReadExResp 130787 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17935040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 280235 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 280235 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 280235 # Request fanout histogram +system.membus.reqLayer0.occupancy 1235714000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1525262750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c949b9a6e..e5a2f02e5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057847 # Number of seconds simulated -sim_ticks 57847312000 # Number of ticks simulated -final_tick 57847312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057816 # Number of seconds simulated +sim_ticks 57815555000 # Number of ticks simulated +final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186854 # Simulator instruction rate (inst/s) -host_op_rate 238959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152421830 # Simulator tick rate (ticks/s) -host_mem_usage 261476 # Number of bytes of host memory used -host_seconds 379.52 # Real time elapsed on the host +host_inst_rate 199176 # Simulator instruction rate (inst/s) +host_op_rate 254717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162383906 # Simulator tick rate (ticks/s) +host_mem_usage 320240 # Number of bytes of host memory used +host_seconds 356.04 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8247680 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 8247808 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 128870 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 142576720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142576720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92880098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92880098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92880098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 142576720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235456818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128870 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 142657249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 142657249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128872 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128870 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247680 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::0 8159 # Per bank write bursts system.physmem.perBankRdBursts::1 8375 # Per bank write bursts system.physmem.perBankRdBursts::2 8229 # Per bank write bursts system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8319 # Per bank write bursts +system.physmem.perBankRdBursts::4 8320 # Per bank write bursts system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8089 # Per bank write bursts +system.physmem.perBankRdBursts::6 8088 # Per bank write bursts system.physmem.perBankRdBursts::7 7970 # Per bank write bursts system.physmem.perBankRdBursts::8 8071 # Per bank write bursts -system.physmem.perBankRdBursts::9 7641 # Per bank write bursts -system.physmem.perBankRdBursts::10 7819 # Per bank write bursts +system.physmem.perBankRdBursts::9 7640 # Per bank write bursts +system.physmem.perBankRdBursts::10 7820 # Per bank write bursts system.physmem.perBankRdBursts::11 7830 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts system.physmem.perBankRdBursts::14 7977 # Per bank write bursts system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5181 # Per bank write bursts +system.physmem.perBankWrBursts::0 5183 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5198 # Per bank write bursts -system.physmem.perBankWrBursts::7 5047 # Per bank write bursts +system.physmem.perBankWrBursts::6 5194 # Per bank write bursts +system.physmem.perBankWrBursts::7 5048 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::9 5086 # Per bank write bursts +system.physmem.perBankWrBursts::10 5252 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts @@ -78,14 +78,14 @@ system.physmem.perBankWrBursts::14 5451 # Pe system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57847280000 # Total gap between requests +system.physmem.totGap 57815523000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128870 # Read request sizes (log2) +system.physmem.readPktSize::6 128872 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,7 +95,7 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 83951 # Write request sizes (log2) system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -189,97 +189,110 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.780687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.561409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.824723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12139 31.63% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8088 21.07% 52.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4086 10.65% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2872 7.48% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2530 6.59% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1664 4.34% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1273 3.32% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1227 3.20% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4500 11.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38379 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.981187 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 361.178240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.276377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.259366 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.777117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4528 87.82% 87.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 480 9.31% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 121 2.35% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 14 0.27% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads -system.physmem.totQLat 1539171500 # Total ticks spent queuing -system.physmem.totMemAccLat 3955390250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11944.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 1505377000 # Total ticks spent queuing +system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30694.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.88 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.84 # Data bus utilization in percentage system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing -system.physmem.readRowHits 112176 # Number of row buffer hits during reads -system.physmem.writeRowHits 62224 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes -system.physmem.avgGap 271811.90 # Average gap between requests -system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 32236826000 # Time in different power states -system.physmem.memoryStateTime::REF 1931540000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23675959000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 151237800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 138899880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 82520625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 75788625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 512678400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 492078600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 272322000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 271486080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3778092240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3778092240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 11712850200 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 11277598770 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 24432156750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 24813956250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 40941858015 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 40847900445 # Total energy per rank (pJ) -system.physmem.averagePower::0 707.794027 # Core power per rank (mW) -system.physmem.averagePower::1 706.169709 # Core power per rank (mW) -system.cpu.branchPred.lookups 14825675 # Number of BP lookups -system.cpu.branchPred.condPredicted 9917897 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 395023 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9456669 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6745546 # Number of BTB hits +system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing +system.physmem.readRowHits 112203 # Number of row buffer hits during reads +system.physmem.writeRowHits 62134 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes +system.physmem.avgGap 271660.13 # Average gap between requests +system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.837327 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.292941 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 14822198 # Number of BP lookups +system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.331100 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719567 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -301,6 +314,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -322,6 +343,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -343,6 +372,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -365,89 +402,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115694624 # number of cpu cycles simulated +system.cpu.numCycles 115631110 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1146301 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.631452 # CPI: cycles per instruction -system.cpu.ipc 0.612951 # IPC: instructions per cycle -system.cpu.tickCycles 96938261 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18756363 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156422 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.596798 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42665450 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160518 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.798540 # Average number of references to valid blocks. +system.cpu.cpi 1.630556 # CPI: cycles per instruction +system.cpu.ipc 0.613288 # IPC: instructions per cycle +system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156428 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.596798 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993310 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993310 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.581764 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 750 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86015580 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86015580 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 22989734 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22989734 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19643878 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643878 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 22989229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 19643835 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 42633612 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42633612 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 42633612 # number of overall hits -system.cpu.dcache.overall_hits::total 42633612 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 56058 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56058 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 206023 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206023 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 262081 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262081 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 262081 # number of overall misses -system.cpu.dcache.overall_misses::total 262081 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2156088187 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2156088187 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15241867750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15241867750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17397955937 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17397955937 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17397955937 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17397955937 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 23045792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23045792 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 42633064 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 42633064 # number of overall hits +system.cpu.dcache.overall_hits::total 42633064 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 56065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 206066 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 262131 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 262131 # number of overall misses +system.cpu.dcache.overall_misses::total 262131 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2147242437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15196521000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 17343763437 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 17343763437 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42895693 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42895693 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42895693 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42895693 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002432 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002432 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010379 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010379 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38461.739395 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38461.739395 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73981.389214 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73981.389214 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66383.888710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66383.888710 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 42895195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42895195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002433 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.006111 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.006111 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38299.160564 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73745.892093 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,32 +493,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128433 # number of writebacks -system.cpu.dcache.writebacks::total 128433 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2574 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2574 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 98989 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 98989 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 101563 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101563 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 101563 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101563 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53484 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53484 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107034 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 160518 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160518 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 160518 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160518 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1995361313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1995361313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7633992250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7633992250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9629353563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9629353563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9629353563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9629353563 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks +system.cpu.dcache.writebacks::total 128441 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2577 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99030 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number 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misses +system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1987609313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7609976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9597585313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9597585313 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses @@ -490,68 +527,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37307.630562 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37307.630562 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71323.058561 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71323.058561 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59989.244589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59989.244589 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37159.910877 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71097.350424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59789.098907 # average overall mshr miss latency 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# number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001781 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001781 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001781 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001781 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001781 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001781 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20061.653287 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20061.653287 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20061.653287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 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# number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44746 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44746 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44746 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44746 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44746 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44746 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 806263262 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 806263262 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 806263262 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 806263262 # number of demand (read+write) MSHR miss cycles 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demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17989.145020 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95732 # number of replacements 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7479393750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9466694250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9466694250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9466694250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9466694250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 98230 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 98230 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128433 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128433 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq 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miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 98213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 98213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128441 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128441 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107036 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107036 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 205249 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205249 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 205249 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205249 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271502 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.271502 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955576 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955576 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628242 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.628242 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628242 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.628242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74182.027002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74182.027002 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72890.908380 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,52 +710,52 @@ system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26590 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26590 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26592 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 128871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 128871 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128871 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1644904750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1644904750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6188348750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6188348750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7833253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7833253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7833253500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7833253500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270691 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270691 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627831 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627831 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 128873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 128873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128873 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1635105500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1635105500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6164329000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6164329000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7799434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7799434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7799434500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7799434500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270758 # mshr miss rate for ReadReq accesses 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449469 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 538960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2863680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21356544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128441 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107036 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107036 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89449 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449489 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 538938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2862336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18493760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21356096 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333697 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333690 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -727,41 +764,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 333697 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333697 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295281500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68080238 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268447937 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26589 # Transaction distribution -system.membus.trans_dist::ReadResp 26589 # Transaction distribution +system.membus.trans_dist::ReadReq 26591 # Transaction distribution +system.membus.trans_dist::ReadResp 26591 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution system.membus.trans_dist::ReadExReq 102281 # Transaction distribution system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212821 # Request fanout histogram +system.membus.snoop_fanout::samples 212823 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212821 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212821 # Request fanout histogram -system.membus.reqLayer0.occupancy 929388500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 212823 # Request fanout histogram +system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1213397000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index d04d5cf1b..6394c9beb 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.032615 # Number of seconds simulated -sim_ticks 32615215000 # Number of ticks simulated -final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033020 # Number of seconds simulated +sim_ticks 33019504000 # Number of ticks simulated +final_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125661 # Simulator instruction rate (inst/s) -host_op_rate 160706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57800178 # Simulator tick rate (ticks/s) -host_mem_usage 335740 # Number of bytes of host memory used -host_seconds 564.28 # Real time elapsed on the host +host_inst_rate 123822 # Simulator instruction rate (inst/s) +host_op_rate 158353 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57659893 # Simulator tick rate (ticks/s) +host_mem_usage 322352 # Number of bytes of host memory used +host_seconds 572.66 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory -system.physmem.bytes_read::total 9977536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory -system.physmem.bytes_written::total 6303424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory -system.physmem.num_reads::total 155899 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 98491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 155899 # Number of read requests accepted -system.physmem.writeReqs 98491 # Number of write requests accepted -system.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory +system.physmem.bytes_read::total 9307712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory +system.physmem.bytes_written::total 6262016 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145433 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97844 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145433 # Number of read requests accepted +system.physmem.writeReqs 97844 # Number of write requests accepted +system.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10106 # Per bank write bursts -system.physmem.perBankRdBursts::1 10077 # Per bank write bursts -system.physmem.perBankRdBursts::2 9750 # Per bank write bursts -system.physmem.perBankRdBursts::3 10345 # Per bank write bursts -system.physmem.perBankRdBursts::4 10619 # Per bank write bursts -system.physmem.perBankRdBursts::5 10733 # Per bank write bursts -system.physmem.perBankRdBursts::6 9548 # Per bank write bursts -system.physmem.perBankRdBursts::7 9567 # Per bank write bursts -system.physmem.perBankRdBursts::8 9971 # Per bank write bursts -system.physmem.perBankRdBursts::9 9445 # Per bank write bursts -system.physmem.perBankRdBursts::10 9639 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 8930 # Per bank write bursts -system.physmem.perBankRdBursts::13 9084 # Per bank write bursts -system.physmem.perBankRdBursts::14 9062 # Per bank write bursts -system.physmem.perBankRdBursts::15 9408 # Per bank write bursts -system.physmem.perBankWrBursts::0 6017 # Per bank write bursts -system.physmem.perBankWrBursts::1 6275 # Per bank write bursts -system.physmem.perBankWrBursts::2 6171 # Per bank write bursts -system.physmem.perBankWrBursts::3 6231 # Per bank write bursts -system.physmem.perBankWrBursts::4 6142 # Per bank write bursts -system.physmem.perBankWrBursts::5 6389 # Per bank write bursts -system.physmem.perBankWrBursts::6 6054 # Per bank write bursts -system.physmem.perBankWrBursts::7 6025 # Per bank write bursts -system.physmem.perBankWrBursts::8 6057 # Per bank write bursts -system.physmem.perBankWrBursts::9 6227 # Per bank write bursts -system.physmem.perBankWrBursts::10 6350 # Per bank write bursts -system.physmem.perBankWrBursts::11 5949 # Per bank write bursts -system.physmem.perBankWrBursts::12 6129 # Per bank write bursts -system.physmem.perBankWrBursts::13 6148 # Per bank write bursts -system.physmem.perBankWrBursts::14 6212 # Per bank write bursts -system.physmem.perBankWrBursts::15 6088 # Per bank write bursts +system.physmem.perBankRdBursts::0 9146 # Per bank write bursts +system.physmem.perBankRdBursts::1 9381 # Per bank write bursts +system.physmem.perBankRdBursts::2 9349 # Per bank write bursts +system.physmem.perBankRdBursts::3 9489 # Per bank write bursts +system.physmem.perBankRdBursts::4 9691 # Per bank write bursts +system.physmem.perBankRdBursts::5 9742 # Per bank write bursts +system.physmem.perBankRdBursts::6 9065 # Per bank write bursts +system.physmem.perBankRdBursts::7 9033 # Per bank write bursts +system.physmem.perBankRdBursts::8 9160 # Per bank write bursts +system.physmem.perBankRdBursts::9 8585 # Per bank write bursts +system.physmem.perBankRdBursts::10 8818 # Per bank write bursts +system.physmem.perBankRdBursts::11 8754 # Per bank write bursts +system.physmem.perBankRdBursts::12 8666 # Per bank write bursts +system.physmem.perBankRdBursts::13 8713 # Per bank write bursts +system.physmem.perBankRdBursts::14 8726 # Per bank write bursts +system.physmem.perBankRdBursts::15 9002 # Per bank write bursts +system.physmem.perBankWrBursts::0 5993 # Per bank write bursts +system.physmem.perBankWrBursts::1 6194 # Per bank write bursts +system.physmem.perBankWrBursts::2 6159 # Per bank write bursts +system.physmem.perBankWrBursts::3 6198 # Per bank write bursts +system.physmem.perBankWrBursts::4 6133 # Per bank write bursts +system.physmem.perBankWrBursts::5 6325 # Per bank write bursts +system.physmem.perBankWrBursts::6 6074 # Per bank write bursts +system.physmem.perBankWrBursts::7 6046 # Per bank write bursts +system.physmem.perBankWrBursts::8 6012 # Per bank write bursts +system.physmem.perBankWrBursts::9 6139 # Per bank write bursts +system.physmem.perBankWrBursts::10 6243 # Per bank write bursts +system.physmem.perBankWrBursts::11 5934 # Per bank write bursts +system.physmem.perBankWrBursts::12 6049 # Per bank write bursts +system.physmem.perBankWrBursts::13 6103 # Per bank write bursts +system.physmem.perBankWrBursts::14 6164 # Per bank write bursts +system.physmem.perBankWrBursts::15 6052 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32615126500 # Total gap between requests +system.physmem.totGap 33019298500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155899 # Read request sizes (log2) +system.physmem.readPktSize::6 145433 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 98491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97844 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -197,125 +197,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads -system.physmem.totQLat 7435933847 # Total ticks spent queuing -system.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 778800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads +system.physmem.totQLat 7598607995 # Total ticks spent queuing +system.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 726600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.90 # Data bus utilization in percentage -system.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing -system.physmem.readRowHits 126861 # Number of row buffer hits during reads -system.physmem.writeRowHits 35985 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes -system.physmem.avgGap 128209.15 # Average gap between requests -system.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states -system.physmem.memoryStateTime::REF 1088880000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 352167480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 337674960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 192154875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 184247250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 628633200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 584321400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 319101120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 318206880 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 2129849280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 2129849280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 12060126405 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 11622718665 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 8986386750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 9370077750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 24668419110 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 24547096185 # Total energy per rank (pJ) -system.physmem.averagePower::0 756.489386 # Core power per rank (mW) -system.physmem.averagePower::1 752.768859 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 149976 # Transaction distribution -system.membus.trans_dist::ReadResp 149976 # Transaction distribution -system.membus.trans_dist::Writeback 98491 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 5923 # Transaction distribution -system.membus.trans_dist::ReadExResp 5923 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 254396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254396 # Request fanout histogram -system.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.4 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 17209876 # Number of BP lookups -system.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675638 # Number of BTB hits +system.physmem.busUtil 3.68 # Data bus utilization in percentage +system.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 118226 # Number of row buffer hits during reads +system.physmem.writeRowHits 36119 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes +system.physmem.avgGap 135727.17 # Average gap between requests +system.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.509165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states +system.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ) +system.physmem_1.averagePower 748.955517 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states +system.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 17204705 # Number of BP lookups +system.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7673903 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -358,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -379,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -401,131 +411,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 65230431 # number of cpu cycles simulated +system.cpu.numCycles 66039009 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322461 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31532227 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32193664 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31530881 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32193949 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18671 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18665 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued @@ -551,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94860274 # Type of FU issued -system.cpu.iq.rate 1.454233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 94858951 # Type of FU issued +system.cpu.iq.rate 1.436408 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9866 # number of nop insts executed -system.cpu.iew.exec_refs 44709300 # number of memory reference insts executed -system.cpu.iew.exec_branches 14252629 # Number of branches executed -system.cpu.iew.exec_stores 20981511 # Number of stores executed -system.cpu.iew.exec_rate 1.440176 # Inst execution rate -system.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93464426 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44933898 # num instructions producing a value -system.cpu.iew.wb_consumers 76510027 # num instructions consuming a value +system.cpu.iew.exec_nop 9863 # number of nop insts executed +system.cpu.iew.exec_refs 44710370 # number of memory reference insts executed +system.cpu.iew.exec_branches 14251746 # Number of branches executed +system.cpu.iew.exec_stores 20982459 # Number of stores executed +system.cpu.iew.exec_rate 1.422528 # Inst execution rate +system.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93463063 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44927637 # num instructions producing a value +system.cpu.iew.wb_consumers 76497349 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.432835 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back +system.cpu.iew.wb_rate 1.415271 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 706597 1.10% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 586126 0.91% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3803876 5.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64238392 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -674,506 +684,528 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction -system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3803876 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 157213253 # The number of ROB reads -system.cpu.rob.rob_writes 195483388 # The number of ROB writes -system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 157616533 # The number of ROB reads +system.cpu.rob.rob_writes 195472136 # The number of ROB writes +system.cpu.timesIdled 23660 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 744970 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.919935 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads -system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102236524 # number of integer regfile reads -system.cpu.int_regfile_writes 56794814 # number of integer regfile writes +system.cpu.cpi 0.931339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.931339 # CPI: Total CPI of All Threads +system.cpu.ipc 1.073723 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.073723 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102238235 # number of integer regfile reads +system.cpu.int_regfile_writes 56792997 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346002142 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804540 # number of cc regfile writes -system.cpu.misc_regfile_reads 44207937 # number of misc regfile reads +system.cpu.cc_regfile_reads 345997909 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804494 # number of cc regfile writes +system.cpu.misc_regfile_reads 44208348 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 261186 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 323466 # number of replacements -system.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323978 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.239069 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1054590000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.438944 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996951 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996951 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485280 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.769602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40441610 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485792 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.248818 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 148406000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.769602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 84635072 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84635072 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21513403 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21513403 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18834640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18834640 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 62245 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 62245 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40348043 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40348043 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40410288 # number of overall hits +system.cpu.dcache.overall_hits::total 40410288 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 550665 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 550665 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1015261 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1015261 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 66581 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 66581 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1565926 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1565926 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1632507 # number of overall misses +system.cpu.dcache.overall_misses::total 1632507 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8659099753 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8659099753 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14372727937 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14372727937 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4891750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4891750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23031827690 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23031827690 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23031827690 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23031827690 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 41913969 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41913969 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42042795 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42042795 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024958 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.024958 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051147 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051147 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037360 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037360 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038830 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038830 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15724.805014 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15724.805014 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14156.682801 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14156.682801 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8942.870201 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8942.870201 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14708.120109 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14708.120109 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14108.256620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14108.256620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2883834 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 127457 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.625937 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 264417 # number of writebacks +system.cpu.dcache.writebacks::total 264417 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 250985 # number of ReadReq MSHR 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replacements +system.cpu.icache.tags.tagsinuse 510.284584 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22426703 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323380 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.350928 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1086653000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.284584 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996650 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996650 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id 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-system.cpu.icache.overall_avg_miss_latency::total 8629.273549 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 97738 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12080 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8.090894 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 45841045 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45841045 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22426703 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22426703 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22426703 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22426703 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22426703 # number of overall hits +system.cpu.icache.overall_hits::total 22426703 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 332124 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 332124 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 332124 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 332124 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 332124 # number of overall misses +system.cpu.icache.overall_misses::total 332124 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3299467842 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3299467842 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3299467842 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3299467842 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3299467842 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3299467842 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22758827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22758827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22758827 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22758827 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22758827 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22758827 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014593 # miss rate for ReadReq accesses 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latency +system.cpu.icache.blocked_cycles::no_mshrs 226617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 46 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14091 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.082393 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7645 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7645 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7645 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7645 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7645 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7645 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323989 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323989 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323989 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323989 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323989 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323989 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325660123 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2325660123 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7178.207047 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7178.207047 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8733 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8733 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8733 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8733 # number of demand (read+write) MSHR hits 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(read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2699093031 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2699093031 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2699093031 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014209 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014209 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8346.221852 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8346.221852 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 3266027 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 304781 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2719229 # number of hwpf that were already in the cache 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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2641163503 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2800231003 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159067500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2641163503 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15016026778 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.090752 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.049420 # mshr miss rate for ReadReq accesses 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(read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3411923962 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 569300762 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2842623200 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14808082489 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092170 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060976 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.039835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.039835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.047662 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059964 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.293549 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 76807.098020 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73361.555900 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73579.913798 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61348.605998 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66866.002028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66866.002028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72550.483276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63167.394888 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199118 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61887.244483 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74114.210894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71321.930066 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 101210.121999 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65413.264199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65413.264199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70318.500484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 485318 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.841997 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40443714 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485830 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.246638 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 139928000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.841997 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997738 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997738 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84640426 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84640426 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21515343 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21515343 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834765 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834765 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 62288 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 62288 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15377 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15377 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40350108 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40350108 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40412396 # number of overall hits -system.cpu.dcache.overall_hits::total 40412396 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 551365 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 551365 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1015136 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1015136 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 66556 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 66556 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 549 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 549 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1566501 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1566501 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1633057 # number of overall misses -system.cpu.dcache.overall_misses::total 1633057 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8548612161 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8548612161 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13150540915 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13150540915 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5021750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5021750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21699153076 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21699153076 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21699153076 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21699153076 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22066708 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22066708 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41916609 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41916609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42045453 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42045453 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024986 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024986 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051141 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051141 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516563 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.516563 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034472 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034472 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037372 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037372 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038840 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038840 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15504.451971 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15504.451971 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12954.462176 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12954.462176 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9147.085610 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9147.085610 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13851.988014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13851.988014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13287.443779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13287.443779 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2567726 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 127351 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.214286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20.162590 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 256573 # number of writebacks -system.cpu.dcache.writebacks::total 256573 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 251643 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 251643 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866615 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866615 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 549 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 549 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118258 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118258 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118258 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 169293 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 137181 # Transaction distribution +system.membus.trans_dist::ReadResp 137181 # Transaction distribution +system.membus.trans_dist::Writeback 97844 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 8252 # Transaction distribution +system.membus.trans_dist::ReadExResp 8252 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 243283 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 243283 # Request fanout histogram +system.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index b1db16392..23c0d1c87 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011000 # Number of ticks simulated final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264072 # Simulator instruction rate (inst/s) -host_op_rate 337712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182321320 # Simulator tick rate (ticks/s) -host_mem_usage 304496 # Number of bytes of host memory used -host_seconds 268.54 # Real time elapsed on the host +host_inst_rate 1376675 # Simulator instruction rate (inst/s) +host_op_rate 1760576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 950486092 # Simulator tick rate (ticks/s) +host_mem_usage 308184 # Number of bytes of host memory used +host_seconds 51.51 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1606621596 # Wr system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 100925135 # Transaction distribution -system.membus.trans_dist::ReadResp 100941054 # Transaction distribution -system.membus.trans_dist::WriteReq 19849901 # Transaction distribution -system.membus.trans_dist::WriteResp 19849901 # Transaction distribution -system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution -system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930618 # Request fanout histogram -system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 120930618 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction +system.membus.trans_dist::ReadReq 100925135 # Transaction distribution +system.membus.trans_dist::ReadResp 100941054 # Transaction distribution +system.membus.trans_dist::WriteReq 19849901 # Transaction distribution +system.membus.trans_dist::WriteResp 19849901 # Transaction distribution +system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution +system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 120930618 # Request fanout histogram +system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 120930618 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index baa7e0631..938385651 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.127294 # Nu sim_ticks 127293983000 # Number of ticks simulated final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 949441 # Simulator instruction rate (inst/s) -host_op_rate 1212170 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1717378261 # Simulator tick rate (ticks/s) -host_mem_usage 313972 # Number of bytes of host memory used -host_seconds 74.12 # Real time elapsed on the host +host_inst_rate 894668 # Simulator instruction rate (inst/s) +host_op_rate 1142240 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618302823 # Simulator tick rate (ticks/s) +host_mem_usage 317432 # Number of bytes of host memory used +host_seconds 78.66 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 42187194 # To system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 25532 # Transaction distribution -system.membus.trans_dist::ReadResp 25532 # Transaction distribution -system.membus.trans_dist::Writeback 83909 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214631 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214631 # Request fanout histogram -system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,143 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits +system.cpu.dcache.overall_hits::total 42576328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses +system.cpu.dcache.overall_misses::total 177384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks +system.cpu.dcache.writebacks::total 128239 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. @@ -439,143 +584,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits -system.cpu.dcache.overall_hits::total 42576328 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses -system.cpu.dcache.overall_misses::total 177384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks -system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution @@ -609,5 +617,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 28362000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 25532 # Transaction distribution +system.membus.trans_dist::ReadResp 25532 # Transaction distribution +system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214631 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214631 # Request fanout histogram +system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 38d19f012..e7cd333d6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.200149 # Number of seconds simulated -sim_ticks 1200148658000 # Number of ticks simulated -final_tick 1200148658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.199774 # Number of seconds simulated +sim_ticks 1199774280000 # Number of ticks simulated +final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 401299 # Simulator instruction rate (inst/s) -host_op_rate 401299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263701147 # Simulator tick rate (ticks/s) -host_mem_usage 236908 # Number of bytes of host memory used -host_seconds 4551.17 # Real time elapsed on the host +host_inst_rate 344306 # Simulator instruction rate (inst/s) +host_op_rate 344306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226179780 # Simulator tick rate (ticks/s) +host_mem_usage 294788 # Number of bytes of host memory used +host_seconds 5304.52 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 125506304 # Number of bytes read from this memory -system.physmem.bytes_read::total 125506304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 125505984 # Number of bytes read from this memory +system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1961036 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1961031 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 104575632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 104575632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54299513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54299513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54299513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 104575632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 158875145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961036 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 104607997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961031 # Number of read requests accepted system.physmem.writeReqs 1018242 # Number of write requests accepted -system.physmem.readBursts 1961036 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1961031 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125423936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82368 # Total number of bytes read from write queue -system.physmem.bytesWritten 65165888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125506304 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 125423808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82176 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166208 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125505984 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1287 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1284 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118759 # Per bank write bursts -system.physmem.perBankRdBursts::1 114099 # Per bank write bursts -system.physmem.perBankRdBursts::2 116224 # Per bank write bursts -system.physmem.perBankRdBursts::3 117761 # Per bank write bursts -system.physmem.perBankRdBursts::4 117826 # Per bank write bursts -system.physmem.perBankRdBursts::5 117519 # Per bank write bursts -system.physmem.perBankRdBursts::6 119878 # Per bank write bursts -system.physmem.perBankRdBursts::7 124524 # Per bank write bursts -system.physmem.perBankRdBursts::8 126972 # Per bank write bursts -system.physmem.perBankRdBursts::9 130092 # Per bank write bursts -system.physmem.perBankRdBursts::10 128660 # Per bank write bursts -system.physmem.perBankRdBursts::11 130342 # Per bank write bursts +system.physmem.perBankRdBursts::0 118757 # Per bank write bursts +system.physmem.perBankRdBursts::1 114096 # Per bank write bursts +system.physmem.perBankRdBursts::2 116226 # Per bank write bursts +system.physmem.perBankRdBursts::3 117770 # Per bank write bursts +system.physmem.perBankRdBursts::4 117824 # Per bank write bursts +system.physmem.perBankRdBursts::5 117523 # Per bank write bursts +system.physmem.perBankRdBursts::6 119882 # Per bank write bursts +system.physmem.perBankRdBursts::7 124516 # Per bank write bursts +system.physmem.perBankRdBursts::8 126973 # Per bank write bursts +system.physmem.perBankRdBursts::9 130090 # Per bank write bursts +system.physmem.perBankRdBursts::10 128654 # Per bank write bursts +system.physmem.perBankRdBursts::11 130347 # Per bank write bursts system.physmem.perBankRdBursts::12 126055 # Per bank write bursts -system.physmem.perBankRdBursts::13 125250 # Per bank write bursts -system.physmem.perBankRdBursts::14 122599 # Per bank write bursts -system.physmem.perBankRdBursts::15 123189 # Per bank write bursts +system.physmem.perBankRdBursts::13 125249 # Per bank write bursts +system.physmem.perBankRdBursts::14 122591 # Per bank write bursts +system.physmem.perBankRdBursts::15 123194 # Per bank write bursts system.physmem.perBankWrBursts::0 61222 # Per bank write bursts -system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60565 # Per bank write bursts +system.physmem.perBankWrBursts::1 61485 # Per bank write bursts +system.physmem.perBankWrBursts::2 60564 # Per bank write bursts system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61662 # Per bank write bursts -system.physmem.perBankWrBursts::5 63103 # Per bank write bursts +system.physmem.perBankWrBursts::4 61658 # Per bank write bursts +system.physmem.perBankWrBursts::5 63101 # Per bank write bursts system.physmem.perBankWrBursts::6 64148 # Per bank write bursts -system.physmem.perBankWrBursts::7 65614 # Per bank write bursts -system.physmem.perBankWrBursts::8 65330 # Per bank write bursts -system.physmem.perBankWrBursts::9 65779 # Per bank write bursts -system.physmem.perBankWrBursts::10 65300 # Per bank write bursts -system.physmem.perBankWrBursts::11 65644 # Per bank write bursts -system.physmem.perBankWrBursts::12 64162 # Per bank write bursts -system.physmem.perBankWrBursts::13 64212 # Per bank write bursts -system.physmem.perBankWrBursts::14 64570 # Per bank write bursts -system.physmem.perBankWrBursts::15 64181 # Per bank write bursts +system.physmem.perBankWrBursts::7 65617 # Per bank write bursts +system.physmem.perBankWrBursts::8 65332 # Per bank write bursts +system.physmem.perBankWrBursts::9 65778 # Per bank write bursts +system.physmem.perBankWrBursts::10 65295 # Per bank write bursts +system.physmem.perBankWrBursts::11 65646 # Per bank write bursts +system.physmem.perBankWrBursts::12 64171 # Per bank write bursts +system.physmem.perBankWrBursts::13 64211 # Per bank write bursts +system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1200148547500 # Total gap between requests +system.physmem.totGap 1199774169500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961036 # Read request sizes (log2) +system.physmem.readPktSize::6 1961031 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1834284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125445 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,35 +140,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -189,128 +189,129 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1837714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.708116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.073776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.879385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1458610 79.37% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 262385 14.28% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49383 2.69% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20628 1.12% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12966 0.71% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7221 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5354 0.29% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4357 0.24% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16810 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1837714 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59460 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.957232 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.327917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59419 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1838370 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.671596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.054008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.842659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1459678 79.40% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 262161 14.26% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49287 2.68% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20645 1.12% 97.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12893 0.70% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7143 0.39% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5357 0.29% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4451 0.24% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16755 0.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1838370 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59429 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.975652 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.968947 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59388 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59460 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59460 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.124403 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.088362 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.116973 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27861 46.86% 46.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1344 2.26% 49.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 25901 43.56% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3838 6.45% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 438 0.74% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 56 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59460 # Writes before turning the bus around for reads -system.physmem.totQLat 37078229500 # Total ticks spent queuing -system.physmem.totMemAccLat 73823523250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18919.89 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59429 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.133420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.097680 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.110939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27565 46.38% 46.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1269 2.14% 48.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26249 44.17% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3908 6.58% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 362 0.61% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 56 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59429 # Writes before turning the bus around for reads +system.physmem.totQLat 36751953000 # Total ticks spent queuing +system.physmem.totMemAccLat 73497209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798735000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18753.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37669.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 104.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 104.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37503.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 104.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 104.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.24 # Data bus utilization in percentage system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 726316 # Number of row buffer hits during reads -system.physmem.writeRowHits 413927 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.65 # Row buffer hit rate for writes -system.physmem.avgGap 402832.01 # Average gap between requests -system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 393584177750 # Time in different power states -system.physmem.memoryStateTime::REF 40075360000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 766482185250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6742219680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7150867920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3678790500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3901763250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7383355200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7901907000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3233772720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3364273440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 78387404160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 78387404160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 410122352430 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 423496116225 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 360328576500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 348597204750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 869876471190 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 872799536745 # Total energy per rank (pJ) -system.physmem.averagePower::0 724.811465 # Core power per rank (mW) -system.physmem.averagePower::1 727.247065 # Core power per rank (mW) -system.cpu.branchPred.lookups 246247636 # Number of BP lookups -system.cpu.branchPred.condPredicted 186450048 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15699340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168260719 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165258168 # Number of BTB hits +system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing +system.physmem.readRowHits 726418 # Number of row buffer hits during reads +system.physmem.writeRowHits 413172 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.58 # Row buffer hit rate for writes +system.physmem.avgGap 402707.03 # Average gap between requests +system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6745500720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3680580750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383386400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 409753789290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 360427621500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 869587605780 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.796496 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 596865139750 # Time in different power states +system.physmem_0.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 562842538250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7152516000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3902662500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7901961600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364241040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 422708761260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 349063611000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 872456746680 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.187909 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 577877428500 # Time in different power states +system.physmem_1.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 581827655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 246222594 # Number of BP lookups +system.cpu.branchPred.condPredicted 186441188 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15682162 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167748253 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165224895 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.215537 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18428845 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104881 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.495747 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18427327 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104678 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452532318 # DTB read hits -system.cpu.dtb.read_misses 4979776 # DTB read misses +system.cpu.dtb.read_hits 452533853 # DTB read hits +system.cpu.dtb.read_misses 4979561 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457512094 # DTB read accesses -system.cpu.dtb.write_hits 161379130 # DTB write hits -system.cpu.dtb.write_misses 1710165 # DTB write misses +system.cpu.dtb.read_accesses 457513414 # DTB read accesses +system.cpu.dtb.write_hits 161377742 # DTB write hits +system.cpu.dtb.write_misses 1710117 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163089295 # DTB write accesses -system.cpu.dtb.data_hits 613911448 # DTB hits -system.cpu.dtb.data_misses 6689941 # DTB misses +system.cpu.dtb.write_accesses 163087859 # DTB write accesses +system.cpu.dtb.data_hits 613911595 # DTB hits +system.cpu.dtb.data_misses 6689678 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601389 # DTB accesses -system.cpu.itb.fetch_hits 598579568 # ITB hits +system.cpu.dtb.data_accesses 620601273 # DTB accesses +system.cpu.itb.fetch_hits 598493672 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598579587 # ITB accesses +system.cpu.itb.fetch_accesses 598493691 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,66 +325,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2400297316 # number of cpu cycles simulated +system.cpu.numCycles 2399548560 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52410829 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52395177 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.314239 # CPI: cycles per instruction -system.cpu.ipc 0.760897 # IPC: instructions per cycle -system.cpu.tickCycles 2077436531 # Number of cycles that the object actually ticked -system.cpu.idleCycles 322860785 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121980 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.680046 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601827690 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126076 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945943 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16791074000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.680046 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996260 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996260 # Average percentage of cache occupancy +system.cpu.cpi 1.313829 # CPI: cycles per instruction +system.cpu.ipc 0.761134 # IPC: instructions per cycle +system.cpu.tickCycles 2077217503 # Number of cycles that the object actually ticked +system.cpu.idleCycles 322331057 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121997 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.675710 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601828569 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.675710 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.996259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1617 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1613 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2310 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231838176 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231838176 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 443337984 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443337984 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 158489706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158489706 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 601827690 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601827690 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 601827690 # number of overall hits -system.cpu.dcache.overall_hits::total 601827690 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 7289564 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289564 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238796 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238796 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 9528360 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9528360 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 9528360 # number of overall misses -system.cpu.dcache.overall_misses::total 9528360 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178244544500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 178244544500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101115441000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101115441000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 279359985500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 279359985500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 279359985500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 279359985500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 450627548 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450627548 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 443338834 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 158489735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 601828569 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 601828569 # number of overall hits +system.cpu.dcache.overall_hits::total 601828569 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 7289569 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2238767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 9528336 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 9528336 # number of overall misses +system.cpu.dcache.overall_misses::total 9528336 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 278998136500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 611356050 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 611356050 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356050 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 611356905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 611356905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013929 # miss rate for WriteReq accesses @@ -392,14 +393,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.015586 system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.015586 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24452.017226 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24452.017226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45165.098115 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45165.098115 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29318.789960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29318.789960 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29318.789960 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24423.897490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45095.559520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29280.887712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,32 +409,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700593 # number of writebacks -system.cpu.dcache.writebacks::total 3700593 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50804 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50804 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351480 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 351480 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 402284 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 402284 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 402284 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 402284 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238760 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238760 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887316 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126076 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126076 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126076 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126076 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162288114750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162288114750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76072677250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76072677250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238360792000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 238360792000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238360792000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 238360792000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks +system.cpu.dcache.writebacks::total 3700624 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50811 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 351432 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 402243 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 402243 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238758 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126093 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162083992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75948494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 238032486500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 238032486500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses @@ -442,66 +443,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014928 system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014928 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22419.325237 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22419.325237 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40307.334463 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40307.334463 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26118.650776 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26118.650776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26118.650776 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26118.650776 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22391.132844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40241.130748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26082.627747 # average overall mshr miss latency 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warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 751.335570 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366863 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366863 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1197160094 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1197160094 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 598578610 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 598578610 # number of ReadReq hits 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demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214859 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214859 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79821.314197 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80741.377895 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80187.011450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80187.011450 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -617,91 +618,91 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks system.cpu.l2cache.writebacks::total 1018242 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1181592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779444 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 779444 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961036 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961036 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79676806000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79676806000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53247448000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53247448000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132924254000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 132924254000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132924254000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 132924254000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412991 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67431.741244 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67431.741244 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68314.655062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68314.655062 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67782.668957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67782.668957 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779450 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961031 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961031 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961031 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79473588750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53122771000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 132596359750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700593 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887316 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887316 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954661 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820906816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820968128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887335 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952810 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820909888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820971264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827676 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827627 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827676 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114406500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827676 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114462000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1631750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1635250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14010883500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14011262000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181592 # Transaction distribution -system.membus.trans_dist::ReadResp 1181592 # Transaction distribution +system.membus.trans_dist::ReadReq 1181581 # Transaction distribution +system.membus.trans_dist::ReadResp 1181581 # Transaction distribution system.membus.trans_dist::Writeback 1018242 # Transaction distribution -system.membus.trans_dist::ReadExReq 779444 # Transaction distribution -system.membus.trans_dist::ReadExResp 779444 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940314 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940314 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673792 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 779450 # Transaction distribution +system.membus.trans_dist::ReadExResp 779450 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940304 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190673472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979278 # Request fanout histogram +system.membus.snoop_fanout::samples 2979273 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979278 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979273 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979278 # Request fanout histogram -system.membus.reqLayer0.occupancy 11833253000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2979273 # Request fanout histogram +system.membus.reqLayer0.occupancy 11833185000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18446066000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18446289250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 704344325..9b6ff7bd3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.662267 # Number of seconds simulated -sim_ticks 662266942000 # Number of ticks simulated -final_tick 662266942000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.662030 # Number of seconds simulated +sim_ticks 662030381000 # Number of ticks simulated +final_tick 662030381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189043 # Simulator instruction rate (inst/s) -host_op_rate 189043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72116099 # Simulator tick rate (ticks/s) -host_mem_usage 239436 # Number of bytes of host memory used -host_seconds 9183.34 # Real time elapsed on the host +host_inst_rate 173779 # Simulator instruction rate (inst/s) +host_op_rate 173779 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66269486 # Simulator tick rate (ticks/s) +host_mem_usage 296312 # Number of bytes of host memory used +host_seconds 9989.97 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 62272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125973696 # Number of bytes read from this memory -system.physmem.bytes_read::total 126035968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65304064 # Number of bytes written to this memory -system.physmem.bytes_written::total 65304064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968339 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020376 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020376 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190215890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190309919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94029 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94029 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98606861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98606861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98606861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190215890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 288916779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969312 # Number of read requests accepted -system.physmem.writeReqs 1020376 # Number of write requests accepted -system.physmem.readBursts 1969312 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020376 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125955072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80896 # Total number of bytes read from write queue -system.physmem.bytesWritten 65302080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126035968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65304064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1264 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125964224 # Number of bytes read from this memory +system.physmem.bytes_read::total 126026048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65301568 # Number of bytes written to this memory +system.physmem.bytes_written::total 65301568 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968191 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020337 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020337 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 190269552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 190362937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98638325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98638325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98638325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 190269552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 289001263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969157 # Number of read requests accepted +system.physmem.writeReqs 1020337 # Number of write requests accepted +system.physmem.readBursts 1969157 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020337 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125945216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 80832 # Total number of bytes read from write queue +system.physmem.bytesWritten 65299584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126026048 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65301568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1263 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119151 # Per bank write bursts -system.physmem.perBankRdBursts::1 114520 # Per bank write bursts -system.physmem.perBankRdBursts::2 116626 # Per bank write bursts -system.physmem.perBankRdBursts::3 118169 # Per bank write bursts -system.physmem.perBankRdBursts::4 118249 # Per bank write bursts -system.physmem.perBankRdBursts::5 117904 # Per bank write bursts -system.physmem.perBankRdBursts::6 120341 # Per bank write bursts -system.physmem.perBankRdBursts::7 125053 # Per bank write bursts -system.physmem.perBankRdBursts::8 127649 # Per bank write bursts -system.physmem.perBankRdBursts::9 130602 # Per bank write bursts -system.physmem.perBankRdBursts::10 129289 # Per bank write bursts -system.physmem.perBankRdBursts::11 130962 # Per bank write bursts -system.physmem.perBankRdBursts::12 126769 # Per bank write bursts -system.physmem.perBankRdBursts::13 125905 # Per bank write bursts -system.physmem.perBankRdBursts::14 123070 # Per bank write bursts -system.physmem.perBankRdBursts::15 123789 # Per bank write bursts -system.physmem.perBankWrBursts::0 61320 # Per bank write bursts +system.physmem.perBankRdBursts::0 119107 # Per bank write bursts +system.physmem.perBankRdBursts::1 114513 # Per bank write bursts +system.physmem.perBankRdBursts::2 116588 # Per bank write bursts +system.physmem.perBankRdBursts::3 118130 # Per bank write bursts +system.physmem.perBankRdBursts::4 118281 # Per bank write bursts +system.physmem.perBankRdBursts::5 117894 # Per bank write bursts +system.physmem.perBankRdBursts::6 120372 # Per bank write bursts +system.physmem.perBankRdBursts::7 125027 # Per bank write bursts +system.physmem.perBankRdBursts::8 127642 # Per bank write bursts +system.physmem.perBankRdBursts::9 130604 # Per bank write bursts +system.physmem.perBankRdBursts::10 129295 # Per bank write bursts +system.physmem.perBankRdBursts::11 130929 # Per bank write bursts +system.physmem.perBankRdBursts::12 126770 # Per bank write bursts +system.physmem.perBankRdBursts::13 125862 # Per bank write bursts +system.physmem.perBankRdBursts::14 123081 # Per bank write bursts +system.physmem.perBankRdBursts::15 123799 # Per bank write bursts +system.physmem.perBankWrBursts::0 61289 # Per bank write bursts system.physmem.perBankWrBursts::1 61597 # Per bank write bursts -system.physmem.perBankWrBursts::2 60678 # Per bank write bursts -system.physmem.perBankWrBursts::3 61357 # Per bank write bursts -system.physmem.perBankWrBursts::4 61793 # Per bank write bursts -system.physmem.perBankWrBursts::5 63216 # Per bank write bursts -system.physmem.perBankWrBursts::6 64269 # Per bank write bursts -system.physmem.perBankWrBursts::7 65744 # Per bank write bursts -system.physmem.perBankWrBursts::8 65524 # Per bank write bursts -system.physmem.perBankWrBursts::9 65904 # Per bank write bursts -system.physmem.perBankWrBursts::10 65459 # Per bank write bursts -system.physmem.perBankWrBursts::11 65777 # Per bank write bursts -system.physmem.perBankWrBursts::12 64349 # Per bank write bursts -system.physmem.perBankWrBursts::13 64362 # Per bank write bursts -system.physmem.perBankWrBursts::14 64665 # Per bank write bursts -system.physmem.perBankWrBursts::15 64331 # Per bank write bursts +system.physmem.perBankWrBursts::2 60658 # Per bank write bursts +system.physmem.perBankWrBursts::3 61339 # Per bank write bursts +system.physmem.perBankWrBursts::4 61821 # Per bank write bursts +system.physmem.perBankWrBursts::5 63209 # Per bank write bursts +system.physmem.perBankWrBursts::6 64289 # Per bank write bursts +system.physmem.perBankWrBursts::7 65739 # Per bank write bursts +system.physmem.perBankWrBursts::8 65503 # Per bank write bursts +system.physmem.perBankWrBursts::9 65920 # Per bank write bursts +system.physmem.perBankWrBursts::10 65439 # Per bank write bursts +system.physmem.perBankWrBursts::11 65771 # Per bank write bursts +system.physmem.perBankWrBursts::12 64363 # Per bank write bursts +system.physmem.perBankWrBursts::13 64352 # Per bank write bursts +system.physmem.perBankWrBursts::14 64685 # Per bank write bursts +system.physmem.perBankWrBursts::15 64332 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 662266852500 # Total gap between requests +system.physmem.totGap 662030291500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969312 # Read request sizes (log2) +system.physmem.readPktSize::6 1969157 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020376 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020337 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 248303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 76115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,38 +144,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 63086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 64803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -193,151 +193,142 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1775882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.694867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.878503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.793796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1380775 77.75% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271356 15.28% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53913 3.04% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21326 1.20% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12854 0.72% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6480 0.36% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5132 0.29% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3787 0.21% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20259 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1775882 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59943 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.788466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.189780 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59903 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 15 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1776224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.667141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.863857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.742577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1381396 77.77% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271071 15.26% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53950 3.04% 96.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21226 1.20% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12955 0.73% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6597 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5003 0.28% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3759 0.21% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20267 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1776224 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59925 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.795728 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 163.660245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59887 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59943 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59943 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.021921 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.980571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.225631 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 33661 56.16% 56.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 25267 42.15% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 929 1.55% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 52 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59943 # Writes before turning the bus around for reads -system.physmem.totQLat 41251747750 # Total ticks spent queuing -system.physmem.totMemAccLat 78152647750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9840240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20960.74 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59925 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.026383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.985304 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.212732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31950 53.32% 53.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1595 2.66% 55.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20819 34.74% 90.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4577 7.64% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 750 1.25% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 154 0.26% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 27 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59925 # Writes before turning the bus around for reads +system.physmem.totQLat 40790268000 # Total ticks spent queuing +system.physmem.totMemAccLat 77688280500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9839470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20727.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39710.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39477.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 190.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 98.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 190.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 98.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.26 # Data bus utilization in percentage system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 795732 # Number of row buffer hits during reads -system.physmem.writeRowHits 416769 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.84 # Row buffer hit rate for writes -system.physmem.avgGap 221517.05 # Average gap between requests -system.physmem.pageHitRate 40.57 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 126335534000 # Time in different power states -system.physmem.memoryStateTime::REF 22114300000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 513810229000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 6510407400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 6915200040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3552305625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 3773174625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7409890800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 7939939800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3239831520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3372004080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 43255570800 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 43255570800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 299907401805 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 307252084365 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 134279187750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 127836483750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 498154595700 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 500344457460 # Total energy per rank (pJ) -system.physmem.averagePower::0 752.204234 # Core power per rank (mW) -system.physmem.averagePower::1 755.510885 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 1197969 # Transaction distribution -system.membus.trans_dist::ReadResp 1197969 # Transaction distribution -system.membus.trans_dist::Writeback 1020376 # Transaction distribution -system.membus.trans_dist::ReadExReq 771343 # Transaction distribution -system.membus.trans_dist::ReadExResp 771343 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4959000 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4959000 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191340032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191340032 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2989688 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2989688 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2989688 # Request fanout histogram -system.membus.reqLayer0.occupancy 11823557000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18423875500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 410506798 # Number of BP lookups -system.cpu.branchPred.condPredicted 318826270 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16270103 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 283363020 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279346814 # Number of BTB hits +system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing +system.physmem.readRowHits 795786 # Number of row buffer hits during reads +system.physmem.writeRowHits 416180 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.79 # Row buffer hit rate for writes +system.physmem.avgGap 221452.29 # Average gap between requests +system.physmem.pageHitRate 40.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6511261680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3552771750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7409259000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3239617680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 299928124440 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134120853750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 498002202300 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.239455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 221171423750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 418748256250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6916946400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3774127500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7939518600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3371965200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 306633623535 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128238837000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 500115332235 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.431368 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 211341940750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 428577885750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 410531758 # Number of BP lookups +system.cpu.branchPred.condPredicted 318847451 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16269165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 283137932 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279377578 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.582664 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26372853 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.671900 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26373623 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646169518 # DTB read hits -system.cpu.dtb.read_misses 12159492 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 658329010 # DTB read accesses -system.cpu.dtb.write_hits 218199205 # DTB write hits -system.cpu.dtb.write_misses 7515385 # DTB write misses +system.cpu.dtb.read_hits 646133385 # DTB read hits +system.cpu.dtb.read_misses 12154937 # DTB read misses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_accesses 658288322 # DTB read accesses +system.cpu.dtb.write_hits 218173916 # DTB write hits +system.cpu.dtb.write_misses 7514058 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225714590 # DTB write accesses -system.cpu.dtb.data_hits 864368723 # DTB hits -system.cpu.dtb.data_misses 19674877 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 884043600 # DTB accesses -system.cpu.itb.fetch_hits 422435766 # ITB hits -system.cpu.itb.fetch_misses 46 # ITB misses +system.cpu.dtb.write_accesses 225687974 # DTB write accesses +system.cpu.dtb.data_hits 864307301 # DTB hits +system.cpu.dtb.data_misses 19668995 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 883976296 # DTB accesses +system.cpu.itb.fetch_hits 422458110 # ITB hits +system.cpu.itb.fetch_misses 45 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422435812 # ITB accesses +system.cpu.itb.fetch_accesses 422458155 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,98 +342,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1324533885 # number of cpu cycles simulated +system.cpu.numCycles 1324060763 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433728129 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419447982 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410506798 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305719667 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 867740174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45999556 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1859 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 122 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422435766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8419815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1324470151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.157662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433748906 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3419441963 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410531758 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305751201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 867248304 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45995858 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1804 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422458110 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8422260 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1323997070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582666 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.157790 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 697483370 52.66% 52.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48005474 3.62% 56.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24395138 1.84% 58.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45249876 3.42% 61.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142980828 10.80% 72.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66219617 5.00% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43796288 3.31% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29613001 2.24% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226726559 17.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 696991073 52.64% 52.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48002120 3.63% 56.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24407254 1.84% 58.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45263157 3.42% 61.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142993214 10.80% 72.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66222276 5.00% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43788088 3.31% 80.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29616004 2.24% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226713884 17.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1324470151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309925 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.581624 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355594570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 385179518 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525809516 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34887563 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22998984 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62292881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264034617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2122 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22998984 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373946851 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 205483814 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7143 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538725666 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183307693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181027912 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1764061 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19006533 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140449897 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27939508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377346604 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126580900 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126409923 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 170976 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1323997070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310055 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.582542 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355597650 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 384696746 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525812607 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34892959 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22997108 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62293389 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 869 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264034948 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2192 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22997108 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373957968 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 205165673 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7731 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538730067 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183138523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181033284 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1755579 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18983042 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 140285341 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27927823 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377354751 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4126620289 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4126448707 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 171581 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001143641 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 182 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 180 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99171579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719206222 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272877842 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90853191 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58764648 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889718435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624030011 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1568714 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139278450 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505521247 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 134 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1324470151 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151140 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001151788 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 192 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 191 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99207749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719206023 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272877739 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90880933 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59162115 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2889782486 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 178 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624016708 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1570062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1139342915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 505618557 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 149 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1323997070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981890 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.151111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 520285766 39.28% 39.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169352294 12.79% 52.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158263377 11.95% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149147598 11.26% 75.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126214674 9.53% 84.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84460771 6.38% 91.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68224303 5.15% 96.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33971144 2.56% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14550224 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 519747645 39.26% 39.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169377682 12.79% 52.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158338012 11.96% 64.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149173722 11.27% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126185648 9.53% 84.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84437665 6.38% 91.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68199937 5.15% 96.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33982775 2.57% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14553984 1.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1324470151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1323997070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13169928 35.70% 35.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13171575 35.70% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available @@ -471,118 +462,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19111172 51.81% 87.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4608428 12.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19111155 51.80% 87.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4612971 12.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719281995 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719329788 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 125 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896550 0.03% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 159 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672977290 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230873835 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 895316 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 672939161 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230852080 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624030011 # Type of FU issued -system.cpu.iq.rate 1.981097 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36889528 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6609007948 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4027844088 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521909296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1980467 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1299263 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 893137 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659936163 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 983376 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69546745 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624016708 # Type of FU issued +system.cpu.iq.rate 1.981795 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36895701 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014061 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6608517036 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4027973051 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2521923586 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1979213 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1297888 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 892539 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2659929620 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 982789 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69543206 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274610559 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379781 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 148802 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112149340 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274610360 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379362 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 147727 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112149237 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6024507 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6023017 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22998984 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147954834 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18526434 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3040938881 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6690511 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719206222 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272877842 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 163 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 822212 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17973283 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 148802 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10902941 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8845995 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19748936 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578346915 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658329015 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45683096 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22997108 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 147758887 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18474565 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3040988458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6691344 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719206023 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272877739 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 178 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 822290 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17921565 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 147727 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10901488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8843129 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19744617 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578330269 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658288327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45686439 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151220283 # number of nop insts executed -system.cpu.iew.exec_refs 884043668 # number of memory reference insts executed -system.cpu.iew.exec_branches 315967801 # Number of branches executed -system.cpu.iew.exec_stores 225714653 # Number of stores executed -system.cpu.iew.exec_rate 1.946607 # Inst execution rate -system.cpu.iew.wb_sent 2552803336 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522802433 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489230488 # num instructions producing a value -system.cpu.iew.wb_consumers 1920481156 # num instructions consuming a value +system.cpu.iew.exec_nop 151205794 # number of nop insts executed +system.cpu.iew.exec_refs 883976375 # number of memory reference insts executed +system.cpu.iew.exec_branches 315983093 # Number of branches executed +system.cpu.iew.exec_stores 225688048 # Number of stores executed +system.cpu.iew.exec_rate 1.947290 # Inst execution rate +system.cpu.iew.wb_sent 2552817971 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2522816125 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489246506 # num instructions producing a value +system.cpu.iew.wb_consumers 1920479792 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904672 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775447 # average fanout of values written-back +system.cpu.iew.wb_rate 1.905363 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775455 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005079964 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005136223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16269309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1185591559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.534913 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558094 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16268344 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1185116972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.535528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.558449 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 696399330 58.74% 58.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159901902 13.49% 72.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79790439 6.73% 78.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52118707 4.40% 83.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28427889 2.40% 85.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19400301 1.64% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20045609 1.69% 89.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23104546 1.95% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106402836 8.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 695949152 58.72% 58.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159874809 13.49% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79784402 6.73% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52116706 4.40% 83.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28440614 2.40% 85.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19407125 1.64% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20027045 1.69% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23110908 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106406211 8.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1185591559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1185116972 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,233 +619,339 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106402836 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106406211 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3818269613 # The number of ROB reads -system.cpu.rob.rob_writes 5788733936 # The number of ROB writes -system.cpu.timesIdled 729 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3817847910 # The number of ROB reads +system.cpu.rob.rob_writes 5788846951 # The number of ROB writes +system.cpu.timesIdled 724 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 63693 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762961 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762961 # CPI: Total CPI of All Threads -system.cpu.ipc 1.310683 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.310683 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467602221 # number of integer regfile reads -system.cpu.int_regfile_writes 2022271322 # number of integer regfile writes -system.cpu.fp_regfile_reads 45596 # number of floating regfile reads -system.cpu.fp_regfile_writes 565 # number of floating regfile writes +system.cpu.cpi 0.762689 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762689 # CPI: Total CPI of All Threads +system.cpu.ipc 1.311151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.311151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3467581476 # number of integer regfile reads +system.cpu.int_regfile_writes 2022302956 # number of integer regfile writes +system.cpu.fp_regfile_reads 46080 # number of floating regfile reads +system.cpu.fp_regfile_writes 592 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 7335000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7335000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879134 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879134 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1946 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22169148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22171094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829183168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 829245440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12957100 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12957100 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12957100 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10221444363 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1621500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14117208750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 9209012 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.412521 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713854428 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9213108 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.482477 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.412521 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 751 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2935 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1472845170 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472845170 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558341279 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558341279 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155513145 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155513145 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 713854424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713854424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713854424 # number of overall hits +system.cpu.dcache.overall_hits::total 713854424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12746245 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12746245 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5215357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5215357 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 17961602 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17961602 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17961602 # number of overall misses +system.cpu.dcache.overall_misses::total 17961602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 384451562750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 384451562750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289305166008 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289305166008 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 673756728758 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 673756728758 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 673756728758 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 673756728758 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 731816026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731816026 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731816026 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731816026 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024544 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024544 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024544 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024544 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30161.946734 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30161.946734 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55471.785730 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55471.785730 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37510.948564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37510.948564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14120110 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8634302 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1055091 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67341 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.382836 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 128.217609 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3742780 # number of writebacks +system.cpu.dcache.writebacks::total 3742780 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412238 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5412238 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3336257 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3336257 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8748495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8748495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8748495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8748495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334007 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334007 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9213107 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9213107 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9213107 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9213107 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168659488250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168659488250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77208966781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77208966781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245868455031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245868455031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245868455031 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245868455031 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22996.908545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22996.908545 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41088.269268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41088.269268 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency 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437325.657350 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 772.533395 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 972 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844872503 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844872503 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422434249 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422434249 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422434249 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422434249 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422434249 # number of overall hits -system.cpu.icache.overall_hits::total 422434249 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1516 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1516 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1516 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1516 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1516 # number of overall misses -system.cpu.icache.overall_misses::total 1516 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 104441749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 104441749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 104441749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 104441749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 104441749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 104441749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422435765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422435765 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422435765 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422435765 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422435765 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422435765 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 770.158211 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376054 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376054 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 899 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 844917184 # Number of tag accesses +system.cpu.icache.tags.data_accesses 844917184 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422456585 # number of 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number of cycles access was blocked @@ -863,188 +960,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1020376 # number of writebacks -system.cpu.l2cache.writebacks::total 1020376 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196996 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1197969 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 771343 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 973 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83954773750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54083955498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54083955498 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58998750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137979730498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138038729248 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58998750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137979730498 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138038729248 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163211 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163322 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410478 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410478 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410452 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 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per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997904 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 748 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2938 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472907715 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472907715 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558369192 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558369192 # 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miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024546 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024546 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024546 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024546 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30253.272148 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30253.272148 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55516.215163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55516.215163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency 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ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334043 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879117 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879117 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213160 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9213160 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9213160 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9213160 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168998137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168998137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77338215218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77338215218 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 246336352218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 246336352218 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 246336352218 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 246336352218 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23042.970569 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23042.970569 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41156.679024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41156.679024 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26737.444288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26737.444288 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 7334962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7334962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742780 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879112 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879112 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22170928 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829176832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829238656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 12957003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12957003 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12957003 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221354853 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1610750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14117356000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1197871 # Transaction distribution +system.membus.trans_dist::ReadResp 1197871 # Transaction distribution +system.membus.trans_dist::Writeback 1020337 # Transaction distribution +system.membus.trans_dist::ReadExReq 771286 # Transaction distribution +system.membus.trans_dist::ReadExResp 771286 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4958651 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2989494 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989494 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2989494 # Request fanout histogram +system.membus.reqLayer0.occupancy 11823428000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 18423304250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index b905eb22a..1d6a1c5a9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.108945 # Number of seconds simulated -sim_ticks 1108944740000 # Number of ticks simulated -final_tick 1108944740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.108725 # Number of seconds simulated +sim_ticks 1108725388000 # Number of ticks simulated +final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239014 # Simulator instruction rate (inst/s) -host_op_rate 257501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171603826 # Simulator tick rate (ticks/s) -host_mem_usage 253696 # Number of bytes of host memory used -host_seconds 6462.24 # Real time elapsed on the host +host_inst_rate 243193 # Simulator instruction rate (inst/s) +host_op_rate 262004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174570169 # Simulator tick rate (ticks/s) +host_mem_usage 311428 # Number of bytes of host memory used +host_seconds 6351.17 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131625408 # Number of bytes read from this memory -system.physmem.bytes_read::total 131625408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 131558336 # Number of bytes read from this memory +system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66989632 # Number of bytes written to this memory -system.physmem.bytes_written::total 66989632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2056647 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2056647 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046713 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046713 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 118694289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 118694289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60408449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60408449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60408449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 118694289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 179102739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2056647 # Number of read requests accepted -system.physmem.writeReqs 1046713 # Number of write requests accepted -system.physmem.readBursts 2056647 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046713 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131542016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83392 # Total number of bytes read from write queue -system.physmem.bytesWritten 66988032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131625408 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66989632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1303 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory +system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2055599 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 118657277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055599 # Number of read requests accepted +system.physmem.writeReqs 1046417 # Number of write requests accepted +system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue +system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128036 # Per bank write bursts -system.physmem.perBankRdBursts::1 125234 # Per bank write bursts -system.physmem.perBankRdBursts::2 122300 # Per bank write bursts -system.physmem.perBankRdBursts::3 124230 # Per bank write bursts -system.physmem.perBankRdBursts::4 123415 # Per bank write bursts -system.physmem.perBankRdBursts::5 123345 # Per bank write bursts -system.physmem.perBankRdBursts::6 123964 # Per bank write bursts -system.physmem.perBankRdBursts::7 124409 # Per bank write bursts -system.physmem.perBankRdBursts::8 131872 # Per bank write bursts -system.physmem.perBankRdBursts::9 134140 # Per bank write bursts -system.physmem.perBankRdBursts::10 132473 # Per bank write bursts -system.physmem.perBankRdBursts::11 133756 # Per bank write bursts -system.physmem.perBankRdBursts::12 133901 # Per bank write bursts -system.physmem.perBankRdBursts::13 134102 # Per bank write bursts -system.physmem.perBankRdBursts::14 129958 # Per bank write bursts -system.physmem.perBankRdBursts::15 130209 # Per bank write bursts -system.physmem.perBankWrBursts::0 65849 # Per bank write bursts -system.physmem.perBankWrBursts::1 64131 # Per bank write bursts -system.physmem.perBankWrBursts::2 62381 # Per bank write bursts -system.physmem.perBankWrBursts::3 62840 # Per bank write bursts -system.physmem.perBankWrBursts::4 62871 # Per bank write bursts -system.physmem.perBankWrBursts::5 62990 # Per bank write bursts -system.physmem.perBankWrBursts::6 64312 # Per bank write bursts -system.physmem.perBankWrBursts::7 65310 # Per bank write bursts -system.physmem.perBankWrBursts::8 67027 # Per bank write bursts -system.physmem.perBankWrBursts::9 67624 # Per bank write bursts -system.physmem.perBankWrBursts::10 67292 # Per bank write bursts -system.physmem.perBankWrBursts::11 67645 # Per bank write bursts -system.physmem.perBankWrBursts::12 67063 # Per bank write bursts -system.physmem.perBankWrBursts::13 67560 # Per bank write bursts -system.physmem.perBankWrBursts::14 66200 # Per bank write bursts -system.physmem.perBankWrBursts::15 65593 # Per bank write bursts +system.physmem.perBankRdBursts::0 127971 # Per bank write bursts +system.physmem.perBankRdBursts::1 125115 # Per bank write bursts +system.physmem.perBankRdBursts::2 122192 # Per bank write bursts +system.physmem.perBankRdBursts::3 124223 # Per bank write bursts +system.physmem.perBankRdBursts::4 123351 # Per bank write bursts +system.physmem.perBankRdBursts::5 123340 # Per bank write bursts +system.physmem.perBankRdBursts::6 123758 # Per bank write bursts +system.physmem.perBankRdBursts::7 124120 # Per bank write bursts +system.physmem.perBankRdBursts::8 131994 # Per bank write bursts +system.physmem.perBankRdBursts::9 134060 # Per bank write bursts +system.physmem.perBankRdBursts::10 132574 # Per bank write bursts +system.physmem.perBankRdBursts::11 133683 # Per bank write bursts +system.physmem.perBankRdBursts::12 133864 # Per bank write bursts +system.physmem.perBankRdBursts::13 133891 # Per bank write bursts +system.physmem.perBankRdBursts::14 129793 # Per bank write bursts +system.physmem.perBankRdBursts::15 130326 # Per bank write bursts +system.physmem.perBankWrBursts::0 65785 # Per bank write bursts +system.physmem.perBankWrBursts::1 64106 # Per bank write bursts +system.physmem.perBankWrBursts::2 62369 # Per bank write bursts +system.physmem.perBankWrBursts::3 62872 # Per bank write bursts +system.physmem.perBankWrBursts::4 62855 # Per bank write bursts +system.physmem.perBankWrBursts::5 62943 # Per bank write bursts +system.physmem.perBankWrBursts::6 64256 # Per bank write bursts +system.physmem.perBankWrBursts::7 65177 # Per bank write bursts +system.physmem.perBankWrBursts::8 67064 # Per bank write bursts +system.physmem.perBankWrBursts::9 67603 # Per bank write bursts +system.physmem.perBankWrBursts::10 67361 # Per bank write bursts +system.physmem.perBankWrBursts::11 67637 # Per bank write bursts +system.physmem.perBankWrBursts::12 67067 # Per bank write bursts +system.physmem.perBankWrBursts::13 67487 # Per bank write bursts +system.physmem.perBankWrBursts::14 66154 # Per bank write bursts +system.physmem.perBankWrBursts::15 65656 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1108944651500 # Total gap between requests +system.physmem.totGap 1108725299500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2056647 # Read request sizes (log2) +system.physmem.readPktSize::6 2055599 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046713 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1923205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132121 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046417 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,28 +140,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -189,104 +189,114 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1918209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.496643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.775288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.095886 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1492147 77.79% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 306422 15.97% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52965 2.76% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21185 1.10% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13242 0.69% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7471 0.39% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5204 0.27% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3914 0.20% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15659 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1918209 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61025 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.632724 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.189303 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60982 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61025 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61025 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.151790 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.116821 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.097688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27581 45.20% 45.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1180 1.93% 47.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28172 46.16% 93.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3706 6.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 317 0.52% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 54 0.09% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61025 # Writes before turning the bus around for reads -system.physmem.totQLat 38537340500 # Total ticks spent queuing -system.physmem.totMemAccLat 77075040500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10276720000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18749.83 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads +system.physmem.totQLat 38268969000 # Total ticks spent queuing +system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37499.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 118.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 118.69 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.40 # Data bus utilization in percentage system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing -system.physmem.readRowHits 777039 # Number of row buffer hits during reads -system.physmem.writeRowHits 406774 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.86 # Row buffer hit rate for writes -system.physmem.avgGap 357336.77 # Average gap between requests +system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing +system.physmem.readRowHits 776845 # Number of row buffer hits during reads +system.physmem.writeRowHits 406412 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes +system.physmem.avgGap 357420.88 # Average gap between requests system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 313164826000 # Time in different power states -system.physmem.memoryStateTime::REF 37029980000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 758746776000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 7075638360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 7426006560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 3860715375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 4051888500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 7760165400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 8271151200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3309232320 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3473305920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 72430640880 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 72430640880 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 416866648005 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 425333204280 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 299692308000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 292265504250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 810995348340 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 813251701590 # Total energy per rank (pJ) -system.physmem.averagePower::0 731.323936 # Core power per rank (mW) -system.physmem.averagePower::1 733.358627 # Core power per rank (mW) -system.cpu.branchPred.lookups 240152510 # Number of BP lookups -system.cpu.branchPred.condPredicted 186756179 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14598640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131763268 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122287171 # Number of BTB hits +system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.249224 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.347080 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 240158127 # Number of BP lookups +system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.808241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15660181 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -308,6 +318,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -329,6 +347,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -350,6 +376,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -372,90 +406,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2217889480 # number of cpu cycles simulated +system.cpu.numCycles 2217450776 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40077128 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435933 # CPI: cycles per instruction -system.cpu.ipc 0.696411 # IPC: instructions per cycle -system.cpu.tickCycles 1838736315 # Number of cycles that the object actually ticked -system.cpu.idleCycles 379153165 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9224311 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.608602 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624084220 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9228407 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.626430 # Average number of references to valid blocks. +system.cpu.cpi 1.435649 # CPI: cycles per instruction +system.cpu.ipc 0.696549 # IPC: instructions per cycle +system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked +system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9223724 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.608602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.606596 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1292 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2484 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276551305 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276551305 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 453737568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453737568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 170346530 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170346530 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 453740634 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 170346644 # number of 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accesses -system.cpu.dcache.demand_accesses::total 633661327 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 633661327 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633661327 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 633663803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 633663803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015114 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015114 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015114 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015114 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25021.200545 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25021.200545 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45351.971206 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45351.971206 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29775.300768 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29775.300768 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.015113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.015113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24996.213876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45279.794101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -464,101 +498,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks -system.cpu.dcache.writebacks::total 3700618 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348609 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 348609 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 348822 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348822 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 348822 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348822 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7337499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7337499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890908 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890908 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9228407 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9228407 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9228407 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9228407 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168505826254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168505826254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77457723500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77457723500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245963549754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245963549754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245963549754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245963549754 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015914 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015914 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks +system.cpu.dcache.writebacks::total 3701129 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 221 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348484 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 348705 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9227820 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014564 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014564 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22965.022040 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22965.022040 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40963.242791 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40963.242791 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses 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misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.026879 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466133968 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 568456.058537 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.026879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322767 # Average percentage of cache occupancy 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-system.cpu.l2cache.writebacks::writebacks 1046713 # number of writebacks -system.cpu.l2cache.writebacks::total 1046713 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks +system.cpu.l2cache.writebacks::total 1046417 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1256323 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1256323 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800324 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800324 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2056647 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2056647 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2056647 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2056647 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84521118250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84521118250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54527231750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54527231750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139048350000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 139048350000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139048350000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 139048350000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222841 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222841 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67276.582734 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67276.582734 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68131.446452 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68131.446452 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800096 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84332667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54391877500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138724544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138724544500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67170.422532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67981.689072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7338319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7338319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22157432 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22159072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827457600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827510080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12929845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -734,41 +768,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12929845 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12929845 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10165540500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1391499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14187091746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1256323 # Transaction distribution -system.membus.trans_dist::ReadResp 1256323 # Transaction distribution -system.membus.trans_dist::Writeback 1046713 # Transaction distribution -system.membus.trans_dist::ReadExReq 800324 # Transaction distribution -system.membus.trans_dist::ReadExResp 800324 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5160007 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5160007 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198615040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198615040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255503 # Transaction distribution +system.membus.trans_dist::ReadResp 1255503 # Transaction distribution +system.membus.trans_dist::Writeback 1046417 # Transaction distribution +system.membus.trans_dist::ReadExReq 800096 # Transaction distribution +system.membus.trans_dist::ReadExResp 800096 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3103360 # Request fanout histogram +system.membus.snoop_fanout::samples 3102016 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3103360 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3103360 # Request fanout histogram -system.membus.reqLayer0.occupancy 12130659500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3102016 # Request fanout histogram +system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19439818500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index dd7b09a8e..2039a5a26 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.753004 # Number of seconds simulated -sim_ticks 753003557500 # Number of ticks simulated -final_tick 753003557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.756343 # Number of seconds simulated +sim_ticks 756342731500 # Number of ticks simulated +final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139146 # Simulator instruction rate (inst/s) -host_op_rate 149909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67836303 # Simulator tick rate (ticks/s) -host_mem_usage 311432 # Number of bytes of host memory used -host_seconds 11100.30 # Real time elapsed on the host +host_inst_rate 137786 # Simulator instruction rate (inst/s) +host_op_rate 148444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67471289 # Simulator tick rate (ticks/s) +host_mem_usage 311496 # Number of bytes of host memory used +host_seconds 11209.85 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 14592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 231381248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 95077696 # Number of bytes read from this memory -system.physmem.bytes_read::total 326473536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 107048704 # Number of bytes written to this memory -system.physmem.bytes_written::total 107048704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3615332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1485589 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5101149 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1672636 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1672636 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 307277762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 126264604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 433561744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 142162282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 142162282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 142162282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 307277762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 126264604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 575724026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5101149 # Number of read requests accepted -system.physmem.writeReqs 1672636 # Number of write requests accepted -system.physmem.readBursts 5101149 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1672636 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 326003456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 470080 # Total number of bytes read from write queue -system.physmem.bytesWritten 107046272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 326473536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 107048704 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7345 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory +system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory +system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4720345 # Number of read requests accepted +system.physmem.writeReqs 1638491 # Number of write requests accepted +system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue +system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 320458 # Per bank write bursts -system.physmem.perBankRdBursts::1 318552 # Per bank write bursts -system.physmem.perBankRdBursts::2 312159 # Per bank write bursts -system.physmem.perBankRdBursts::3 320321 # Per bank write bursts -system.physmem.perBankRdBursts::4 313091 # Per bank write bursts -system.physmem.perBankRdBursts::5 313451 # Per bank write bursts -system.physmem.perBankRdBursts::6 306429 # Per bank write bursts -system.physmem.perBankRdBursts::7 300886 # Per bank write bursts -system.physmem.perBankRdBursts::8 320656 # Per bank write bursts -system.physmem.perBankRdBursts::9 326914 # Per bank write bursts -system.physmem.perBankRdBursts::10 318873 # Per bank write bursts -system.physmem.perBankRdBursts::11 328947 # Per bank write bursts -system.physmem.perBankRdBursts::12 326980 # Per bank write bursts -system.physmem.perBankRdBursts::13 328236 # Per bank write bursts -system.physmem.perBankRdBursts::14 322345 # Per bank write bursts -system.physmem.perBankRdBursts::15 315506 # Per bank write bursts -system.physmem.perBankWrBursts::0 106372 # Per bank write bursts -system.physmem.perBankWrBursts::1 103970 # Per bank write bursts -system.physmem.perBankWrBursts::2 101390 # Per bank write bursts -system.physmem.perBankWrBursts::3 102163 # Per bank write bursts -system.physmem.perBankWrBursts::4 101308 # Per bank write bursts -system.physmem.perBankWrBursts::5 100856 # Per bank write bursts -system.physmem.perBankWrBursts::6 104858 # Per bank write bursts -system.physmem.perBankWrBursts::7 106447 # Per bank write bursts -system.physmem.perBankWrBursts::8 107624 # Per bank write bursts -system.physmem.perBankWrBursts::9 106732 # Per bank write bursts -system.physmem.perBankWrBursts::10 104273 # Per bank write bursts -system.physmem.perBankWrBursts::11 105282 # Per bank write bursts -system.physmem.perBankWrBursts::12 105198 # Per bank write bursts -system.physmem.perBankWrBursts::13 104874 # Per bank write bursts -system.physmem.perBankWrBursts::14 106564 # Per bank write bursts -system.physmem.perBankWrBursts::15 104687 # Per bank write bursts +system.physmem.perBankRdBursts::0 296862 # Per bank write bursts +system.physmem.perBankRdBursts::1 294626 # Per bank write bursts +system.physmem.perBankRdBursts::2 288270 # Per bank write bursts +system.physmem.perBankRdBursts::3 292812 # Per bank write bursts +system.physmem.perBankRdBursts::4 290199 # Per bank write bursts +system.physmem.perBankRdBursts::5 289793 # Per bank write bursts +system.physmem.perBankRdBursts::6 284872 # Per bank write bursts +system.physmem.perBankRdBursts::7 281493 # Per bank write bursts +system.physmem.perBankRdBursts::8 297311 # Per bank write bursts +system.physmem.perBankRdBursts::9 303290 # Per bank write bursts +system.physmem.perBankRdBursts::10 295469 # Per bank write bursts +system.physmem.perBankRdBursts::11 301855 # Per bank write bursts +system.physmem.perBankRdBursts::12 303298 # Per bank write bursts +system.physmem.perBankRdBursts::13 302373 # Per bank write bursts +system.physmem.perBankRdBursts::14 297652 # Per bank write bursts +system.physmem.perBankRdBursts::15 293020 # Per bank write bursts +system.physmem.perBankWrBursts::0 104131 # Per bank write bursts +system.physmem.perBankWrBursts::1 101826 # Per bank write bursts +system.physmem.perBankWrBursts::2 99098 # Per bank write bursts +system.physmem.perBankWrBursts::3 99979 # Per bank write bursts +system.physmem.perBankWrBursts::4 99438 # Per bank write bursts +system.physmem.perBankWrBursts::5 99115 # Per bank write bursts +system.physmem.perBankWrBursts::6 102674 # Per bank write bursts +system.physmem.perBankWrBursts::7 104427 # Per bank write bursts +system.physmem.perBankWrBursts::8 105209 # Per bank write bursts +system.physmem.perBankWrBursts::9 104570 # Per bank write bursts +system.physmem.perBankWrBursts::10 102342 # Per bank write bursts +system.physmem.perBankWrBursts::11 102683 # Per bank write bursts +system.physmem.perBankWrBursts::12 102787 # Per bank write bursts +system.physmem.perBankWrBursts::13 102808 # Per bank write bursts +system.physmem.perBankWrBursts::14 104630 # Per bank write bursts +system.physmem.perBankWrBursts::15 102728 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 753003515500 # Total gap between requests +system.physmem.totGap 756342591500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5101149 # Read request sizes (log2) +system.physmem.readPktSize::6 4720345 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1672636 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2761902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1096580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 406963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 307813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 214927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 130899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 69362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 43944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 12494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 6876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 4504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 473 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1638491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,38 +148,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 25442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 58935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 74795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 105264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 108420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 110279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 111519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 112924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 114921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 116959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 109523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 106852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 104984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 103460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -197,140 +197,132 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4344411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 99.679291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.657847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 113.406930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3407328 78.43% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 696147 16.02% 94.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 107309 2.47% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 43326 1.00% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 33261 0.77% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16273 0.37% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9699 0.22% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6677 0.15% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24391 0.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4344411 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 100519 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 50.674768 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.618065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.194987 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 98006 97.50% 97.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1235 1.23% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 738 0.73% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 394 0.39% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 104 0.10% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 26 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 7 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3327 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 100519 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 100519 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.639620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.599991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.204272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73763 73.38% 73.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1810 1.80% 75.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17937 17.84% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4183 4.16% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1485 1.48% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 646 0.64% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 326 0.32% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 183 0.18% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 100 0.10% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 51 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 100519 # Writes before turning the bus around for reads -system.physmem.totQLat 147032532073 # Total ticks spent queuing -system.physmem.totMemAccLat 242541357073 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 25469020000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28864.98 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads +system.physmem.totQLat 132475907765 # Total ticks spent queuing +system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47614.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 432.94 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 142.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 433.56 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 142.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.49 # Data bus utilization in percentage -system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.11 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 2056015 # Number of row buffer hits during reads -system.physmem.writeRowHits 365966 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.88 # Row buffer hit rate for writes -system.physmem.avgGap 111164.37 # Average gap between requests -system.physmem.pageHitRate 35.79 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 77100737509 # Time in different power states -system.physmem.memoryStateTime::REF 25144340000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 650755672741 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 16285857840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 16557549120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 8886132750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 9034377000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19540895400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 20189722800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5361143760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5476960800 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 49182329040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 49182329040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 403433749845 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 404376910605 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 97911188250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 97083854250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 600601296885 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 601901703615 # Total energy per rank (pJ) -system.physmem.averagePower::0 797.610503 # Core power per rank (mW) -system.physmem.averagePower::1 799.337469 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4164250 # Transaction distribution -system.membus.trans_dist::ReadResp 4164249 # Transaction distribution -system.membus.trans_dist::Writeback 1672636 # Transaction distribution -system.membus.trans_dist::ReadExReq 936899 # Transaction distribution -system.membus.trans_dist::ReadExResp 936899 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11874933 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11874933 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 433522176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 433522176 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6773785 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6773785 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6773785 # Request fanout histogram -system.membus.reqLayer0.occupancy 21336071694 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 47387677526 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.3 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 286237274 # Number of BP lookups -system.cpu.branchPred.condPredicted 223376247 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157873028 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150326972 # Number of BTB hits +system.physmem.busUtil 4.20 # Data bus utilization in percentage +system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 1712938 # Number of row buffer hits during reads +system.physmem.writeRowHits 353078 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes +system.physmem.avgGap 118943.56 # Average gap between requests +system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.094387 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states +system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ) +system.physmem_1.averagePower 795.815775 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states +system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 286251205 # Number of BP lookups +system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.220174 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640209 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -352,6 +344,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -373,6 +373,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,6 +402,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -416,233 +432,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1506007116 # number of cpu cycles simulated +system.cpu.numCycles 1512685464 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13915908 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067206547 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286237274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166967181 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1477423210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29286859 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656844028 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 587 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1505982817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.470565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.223309 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 423738570 28.14% 28.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465347942 30.90% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101390896 6.73% 65.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515505409 34.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1505982817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.190064 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372641 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74738188 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 508470466 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849951241 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58180203 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642719 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42195522 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 748 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037029518 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52402529 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642719 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139800206 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 434773312 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14137 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837909741 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 78842702 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976226014 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26698193 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45123172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125355 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1314299 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18015097 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985707207 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127389229 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432660668 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310808262 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111604908 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542499825 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199292304 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26858708 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28865215 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947820848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 155 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857727691 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13537484 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 279225798 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 646033301 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1505982817 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.233565 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149736 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 553461726 36.75% 36.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325286672 21.60% 58.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378400557 25.13% 83.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219701727 14.59% 98.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29125951 1.93% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6184 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1505982817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166582994 41.01% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1992 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191579576 47.17% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 48024706 11.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138365513 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800977 0.04% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 26 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532245079 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186316069 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857727691 # Type of FU issued -system.cpu.iq.rate 1.233545 # Inst issue rate -system.cpu.iq.fu_busy_cnt 406189268 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218648 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5641164724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2227059400 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805827330 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263916833 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17868715 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued +system.cpu.iq.rate 1.228002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84193491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12979 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24445259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4569389 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5015263 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642719 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25280273 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1153411 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947821148 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542499825 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199292304 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158606 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 993784 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12979 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7710323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8723960 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16434283 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1828067374 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 517076026 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29660317 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 698832649 # number of memory reference insts executed -system.cpu.iew.exec_branches 229600081 # Number of branches executed -system.cpu.iew.exec_stores 181756623 # Number of stores executed -system.cpu.iew.exec_rate 1.213850 # Inst execution rate -system.cpu.iew.wb_sent 1808848691 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805827397 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169333238 # num instructions producing a value -system.cpu.iew.wb_consumers 1689629138 # num instructions consuming a value +system.cpu.iew.exec_nop 81 # number of nop insts executed +system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed +system.cpu.iew.exec_branches 229598858 # Number of branches executed +system.cpu.iew.exec_stores 181759645 # Number of stores executed +system.cpu.iew.exec_rate 1.208393 # Inst execution rate +system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169265268 # num instructions producing a value +system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.199083 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692065 # average fanout of values written-back +system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257853927 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630548 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1466512041 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.134687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.044179 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 886829793 60.47% 60.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250699029 17.09% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 109472668 7.46% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55016344 3.75% 88.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29216480 1.99% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 33954895 2.32% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24874922 1.70% 94.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18134171 1.24% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58313739 3.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1466512041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -688,390 +704,77 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 58313739 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3330084063 # The number of ROB reads -system.cpu.rob.rob_writes 3883248692 # The number of ROB writes -system.cpu.timesIdled 433 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24299 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3336711734 # The number of ROB reads +system.cpu.rob.rob_writes 3883178493 # The number of ROB writes +system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.975038 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.975038 # CPI: Total CPI of All Threads -system.cpu.ipc 1.025601 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.025601 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2176017062 # number of integer regfile reads -system.cpu.int_regfile_writes 1261587528 # number of integer regfile writes +system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads +system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads +system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 49 # number of floating regfile writes -system.cpu.cc_regfile_reads 6966468810 # number of cc regfile reads -system.cpu.cc_regfile_writes 551975360 # number of cc regfile writes -system.cpu.misc_regfile_reads 675847678 # number of misc regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads +system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes +system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 14271352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14271352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4800041 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2156446 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737659 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2176 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38815887 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38818063 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1395709696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1395779328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2156446 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23967212 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.089975 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.286146 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21810766 91.00% 91.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 2156446 9.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23967212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15706134446 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1655247 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25977831897 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 600 # number of replacements -system.cpu.icache.tags.tagsinuse 446.759697 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656842791 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1088 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 603715.800551 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 446.759697 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.872578 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.872578 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313689140 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313689140 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656842791 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656842791 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656842791 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656842791 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656842791 # number of overall hits -system.cpu.icache.overall_hits::total 656842791 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1235 # number of overall misses -system.cpu.icache.overall_misses::total 1235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31675742 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31675742 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31675742 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31675742 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31675742 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31675742 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656844026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656844026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656844026 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656844026 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656844026 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656844026 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25648.374089 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25648.374089 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25648.374089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25648.374089 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3135 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 123 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.487805 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1088 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1088 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1088 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1088 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1088 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1088 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25912248 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25912248 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25912248 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25912248 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25912248 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25912248 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23816.404412 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23816.404412 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 15355050 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 500576 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 12135733 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 866797 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 351771 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 1500173 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5090638 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 5094046 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16133.549273 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 15376042 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5109996 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.009013 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 29446587000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4939.304770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3.959471 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6800.251946 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4390.033086 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.301471 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000242 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.415054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.267946 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14923 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 102 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 570 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 346 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 521 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2353 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9340 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.910828 # Percentage of cache occupancy per task id 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-system.cpu.l2cache.demand_accesses::cpu.data 17007923 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17009011 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1088 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17007923 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17009011 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.235294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.192321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.192324 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.343768 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.343768 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235294 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216698 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216700 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235294 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216698 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216700 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77465.816406 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79009.282865 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79009.138906 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 99495.412851 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 99495.412851 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77465.816406 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84240.437550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84239.967020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77465.816406 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84240.437550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84239.967020 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 114068 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3696 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30.862554 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1672636 # number of writebacks -system.cpu.l2cache.writebacks::total 1672636 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67618 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 67646 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 4482 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 4482 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 72100 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 72128 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 72100 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 72128 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2676852 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2677080 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1500168 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 936637 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 936637 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3613489 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3613717 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3613489 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5113885 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16681749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 190526161225 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 190542842974 # number of ReadReq MSHR miss cycles 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212459 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.300657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73165.565789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.455806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71175.625298 # average ReadReq mshr miss latency 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cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17007297 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 449 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335546211 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335546211 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469430568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469430568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168947154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168947154 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638377722 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638377722 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638377722 # number of overall hits -system.cpu.dcache.overall_hits::total 638377722 # number of overall hits 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2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 20891298 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20891298 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20891300 # number of overall misses -system.cpu.dcache.overall_misses::total 20891300 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 389285003128 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 389285003128 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129453998118 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129453998118 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 384750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 384750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 518739001246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 518739001246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 518739001246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 518739001246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486682973 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486682973 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses 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535479278115 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -1080,92 +783,421 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659269020 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659269020 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659269022 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659269022 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035449 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035449 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.021085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.031689 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.031689 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031689 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031689 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22564.100665 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22564.100665 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35575.104329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35575.104329 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 96187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 96187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24830.386376 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24830.386376 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24830.383999 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24830.383999 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20820542 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1650046 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1039120 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 52884 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.036706 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 31.201233 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4800041 # number of writebacks -system.cpu.dcache.writebacks::total 4800041 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2982110 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2982110 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 901266 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 901266 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks +system.cpu.dcache.writebacks::total 4837992 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1053221 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3883376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3883376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3883376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3883376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270295 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14270295 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737627 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737627 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4041425 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4041425 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4041425 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4041425 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270355 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14270355 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737453 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737453 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17007922 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17007922 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17007923 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17007923 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 301459973376 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 301459973376 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108130443900 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 108130443900 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 101000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 101000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 409590417276 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 409590417276 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 409590518276 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 409590518276 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17007808 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17007808 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17007809 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17007809 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 303479537034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 303479537034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 110174073244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 110174073244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 413653610278 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 413653610278 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 413653672278 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 413653672278 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029319 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029319 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015861 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015861 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025798 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025798 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21124.999404 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21124.999404 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39497.873122 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39497.873122 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 101000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 101000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24082.331591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24082.331591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24082.336113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24082.336113 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025796 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025796 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21266.432197 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21266.432197 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40246.927799 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40246.927799 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24321.394637 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24321.394637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24321.396852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24321.396852 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 591 # number of replacements +system.cpu.icache.tags.tagsinuse 445.749905 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656876635 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 608782.794254 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 445.749905 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.870605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.870605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313757597 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313757597 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656876635 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656876635 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656876635 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656876635 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656876635 # number of overall hits +system.cpu.icache.overall_hits::total 656876635 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1624 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1624 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1624 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1624 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1624 # number of overall misses +system.cpu.icache.overall_misses::total 1624 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 95182738 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 95182738 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 95182738 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 95182738 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 95182738 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 95182738 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656878259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656878259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656878259 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656878259 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656878259 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656878259 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 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of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69657739 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69657739 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69657739 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64557.682113 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64557.682113 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.prefetcher.num_hwpf_issued 10957108 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11640584 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 428597 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant 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accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency 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distribution +system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1352607 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3738412 # Transaction distribution +system.membus.trans_dist::ReadResp 3738412 # Transaction distribution +system.membus.trans_dist::Writeback 1638491 # Transaction distribution +system.membus.trans_dist::ReadExReq 981933 # Transaction distribution +system.membus.trans_dist::ReadExResp 981933 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6358836 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6358836 # Request fanout histogram +system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index fc3ec094e..c26ad4c6d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490000 # Number of ticks simulated final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2048371 # Simulator instruction rate (inst/s) -host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1103406177 # Simulator tick rate (ticks/s) -host_mem_usage 296712 # Number of bytes of host memory used -host_seconds 754.04 # Real time elapsed on the host +host_inst_rate 1680600 # Simulator instruction rate (inst/s) +host_op_rate 1810592 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 905297170 # Simulator tick rate (ticks/s) +host_mem_usage 301428 # Number of bytes of host memory used +host_seconds 919.05 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 750174605 # Wr system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution -system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution -system.membus.trans_dist::WriteReq 172586047 # Transaction distribution -system.membus.trans_dist::WriteResp 172586047 # Transaction distribution -system.membus.trans_dist::SoftPFReq 1 # Transaction distribution -system.membus.trans_dist::SoftPFResp 1 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondResp 61 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram -system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 2172060894 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction +system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution +system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution +system.membus.trans_dist::WriteReq 172586047 # Transaction distribution +system.membus.trans_dist::WriteResp 172586047 # Transaction distribution +system.membus.trans_dist::SoftPFReq 1 # Transaction distribution +system.membus.trans_dist::SoftPFResp 1 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondResp 61 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram +system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 2172060894 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 1aeb45981..89012dc1c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.363671 # Nu sim_ticks 2363670998000 # Number of ticks simulated final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1205605 # Simulator instruction rate (inst/s) -host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1851916301 # Simulator tick rate (ticks/s) -host_mem_usage 306192 # Number of bytes of host memory used -host_seconds 1276.34 # Real time elapsed on the host +host_inst_rate 1113267 # Simulator instruction rate (inst/s) +host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1710076181 # Simulator tick rate (ticks/s) +host_mem_usage 309628 # Number of bytes of host memory used +host_seconds 1382.20 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 27542188 # To system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1177898 # Transaction distribution -system.membus.trans_dist::ReadResp 1177898 # Transaction distribution -system.membus.trans_dist::Writeback 1017198 # Transaction distribution -system.membus.trans_dist::ReadExReq 780876 # Transaction distribution -system.membus.trans_dist::ReadExResp 780876 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2975972 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2975972 # Request fanout histogram -system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,137 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits +system.cpu.dcache.overall_hits::total 618379947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses +system.cpu.dcache.overall_misses::total 9115236 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks +system.cpu.dcache.writebacks::total 3697418 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. @@ -438,137 +577,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits -system.cpu.dcache.overall_hits::total 618379947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses -system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks -system.cpu.dcache.writebacks::total 3697418 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution @@ -602,5 +610,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 957000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1177898 # Transaction distribution +system.membus.trans_dist::ReadResp 1177898 # Transaction distribution +system.membus.trans_dist::Writeback 1017198 # Transaction distribution +system.membus.trans_dist::ReadExReq 780876 # Transaction distribution +system.membus.trans_dist::ReadExResp 780876 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2975972 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2975972 # Request fanout histogram +system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 38e101aaf..3a5076b7f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.052167 # Nu sim_ticks 52167245000 # Number of ticks simulated final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231551 # Simulator instruction rate (inst/s) -host_op_rate 231551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131435822 # Simulator tick rate (ticks/s) -host_mem_usage 240584 # Number of bytes of host memory used -host_seconds 396.90 # Real time elapsed on the host +host_inst_rate 368966 # Simulator instruction rate (inst/s) +host_op_rate 368966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209437459 # Simulator tick rate (ticks/s) +host_mem_usage 299464 # Number of bytes of host memory used +host_seconds 249.08 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 386 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.254620 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.254822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.143137 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 322 33.06% 33.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190 19.51% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 9.86% 62.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 102 10.47% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 61 6.26% 79.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.70% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 25 2.57% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 2.57% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 117 12.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 974 # Bytes accessed per row activation -system.physmem.totQLat 31955000 # Total ticks spent queuing -system.physmem.totMemAccLat 131667500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.971193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 211.834828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.374999 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 320 32.92% 32.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191 19.65% 52.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96 9.88% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 99 10.19% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 6.48% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 3.70% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.47% 85.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 26 2.67% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 117 12.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 972 # Bytes accessed per row activation +system.physmem.totQLat 32099750 # Total ticks spent queuing +system.physmem.totMemAccLat 131812250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6008.84 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6036.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24758.84 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24786.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s @@ -212,43 +212,48 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4336 # Number of row buffer hits during reads +system.physmem.readRowHits 4338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 9809545.60 # Average gap between requests -system.physmem.pageHitRate 81.53 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49062382500 # Time in different power states -system.physmem.memoryStateTime::REF 1741740000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1356240000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3530520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1926375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19827600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 21216000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1740241350 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1807017705 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29769681750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29711106000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34942051035 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34952037330 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.896806 # Core power per rank (mW) -system.physmem.averagePower::1 670.088260 # Core power per rank (mW) -system.cpu.branchPred.lookups 11476347 # Number of BP lookups +system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3530520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1926375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19827600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1740830445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29769165000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34942123380 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.898193 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49520504500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898118000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3772440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2058375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1807143390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29710995750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34952029395 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.088108 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49425818250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 995309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 11476348 # Number of BP lookups system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176736 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 1176737 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -267,10 +272,10 @@ system.cpu.dtb.data_hits 26977004 # DT system.cpu.dtb.data_misses 47407 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27024411 # DTB accesses -system.cpu.itb.fetch_hits 23068125 # ITB hits +system.cpu.itb.fetch_hits 23068130 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23068213 # ITB accesses +system.cpu.itb.fetch_accesses 23068218 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,15 +298,15 @@ system.cpu.discardedOps 2153944 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.135266 # CPI: cycles per instruction system.cpu.ipc 0.880851 # IPC: instructions per cycle -system.cpu.tickCycles 102681426 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1653064 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 102681434 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1653056 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.700924 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1448.700214 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700924 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700214 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -329,14 +334,14 @@ system.cpu.dcache.demand_misses::cpu.inst 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37712750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37712750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 194587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 194587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 232300250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232300250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 232300250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232300250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37684500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 195045500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 232730000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 232730000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 20070465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) @@ -353,14 +358,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72664.258189 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72664.258189 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66845.585709 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66845.585709 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67726.020408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67726.020408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67726.020408 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72609.826590 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67002.919959 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,14 +392,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151325500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151325500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151325500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151325500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 34103500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 117640500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151744000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151744000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses @@ -403,24 +408,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70379.381443 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70379.381443 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67158.452722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67158.452722 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67858.968610 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67858.968610 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70316.494845 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67415.759312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13871 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.666168 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23052289 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.665289 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23052294 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1455.780802 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1455.781118 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.666168 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801107 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801107 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.665289 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801106 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -428,44 +433,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669 system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46152085 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46152085 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23052289 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23052289 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23052289 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23052289 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23052289 # number of overall hits -system.cpu.icache.overall_hits::total 23052289 # number of overall hits +system.cpu.icache.tags.tag_accesses 46152095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46152095 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23052294 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23052294 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23052294 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23052294 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23052294 # number of overall hits +system.cpu.icache.overall_hits::total 23052294 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses system.cpu.icache.overall_misses::total 15836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386603500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386603500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 386603500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386603500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 386603500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386603500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23068125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23068125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23068125 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23068125 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23068125 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23068125 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 386327750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 386327750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 386327750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 386327750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 386327750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 386327750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23068130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23068130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23068130 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23068130 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23068130 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23068130 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24412.951503 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24412.951503 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24412.951503 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24412.951503 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24412.951503 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24395.538646 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24395.538646 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,33 +485,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15836 system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353567500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353567500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353567500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353567500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353567500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353567500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353292250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 353292250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353292250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 353292250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353292250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 353292250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22326.818641 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22326.818641 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22326.818641 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22326.818641 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2479.834280 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2479.833240 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.054210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.053168 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075136 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy @@ -537,14 +542,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5318 # system.cpu.l2cache.demand_misses::total 5318 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 5318 # number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 244164500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 244164500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115186000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115186000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 359350500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359350500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 359350500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359350500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 243859250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 115635000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 359494250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 359494250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 16320 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) @@ -563,14 +568,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.294381 system.cpu.l2cache.demand_miss_rate::total 0.294381 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.294381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67842.317310 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67842.317310 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67007.562536 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67007.562536 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67572.489658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67572.489658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67572.489658 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67757.502084 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67268.760908 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67599.520496 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,14 +592,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5318 system.cpu.l2cache.demand_mshr_misses::total 5318 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 5318 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198927000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198927000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93369000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292296000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 292296000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292296000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 292296000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 198623250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 93817500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292440750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.220527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses @@ -603,14 +608,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294381 system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294381 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55272.853570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.853570 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54315.881326 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54315.881326 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54963.520120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54963.520120 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55188.455126 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54576.788831 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution @@ -637,9 +642,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24435500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24435250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 3599 # Transaction distribution system.membus.trans_dist::ReadResp 3599 # Transaction distribution @@ -660,9 +665,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6477500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6478000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50028000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50027750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 3e567522b..fbd001a0c 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022159 # Nu sim_ticks 22159411000 # Number of ticks simulated final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173006 # Simulator instruction rate (inst/s) -host_op_rate 173006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45541949 # Simulator tick rate (ticks/s) -host_mem_usage 243048 # Number of bytes of host memory used -host_seconds 486.57 # Real time elapsed on the host +host_inst_rate 210811 # Simulator instruction rate (inst/s) +host_op_rate 210811 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55493646 # Simulator tick rate (ticks/s) +host_mem_usage 299980 # Number of bytes of host memory used +host_seconds 399.31 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # By system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 41291750 # Total ticks spent queuing -system.physmem.totMemAccLat 139391750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 41292000 # Total ticks spent queuing +system.physmem.totMemAccLat 139392000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7892.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7892.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26642.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26642.20 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 83.22 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 4235344.32 # Average gap between requests system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 20543925500 # Time in different power states -system.physmem.memoryStateTime::REF 739700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 868697500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3137400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3341520 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1711875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1823250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 19453200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 20802600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 893934990 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 919865430 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 12507131250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 12484385250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 14872221915 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14877071250 # Total energy per rank (pJ) -system.physmem.averagePower::0 671.367239 # Core power per rank (mW) -system.physmem.averagePower::1 671.586150 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1709 # Transaction distribution -system.membus.trans_dist::ReadExResp 1709 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5232 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5232 # Request fanout histogram -system.membus.reqLayer0.occupancy 6530000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48921000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19453200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 894020490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12507056250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14872232415 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.367713 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20804380500 # Time in different power states +system.physmem_0.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 608242500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20802600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 920005650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12484262250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14877088470 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.586927 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20766250250 # Time in different power states +system.physmem_1.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 646430250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 16298030 # Number of BP lookups system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -314,22 +296,22 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 44318823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16859440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 16859439 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26218420 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 26218422 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44094962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 44094963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19653197 44.57% 44.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19653198 44.57% 44.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) @@ -341,11 +323,11 @@ system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44094962 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 44094963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13063436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8246929 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 13063435 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8246931 # Number of cycles decode is blocked system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing @@ -354,16 +336,16 @@ system.cpu.decode.BranchMispred 12053 # Nu system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14206626 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4728528 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 14206625 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4728440 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3626870 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 3626960 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 46116 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 46206 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups @@ -384,23 +366,23 @@ system.cpu.iq.iqSquashedInstsIssued 120259 # Nu system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44094962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 44094963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7754469 17.59% 43.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7754470 17.59% 43.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4489383 10.18% 84.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2977389 6.75% 90.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4489384 10.18% 84.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2977388 6.75% 90.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44094962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44094963 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available @@ -473,7 +455,7 @@ system.cpu.iq.FU_type_0::total 100102500 # Ty system.cpu.iq.rate 2.258690 # Inst issue rate system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231175585 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 231175586 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads @@ -493,15 +475,15 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3707628 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461879 # Number of cycles IEW is unblocking +system.cpu.iew.iewBlockCycles 3707612 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 461807 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 414957 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 414885 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly @@ -517,8 +499,8 @@ system.cpu.iew.exec_stores 7162603 # Nu system.cpu.iew.exec_rate 2.227716 # Inst execution rate system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67088119 # num instructions producing a value -system.cpu.iew.wb_consumers 95122375 # num instructions consuming a value +system.cpu.iew.wb_producers 67088120 # num instructions producing a value +system.cpu.iew.wb_consumers 95122376 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back @@ -526,11 +508,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39466886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 39466887 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14969499 37.93% 37.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14969500 37.93% 37.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle @@ -542,7 +524,7 @@ system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39466886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39466887 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -590,10 +572,10 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 156894390 # The number of ROB reads +system.cpu.rob.rob_reads 156894391 # The number of ROB reads system.cpu.rob.rob_writes 251967276 # The number of ROB writes system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223861 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 223860 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction @@ -606,42 +588,149 @@ system.cpu.fp_regfile_reads 6250590 # nu system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes system.cpu.misc_regfile_reads 718773 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17856500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 160 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.564933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits +system.cpu.dcache.overall_hits::total 28680491 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses +system.cpu.dcache.overall_misses::total 9410 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65475750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65475750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 523849968 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 523849968 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 589325718 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 589325718 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 589325718 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 589325718 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62836.612284 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62836.612284 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62601.573614 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62601.573614 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62627.600213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62627.600213 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29227 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.692394 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 110 # number of writebacks +system.cpu.dcache.writebacks::total 110 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36153000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36153000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125731745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 125731745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161884745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161884745 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70473.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70473.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72509.656863 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72509.656863 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9583 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.631019 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1600.631053 # Cycle average of tags in use system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631019 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631053 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id @@ -665,12 +754,12 @@ system.cpu.icache.demand_misses::cpu.inst 14533 # n system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses system.cpu.icache.overall_misses::total 14533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419606250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419606250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419606250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419606250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419606250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419606250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 419570250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 419570250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 419570250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 419570250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 419570250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 419570250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses @@ -683,12 +772,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28872.651896 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28872.651896 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28872.651896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28872.651896 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28870.174775 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28870.174775 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28870.174775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28870.174775 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -709,34 +798,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11519 system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306578000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306578000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306551250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 306551250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306551250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 306551250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306551250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 306551250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26614.983940 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26614.983940 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.661689 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.661689 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2401.991277 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2401.991328 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.703654 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347182 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940441 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.703660 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347225 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940444 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy @@ -774,17 +863,17 @@ system.cpu.l2cache.demand_misses::total 5232 # nu system.cpu.l2cache.overall_misses::cpu.inst 3065 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2167 # number of overall misses system.cpu.l2cache.overall_misses::total 5232 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210511250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35108000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245619250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123622250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 123622250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210511250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158730250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369241500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210511250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158730250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369241500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210484500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35100000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245584500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123658250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 123658250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210484500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158758250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 369242750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210484500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158758250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 369242750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11519 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12032 # number of ReadReq accesses(hits+misses) @@ -809,17 +898,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380039 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266082 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963968 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.380039 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68682.300163 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76655.021834 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69718.776611 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72336.015214 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72336.015214 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70573.681193 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70573.681193 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68673.572594 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76637.554585 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69708.912858 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72357.080164 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72357.080164 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70573.920107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70573.920107 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,17 +928,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5232 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3065 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171684750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29423500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201108250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102762250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102762250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171684750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132185750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 303870500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171684750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132185750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 303870500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29415000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201074500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102798250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102798250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132213250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 303872750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171659500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132213250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 303872750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292803 # mshr miss rate for ReadReq accesses @@ -861,153 +950,69 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380039 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380039 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56014.600326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64243.449782 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57084.374113 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60130.046811 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60130.046811 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.362153 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64224.890830 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57074.794209 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60151.111761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60151.111761 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 160 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.564755 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564755 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits -system.cpu.dcache.overall_hits::total 28680491 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses -system.cpu.dcache.overall_misses::total 9410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65491750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65491750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 523624968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 523624968 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 589116718 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 589116718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 589116718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 589116718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.967370 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.967370 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62574.685468 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62574.685468 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62605.389798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62605.389798 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29209 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.672260 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 110 # number of writebacks -system.cpu.dcache.writebacks::total 110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125695745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125695745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161856745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161856745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161856745 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161856745 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70489.278752 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70489.278752 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72488.895617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72488.895617 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17856250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3523 # Transaction distribution +system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.membus.trans_dist::ReadExReq 1709 # Transaction distribution +system.membus.trans_dist::ReadExResp 1709 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5232 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5232 # Request fanout histogram +system.membus.reqLayer0.occupancy 6529000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 48920250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index be651ff21..75d7eb795 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131746 # Nu sim_ticks 131745950000 # Number of ticks simulated final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190259 # Simulator instruction rate (inst/s) -host_op_rate 200564 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145463120 # Simulator tick rate (ticks/s) -host_mem_usage 256996 # Number of bytes of host memory used -host_seconds 905.70 # Real time elapsed on the host +host_inst_rate 246838 # Simulator instruction rate (inst/s) +host_op_rate 260207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188720644 # Simulator tick rate (ticks/s) +host_mem_usage 315756 # Number of bytes of host memory used +host_seconds 698.10 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # By system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 28129500 # Total ticks spent queuing -system.physmem.totMemAccLat 100635750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 28130750 # Total ticks spent queuing +system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7274.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26024.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 76.29 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 34069268.55 # Average gap between requests system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 125856871250 # Time in different power states -system.physmem.memoryStateTime::REF 4399200000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1487617250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3092040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1687125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 16177200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 13767000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 3575888730 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3595740120 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 75909421500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 75892008000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 88111101795 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 88112204505 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.807404 # Core power per rank (mW) -system.physmem.averagePower::1 668.815774 # Core power per rank (mW) +system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.807422 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.815773 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 49935043 # Number of BP lookups system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect @@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct 95.508866 # BT system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -348,12 +385,12 @@ system.cpu.ipc 0.653978 # IP system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.772721 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772721 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772724 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -387,12 +424,12 @@ system.cpu.dcache.overall_misses::cpu.inst 2436 # system.cpu.dcache.overall_misses::total 2436 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54011984 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115580250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115580250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 169592234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169592234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 169592234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169592234 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115610250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 169622234 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 169622234 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 28356322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) @@ -415,12 +452,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000060 system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70304.288321 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70304.288321 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69619.143678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69619.143678 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70322.536496 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69631.458949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,12 +486,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 1810 system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47293264 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76493500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76493500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123786764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123786764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123786764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 123786764 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76508500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123801764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses @@ -465,20 +502,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66423.123596 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69666.211293 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69666.211293 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69679.872495 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68398.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2909 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.880839 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880839 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id @@ -502,12 +539,12 @@ system.cpu.icache.demand_misses::cpu.inst 4706 # n system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses system.cpu.icache.overall_misses::total 4706 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186392247 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186392247 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186392247 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186392247 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186392247 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186392247 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses @@ -520,12 +557,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39607.362303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39607.362303 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39607.362303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39607.362303 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,33 +577,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4706 system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176061753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176061753 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176061753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176061753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176061753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176061753 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37412.187208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37412.187208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520468 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491287 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy @@ -597,14 +634,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 3885 # system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3885 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191698500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 191698500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75314000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75314000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 267012500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267012500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 267012500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267012500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191684250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75329000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 267013250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 267013250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) @@ -623,14 +660,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.596225 system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.596225 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68581.127013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69109.174312 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,14 +690,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155803750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155803750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61486500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61486500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217290250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 217290250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217290250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 217290250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155790000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61501500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217291500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217291500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses @@ -669,14 +706,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56079.913607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56423.394495 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution @@ -707,7 +744,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 5 # system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7517747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) @@ -732,7 +769,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 3867 # Request fanout histogram system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36361250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index eede9a19d..30df36f38 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084956 # Number of seconds simulated -sim_ticks 84955935500 # Number of ticks simulated -final_tick 84955935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085008 # Number of seconds simulated +sim_ticks 85008313500 # Number of ticks simulated +final_tick 85008313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133775 # Simulator instruction rate (inst/s) -host_op_rate 141021 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65959289 # Simulator tick rate (ticks/s) -host_mem_usage 311648 # Number of bytes of host memory used -host_seconds 1288.01 # Real time elapsed on the host +host_inst_rate 130085 # Simulator instruction rate (inst/s) +host_op_rate 137131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64179279 # Simulator tick rate (ticks/s) +host_mem_usage 313784 # Number of bytes of host memory used +host_seconds 1324.54 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 35328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 268480 # Number of bytes read from this memory -system.physmem.bytes_read::total 322048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18240 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 552 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 4195 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5032 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 214700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 415839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 3160227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3790765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 214700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 214700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 214700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 415839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 3160227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3790765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5032 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory +system.physmem.bytes_read::total 246528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127168 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3852 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1495948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 564651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 839447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2900046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1495948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1495948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1495948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 564651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 839447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2900046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3852 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5032 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3852 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 322048 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 246528 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 322048 # Total read bytes from the system interface side +system.physmem.bytesReadSys 246528 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 395 # Per bank write bursts -system.physmem.perBankRdBursts::1 288 # Per bank write bursts -system.physmem.perBankRdBursts::2 188 # Per bank write bursts -system.physmem.perBankRdBursts::3 388 # Per bank write bursts -system.physmem.perBankRdBursts::4 399 # Per bank write bursts -system.physmem.perBankRdBursts::5 367 # Per bank write bursts -system.physmem.perBankRdBursts::6 381 # Per bank write bursts -system.physmem.perBankRdBursts::7 279 # Per bank write bursts -system.physmem.perBankRdBursts::8 314 # Per bank write bursts -system.physmem.perBankRdBursts::9 341 # Per bank write bursts -system.physmem.perBankRdBursts::10 369 # Per bank write bursts -system.physmem.perBankRdBursts::11 260 # Per bank write bursts -system.physmem.perBankRdBursts::12 244 # Per bank write bursts -system.physmem.perBankRdBursts::13 279 # Per bank write bursts -system.physmem.perBankRdBursts::14 295 # Per bank write bursts -system.physmem.perBankRdBursts::15 245 # Per bank write bursts +system.physmem.perBankRdBursts::0 309 # Per bank write bursts +system.physmem.perBankRdBursts::1 223 # Per bank write bursts +system.physmem.perBankRdBursts::2 142 # Per bank write bursts +system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::4 300 # Per bank write bursts +system.physmem.perBankRdBursts::5 302 # Per bank write bursts +system.physmem.perBankRdBursts::6 262 # Per bank write bursts +system.physmem.perBankRdBursts::7 237 # Per bank write bursts +system.physmem.perBankRdBursts::8 252 # Per bank write bursts +system.physmem.perBankRdBursts::9 218 # Per bank write bursts +system.physmem.perBankRdBursts::10 293 # Per bank write bursts +system.physmem.perBankRdBursts::11 194 # Per bank write bursts +system.physmem.perBankRdBursts::12 193 # Per bank write bursts +system.physmem.perBankRdBursts::13 212 # Per bank write bursts +system.physmem.perBankRdBursts::14 211 # Per bank write bursts +system.physmem.perBankRdBursts::15 194 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 84955621000 # Total gap between requests +system.physmem.totGap 85008170000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5032 # Read request sizes (log2) +system.physmem.readPktSize::6 3852 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,98 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 467.413643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 304.114713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 362.347713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 143 20.75% 20.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 123 17.85% 38.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 63 9.14% 47.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 10.01% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 45 6.53% 64.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 51 7.40% 71.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 42 6.10% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 3.05% 80.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 132 19.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 689 # Bytes accessed per row activation -system.physmem.totQLat 114920157 # Total ticks spent queuing -system.physmem.totMemAccLat 209270157 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 25160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22837.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.936842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.366462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.047629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 237 31.18% 31.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 182 23.95% 55.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 69 9.08% 64.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 96 12.63% 76.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.61% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 5.92% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 2.37% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 14 1.84% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 64 8.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 760 # Bytes accessed per row activation +system.physmem.totQLat 36289181 # Total ticks spent queuing +system.physmem.totMemAccLat 108514181 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19260000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9420.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41587.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28170.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing +system.physmem.avgRdQLen 3.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4343 # Number of row buffer hits during reads +system.physmem.readRowHits 3085 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 16883072.54 # Average gap between requests -system.physmem.pageHitRate 86.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 81214099250 # Time in different power states -system.physmem.memoryStateTime::REF 2836600000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 905088250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2585520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2623320 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1410750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1431375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 20943000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 18306600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 5548898160 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 5548898160 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 2301036705 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 2237438385 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 48955167000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 49010955000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 56830041135 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 56819652840 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.934726 # Core power per rank (mW) -system.physmem.averagePower::1 668.812447 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 4821 # Transaction distribution -system.membus.trans_dist::ReadResp 4821 # Transaction distribution -system.membus.trans_dist::ReadExReq 211 # Transaction distribution -system.membus.trans_dist::ReadExResp 211 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 322048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 322048 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5032 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5032 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5032 # Request fanout histogram -system.membus.reqLayer0.occupancy 5681641 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46027985 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85925623 # Number of BP lookups -system.cpu.branchPred.condPredicted 68405598 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6015157 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40113883 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39024614 # Number of BTB hits +system.physmem.avgGap 22068579.96 # Average gap between requests +system.physmem.pageHitRate 80.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2721600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1485000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2339255205 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48949672500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56861323425 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.935094 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81434793722 # Time in different power states +system.physmem_0.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 733662278 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3001320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1637625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13540800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2301878880 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48982450500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56854458645 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.854443 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81486384408 # Time in different power states +system.physmem_1.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 678791592 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 85929478 # Number of BP lookups +system.cpu.branchPred.condPredicted 68409655 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6016514 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40103730 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39019729 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.284559 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3701789 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81904 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.297007 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3701200 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81899 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -303,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -324,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -345,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -367,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169911872 # number of cpu cycles simulated +system.cpu.numCycles 170016628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5595281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349266175 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85925623 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42726403 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158254745 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12044333 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingQuiesceStallCycles 37 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 592 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78952832 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17522 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169872950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.151005 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.046766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5612512 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349284796 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85929478 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42720929 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158258026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12046973 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1522 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 2068 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78953849 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17938 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169897637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150791 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.046975 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17324644 10.20% 10.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30203623 17.78% 27.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31840188 18.74% 46.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90504495 53.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17345965 10.21% 10.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30201314 17.78% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31838054 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90512304 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169872950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505707 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.055573 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17551129 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17096204 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122646615 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6731659 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5847343 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11137012 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306601093 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27639828 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5847343 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37738327 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8403981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578579 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108919553 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8385167 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278647204 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13415116 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3048397 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841923 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187656 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 31854 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 78402 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483062515 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196895890 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297562467 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006395 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169897637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505418 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.054416 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17565023 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17095500 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122663721 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6724834 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5848559 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11136257 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190151 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306621954 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27645544 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5848559 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37752791 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8406678 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 578098 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108929543 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8381968 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278665579 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13416120 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3045260 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842372 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187359 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 31268 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 80203 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483123422 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196973277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297590130 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005585 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190085586 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23420 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13351603 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34138378 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14478835 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2550837 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1806189 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264810642 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 190146493 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23418 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13341047 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34139788 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476953 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2546690 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1793951 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264825375 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214907655 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190996 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82629036 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219889900 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 214906973 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5192109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82644277 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219958197 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169872950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.265108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 169897637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017502 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52803027 31.08% 31.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36096104 21.25% 52.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65778237 38.72% 91.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13576092 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571163 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47813 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 514 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52826553 31.09% 31.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36096362 21.25% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65782146 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13572889 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571303 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47864 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 520 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169872950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169897637 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35609099 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152890 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35601312 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152935 0.28% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available @@ -475,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1075 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35725 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 330 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35738 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 318 0.00% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 815 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34388 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 217 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 812 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34382 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 216 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14076935 26.13% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3950981 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078938 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3947834 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167347451 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918969 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167350726 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918985 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -509,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33024 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165192 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245769 0.11% 78.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460683 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206710 0.10% 78.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71622 0.03% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460475 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32005523 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13376375 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32004909 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373295 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214907655 # Type of FU issued -system.cpu.iq.rate 1.264818 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53862656 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250632 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654786826 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 345480396 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204601887 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3955086 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2012108 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806636 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266634716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2135595 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601086 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214906973 # Type of FU issued +system.cpu.iq.rate 1.264035 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53853755 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654805304 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 345511813 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204602678 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952143 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2010627 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806422 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266627552 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133176 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600193 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6242234 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7548 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7115 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1834201 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6243644 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7556 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7106 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832319 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25938 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 647 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 661 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5847343 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682283 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37485 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264872462 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5848559 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681569 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36478 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264887188 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34138378 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14478835 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 34139788 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476953 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3828 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30448 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7115 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3233466 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3245683 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6479149 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207525838 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30720478 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7381817 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3814 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29479 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7106 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3233640 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247282 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6480922 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207527385 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30721175 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7379588 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15970 # number of nop insts executed -system.cpu.iew.exec_refs 43862877 # number of memory reference insts executed -system.cpu.iew.exec_branches 44936358 # Number of branches executed -system.cpu.iew.exec_stores 13142399 # Number of stores executed -system.cpu.iew.exec_rate 1.221373 # Inst execution rate -system.cpu.iew.wb_sent 206743657 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206408523 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129467920 # num instructions producing a value -system.cpu.iew.wb_consumers 221670950 # num instructions consuming a value +system.cpu.iew.exec_nop 15963 # number of nop insts executed +system.cpu.iew.exec_refs 43860513 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937173 # Number of branches executed +system.cpu.iew.exec_stores 13139338 # Number of stores executed +system.cpu.iew.exec_rate 1.220630 # Inst execution rate +system.cpu.iew.wb_sent 206744227 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206409100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129466460 # num instructions producing a value +system.cpu.iew.wb_consumers 221676348 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.214798 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584055 # average fanout of values written-back +system.cpu.iew.wb_rate 1.214052 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584034 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69532618 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69543087 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5840334 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158431709 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146553 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646732 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5841587 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158455572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146380 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73650115 46.49% 46.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41279051 26.05% 72.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22553954 14.24% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9627262 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3547678 2.24% 95.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2148088 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1282361 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 989322 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3353878 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73674398 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41276379 26.05% 72.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22551197 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9630660 6.08% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3550983 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2150131 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280461 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 988669 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3352694 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158431709 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158455572 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -641,487 +655,505 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 3353878 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3352694 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 406255589 # The number of ROB reads -system.cpu.rob.rob_writes 513821132 # The number of ROB writes -system.cpu.timesIdled 2630 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38922 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 406291105 # The number of ROB reads +system.cpu.rob.rob_writes 513842853 # The number of ROB writes +system.cpu.timesIdled 3394 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 118991 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986122 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986122 # CPI: Total CPI of All Threads -system.cpu.ipc 1.014073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.014073 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218958580 # number of integer regfile reads -system.cpu.int_regfile_writes 114511116 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904510 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441819 # number of floating regfile writes -system.cpu.cc_regfile_reads 709580018 # number of cc regfile reads -system.cpu.cc_regfile_writes 229533397 # number of cc regfile writes -system.cpu.misc_regfile_reads 59318521 # number of misc regfile reads +system.cpu.cpi 0.986730 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986730 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013448 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013448 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218960053 # number of integer regfile reads +system.cpu.int_regfile_writes 114514072 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904445 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441481 # number of floating regfile writes +system.cpu.cc_regfile_reads 709585079 # number of cc regfile reads +system.cpu.cc_regfile_writes 229544416 # number of cc regfile writes +system.cpu.misc_regfile_reads 59313443 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 119664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 7801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8632 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109774 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211691 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321465 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3512768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 7801 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 200978 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.038815 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.193155 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 193177 96.12% 96.12% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 7801 3.88% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 200978 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161464494 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82370974 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110177995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 54375 # number of replacements -system.cpu.icache.tags.tagsinuse 510.661166 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78896017 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54887 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1437.426294 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84218922500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.661166 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997385 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997385 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157960533 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157960533 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78896017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78896017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78896017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78896017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78896017 # number of overall hits -system.cpu.icache.overall_hits::total 78896017 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 56806 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 56806 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 56806 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 56806 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 56806 # number of overall misses -system.cpu.icache.overall_misses::total 56806 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 474677200 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 474677200 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 474677200 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 474677200 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 474677200 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 474677200 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78952823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78952823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78952823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78952823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78952823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78952823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000719 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000719 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000719 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000719 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000719 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8356.110270 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8356.110270 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8356.110270 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8356.110270 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 16306 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2267 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7.192766 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1919 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1919 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1919 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1919 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1919 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1919 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54887 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54887 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54887 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54887 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54887 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54887 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 380604754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 380604754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 380604754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 380604754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 380604754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 380604754 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6934.333339 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6934.333339 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 435044 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 3068 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 422406 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3291 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 894 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 5385 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 26500 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3680.652694 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 181097 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4769 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 37.973789 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 700.245747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 217.753448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 276.465568 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2486.187931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042740 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.013291 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016874 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.151745 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.224649 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 3319 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1450 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 648 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2491 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 987 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.202576 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.088501 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3104105 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3104105 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 54552 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 64413 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 118965 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 64873 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 64873 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8421 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8421 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 54552 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 72834 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 127386 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 54552 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 72834 # number of overall hits -system.cpu.l2cache.overall_hits::total 127386 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 364 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 699 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 575 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 910 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 575 # number of overall misses -system.cpu.l2cache.overall_misses::total 910 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24852997 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26184000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 51036997 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15318999 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15318999 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24852997 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 41502999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 66355996 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24852997 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 41502999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 66355996 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 54887 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 64777 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 119664 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 64873 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 64873 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8632 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8632 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54887 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 128296 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54887 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 128296 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.006103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.005619 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.005841 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.024444 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.024444 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.006103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.007833 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.007093 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.006103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.007833 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.007093 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74188.050746 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71934.065934 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73014.301860 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72601.890995 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72601.890995 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72918.676923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72918.676923 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 2973 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 134 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.186567 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 50 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 50 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 50 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 285 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 5385 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 5385 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 285 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 552 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 285 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 552 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 5385 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 6222 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20480998 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 42531748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 326822301 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13544999 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13544999 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20480998 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 35595749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 56076747 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20480998 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 35595749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 382899048 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.005264 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005231 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.024444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.024444 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.006524 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.048497 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71863.150877 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64664.956012 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67942.089457 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60691.235097 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64194.308057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64194.308057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66997.308244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61539.544841 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 72897 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.503812 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115488 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.439547 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41117509 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.087837 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 471699000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.503812 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999031 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999031 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 560.115367 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 497141250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.439547 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998905 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998905 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82528199 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82528199 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28728737 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28728737 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341838 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341838 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82532283 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82532283 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28730746 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28730746 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341850 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341850 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41070575 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41070575 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41070936 # number of overall hits -system.cpu.dcache.overall_hits::total 41070936 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89075 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89075 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22449 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22449 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 121 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41072596 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41072596 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41072957 # number of overall hits +system.cpu.dcache.overall_hits::total 41072957 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22437 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22437 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 111524 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 111524 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 111645 # number of overall misses -system.cpu.dcache.overall_misses::total 111645 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 824002993 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 824002993 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 221780748 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 221780748 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2327000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2327000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1045783741 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1045783741 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1045783741 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1045783741 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28817812 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28817812 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 111548 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 111548 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 111666 # number of overall misses +system.cpu.dcache.overall_misses::total 111666 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 835319240 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 835319240 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 222952999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 222952999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2325000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2325000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1058272239 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1058272239 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1058272239 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1058272239 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28819857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28819857 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 482 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 482 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41182099 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41182099 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41182581 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41182581 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003091 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003091 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001816 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001816 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.251037 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.251037 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41184144 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41184144 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41184623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41184623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003092 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003092 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001815 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001815 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002708 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002708 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9250.665091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9250.665091 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9879.315248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9879.315248 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8881.679389 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8881.679389 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9377.207964 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9377.207964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9367.045018 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9367.045018 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 279 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7362 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 531 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.864407 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9373.918371 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9373.918371 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9936.845345 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9936.845345 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8874.045802 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8874.045802 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9487.146690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9487.146690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9477.121407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9477.121407 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7730 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 532 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14.530075 # average number of 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WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 13871 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38233 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38233 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38233 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38233 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64732 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64732 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8559 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8559 # number of WriteReq MSHR misses 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WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1036250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1036250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 558105503 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 558105503 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 559141753 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 559141753 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 491417758 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 491417758 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74043249 # number of WriteReq MSHR miss cycles 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for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.244813 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.244813 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001783 # mshr miss rate for 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-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7616.801114 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7616.801114 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7592.042980 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7592.042980 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8643.853491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8643.853491 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8543.478261 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8543.478261 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7714.969943 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7714.969943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7716.267855 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7716.267855 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 54440 # number of replacements +system.cpu.icache.tags.tagsinuse 510.617911 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78896507 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54952 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.734951 # Average number of references to valid blocks. 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of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78953824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78953824 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000726 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000726 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000726 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000726 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000726 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000726 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10232.839803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10232.839803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10232.839803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10232.839803 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 47827 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2525 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.941386 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2365 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2365 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2365 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2365 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2365 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2365 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54952 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54952 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54952 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54952 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54952 # number of overall MSHR misses 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accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.010326 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.021424 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036250 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.010326 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.021424 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61036.144578 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66216.539197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 62113.419483 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65178.723404 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65178.723404 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 62375.363636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 62375.363636 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits 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misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 750 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1816 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4553 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104199500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29901250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134100750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 63393390 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13328500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13328500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104199500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43229750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 147429250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104199500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43229750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 210822640 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020898 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027209 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021323 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035470 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52440.613991 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58060.679612 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53597.422062 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34908.254405 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56717.021277 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56717.021277 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53865.272196 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46304.115967 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 119724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8637 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321596 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12367040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2213 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 195448 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011323 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105804 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 193235 98.87% 98.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 2213 1.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 195448 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161491500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 82814471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 110208992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3617 # Transaction distribution +system.membus.trans_dist::ReadResp 3617 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7704 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3852 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3852 # Request fanout histogram +system.membus.reqLayer0.occupancy 5007645 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 36124927 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index b068c4279..7ececc2b6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491000 # Number of ticks simulated final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2060285 # Simulator instruction rate (inst/s) -host_op_rate 2171872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1190808654 # Simulator tick rate (ticks/s) -host_mem_usage 300012 # Number of bytes of host memory used -host_seconds 83.64 # Real time elapsed on the host +host_inst_rate 1699536 # Simulator instruction rate (inst/s) +host_op_rate 1791584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 982302061 # Simulator tick rate (ticks/s) +host_mem_usage 304728 # Number of bytes of host memory used +host_seconds 101.39 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 454362795 # Wr system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 217614902 # Transaction distribution -system.membus.trans_dist::ReadResp 217637309 # Transaction distribution -system.membus.trans_dist::WriteReq 12364287 # Transaction distribution -system.membus.trans_dist::WriteResp 12364287 # Transaction distribution -system.membus.trans_dist::SoftPFReq 463 # Transaction distribution -system.membus.trans_dist::SoftPFResp 463 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 230024466 # Request fanout histogram -system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 230024466 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction +system.membus.trans_dist::ReadReq 217614902 # Transaction distribution +system.membus.trans_dist::ReadResp 217637309 # Transaction distribution +system.membus.trans_dist::WriteReq 12364287 # Transaction distribution +system.membus.trans_dist::WriteResp 12364287 # Transaction distribution +system.membus.trans_dist::SoftPFReq 463 # Transaction distribution +system.membus.trans_dist::SoftPFResp 463 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution +system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 230024466 # Request fanout histogram +system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 230024466 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 394a8f6cf..62a10ca2c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230173 # Nu sim_ticks 230173357000 # Number of ticks simulated final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1215411 # Simulator instruction rate (inst/s) -host_op_rate 1281349 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1627973861 # Simulator tick rate (ticks/s) -host_mem_usage 309492 # Number of bytes of host memory used -host_seconds 141.39 # Real time elapsed on the host +host_inst_rate 1229194 # Simulator instruction rate (inst/s) +host_op_rate 1295881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1646435898 # Simulator tick rate (ticks/s) +host_mem_usage 312932 # Number of bytes of host memory used +host_seconds 139.80 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 480751 # In system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 2361 # Transaction distribution -system.membus.trans_dist::ReadResp 2361 # Transaction distribution -system.membus.trans_dist::ReadExReq 1092 # Transaction distribution -system.membus.trans_dist::ReadExResp 1092 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3453 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,139 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits +system.cpu.dcache.overall_hits::total 40117812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses +system.cpu.dcache.overall_misses::total 1789 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. @@ -430,139 +572,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits -system.cpu.dcache.overall_hits::total 40117812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses -system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution @@ -596,5 +605,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 4576500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 2361 # Transaction distribution +system.membus.trans_dist::ReadResp 2361 # Transaction distribution +system.membus.trans_dist::ReadExReq 1092 # Transaction distribution +system.membus.trans_dist::ReadExResp 1092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3453 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3453 # Request fanout histogram +system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index c2d74a54c..85460c89a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148694 # Number of seconds simulated -sim_ticks 148694012000 # Number of ticks simulated -final_tick 148694012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148652 # Number of seconds simulated +sim_ticks 148652306000 # Number of ticks simulated +final_tick 148652306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81223 # Simulator instruction rate (inst/s) -host_op_rate 136137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91445548 # Simulator tick rate (ticks/s) -host_mem_usage 288088 # Number of bytes of host memory used -host_seconds 1626.04 # Real time elapsed on the host +host_inst_rate 83185 # Simulator instruction rate (inst/s) +host_op_rate 139426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93628996 # Simulator tick rate (ticks/s) +host_mem_usage 346568 # Number of bytes of host memory used +host_seconds 1587.67 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 223936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125888 # Number of bytes read from this memory -system.physmem.bytes_read::total 349824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 223936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 223936 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1967 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5466 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1506019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 846625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2352643 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1506019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1506019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1506019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 846625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2352643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5466 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125696 # Number of bytes read from this memory +system.physmem.bytes_read::total 350464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1964 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5476 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1512038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 845570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2357609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1512038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1512038 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1512038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 845570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2357609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5476 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5466 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5476 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 349824 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 350464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 349824 # Total read bytes from the system interface side +system.physmem.bytesReadSys 350464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 294 # Per bank write bursts -system.physmem.perBankRdBursts::1 361 # Per bank write bursts -system.physmem.perBankRdBursts::2 463 # Per bank write bursts -system.physmem.perBankRdBursts::3 372 # Per bank write bursts -system.physmem.perBankRdBursts::4 337 # Per bank write bursts -system.physmem.perBankRdBursts::5 332 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 324 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 295 # Per bank write bursts +system.physmem.perBankRdBursts::1 363 # Per bank write bursts +system.physmem.perBankRdBursts::2 461 # Per bank write bursts +system.physmem.perBankRdBursts::3 370 # Per bank write bursts +system.physmem.perBankRdBursts::4 335 # Per bank write bursts +system.physmem.perBankRdBursts::5 334 # Per bank write bursts system.physmem.perBankRdBursts::6 400 # Per bank write bursts -system.physmem.perBankRdBursts::7 384 # Per bank write bursts -system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 235 # Per bank write bursts -system.physmem.perBankRdBursts::11 262 # Per bank write bursts -system.physmem.perBankRdBursts::12 222 # Per bank write bursts -system.physmem.perBankRdBursts::13 508 # Per bank write bursts +system.physmem.perBankRdBursts::7 383 # Per bank write bursts +system.physmem.perBankRdBursts::8 340 # Per bank write bursts +system.physmem.perBankRdBursts::9 286 # Per bank write bursts +system.physmem.perBankRdBursts::10 236 # Per bank write bursts +system.physmem.perBankRdBursts::11 261 # Per bank write bursts +system.physmem.perBankRdBursts::12 219 # Per bank write bursts +system.physmem.perBankRdBursts::13 509 # Per bank write bursts system.physmem.perBankRdBursts::14 392 # Per bank write bursts -system.physmem.perBankRdBursts::15 281 # Per bank write bursts +system.physmem.perBankRdBursts::15 292 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 148693969000 # Total gap between requests +system.physmem.totGap 148652208500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5466 # Read request sizes (log2) +system.physmem.readPktSize::6 5476 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,336 +186,314 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.532444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.678629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.994757 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 454 40.36% 40.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 235 20.89% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 101 8.98% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 52 4.62% 74.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 60 5.33% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 5.24% 85.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 19 1.69% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20 1.78% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1125 # Bytes accessed per row activation -system.physmem.totQLat 38946250 # Total ticks spent queuing -system.physmem.totMemAccLat 141433750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7125.18 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.265039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.960981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.625541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 464 40.45% 40.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 245 21.36% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 104 9.07% 70.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 4.97% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 54 4.71% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.97% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.09% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 15 1.31% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 127 11.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1147 # Bytes accessed per row activation +system.physmem.totQLat 37377750 # Total ticks spent queuing +system.physmem.totMemAccLat 140052750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27380000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6825.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25875.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25575.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.35 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4331 # Number of row buffer hits during reads +system.physmem.readRowHits 4321 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27203433.77 # Average gap between requests -system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 142073657250 # Time in different power states -system.physmem.memoryStateTime::REF 4964960000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1647900000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 4982040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3500280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2718375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1909875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 22776000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 19507800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 9711461760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 9711461760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 4022315865 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3825718020 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 85683555000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 85856009250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 99447809040 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 99418106985 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.842205 # Core power per rank (mW) -system.physmem.averagePower::1 668.642442 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 3933 # Transaction distribution -system.membus.trans_dist::ReadResp 3932 # Transaction distribution -system.membus.trans_dist::UpgradeReq 296 # Transaction distribution -system.membus.trans_dist::UpgradeResp 296 # Transaction distribution -system.membus.trans_dist::ReadExReq 1533 # Transaction distribution -system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11523 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 349760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5762 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5762 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5762 # Request fanout histogram -system.membus.reqLayer0.occupancy 7167000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 51861454 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 22382097 # Number of BP lookups -system.cpu.branchPred.condPredicted 22382097 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1553409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 14143770 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13239374 # Number of BTB hits +system.physmem.avgGap 27146130.11 # Average gap between requests +system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5072760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2767875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22791600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4015280925 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 85666359000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 99421191120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.838371 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 142511183750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1172773250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3575880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1951125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19585800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3861811845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 85800972750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 99396816360 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.674456 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 142739163750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 947728750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 22375930 # Number of BP lookups +system.cpu.branchPred.condPredicted 22375930 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1550820 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14142904 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13245564 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.605694 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1523861 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22060 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.655193 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1524021 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21798 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 297388032 # number of cpu cycles simulated +system.cpu.numCycles 297304620 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27880008 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 249058784 # Number of instructions fetch has processed -system.cpu.fetch.Branches 22382097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14763235 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 267434691 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3695049 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 15 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4561 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42381 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27866919 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 248846814 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22375930 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14769585 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267364531 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3698749 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 56 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 42690 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26649696 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 257275 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 297209306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.380725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.789359 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26638460 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 257102 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 297128244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.381645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.790124 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 229177022 77.11% 77.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5084587 1.71% 78.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4138437 1.39% 80.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4791887 1.61% 81.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4876855 1.64% 83.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5109175 1.72% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5334492 1.79% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4008000 1.35% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34688851 11.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229068376 77.09% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5099613 1.72% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4127262 1.39% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4784384 1.61% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4893969 1.65% 83.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5110538 1.72% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5334476 1.80% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3994023 1.34% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34715603 11.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 297209306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075262 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.837488 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16317003 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 231094890 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26094955 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21854934 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1847524 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 359064274 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1847524 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24114798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 162761005 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 33475 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38241804 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70210700 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350324590 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 42142 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 61992199 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7946895 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 152925 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 405428411 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 972465740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 641794462 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4665474 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 297128244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075263 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.837010 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16329336 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 230975824 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26113582 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21860128 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1849374 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359242894 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1849374 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24118008 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162656356 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 38273 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38263619 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70202614 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350538626 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 41453 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 61947521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7945702 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 153558 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405817730 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972424276 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 641996744 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4657501 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 145998961 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2154 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2076 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 128653734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89733483 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32018253 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63985001 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21567740 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 341091248 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4877 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266696686 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73290 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119329162 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 250439001 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3632 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 297209306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.897336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363195 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 146388280 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2397 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2322 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128546417 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89512895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32023027 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63891013 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21581901 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341300793 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5145 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266928835 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 76764 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119543073 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250225997 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3900 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 297128244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.898362 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364631 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 171484109 57.70% 57.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54269493 18.26% 75.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33638460 11.32% 87.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19147986 6.44% 93.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10817239 3.64% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4351297 1.46% 98.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2217356 0.75% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 890190 0.30% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 393176 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171384973 57.68% 57.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54250707 18.26% 75.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33605057 11.31% 87.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19187938 6.46% 93.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10808168 3.64% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4369052 1.47% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2227260 0.75% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 898004 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 397085 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 297209306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 297128244 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 237582 7.35% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2582537 79.93% 87.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 410926 12.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 240256 7.42% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2591676 80.04% 87.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 406020 12.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211351 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167148119 62.67% 63.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789126 0.30% 63.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035938 2.64% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1214032 0.46% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66518900 24.94% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22779220 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211341 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167360520 62.70% 63.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 793230 0.30% 63.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7036198 2.64% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1213739 0.45% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66512723 24.92% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22801084 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266696686 # Type of FU issued -system.cpu.iq.rate 0.896797 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3231045 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 828907957 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 456425026 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260744620 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4999056 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4321531 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2398079 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266200144 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2516236 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18853700 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266928835 # Type of FU issued +system.cpu.iq.rate 0.897829 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3237952 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012130 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 829304993 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 456859927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 261005005 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4995637 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4315017 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2397122 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266441955 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2513491 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18899538 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33083896 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14048 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 327034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11502536 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 32863308 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14004 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 331776 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11507310 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52807 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52520 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1847524 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 126225383 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5553775 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 341096125 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 111900 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89733483 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32018253 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2073 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2221761 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 397558 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 327034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 687554 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 924641 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1612195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264577830 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65651803 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2118856 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1849374 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126083228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5521965 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341305938 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 113234 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89512895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32023027 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2291 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2224383 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 364956 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 331776 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 682604 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 926974 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1609578 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264820941 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65644877 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2107894 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 88227876 # number of memory reference insts executed -system.cpu.iew.exec_branches 14574542 # Number of branches executed -system.cpu.iew.exec_stores 22576073 # Number of stores executed -system.cpu.iew.exec_rate 0.889672 # Inst execution rate -system.cpu.iew.wb_sent 263857804 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 263142699 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208771445 # num instructions producing a value -system.cpu.iew.wb_consumers 376756650 # num instructions consuming a value +system.cpu.iew.exec_refs 88243318 # number of memory reference insts executed +system.cpu.iew.exec_branches 14594562 # Number of branches executed +system.cpu.iew.exec_stores 22598441 # Number of stores executed +system.cpu.iew.exec_rate 0.890739 # Inst execution rate +system.cpu.iew.wb_sent 264116022 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263402127 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208929627 # num instructions producing a value +system.cpu.iew.wb_consumers 376950815 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.884846 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554128 # average fanout of values written-back +system.cpu.iew.wb_rate 0.885967 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554262 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119784082 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119991036 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1557714 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 280934178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.787955 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.593006 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1555160 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280815934 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.788286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.594389 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 181002455 64.43% 64.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57799506 20.57% 85.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14236358 5.07% 90.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11930779 4.25% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4218902 1.50% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2886432 1.03% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 918195 0.33% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1050521 0.37% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6891030 2.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180962849 64.44% 64.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57749972 20.57% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14199777 5.06% 90.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11927311 4.25% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4203723 1.50% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2893126 1.03% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 916943 0.33% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048119 0.37% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6914114 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 280934178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280815934 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -561,252 +539,336 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6891030 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6914114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 615190614 # The number of ROB reads -system.cpu.rob.rob_writes 698614569 # The number of ROB writes -system.cpu.timesIdled 3122 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 178726 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615256240 # The number of ROB reads +system.cpu.rob.rob_writes 699066092 # The number of ROB writes +system.cpu.timesIdled 3079 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 176376 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.251725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.251725 # CPI: Total CPI of All Threads -system.cpu.ipc 0.444104 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.444104 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 456362005 # number of integer regfile reads -system.cpu.int_regfile_writes 239113538 # number of integer regfile writes -system.cpu.fp_regfile_reads 3275482 # number of floating regfile reads -system.cpu.fp_regfile_writes 2058196 # number of floating regfile writes -system.cpu.cc_regfile_reads 102983282 # number of cc regfile reads -system.cpu.cc_regfile_writes 60177632 # number of cc regfile writes -system.cpu.misc_regfile_reads 136798826 # number of misc regfile reads +system.cpu.cpi 2.251094 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.251094 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444229 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444229 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456513966 # number of integer regfile reads +system.cpu.int_regfile_writes 239334814 # number of integer regfile writes +system.cpu.fp_regfile_reads 3274089 # number of floating regfile reads +system.cpu.fp_regfile_writes 2057271 # number of floating regfile writes +system.cpu.cc_regfile_reads 102998380 # number of cc regfile reads +system.cpu.cc_regfile_writes 60202762 # number of cc regfile writes +system.cpu.misc_regfile_reads 136901121 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 8736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16221 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4632 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 20853 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 509376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 638784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 301 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10583 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10583 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10583 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5301999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12991249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3546296 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 5983 # number of replacements -system.cpu.icache.tags.tagsinuse 1649.665059 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26639065 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7962 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3345.775559 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 52 # number of replacements +system.cpu.dcache.tags.tagsinuse 1443.647680 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 67095165 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2013 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33330.931446 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1443.647680 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352453 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352453 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1961 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 441 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.478760 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134197329 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134197329 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46580786 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46580786 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513865 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513865 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67094651 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67094651 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67094651 # number of overall hits +system.cpu.dcache.overall_hits::total 67094651 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1141 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1866 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1866 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3007 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3007 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3007 # number of overall misses +system.cpu.dcache.overall_misses::total 3007 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64283437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64283437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116004574 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116004574 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 180288011 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 180288011 # number of demand (read+write) miss cycles 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# miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000091 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000091 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56339.559159 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56339.559159 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62167.510182 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62167.510182 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59956.106086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59956.106086 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 248 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.600000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked 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394374749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26649694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26649694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26649694 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26649694 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26649694 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26649694 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses 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overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8262 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293853251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 293853251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293853251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 293853251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293853251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 293853251 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000310 # mshr miss rate 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demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 307237000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196758000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110479000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 307237000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.907368 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.474895 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990826 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.548180 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.439643 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.548180 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56229.214286 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63407.258065 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57021.098119 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.685811 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.685811 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54695.205479 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54695.205479 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56229.214286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56617.437722 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56368.895189 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.556436 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.556436 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56008.539710 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63556.844548 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56833.417850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.540123 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.540123 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54198.303979 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54198.303979 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 52 # number of replacements -system.cpu.dcache.tags.tagsinuse 1451.665096 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 67147234 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33373.376740 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1451.665096 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.354410 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.354410 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1960 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1416 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.478516 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 134301424 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 134301424 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46632911 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46632911 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67146804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67146804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67146804 # number of overall hits -system.cpu.dcache.overall_hits::total 67146804 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1064 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1064 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2902 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2902 # number of overall misses -system.cpu.dcache.overall_misses::total 2902 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63689380 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63689380 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116173296 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116173296 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 179862676 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 179862676 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 179862676 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 179862676 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46633975 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46633975 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67149706 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67149706 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67149706 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67149706 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59858.439850 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59858.439850 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63206.363439 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63206.363439 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61978.868367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61978.868367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61978.868367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 303 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 10 # number of writebacks -system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 590 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 590 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 591 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 591 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 591 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 474 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 474 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1837 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1837 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2311 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2311 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2311 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2311 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33789250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33789250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111812454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 111812454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145601704 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 145601704 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145601704 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 145601704 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000090 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71285.337553 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71285.337553 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60866.877518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60866.877518 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63003.766335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63003.766335 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 8632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15986 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 20676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 630528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 327 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10507 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10507 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5263999 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 12826749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3560824 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3943 # Transaction distribution +system.membus.trans_dist::ReadResp 3943 # Transaction distribution +system.membus.trans_dist::UpgradeReq 324 # Transaction distribution +system.membus.trans_dist::UpgradeResp 324 # Transaction distribution +system.membus.trans_dist::ReadExReq 1533 # Transaction distribution +system.membus.trans_dist::ReadExResp 1533 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11600 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5800 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5800 # Request fanout histogram +system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 51890176 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 9ca2241e2..7159169af 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962845 # Number of seconds simulated -sim_ticks 1962844580000 # Number of ticks simulated -final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962843 # Number of seconds simulated +sim_ticks 1962842856000 # Number of ticks simulated +final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1184099 # Simulator instruction rate (inst/s) -host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38148129943 # Simulator tick rate (ticks/s) -host_mem_usage 318172 # Number of bytes of host memory used -host_seconds 51.45 # Real time elapsed on the host -sim_insts 60925667 # Number of instructions simulated -sim_ops 60925667 # Number of ops (including micro ops) simulated +host_inst_rate 1228880 # Simulator instruction rate (inst/s) +host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39594262798 # Simulator tick rate (ticks/s) +host_mem_usage 373652 # Number of bytes of host memory used +host_seconds 49.57 # Real time elapsed on the host +sim_insts 60920382 # Number of instructions simulated +sim_ops 60920382 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory -system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408360 # Number of read requests accepted -system.physmem.writeReqs 162776 # Number of write requests accepted -system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408371 # Number of read requests accepted +system.physmem.writeReqs 162787 # Number of write requests accepted +system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side +system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25705 # Per bank write bursts system.physmem.perBankRdBursts::1 25985 # Per bank write bursts -system.physmem.perBankRdBursts::2 25732 # Per bank write bursts -system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::2 25737 # Per bank write bursts +system.physmem.perBankRdBursts::3 25534 # Per bank write bursts system.physmem.perBankRdBursts::4 24847 # Per bank write bursts -system.physmem.perBankRdBursts::5 24747 # Per bank write bursts +system.physmem.perBankRdBursts::5 24754 # Per bank write bursts system.physmem.perBankRdBursts::6 25534 # Per bank write bursts -system.physmem.perBankRdBursts::7 25495 # Per bank write bursts +system.physmem.perBankRdBursts::7 25489 # Per bank write bursts system.physmem.perBankRdBursts::8 25150 # Per bank write bursts system.physmem.perBankRdBursts::9 25518 # Per bank write bursts system.physmem.perBankRdBursts::10 25462 # Per bank write bursts -system.physmem.perBankRdBursts::11 25292 # Per bank write bursts +system.physmem.perBankRdBursts::11 25296 # Per bank write bursts system.physmem.perBankRdBursts::12 25577 # Per bank write bursts system.physmem.perBankRdBursts::13 25454 # Per bank write bursts system.physmem.perBankRdBursts::14 26241 # Per bank write bursts -system.physmem.perBankRdBursts::15 25973 # Per bank write bursts -system.physmem.perBankWrBursts::0 10613 # Per bank write bursts -system.physmem.perBankWrBursts::1 10753 # Per bank write bursts -system.physmem.perBankWrBursts::2 9796 # Per bank write bursts -system.physmem.perBankWrBursts::3 9387 # Per bank write bursts -system.physmem.perBankWrBursts::4 8893 # Per bank write bursts -system.physmem.perBankWrBursts::5 9110 # Per bank write bursts -system.physmem.perBankWrBursts::6 9958 # Per bank write bursts -system.physmem.perBankWrBursts::7 9669 # Per bank write bursts -system.physmem.perBankWrBursts::8 9689 # Per bank write bursts -system.physmem.perBankWrBursts::9 9901 # Per bank write bursts -system.physmem.perBankWrBursts::10 9876 # Per bank write bursts -system.physmem.perBankWrBursts::11 10215 # Per bank write bursts -system.physmem.perBankWrBursts::12 10815 # Per bank write bursts -system.physmem.perBankWrBursts::13 10652 # Per bank write bursts -system.physmem.perBankWrBursts::14 10531 # Per bank write bursts -system.physmem.perBankWrBursts::15 10637 # Per bank write bursts +system.physmem.perBankRdBursts::15 25977 # Per bank write bursts +system.physmem.perBankWrBursts::0 10598 # Per bank write bursts +system.physmem.perBankWrBursts::1 10761 # Per bank write bursts +system.physmem.perBankWrBursts::2 9727 # Per bank write bursts +system.physmem.perBankWrBursts::3 9433 # Per bank write bursts +system.physmem.perBankWrBursts::4 8910 # Per bank write bursts +system.physmem.perBankWrBursts::5 9140 # Per bank write bursts +system.physmem.perBankWrBursts::6 9908 # Per bank write bursts +system.physmem.perBankWrBursts::7 9771 # Per bank write bursts +system.physmem.perBankWrBursts::8 9710 # Per bank write bursts +system.physmem.perBankWrBursts::9 9867 # Per bank write bursts +system.physmem.perBankWrBursts::10 9923 # Per bank write bursts +system.physmem.perBankWrBursts::11 10306 # Per bank write bursts +system.physmem.perBankWrBursts::12 10733 # Per bank write bursts +system.physmem.perBankWrBursts::13 10678 # Per bank write bursts +system.physmem.perBankWrBursts::14 10553 # Per bank write bursts +system.physmem.perBankWrBursts::15 10567 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1962839541500 # Total gap between requests +system.physmem.totGap 1962837817500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408360 # Read request sizes (log2) +system.physmem.readPktSize::6 408371 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162776 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 162787 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,173 +158,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads -system.physmem.totQLat 2202002500 # Total ticks spent queuing -system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads +system.physmem.totQLat 2189518000 # Total ticks spent queuing +system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing -system.physmem.readRowHits 365785 # Number of row buffer hits during reads -system.physmem.writeRowHits 133797 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes -system.physmem.avgGap 3436728.80 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states -system.physmem.memoryStateTime::REF 65543660000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.686708 # Core power per rank (mW) -system.physmem.averagePower::1 670.738650 # Core power per rank (mW) +system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing +system.physmem.readRowHits 365775 # Number of row buffer hits during reads +system.physmem.writeRowHits 133752 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes +system.physmem.avgGap 3436593.41 # Average gap between requests +system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.687203 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states +system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.737211 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states +system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7534386 # DTB read hits +system.cpu0.dtb.read_hits 7535038 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5126601 # DTB write hits +system.cpu0.dtb.write_hits 5127057 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12660987 # DTB hits +system.cpu0.dtb.data_hits 12662095 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses @@ -344,32 +349,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925689160 # number of cpu cycles simulated +system.cpu0.numCycles 3925685712 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47974635 # Number of instructions committed -system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses +system.cpu0.committedInsts 47981838 # Number of instructions committed +system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses -system.cpu0.num_func_calls 1202793 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44501266 # number of integer instructions +system.cpu0.num_func_calls 1202945 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44508329 # number of integer instructions system.cpu0.num_fp_insts 212945 # number of float instructions -system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written +system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written -system.cpu0.num_mem_refs 12702031 # number of memory refs -system.cpu0.num_load_insts 7562183 # Number of load instructions -system.cpu0.num_store_insts 5139848 # Number of store instructions -system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles +system.cpu0.num_mem_refs 12703139 # number of memory refs +system.cpu0.num_load_insts 7562835 # Number of load instructions +system.cpu0.num_store_insts 5140304 # Number of store instructions +system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles -system.cpu0.Branches 7223323 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction -system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction +system.cpu0.Branches 7224625 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction +system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction +system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction @@ -397,11 +402,11 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction +system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47983653 # Class of executed instruction +system.cpu0.op_class::total 47990856 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed @@ -417,12 +422,12 @@ system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # nu system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -487,98 +492,98 @@ system.cpu0.kern.mode_switch_good::kernel 0.195209 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3098 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1190018 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1190069 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits -system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5575 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1199856 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1199856 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1199856 # number of overall misses -system.cpu0.dcache.overall_misses::total 1199856 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27226306250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27226306250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10348541688 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10348541688 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149709000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149709000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses +system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits +system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses +system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq 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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,62 +592,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of 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uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267126500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267126500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728626000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728626000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127457 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127457 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.writebacks::writebacks 685914 # number of writebacks +system.cpu0.dcache.writebacks::total 685914 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942274 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942274 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257633 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 257633 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5579 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5579 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199907 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1199907 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199907 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1199907 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25214933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25214933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9773693814 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9773693814 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122568000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122568000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31544105 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31544105 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34988626814 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34988626814 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34988626814 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34988626814 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267119000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267119000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728620000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728620000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127450 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127450 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097053 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097053 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26759.661203 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26759.661203 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37936.498096 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37936.498096 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.695893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.695893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5654.078688 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5654.078688 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -650,13 +655,13 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 699671 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 699791 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.391652 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47290432 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700302 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.528626 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391652 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -665,44 +670,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits -system.cpu0.icache.overall_hits::total 47283349 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses -system.cpu0.icache.overall_misses::total 700305 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits +system.cpu0.icache.overall_hits::total 47290432 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700425 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700425 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700425 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700425 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700425 # number of overall misses +system.cpu0.icache.overall_misses::total 700425 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9965953746 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9965953746 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9965953746 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9965953746 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9965953746 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9965953746 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,51 +716,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2382379 # DTB read hits +system.cpu1.dtb.read_hits 2381610 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1702197 # DTB write hits +system.cpu1.dtb.write_hits 1701782 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4084576 # DTB hits +system.cpu1.dtb.data_hits 4083392 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1808740 # ITB hits +system.cpu1.itb.fetch_hits 1808769 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1809804 # ITB accesses +system.cpu1.itb.fetch_accesses 1809833 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -768,87 +773,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923834014 # number of cpu cycles simulated +system.cpu1.numCycles 3923834021 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12951032 # Number of instructions committed -system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses +system.cpu1.committedInsts 12938544 # Number of instructions committed +system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses -system.cpu1.num_func_calls 411532 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11936898 # number of integer instructions +system.cpu1.num_func_calls 411382 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11924615 # number of integer instructions system.cpu1.num_fp_insts 171199 # number of float instructions -system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written -system.cpu1.num_mem_refs 4107226 # number of memory refs -system.cpu1.num_load_insts 2395961 # Number of load instructions -system.cpu1.num_store_insts 1711265 # Number of store instructions -system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles -system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles -system.cpu1.Branches 1849703 # Number of branches fetched -system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction -system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction -system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction -system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 4106042 # number of memory refs +system.cpu1.num_load_insts 2395192 # Number of load instructions +system.cpu1.num_store_insts 1710850 # Number of store instructions +system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles +system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles +system.cpu1.Branches 1847277 # Number of branches fetched +system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction +system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12953911 # Class of executed instruction +system.cpu1.op_class::total 12941423 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -870,7 +875,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # nu system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed @@ -879,108 +884,108 @@ system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # nu system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71465 # number of callpals executed +system.cpu1.kern.callpal::total 71468 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 803 -system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::kernel 804 +system.cpu1.kern.mode_good::user 368 system.cpu1.kern.mode_good::idle 436 -system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1968 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 157269 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 157282 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits -system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits +system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits +system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 172223 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 172223 # number of overall misses -system.cpu1.dcache.overall_misses::total 172223 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1389994499 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1389994499 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079772299 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1079772299 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80592000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80592000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43791416 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43791416 # number of StoreCondReq miss cycles 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-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56202 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56202 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3984352 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3984352 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3984352 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3984352 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049259 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049259 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034668 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034668 # miss rate for WriteReq accesses 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overall miss latency +system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 172235 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 172235 # number of overall misses +system.cpu1.dcache.overall_misses::total 172235 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1388298999 # number of ReadReq miss cycles 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0.106167 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043241 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043241 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043241 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043241 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.991181 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.991181 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18890.673492 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18890.673492 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9051.274851 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9051.274851 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.307525 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.307525 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14327.368427 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14327.368427 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -989,62 +994,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 107940 # number of writebacks -system.cpu1.dcache.writebacks::total 107940 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 107942 # number of writebacks +system.cpu1.dcache.writebacks::total 107942 # number of writebacks system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57126 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57126 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8902 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8902 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5962 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5962 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172223 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172223 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172223 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172223 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1159712501 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1159712501 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962952701 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962952701 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62788000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62788000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31865584 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31865584 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2122665202 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2122665202 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2122665202 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2122665202 # number of overall MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57138 # number of WriteReq MSHR misses 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accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049259 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034668 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034668 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157065 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157065 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106082 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106082 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043225 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043225 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7053.246461 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7053.246461 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.780946 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.780946 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726754500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726754500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749201000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749201000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049276 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049276 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034684 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034684 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157078 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157078 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106167 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1052,13 +1057,13 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 318302 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 318148 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1066,44 +1071,44 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits -system.cpu1.icache.overall_hits::total 12635057 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses -system.cpu1.icache.overall_misses::total 318854 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits +system.cpu1.icache.overall_hits::total 12622723 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses +system.cpu1.icache.overall_misses::total 318700 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1112,30 +1117,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1208,7 +1213,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -1217,14 +1222,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1240,8 +1245,8 @@ system.iocache.overall_misses::tsunami.ide 176 # system.iocache.overall_misses::total 176 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles @@ -1264,17 +1269,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1290,8 +1295,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 176 system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles @@ -1306,187 +1311,187 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276130.244056 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276130.244056 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342754 # number of replacements -system.l2c.tags.tagsinuse 65220.433043 # Cycle average of tags in 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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765820 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.867130 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954109 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975506 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964819 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475999 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119678 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417896 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173317 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173317 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942939 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766781 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.867973 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975532 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964856 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475985 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119692 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.417881 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173319 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173319 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52550.828390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59817.406143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52934.752136 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.230223 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.575758 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.442405 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.871508 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.176663 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10026.386313 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56413.793892 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61161.826847 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56635.575673 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1621,96 +1626,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292732 # Transaction distribution -system.membus.trans_dist::ReadResp 292732 # Transaction distribution +system.membus.trans_dist::ReadReq 292731 # Transaction distribution +system.membus.trans_dist::ReadResp 292731 # Transaction distribution system.membus.trans_dist::WriteReq 14079 # Transaction distribution system.membus.trans_dist::WriteResp 14079 # Transaction distribution -system.membus.trans_dist::Writeback 121224 # Transaction distribution +system.membus.trans_dist::Writeback 121235 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution -system.membus.trans_dist::ReadExReq 124094 # Transaction distribution -system.membus.trans_dist::ReadExResp 123249 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution +system.membus.trans_dist::ReadExReq 124107 # Transaction distribution +system.membus.trans_dist::ReadExResp 123261 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22113 # Total snoops (count) -system.membus.snoop_fanout::samples 600297 # Request fanout histogram +system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22119 # Total snoops (count) +system.membus.snoop_fanout::samples 600328 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600297 # Request fanout histogram -system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 600328 # Request fanout histogram +system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 99450 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 99473 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 166d29f48..5c3a9c7d0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920428 # Number of seconds simulated -sim_ticks 1920427877000 # Number of ticks simulated -final_tick 1920427877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920419 # Number of seconds simulated +sim_ticks 1920418772000 # Number of ticks simulated +final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 694902 # Simulator instruction rate (inst/s) -host_op_rate 694902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23785763794 # Simulator tick rate (ticks/s) -host_mem_usage 317148 # Number of bytes of host memory used -host_seconds 80.74 # Real time elapsed on the host -sim_insts 56105324 # Number of instructions simulated -sim_ops 56105324 # Number of ops (including micro ops) simulated +host_inst_rate 1235696 # Simulator instruction rate (inst/s) +host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42298287542 # Simulator tick rate (ticks/s) +host_mem_usage 370580 # Number of bytes of host memory used +host_seconds 45.40 # Real time elapsed on the host +sim_insts 56102800 # Number of instructions simulated +sim_ops 56102800 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25710016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404096 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388411 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory +system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401719 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115689 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115689 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12944149 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13387650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3855441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3855441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3855441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12944149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17243091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401719 # Number of read requests accepted -system.physmem.writeReqs 157241 # Number of write requests accepted -system.physmem.readBursts 401719 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157241 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25703424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 9932992 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25710016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10063424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2011 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401711 # Number of read requests accepted +system.physmem.writeReqs 157234 # Number of write requests accepted +system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue +system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25160 # Per bank write bursts system.physmem.perBankRdBursts::1 25539 # Per bank write bursts system.physmem.perBankRdBursts::2 25602 # Per bank write bursts -system.physmem.perBankRdBursts::3 25522 # Per bank write bursts +system.physmem.perBankRdBursts::3 25523 # Per bank write bursts system.physmem.perBankRdBursts::4 24974 # Per bank write bursts -system.physmem.perBankRdBursts::5 24970 # Per bank write bursts +system.physmem.perBankRdBursts::5 24969 # Per bank write bursts system.physmem.perBankRdBursts::6 24210 # Per bank write bursts -system.physmem.perBankRdBursts::7 24489 # Per bank write bursts +system.physmem.perBankRdBursts::7 24487 # Per bank write bursts system.physmem.perBankRdBursts::8 25140 # Per bank write bursts system.physmem.perBankRdBursts::9 24800 # Per bank write bursts -system.physmem.perBankRdBursts::10 25361 # Per bank write bursts -system.physmem.perBankRdBursts::11 24836 # Per bank write bursts +system.physmem.perBankRdBursts::10 25360 # Per bank write bursts +system.physmem.perBankRdBursts::11 24834 # Per bank write bursts system.physmem.perBankRdBursts::12 24395 # Per bank write bursts system.physmem.perBankRdBursts::13 25368 # Per bank write bursts system.physmem.perBankRdBursts::14 25772 # Per bank write bursts -system.physmem.perBankRdBursts::15 25478 # Per bank write bursts -system.physmem.perBankWrBursts::0 10040 # Per bank write bursts -system.physmem.perBankWrBursts::1 9905 # Per bank write bursts -system.physmem.perBankWrBursts::2 10447 # Per bank write bursts -system.physmem.perBankWrBursts::3 9982 # Per bank write bursts -system.physmem.perBankWrBursts::4 9551 # Per bank write bursts -system.physmem.perBankWrBursts::5 9392 # Per bank write bursts -system.physmem.perBankWrBursts::6 8805 # Per bank write bursts -system.physmem.perBankWrBursts::7 8555 # Per bank write bursts -system.physmem.perBankWrBursts::8 9942 # Per bank write bursts -system.physmem.perBankWrBursts::9 8777 # Per bank write bursts -system.physmem.perBankWrBursts::10 9524 # Per bank write bursts -system.physmem.perBankWrBursts::11 9288 # Per bank write bursts -system.physmem.perBankWrBursts::12 9847 # Per bank write bursts -system.physmem.perBankWrBursts::13 10608 # Per bank write bursts -system.physmem.perBankWrBursts::14 10278 # Per bank write bursts -system.physmem.perBankWrBursts::15 10262 # Per bank write bursts +system.physmem.perBankRdBursts::15 25477 # Per bank write bursts +system.physmem.perBankWrBursts::0 10048 # Per bank write bursts +system.physmem.perBankWrBursts::1 9910 # Per bank write bursts +system.physmem.perBankWrBursts::2 10442 # Per bank write bursts +system.physmem.perBankWrBursts::3 9959 # Per bank write bursts +system.physmem.perBankWrBursts::4 9552 # Per bank write bursts +system.physmem.perBankWrBursts::5 9342 # Per bank write bursts +system.physmem.perBankWrBursts::6 8789 # Per bank write bursts +system.physmem.perBankWrBursts::7 8561 # Per bank write bursts +system.physmem.perBankWrBursts::8 9905 # Per bank write bursts +system.physmem.perBankWrBursts::9 8742 # Per bank write bursts +system.physmem.perBankWrBursts::10 9526 # Per bank write bursts +system.physmem.perBankWrBursts::11 9262 # Per bank write bursts +system.physmem.perBankWrBursts::12 9811 # Per bank write bursts +system.physmem.perBankWrBursts::13 10568 # Per bank write bursts +system.physmem.perBankWrBursts::14 10305 # Per bank write bursts +system.physmem.perBankWrBursts::15 10316 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1920415956000 # Total gap between requests +system.physmem.totGap 1920406851000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401719 # Read request sizes (log2) +system.physmem.readPktSize::6 401711 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157241 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401602 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157234 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -149,119 +149,118 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.458715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.725513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.454187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15065 22.68% 22.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11458 17.25% 39.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4677 7.04% 46.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3146 4.74% 51.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3014 4.54% 56.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1853 2.79% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1319 1.99% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1472 2.22% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24425 36.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5535 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 72.556098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2836.858046 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5532 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5535 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.040289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.079799 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.913440 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4499 81.28% 81.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 176 3.18% 84.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 297 5.37% 89.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.90% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 97 1.75% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 48 0.87% 93.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.20% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 7 0.13% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 21 0.38% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.13% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.25% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.11% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 94.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 11 0.20% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 48 0.87% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.29% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.34% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 91 1.64% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 36 0.65% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 14 0.25% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.25% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.16% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5535 # Writes before turning the bus around for reads -system.physmem.totQLat 2119831750 # Total ticks spent queuing -system.physmem.totMemAccLat 9650131750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5278.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads +system.physmem.totQLat 2115529750 # Total ticks spent queuing +system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24028.26 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s @@ -271,57 +270,62 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing -system.physmem.readRowHits 359880 # Number of row buffer hits during reads -system.physmem.writeRowHits 130510 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.08 # Row buffer hit rate for writes -system.physmem.avgGap 3435694.78 # Average gap between requests -system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1801057353000 # Time in different power states -system.physmem.memoryStateTime::REF 64127180000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55239785750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245964600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 256238640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134206875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 139812750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1563634800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1568970000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 496866960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 508848480 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 125432764080 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 125432764080 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 64118860245 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 64485707400 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1096009968750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1095688173000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1288002266310 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1288080514350 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.686297 # Core power per rank (mW) -system.physmem.averagePower::1 670.727042 # Core power per rank (mW) +system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing +system.physmem.readRowHits 359951 # Number of row buffer hits during reads +system.physmem.writeRowHits 130246 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes +system.physmem.avgGap 3435770.69 # Average gap between requests +system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.686102 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states +system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.730762 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states +system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9053154 # DTB read hits -system.cpu.dtb.read_misses 10325 # DTB read misses +system.cpu.dtb.read_hits 9052701 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728854 # DTB read accesses -system.cpu.dtb.write_hits 6349573 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6349364 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15402727 # DTB hits -system.cpu.dtb.data_misses 11467 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15402065 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020785 # DTB accesses -system.cpu.itb.fetch_hits 4974627 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973977 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979637 # ITB accesses +system.cpu.itb.fetch_accesses 4978974 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -334,34 +338,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840855754 # number of cpu cycles simulated +system.cpu.numCycles 3840837544 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56105324 # Number of instructions committed -system.cpu.committedOps 56105324 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51980283 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1481352 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461346 # number of instructions that are conditional controls -system.cpu.num_int_insts 51980283 # number of integer instructions -system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71211532 # number of times the integer registers were read -system.cpu.num_int_register_writes 38461399 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15455353 # number of memory refs -system.cpu.num_load_insts 9090013 # Number of load instructions -system.cpu.num_store_insts 6365340 # Number of store instructions -system.cpu.num_idle_cycles 3589191785.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251663968.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065523 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934477 # Percentage of idle cycles -system.cpu.Branches 8413247 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197750 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36174854 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 61015 0.11% 70.27% # Class of executed instruction +system.cpu.committedInsts 56102800 # Number of instructions committed +system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1481300 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls +system.cpu.num_int_insts 51978055 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read +system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15454652 # number of memory refs +system.cpu.num_load_insts 9089529 # Number of load instructions +system.cpu.num_store_insts 6365123 # Number of store instructions +system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934485 # Percentage of idle cycles +system.cpu.Branches 8412940 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38089 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -387,34 +391,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9317103 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371414 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953297 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56117158 # Class of executed instruction +system.cpu.op_class::total 56114619 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6382 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74898 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73531 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73531 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149125 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858233349500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91228000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737074000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61365491500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920427143000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692239 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814077 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -450,10 +454,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175962 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -462,26 +466,26 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192910 # number of callpals executed +system.cpu.kern.callpal::total 192900 # number of callpals executed system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1914 +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 system.cpu.kern.mode_good::user 1743 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.324352 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081429 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392857 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46106755000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5190620000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869129766000 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390139 # number of replacements +system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1389979 # number of replacements system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14031130 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390651 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.089613 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy @@ -491,72 +495,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63077780 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63077780 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7803062 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7803062 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648845 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648845 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648845 # number of overall hits -system.cpu.dcache.overall_hits::total 13648845 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304213 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304213 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17228 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17228 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373441 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373441 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373441 # number of overall misses -system.cpu.dcache.overall_misses::total 1373441 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29002641750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29002641750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10915376130 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10915376130 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228802500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228802500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39918017880 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39918017880 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39918017880 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39918017880 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8872290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8872290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149996 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149996 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200258 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200258 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15022286 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15022286 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15022286 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15022286 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120513 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120513 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049466 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049466 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27124.843111 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27124.843111 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35880.702435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35880.702435 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13280.850940 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13280.850940 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29064.239294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29064.239294 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits +system.cpu.dcache.overall_hits::total 13648338 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses +system.cpu.dcache.overall_misses::total 1373292 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -565,54 +569,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834534 # number of writebacks -system.cpu.dcache.writebacks::total 834534 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069228 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069228 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304213 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304213 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17228 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17228 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373441 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373441 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373441 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373441 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26738553250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26738553250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10254282870 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10254282870 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194333500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194333500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36992836120 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36992836120 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36992836120 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36992836120 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009400000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009400000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433673000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433673000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120513 # mshr miss rate for ReadReq accesses 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latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25007.344785 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33707.576172 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33707.576172 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11280.096355 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11280.096355 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency 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928469 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.440358 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 927664 # number of replacements +system.cpu.icache.tags.tagsinuse 508.305908 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55186285 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928175 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.456767 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.305941 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 508.305908 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -635,44 +639,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57045788 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57045788 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55188530 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55188530 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55188530 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55188530 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55188530 # number of overall hits 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12909899750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12909899750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12909899750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12909899750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12909899750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12909899750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56114620 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56114620 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56114620 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56114620 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56114620 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56114620 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016544 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016544 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016544 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016544 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016544 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016544 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13906.509773 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13906.509773 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13906.509773 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13906.509773 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,135 +685,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928629 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928629 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928629 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928629 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928629 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928629 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11049312500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11049312500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11049312500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11049312500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11049312500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11049312500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016548 # 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11898.521907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.521907 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928335 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928335 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928335 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928335 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928335 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928335 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048066250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11048066250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048066250 # number of demand (read+write) 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ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893600000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893600000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227783000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227783000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250318 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141560 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607051619 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607051619 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802917750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20907900119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21710817869 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802917750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20907900119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21710817869 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334182500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334182500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893599000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893599000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227781500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227781500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141588 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173372 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173372 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60251.673813 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52587.208918 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52944.379882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56616.277700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56616.277700 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -885,41 +889,41 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2022188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304196 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857238 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649188 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5506426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59430976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142466452 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201897428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41901 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3195557 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013057 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113520 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153832 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3195557 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424565000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395517500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186897880 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -992,7 +996,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406189794 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -1001,14 +1005,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352352 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525032000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352352 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084522 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084522 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1022,14 +1026,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634918911 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634918911 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1046,19 +1050,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206323 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756971 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1072,14 +1076,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474214911 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474214911 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1088,55 +1092,55 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292355 # Transaction distribution -system.membus.trans_dist::ReadResp 292355 # Transaction distribution +system.membus.trans_dist::ReadReq 292351 # Transaction distribution +system.membus.trans_dist::ReadResp 292351 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115689 # Transaction distribution +system.membus.trans_dist::Writeback 115682 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116723 # Transaction distribution -system.membus.trans_dist::ReadExResp 116723 # Transaction distribution +system.membus.trans_dist::ReadExReq 116719 # Transaction distribution +system.membus.trans_dist::ReadExResp 116719 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30500948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35818004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 559521 # Request fanout histogram +system.membus.snoop_fanout::samples 559506 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 559521 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 559521 # Request fanout histogram -system.membus.reqLayer0.occupancy 30373000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 559506 # Request fanout histogram +system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1824623000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751921620 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index a51b2d079..def60114c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802895 # Nu sim_ticks 2802895103500 # Number of ticks simulated final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 967895 # Simulator instruction rate (inst/s) -host_op_rate 1179365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18476638236 # Simulator tick rate (ticks/s) -host_mem_usage 571628 # Number of bytes of host memory used -host_seconds 151.70 # Real time elapsed on the host +host_inst_rate 834307 # Simulator instruction rate (inst/s) +host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15926512431 # Simulator tick rate (ticks/s) +host_mem_usage 572876 # Number of bytes of host memory used +host_seconds 175.99 # Real time elapsed on the host sim_insts 146829031 # Number of instructions simulated sim_ops 178908942 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -93,6 +93,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -114,6 +122,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7967 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 20339962 # DTB read hits @@ -135,6 +161,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 36731133 # DTB hits system.cpu0.dtb.misses 7967 # DTB misses system.cpu0.dtb.accesses 36739100 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -156,6 +190,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 3358 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 97440315 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -371,15 +423,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 252403 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. @@ -544,6 +593,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -565,6 +622,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3358 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 12173884 # DTB read hits @@ -586,6 +661,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 19761077 # DTB hits system.cpu1.dtb.misses 3358 # DTB misses system.cpu1.dtb.accesses 19764435 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -607,6 +690,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 1734 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 53671431 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -820,15 +921,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 48598 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 5c160a43e..fb9bec115 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1064003 # Simulator instruction rate (inst/s) -host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20746494205 # Simulator tick rate (ticks/s) -host_mem_usage 558936 # Number of bytes of host memory used -host_seconds 134.19 # Real time elapsed on the host +host_inst_rate 1374338 # Simulator instruction rate (inst/s) +host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26797569978 # Simulator tick rate (ticks/s) +host_mem_usage 615488 # Number of bytes of host memory used +host_seconds 103.89 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -70,6 +70,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -91,6 +99,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 10029 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 31526301 # DTB read hits @@ -112,6 +138,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 54650764 # DTB hits system.cpu.dtb.misses 10029 # DTB misses system.cpu.dtb.accesses 54660793 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -133,6 +167,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 147039592 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ede2b82db..391769400 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.867049 # Number of seconds simulated -sim_ticks 2867048515500 # Number of ticks simulated -final_tick 2867048515500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868319 # Number of seconds simulated +sim_ticks 2868318696500 # Number of ticks simulated +final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 753572 # Simulator instruction rate (inst/s) -host_op_rate 911512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16376301643 # Simulator tick rate (ticks/s) -host_mem_usage 607016 # Number of bytes of host memory used -host_seconds 175.07 # Real time elapsed on the host -sim_insts 131930165 # Number of instructions simulated -sim_ops 159581077 # Number of ops (including micro ops) simulated +host_inst_rate 534652 # Simulator instruction rate (inst/s) +host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11631340017 # Simulator tick rate (ticks/s) +host_mem_usage 586476 # Number of bytes of host memory used +host_seconds 246.60 # Real time elapsed on the host +sim_insts 131846562 # Number of instructions simulated +sim_ops 159471778 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 233060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 810048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9243456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 53844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 455584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1704320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12502168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 233060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 53844 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8696768 # Number of bytes written to this memory +system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8714512 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12095 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13183 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 144429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 26630 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 204504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135887 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 282537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3224032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 18780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 158903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 594451 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4360641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 18780 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3033352 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3039541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3033352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 288712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3224032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 18780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 158917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 594451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7400182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 204505 # Number of read requests accepted -system.physmem.writeReqs 176547 # Number of write requests accepted -system.physmem.readBursts 204505 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 176547 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13079232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue -system.physmem.bytesWritten 10932800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12502232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11032848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5691 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15171 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12666 # Per bank write bursts -system.physmem.perBankRdBursts::1 12263 # Per bank write bursts -system.physmem.perBankRdBursts::2 12897 # Per bank write bursts -system.physmem.perBankRdBursts::3 12449 # Per bank write bursts -system.physmem.perBankRdBursts::4 21010 # Per bank write bursts -system.physmem.perBankRdBursts::5 12626 # Per bank write bursts -system.physmem.perBankRdBursts::6 12991 # Per bank write bursts -system.physmem.perBankRdBursts::7 13024 # Per bank write bursts -system.physmem.perBankRdBursts::8 12039 # Per bank write bursts -system.physmem.perBankRdBursts::9 12109 # Per bank write bursts -system.physmem.perBankRdBursts::10 12276 # Per bank write bursts -system.physmem.perBankRdBursts::11 10996 # Per bank write bursts -system.physmem.perBankRdBursts::12 11725 # Per bank write bursts -system.physmem.perBankRdBursts::13 12231 # Per bank write bursts -system.physmem.perBankRdBursts::14 11672 # Per bank write bursts -system.physmem.perBankRdBursts::15 11389 # Per bank write bursts -system.physmem.perBankWrBursts::0 10702 # Per bank write bursts -system.physmem.perBankWrBursts::1 10814 # Per bank write bursts -system.physmem.perBankWrBursts::2 11122 # Per bank write bursts -system.physmem.perBankWrBursts::3 10684 # Per bank write bursts -system.physmem.perBankWrBursts::4 10817 # Per bank write bursts -system.physmem.perBankWrBursts::5 11014 # Per bank write bursts -system.physmem.perBankWrBursts::6 11094 # Per bank write bursts -system.physmem.perBankWrBursts::7 11085 # Per bank write bursts -system.physmem.perBankWrBursts::8 10650 # Per bank write bursts -system.physmem.perBankWrBursts::9 11040 # Per bank write bursts -system.physmem.perBankWrBursts::10 10845 # Per bank write bursts -system.physmem.perBankWrBursts::11 10150 # Per bank write bursts -system.physmem.perBankWrBursts::12 10760 # Per bank write bursts -system.physmem.perBankWrBursts::13 10359 # Per bank write bursts -system.physmem.perBankWrBursts::14 10115 # Per bank write bursts -system.physmem.perBankWrBursts::15 9574 # Per bank write bursts +system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200214 # Number of read requests accepted +system.physmem.writeReqs 175885 # Number of write requests accepted +system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12188 # Per bank write bursts +system.physmem.perBankRdBursts::1 12046 # Per bank write bursts +system.physmem.perBankRdBursts::2 12591 # Per bank write bursts +system.physmem.perBankRdBursts::3 12330 # Per bank write bursts +system.physmem.perBankRdBursts::4 20750 # Per bank write bursts +system.physmem.perBankRdBursts::5 12582 # Per bank write bursts +system.physmem.perBankRdBursts::6 12043 # Per bank write bursts +system.physmem.perBankRdBursts::7 12246 # Per bank write bursts +system.physmem.perBankRdBursts::8 12442 # Per bank write bursts +system.physmem.perBankRdBursts::9 12402 # Per bank write bursts +system.physmem.perBankRdBursts::10 11722 # Per bank write bursts +system.physmem.perBankRdBursts::11 11146 # Per bank write bursts +system.physmem.perBankRdBursts::12 11467 # Per bank write bursts +system.physmem.perBankRdBursts::13 11916 # Per bank write bursts +system.physmem.perBankRdBursts::14 10852 # Per bank write bursts +system.physmem.perBankRdBursts::15 11341 # Per bank write bursts +system.physmem.perBankWrBursts::0 10835 # Per bank write bursts +system.physmem.perBankWrBursts::1 11264 # Per bank write bursts +system.physmem.perBankWrBursts::2 11493 # Per bank write bursts +system.physmem.perBankWrBursts::3 10899 # Per bank write bursts +system.physmem.perBankWrBursts::4 10487 # Per bank write bursts +system.physmem.perBankWrBursts::5 11152 # Per bank write bursts +system.physmem.perBankWrBursts::6 11024 # Per bank write bursts +system.physmem.perBankWrBursts::7 10595 # Per bank write bursts +system.physmem.perBankWrBursts::8 10782 # Per bank write bursts +system.physmem.perBankWrBursts::9 10958 # Per bank write bursts +system.physmem.perBankWrBursts::10 10716 # Per bank write bursts +system.physmem.perBankWrBursts::11 10408 # Per bank write bursts +system.physmem.perBankWrBursts::12 10444 # Per bank write bursts +system.physmem.perBankWrBursts::13 9906 # Per bank write bursts +system.physmem.perBankWrBursts::14 9416 # Per bank write bursts +system.physmem.perBankWrBursts::15 9817 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2867048141000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2868318254500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194735 # Read request sizes (log2) +system.physmem.readPktSize::6 190444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 172111 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 120800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 171449 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -188,178 +184,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 83215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 288.553362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.296581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.078048 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39267 47.19% 47.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16171 19.43% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6480 7.79% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3347 4.02% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3132 3.76% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1913 2.30% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1073 1.29% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1034 1.24% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10798 12.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 83215 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.019171 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 531.269210 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7040 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.258023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.337274 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.786425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5509 78.23% 78.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 384 5.45% 83.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 77 1.09% 84.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 222 3.15% 87.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 122 1.73% 89.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 57 0.81% 90.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.61% 91.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.53% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 124 1.76% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.21% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 18 0.26% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.23% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 34 0.48% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.23% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.38% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 62 0.88% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.16% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.09% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 10 0.14% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.25% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 19 0.27% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.16% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 36 0.51% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 11 0.16% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.10% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads -system.physmem.totQLat 5974898500 # Total ticks spent queuing -system.physmem.totMemAccLat 9806704750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1021815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29236.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads +system.physmem.totQLat 4855930250 # Total ticks spent queuing +system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47986.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 174382 # Number of row buffer hits during reads -system.physmem.writeRowHits 117590 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.82 # Row buffer hit rate for writes -system.physmem.avgGap 7524033.84 # Average gap between requests -system.physmem.pageHitRate 77.81 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731090191250 # Time in different power states -system.physmem.memoryStateTime::REF 95736940000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 40221363750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 330432480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 298672920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 180295500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 162966375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 857422800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 736600800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 565911360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 541034640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82724898285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81530993385 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647661560750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648708845750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919581975815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1919240568510 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.533155 # Core power per rank (mW) -system.physmem.averagePower::1 669.414075 # Core power per rank (mW) +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing +system.physmem.readRowHits 167229 # Number of row buffer hits during reads +system.physmem.writeRowHits 112615 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes +system.physmem.avgGap 7626497.96 # Average gap between requests +system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.622475 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states +system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.527135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -385,6 +382,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -406,27 +411,65 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7749 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22739909 # DTB read hits -system.cpu0.dtb.read_misses 4142 # DTB read misses -system.cpu0.dtb.write_hits 16676295 # DTB write hits -system.cpu0.dtb.write_misses 677 # DTB write misses +system.cpu0.dtb.read_hits 19044092 # DTB read hits +system.cpu0.dtb.read_misses 6608 # DTB read misses +system.cpu0.dtb.write_hits 15688894 # DTB write hits +system.cpu0.dtb.write_misses 1141 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2392 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1346 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22744051 # DTB read accesses -system.cpu0.dtb.write_accesses 16676972 # DTB write accesses +system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 19050700 # DTB read accesses +system.cpu0.dtb.write_accesses 15690035 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 39416204 # DTB hits -system.cpu0.dtb.misses 4819 # DTB misses -system.cpu0.dtb.accesses 39421023 # DTB accesses +system.cpu0.dtb.hits 34732986 # DTB hits +system.cpu0.dtb.misses 7749 # DTB misses +system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -448,8 +491,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 107931670 # ITB inst hits -system.cpu0.itb.inst_misses 2300 # ITB inst misses +system.cpu0.itb.walker.walks 3348 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -458,178 +533,179 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1397 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 107933970 # ITB inst accesses -system.cpu0.itb.hits 107931670 # DTB hits -system.cpu0.itb.misses 2300 # DTB misses -system.cpu0.itb.accesses 107933970 # DTB accesses -system.cpu0.numCycles 5733190951 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses +system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.misses 3348 # DTB misses +system.cpu0.itb.accesses 91514175 # DTB accesses +system.cpu0.numCycles 5736637393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 104697045 # Number of instructions committed -system.cpu0.committedOps 126437300 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 112138973 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4560 # Number of float alu accesses -system.cpu0.num_func_calls 12218983 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14112779 # number of instructions that are conditional controls -system.cpu0.num_int_insts 112138973 # number of integer instructions -system.cpu0.num_fp_insts 4560 # number of float instructions -system.cpu0.num_int_register_reads 207168140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 78157614 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 458862041 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 46623468 # number of times the CC registers were written -system.cpu0.num_mem_refs 40473955 # number of memory refs -system.cpu0.num_load_insts 22968630 # Number of load instructions -system.cpu0.num_store_insts 17505325 # Number of store instructions -system.cpu0.num_idle_cycles 5494072814.437573 # Number of idle cycles -system.cpu0.num_busy_cycles 239118136.562427 # Number of busy cycles -system.cpu0.not_idle_fraction 0.041708 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.958292 # Percentage of idle cycles -system.cpu0.Branches 26957408 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2171 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 89486890 68.80% 68.80% # Class of executed instruction -system.cpu0.op_class::IntMult 99356 0.08% 68.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 6997 0.01% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::MemRead 22968630 17.66% 86.54% # Class of executed instruction -system.cpu0.op_class::MemWrite 17505325 13.46% 100.00% # Class of executed instruction +system.cpu0.committedInsts 89363678 # Number of instructions committed +system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses +system.cpu0.num_func_calls 6606472 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls +system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_fp_insts 9820 # number of float instructions +system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written +system.cpu0.num_mem_refs 35866705 # number of memory refs +system.cpu0.num_load_insts 19295047 # Number of load instructions +system.cpu0.num_store_insts 16571658 # Number of store instructions +system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles +system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles +system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles +system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction +system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction +system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 130069369 # Class of executed instruction +system.cpu0.op_class::total 109543126 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1990 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 555287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.900335 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38705991 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 555652 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 69.658691 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.900335 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 79342035 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 79342035 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 21654746 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21654746 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16040843 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16040843 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 304713 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 304713 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 334336 # number of LoadLockedReq hits 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(read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7946376701 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7946376701 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013885 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.013885 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016156 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016156 # miss rate for WriteReq accesses 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overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7766691538 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5556589244 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5556589244 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4171949493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4171949493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9728538737 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9728538737 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013557 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013557 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.210152 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.210152 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016755 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016755 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.059156 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.059156 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.014664 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.014664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.016672 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.016672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10856.637969 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10856.637969 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13265.336154 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13265.336154 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks +system.cpu0.dcache.writebacks::total 504116 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses 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13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -721,58 +797,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 945322 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483250 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 106985827 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 945834 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 113.112689 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483250 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1099798 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 216809183 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 216809183 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 106985827 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 106985827 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 106985827 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 106985827 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 106985827 # number of overall hits -system.cpu0.icache.overall_hits::total 106985827 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945843 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945843 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945843 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945843 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945843 # number of overall misses -system.cpu0.icache.overall_misses::total 945843 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8025066767 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8025066767 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 107931670 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 107931670 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 107931670 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 107931670 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008763 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.008763 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008763 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.008763 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8484.565374 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8484.565374 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8484.565374 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits +system.cpu0.icache.overall_hits::total 90410508 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses +system.cpu0.icache.overall_misses::total 1100319 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,356 +857,353 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 945843 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 945843 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 945843 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 945843 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 945843 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 945843 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6605629733 # number of ReadReq MSHR miss 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mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.337710 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1140,58 +1213,66 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1585084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1436635 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 420867 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 537670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 82377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43315 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 100677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 246727 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 235853 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1909730 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1979159 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 7030 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14021 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 3909940 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 60570040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 70330266 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 130932182 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 972661 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2913864 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.296127 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.456548 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2050990 70.39% 70.39% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 862874 29.61% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2913864 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1492069922 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116074499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1430234267 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 995136418 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 4367000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 8715750 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1213,27 +1294,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3332 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6438534 # DTB read hits -system.cpu1.dtb.read_misses 5066 # DTB read misses -system.cpu1.dtb.write_hits 5578600 # DTB write hits -system.cpu1.dtb.write_misses 983 # DTB write misses +system.cpu1.dtb.read_hits 10115566 # DTB read hits +system.cpu1.dtb.read_misses 2828 # DTB read misses +system.cpu1.dtb.write_hits 6544640 # DTB write hits +system.cpu1.dtb.write_misses 504 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3048 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6443600 # DTB read accesses -system.cpu1.dtb.write_accesses 5579583 # DTB write accesses +system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10118394 # DTB read accesses +system.cpu1.dtb.write_accesses 6545144 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12017134 # DTB hits -system.cpu1.dtb.misses 6049 # DTB misses -system.cpu1.dtb.accesses 12023183 # DTB accesses +system.cpu1.dtb.hits 16660206 # DTB hits +system.cpu1.dtb.misses 3332 # DTB misses +system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1255,8 +1376,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28023624 # ITB inst hits -system.cpu1.itb.inst_misses 2794 # ITB inst misses +system.cpu1.itb.walker.walks 1746 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 44359905 # ITB inst hits +system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1265,179 +1420,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1901 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28026418 # ITB inst accesses -system.cpu1.itb.hits 28023624 # DTB hits -system.cpu1.itb.misses 2794 # DTB misses -system.cpu1.itb.accesses 28026418 # DTB accesses -system.cpu1.numCycles 5734097031 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses +system.cpu1.itb.hits 44359905 # DTB hits +system.cpu1.itb.misses 1746 # DTB misses +system.cpu1.itb.accesses 44361651 # DTB accesses +system.cpu1.numCycles 5735725430 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 27233120 # Number of instructions committed -system.cpu1.committedOps 33143777 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29468029 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses -system.cpu1.num_func_calls 1518648 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3438745 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29468029 # number of integer instructions -system.cpu1.num_fp_insts 6988 # number of float instructions -system.cpu1.num_int_register_reads 53045981 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20334319 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 119969216 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 12226644 # number of times the CC registers were written -system.cpu1.num_mem_refs 12358568 # number of memory refs -system.cpu1.num_load_insts 6575418 # Number of load instructions -system.cpu1.num_store_insts 5783150 # Number of store instructions -system.cpu1.num_idle_cycles 5655719559.150027 # Number of idle cycles -system.cpu1.num_busy_cycles 78377471.849973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013669 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986331 # Percentage of idle cycles -system.cpu1.Branches 5151142 # Number of branches fetched -system.cpu1.op_class::No_OpClass 168 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 21257809 63.16% 63.16% # Class of executed instruction -system.cpu1.op_class::IntMult 38403 0.11% 63.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4420 0.01% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::MemRead 6575418 19.54% 82.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 5783150 17.18% 100.00% # Class of executed instruction +system.cpu1.committedInsts 42482884 # Number of instructions committed +system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses +system.cpu1.num_func_calls 7121857 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_fp_insts 1857 # number of float instructions +system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written +system.cpu1.num_mem_refs 16924073 # number of memory refs +system.cpu1.num_load_insts 10229886 # Number of load instructions +system.cpu1.num_store_insts 6694187 # Number of store instructions +system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles +system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles +system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles +system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction +system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction +system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 33659368 # Class of executed instruction +system.cpu1.op_class::total 54073981 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2818 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 321673 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.284483 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11622088 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 322185 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.072716 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.284483 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24380907 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24380907 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5961630 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5961630 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5307193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5307193 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 82380 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 82380 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 110885 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 110885 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 104150 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 104150 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11268823 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11268823 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11351203 # number of overall hits -system.cpu1.dcache.overall_hits::total 11351203 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 210202 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 210202 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 138084 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 138084 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 48251 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 48251 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19527 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19527 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23870 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23870 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 348286 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 348286 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 396537 # number of overall misses -system.cpu1.dcache.overall_misses::total 396537 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5459439800 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5459439800 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 130412 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 130412 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 128020 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 128020 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11617109 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11617109 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11747740 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11747740 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034058 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034058 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025358 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025358 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.369369 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.369369 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.186455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.186455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029980 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029980 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033754 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033754 # miss 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replacements +system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task 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15675.162941 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13767.794178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13767.794178 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1446,82 +1600,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 197265 # number of writebacks -system.cpu1.dcache.writebacks::total 197265 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 459 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 459 # number of overall MSHR hits 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number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5382315699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033984 # 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uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses 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23185.906782 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 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system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1529,58 +1683,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 680772 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.691095 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 27342334 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 681284 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.133533 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.691095 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974006 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974006 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 526723 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 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for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1589,361 +1743,347 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 681285 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 681285 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 681285 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 681285 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 681285 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 681285 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4634848490 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4634848490 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4634848490 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4634848490 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4634848490 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4634848490 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles 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mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles 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overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5735095 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 38649 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 5537320 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 267 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 19 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 158840 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 604377 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 130093 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15612.463834 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1076740 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 146334 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.358099 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 47689 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4806.943324 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.120223 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.343631 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 874.835505 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1500.703163 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8425.517990 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.293393 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000082 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053396 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091596 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.514253 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952909 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7913 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 8324 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 47 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 90 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2030 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2875 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4662 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 602 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.482971 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.508057 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21325891 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21325891 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5234 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2693 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 672894 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 186024 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 866845 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 197265 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 197265 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2024 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2024 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1217 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1217 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 69989 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 69989 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5234 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2693 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 672894 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 256013 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 936834 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5234 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2693 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 672894 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 256013 # number of overall hits -system.cpu1.l2cache.overall_hits::total 936834 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 261 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 216 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 8391 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 76389 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 85257 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29955 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29955 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22648 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22648 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36116 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 36116 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 261 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 216 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 8391 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 112505 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 121373 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 261 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 216 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 8391 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 112505 # number of overall misses -system.cpu1.l2cache.overall_misses::total 121373 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 5754999 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4668500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 255474477 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1702549656 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1968447632 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 542491459 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 542491459 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 444517157 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 444517157 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1522000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1522000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1159011538 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1159011538 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 5754999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4668500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 255474477 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2861561194 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3127459170 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 5754999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4668500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 255474477 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2861561194 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3127459170 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 5495 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2909 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 681285 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 262413 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 952102 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 197265 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 197265 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31979 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31979 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23865 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23865 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 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-system.cpu1.l2cache.overall_accesses::cpu1.inst 681285 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 368518 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1058207 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.074252 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.012316 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.291102 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.089546 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936708 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936708 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.949005 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.949005 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1514 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11595 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073120 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.817322 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15244499 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15244499 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1729 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 513133 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 102720 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 620673 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 118649 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 118649 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1485 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1485 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 867 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 867 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28139 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 28139 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3091 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1729 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 513133 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 130859 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 648812 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3091 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1729 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 513133 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 130859 # number of overall hits +system.cpu1.l2cache.overall_hits::total 648812 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 14102 # 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(read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 384250260 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2023461386 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2415322646 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3489000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 384250260 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2023461386 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3230075506 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12590000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 494236499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 506826499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 356773500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 356773500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12590000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 851009999 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 863599999 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402554 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119093 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936708 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936708 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949005 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.949005 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.336732 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.336732 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.113073 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.263175 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15289.635066 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16190.977194 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27298.605103 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15053.474378 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15053.474378 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13783.958363 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13783.958363 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 255400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 255400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24270.038064 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24270.038064 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18603.385918 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency 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mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1953,69 +2093,69 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1351518 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1008638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 197265 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 224398 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84264 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 91097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 123576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 111434 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1362924 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1150758 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8243 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16496 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2538421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43602948 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 39320783 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11636 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 21980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82957347 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 826396 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2054321 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.357816 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1319253 64.22% 64.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 735068 35.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2054321 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 864974439 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89802999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1022245510 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 593726174 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 5334000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 11001001 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59437 # Transaction distribution -system.iobus.trans_dist::WriteResp 23213 # Transaction distribution +system.iobus.trans_dist::ReadReq 31024 # Transaction distribution +system.iobus.trans_dist::ReadResp 31024 # Transaction distribution +system.iobus.trans_dist::WriteReq 59440 # Transaction distribution +system.iobus.trans_dist::WriteResp 23216 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2031,16 +2171,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71586 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2056,11 +2196,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162833 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484089 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40126000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2070,7 +2210,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2100,52 +2240,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347096127 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84737000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36842563 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36459 # number of replacements -system.iocache.tags.tagsinuse 14.453181 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277163175000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.453181 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.903324 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.903324 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328293 # Number of tag accesses -system.iocache.tags.data_accesses 328293 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses -system.iocache.ReadReq_misses::total 253 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses -system.iocache.demand_misses::total 253 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 253 # number of overall misses -system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31619377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31619377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31619377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31619377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31619377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31619377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2154,40 +2294,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124977.774704 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56586 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.829805 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18462377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18462377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18462377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18462377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2196,517 +2336,491 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 132552 # number of replacements -system.l2c.tags.tagsinuse 64217.240538 # Cycle average of tags in use -system.l2c.tags.total_refs 486427 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197317 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.465206 # Average number of references to valid blocks. +system.l2c.tags.replacements 130735 # number of replacements +system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use +system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12673.098262 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.830088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1135.719993 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1432.608438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.654088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 545.091140 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 913.810052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8789.608693 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017330 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590817 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013944 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979877 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 45108 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5031 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39902 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1352 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18116 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.688293 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.299866 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6110572 # Number of tag accesses -system.l2c.tags.data_accesses 6110572 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 80 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 21794 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 138574 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 103 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6377 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 17292 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75612 # number of ReadReq hits -system.l2c.ReadReq_hits::total 267683 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 239712 # number of Writeback hits -system.l2c.Writeback_hits::total 239712 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 8881 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1415 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10296 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 148 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3683 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6574 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 25477 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 138574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 103 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6377 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 20183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 75612 # number of demand (read+write) hits -system.l2c.demand_hits::total 274257 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits 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misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 831 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1568 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 26632 # number of ReadReq misses -system.l2c.ReadReq_misses::total 183594 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 7063 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5704 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 818 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1393 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2211 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 6032 # number of ReadExReq misses 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-system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 268856499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 563379750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14370591021 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 299500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 76052499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 131534999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2969532817 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18380994835 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 5708264 # number of UpgradeReq miss cycles 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uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9260500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728588000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10342463248 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163313 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.097558 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.538254 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.790063 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790076 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.790066 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.822126 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.880554 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857081 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746737 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851178 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.788249 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.556706 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.556706 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70082.930580 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67212.193389 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71413.583546 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87711.162986 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.063146 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.865884 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10092.637660 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10162.975550 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.996411 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.564450 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66867.098475 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59414.478284 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63258.032062 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2721,58 +2835,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 228161 # Transaction distribution -system.membus.trans_dist::ReadResp 228160 # Transaction distribution -system.membus.trans_dist::WriteReq 31188 # Transaction distribution -system.membus.trans_dist::WriteResp 31188 # Transaction distribution -system.membus.trans_dist::Writeback 135887 # Transaction distribution +system.membus.trans_dist::ReadReq 215303 # Transaction distribution +system.membus.trans_dist::ReadResp 215303 # Transaction distribution +system.membus.trans_dist::WriteReq 30982 # Transaction distribution +system.membus.trans_dist::WriteResp 30982 # Transaction distribution +system.membus.trans_dist::Writeback 135225 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85485 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41282 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15173 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 28446 # Transaction distribution -system.membus.trans_dist::ReadExResp 11501 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107950 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 40350 # Transaction distribution +system.membus.trans_dist::ReadExResp 19836 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 676793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 799389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 908311 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162833 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18898536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19090661 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23727141 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129157 # Total snoops (count) -system.membus.snoop_fanout::samples 511174 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123675 # Total snoops (count) +system.membus.snoop_fanout::samples 499419 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 511174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 511174 # Request fanout histogram -system.membus.reqLayer0.occupancy 88144997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 499419 # Request fanout histogram +system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12118496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1838586997 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1967573382 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38564437 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2805,44 +2919,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 630354 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 630338 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31188 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31188 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 239712 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 95586 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41643 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137229 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39856 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39856 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1145062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 504022 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1649084 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33792786 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 11864019 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45656805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 304478 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1039135 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.035103 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.184041 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 286323 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1002658 96.49% 96.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36477 3.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1039135 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1515175521 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1922628953 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1047459467 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 5265a0ac0..b3648bdab 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902845 # Number of seconds simulated -sim_ticks 2902845442000 # Number of ticks simulated -final_tick 2902845442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.902862 # Number of seconds simulated +sim_ticks 2902861767000 # Number of ticks simulated +final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666753 # Simulator instruction rate (inst/s) -host_op_rate 803907 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17201244826 # Simulator tick rate (ticks/s) -host_mem_usage 558784 # Number of bytes of host memory used -host_seconds 168.76 # Real time elapsed on the host -sim_insts 112519801 # Number of instructions simulated -sim_ops 135665611 # Number of ops (including micro ops) simulated +host_inst_rate 747193 # Simulator instruction rate (inst/s) +host_op_rate 900893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19275657141 # Simulator tick rate (ticks/s) +host_mem_usage 615228 # Number of bytes of host memory used +host_seconds 150.60 # Real time elapsed on the host +sim_insts 112525269 # Number of instructions simulated +sim_ops 135672104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1190500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10177864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1190500 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1190500 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7575744 # Number of bytes written to this memory +system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7593268 # Number of bytes written to this memory +system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168002 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118371 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122752 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3095524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3506168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2609765 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2615802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2609765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3101561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6121970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168002 # Number of read requests accepted -system.physmem.writeReqs 158976 # Number of write requests accepted -system.physmem.readBursts 168002 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158976 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10744064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 9803776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10177864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9911604 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5765 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4503 # Number of requests that are neither read nor write +system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168015 # Number of read requests accepted +system.physmem.writeReqs 158980 # Number of write requests accepted +system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9689 # Per bank write bursts -system.physmem.perBankRdBursts::1 9233 # Per bank write bursts -system.physmem.perBankRdBursts::2 10196 # Per bank write bursts -system.physmem.perBankRdBursts::3 10261 # Per bank write bursts +system.physmem.perBankRdBursts::1 9230 # Per bank write bursts +system.physmem.perBankRdBursts::2 10198 # Per bank write bursts +system.physmem.perBankRdBursts::3 10267 # Per bank write bursts system.physmem.perBankRdBursts::4 18984 # Per bank write bursts -system.physmem.perBankRdBursts::5 10217 # Per bank write bursts -system.physmem.perBankRdBursts::6 10550 # Per bank write bursts -system.physmem.perBankRdBursts::7 10349 # Per bank write bursts -system.physmem.perBankRdBursts::8 9691 # Per bank write bursts +system.physmem.perBankRdBursts::5 10226 # Per bank write bursts +system.physmem.perBankRdBursts::6 10551 # Per bank write bursts +system.physmem.perBankRdBursts::7 10350 # Per bank write bursts +system.physmem.perBankRdBursts::8 9702 # Per bank write bursts system.physmem.perBankRdBursts::9 9930 # Per bank write bursts -system.physmem.perBankRdBursts::10 9906 # Per bank write bursts -system.physmem.perBankRdBursts::11 8846 # Per bank write bursts -system.physmem.perBankRdBursts::12 9937 # Per bank write bursts -system.physmem.perBankRdBursts::13 10409 # Per bank write bursts -system.physmem.perBankRdBursts::14 9928 # Per bank write bursts +system.physmem.perBankRdBursts::10 9908 # Per bank write bursts +system.physmem.perBankRdBursts::11 8848 # Per bank write bursts +system.physmem.perBankRdBursts::12 9929 # Per bank write bursts +system.physmem.perBankRdBursts::13 10408 # Per bank write bursts +system.physmem.perBankRdBursts::14 9925 # Per bank write bursts system.physmem.perBankRdBursts::15 9750 # Per bank write bursts -system.physmem.perBankWrBursts::0 9383 # Per bank write bursts -system.physmem.perBankWrBursts::1 8873 # Per bank write bursts -system.physmem.perBankWrBursts::2 10202 # Per bank write bursts -system.physmem.perBankWrBursts::3 10003 # Per bank write bursts -system.physmem.perBankWrBursts::4 9293 # Per bank write bursts -system.physmem.perBankWrBursts::5 9372 # Per bank write bursts -system.physmem.perBankWrBursts::6 9902 # Per bank write bursts -system.physmem.perBankWrBursts::7 9747 # Per bank write bursts -system.physmem.perBankWrBursts::8 9662 # Per bank write bursts -system.physmem.perBankWrBursts::9 9936 # Per bank write bursts -system.physmem.perBankWrBursts::10 9764 # Per bank write bursts -system.physmem.perBankWrBursts::11 9057 # Per bank write bursts -system.physmem.perBankWrBursts::12 9756 # Per bank write bursts -system.physmem.perBankWrBursts::13 9847 # Per bank write bursts -system.physmem.perBankWrBursts::14 9332 # Per bank write bursts -system.physmem.perBankWrBursts::15 9055 # Per bank write bursts +system.physmem.perBankWrBursts::0 9389 # Per bank write bursts +system.physmem.perBankWrBursts::1 8975 # Per bank write bursts +system.physmem.perBankWrBursts::2 10251 # Per bank write bursts +system.physmem.perBankWrBursts::3 9953 # Per bank write bursts +system.physmem.perBankWrBursts::4 9418 # Per bank write bursts +system.physmem.perBankWrBursts::5 9499 # Per bank write bursts +system.physmem.perBankWrBursts::6 9770 # Per bank write bursts +system.physmem.perBankWrBursts::7 9764 # Per bank write bursts +system.physmem.perBankWrBursts::8 9682 # Per bank write bursts +system.physmem.perBankWrBursts::9 9836 # Per bank write bursts +system.physmem.perBankWrBursts::10 9791 # Per bank write bursts +system.physmem.perBankWrBursts::11 9091 # Per bank write bursts +system.physmem.perBankWrBursts::12 9681 # Per bank write bursts +system.physmem.perBankWrBursts::13 9852 # Per bank write bursts +system.physmem.perBankWrBursts::14 9372 # Per bank write bursts +system.physmem.perBankWrBursts::15 9026 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2902845065500 # Total gap between requests +system.physmem.totGap 2902861390500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158430 # Read request sizes (log2) +system.physmem.readPktSize::6 158443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 154595 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see +system.physmem.writePktSize::6 154599 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,114 +159,135 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 338.910027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.312314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 353.501529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21458 35.39% 35.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14532 23.97% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5550 9.15% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3471 5.72% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2318 3.82% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.60% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1018 1.68% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1077 1.78% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9629 15.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60629 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.078561 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 543.579220 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6197 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.711082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.355367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.633562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 5127 82.71% 82.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 245 3.95% 86.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 162 2.61% 89.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 57 0.92% 90.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 142 2.29% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 31 0.50% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 44 0.71% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 53 0.85% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 77 1.24% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 20 0.32% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 101 1.63% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 12 0.19% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 30 0.48% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 13 0.21% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 38 0.61% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 11 0.18% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 15 0.24% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads -system.physmem.totQLat 1496514000 # Total ticks spent queuing -system.physmem.totMemAccLat 4644189000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 839380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8914.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads +system.physmem.totQLat 1487834250 # Total ticks spent queuing +system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27664.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -276,36 +297,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.52 # Average write queue length when enqueuing -system.physmem.readRowHits 138272 # Number of row buffer hits during reads -system.physmem.writeRowHits 122158 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.73 # Row buffer hit rate for writes -system.physmem.avgGap 8877799.32 # Average gap between requests -system.physmem.pageHitRate 81.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755332461750 # Time in different power states -system.physmem.memoryStateTime::REF 96932160000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50580729750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234216360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224138880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127796625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122298000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 697936200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 611488800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 497502000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 495130320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189599304960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189599304960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86744243025 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85632450615 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665611854500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666587111000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943512853670 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1943271922575 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.521448 # Core power per rank (mW) -system.physmem.averagePower::1 669.438449 # Core power per rank (mW) +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 138089 # Number of row buffer hits during reads +system.physmem.writeRowHits 122193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes +system.physmem.avgGap 8877387.70 # Average gap between requests +system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.522458 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states +system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.435479 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states +system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -325,6 +351,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -346,11 +380,41 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 9552 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24536392 # DTB read hits -system.cpu.dtb.read_misses 8144 # DTB read misses -system.cpu.dtb.write_hits 19617454 # DTB write hits +system.cpu.dtb.read_hits 24537663 # DTB read hits +system.cpu.dtb.read_misses 8142 # DTB read misses +system.cpu.dtb.write_hits 19618927 # DTB write hits system.cpu.dtb.write_misses 1410 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -358,15 +422,23 @@ system.cpu.dtb.flush_tlb_mva_asid 0 # Nu system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24544536 # DTB read accesses -system.cpu.dtb.write_accesses 19618864 # DTB write accesses +system.cpu.dtb.read_accesses 24545805 # DTB read accesses +system.cpu.dtb.write_accesses 19620337 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44153846 # DTB hits -system.cpu.dtb.misses 9554 # DTB misses -system.cpu.dtb.accesses 44163400 # DTB accesses +system.cpu.dtb.hits 44156590 # DTB hits +system.cpu.dtb.misses 9552 # DTB misses +system.cpu.dtb.accesses 44166142 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -388,7 +460,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 115618887 # ITB inst hits +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115624412 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -405,38 +507,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115623649 # ITB inst accesses -system.cpu.itb.hits 115618887 # DTB hits +system.cpu.itb.inst_accesses 115629174 # ITB inst accesses +system.cpu.itb.hits 115624412 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115623649 # DTB accesses -system.cpu.numCycles 5805690884 # number of cpu cycles simulated +system.cpu.itb.accesses 115629174 # DTB accesses +system.cpu.numCycles 5805723534 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112519801 # Number of instructions committed -system.cpu.committedOps 135665611 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119963928 # Number of integer alu accesses +system.cpu.committedInsts 112525269 # Number of instructions committed +system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9899743 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15237612 # number of instructions that are conditional controls -system.cpu.num_int_insts 119963928 # number of integer instructions +system.cpu.num_func_calls 9899985 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls +system.cpu.num_int_insts 119969678 # number of integer instructions system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218192496 # number of times the integer registers were read -system.cpu.num_int_register_writes 82697523 # number of times the integer registers were written +system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read +system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 490031044 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51919223 # number of times the CC registers were written -system.cpu.num_mem_refs 45435185 # number of memory refs -system.cpu.num_load_insts 24859277 # Number of load instructions -system.cpu.num_store_insts 20575908 # Number of store instructions -system.cpu.num_idle_cycles 5386811452.570145 # Number of idle cycles -system.cpu.num_busy_cycles 418879431.429856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072150 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927850 # Percentage of idle cycles -system.cpu.Branches 25931479 # Number of branches fetched +system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written +system.cpu.num_mem_refs 45438019 # number of memory refs +system.cpu.num_load_insts 24860597 # Number of load instructions +system.cpu.num_store_insts 20577422 # Number of store instructions +system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles +system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles +system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927847 # Percentage of idle cycles +system.cpu.Branches 25932360 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93227451 67.17% 67.17% # Class of executed instruction -system.cpu.op_class::IntMult 114534 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -460,24 +562,24 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8511 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24859277 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20575908 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138788018 # Class of executed instruction +system.cpu.op_class::total 138794587 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 823273 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850546 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43258722 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823785 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.512151 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 823321 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850546 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -486,168 +588,168 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177222055 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177222055 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23125535 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23125535 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834160 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834160 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392158 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392158 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443620 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443620 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460509 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460509 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41959695 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41959695 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42351853 # number of overall hits -system.cpu.dcache.overall_hits::total 42351853 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 402606 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 402606 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 299098 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 299098 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177233078 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23126684 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23126684 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18835651 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18835651 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392122 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392122 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443636 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460570 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41962335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42354457 # number of overall hits +system.cpu.dcache.overall_hits::total 42354457 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 402703 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 402703 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 299019 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 299019 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22698 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22698 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 701704 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 701704 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 820876 # number of overall misses -system.cpu.dcache.overall_misses::total 820876 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5915644250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5915644250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11659723253 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11659723253 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280150250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 280150250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 701722 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 701722 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 820894 # number of overall misses +system.cpu.dcache.overall_misses::total 820894 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916458250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5916458250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11650381750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11650381750 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280295250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 280295250 # number of LoadLockedReq miss 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uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221078000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015632 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015632 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228856 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228856 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018168 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018168 # mshr miss rate for LoadLockedReq accesses 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uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228872 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228872 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018202 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018202 # mshr miss rate for LoadLockedReq accesses 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WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12086.469523 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12086.469523 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11761.833097 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11761.833097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12058.878321 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12058.878321 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11781.364118 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11781.364118 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22965.920563 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22965.920563 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21409.703280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21409.703280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22954.210069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22954.210069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -655,13 +757,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1700967 # number of replacements -system.cpu.icache.tags.tagsinuse 510.782035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113917402 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1701479 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.951988 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1701491 # number of replacements +system.cpu.icache.tags.tagsinuse 510.782044 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113922403 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1702003 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.934314 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.782035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.782044 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -670,44 +772,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117320372 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117320372 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113917402 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113917402 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113917402 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113917402 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113917402 # number of overall hits -system.cpu.icache.overall_hits::total 113917402 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1701485 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1701485 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1701485 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1701485 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1701485 # number of overall misses -system.cpu.icache.overall_misses::total 1701485 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23258305750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23258305750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23258305750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23258305750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23258305750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23258305750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115618887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115618887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115618887 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115618887 # number of demand (read+write) accesses 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latency -system.cpu.icache.demand_avg_miss_latency::total 13669.415687 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.415687 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13669.415687 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117326421 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117326421 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113922403 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113922403 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113922403 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113922403 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113922403 # number of overall hits +system.cpu.icache.overall_hits::total 113922403 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1702009 # number of ReadReq misses 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-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19848767250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19848767250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19848767250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19848767250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1702009 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1702009 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1702009 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1702009 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1702009 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1702009 # number of overall MSHR misses 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miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.555236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.555236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.555236 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014720 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014720 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014720 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11667.188893 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11667.188893 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 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miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 775288750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1866093500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27282710 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27282710 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353282038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353282038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 467000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7345006540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7345006540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087188750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8131188288 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9218969038 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 467000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1090271000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8120295290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9211100040 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 408750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087188750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8131188288 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9218969038 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1090271000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8120295290 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9211100040 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles @@ -966,48 +1068,48 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013503 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991600 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013504 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991584 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991584 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063283 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063274 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063283 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063274 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60265.451774 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63809.880240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61695.998677 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10058.458564 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10058.458564 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.475107 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.475107 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1017,54 +1119,54 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2296418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2296403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296360 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3420989 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457362 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24821 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5916047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108929528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96856201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205828273 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53126 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3278039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011122 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104872 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53107 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3241581 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3278039 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2354969500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2566643750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312602003 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17845000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution @@ -1161,23 +1263,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347056142 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134557 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298397320000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134557 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070910 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070910 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1193,8 +1295,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9588161260 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9588161260 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles @@ -1217,17 +1319,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264690.847504 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264690.847504 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55275 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7147 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.734014 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1243,8 +1345,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7704503270 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7704503270 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles @@ -1259,64 +1361,64 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212690.571720 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212690.571720 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70650 # Transaction distribution -system.membus.trans_dist::ReadResp 70650 # Transaction distribution +system.membus.trans_dist::ReadReq 70661 # Transaction distribution +system.membus.trans_dist::ReadResp 70661 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 118371 # Transaction distribution +system.membus.trans_dist::Writeback 118375 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 128452 # Transaction distribution -system.membus.trans_dist::ReadExResp 128452 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution +system.membus.trans_dist::ReadExReq 128454 # Transaction distribution +system.membus.trans_dist::ReadExResp 128454 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15454012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15617473 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20252929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 318026 # Request fanout histogram +system.membus.snoop_fanout::samples 318040 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 318026 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 318026 # Request fanout histogram +system.membus.snoop_fanout::total 318040 # Request fanout histogram system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1756500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1589715500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594842247 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index b2b55eb3a..f0c87683a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1108011 # Simulator instruction rate (inst/s) -host_op_rate 1348825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21604583679 # Simulator tick rate (ticks/s) -host_mem_usage 560868 # Number of bytes of host memory used -host_seconds 128.86 # Real time elapsed on the host +host_inst_rate 1311458 # Simulator instruction rate (inst/s) +host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25571502260 # Simulator tick rate (ticks/s) +host_mem_usage 616488 # Number of bytes of host memory used +host_seconds 108.87 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -87,6 +87,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -108,6 +116,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 5682 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 15994592 # DTB read hits @@ -129,6 +155,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 27280368 # DTB hits system.cpu0.dtb.misses 5682 # DTB misses system.cpu0.dtb.accesses 27286050 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -150,6 +184,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 2611 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2611 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2611 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1374 72.85% 72.85% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 512 27.15% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1886 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 74779253 # ITB inst hits system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -408,6 +460,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -429,6 +489,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 6203 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6203 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3703 73.18% 73.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1357 26.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5060 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 15530019 # DTB read hits @@ -450,6 +528,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 27368468 # DTB hits system.cpu1.dtb.misses 6203 # DTB misses system.cpu1.dtb.accesses 27374671 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -471,6 +557,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 3040 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 72259450 # ITB inst hits system.cpu1.itb.inst_misses 3040 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 818a22f67..83b8a4ab7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.177080 # Nu sim_ticks 47177080006500 # Number of ticks simulated final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1024538 # Simulator instruction rate (inst/s) -host_op_rate 1205255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49483118923 # Simulator tick rate (ticks/s) -host_mem_usage 669884 # Number of bytes of host memory used -host_seconds 953.40 # Real time elapsed on the host +host_inst_rate 1049876 # Simulator instruction rate (inst/s) +host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50706899360 # Simulator tick rate (ticks/s) +host_mem_usage 670076 # Number of bytes of host memory used +host_seconds 930.39 # Real time elapsed on the host sim_insts 976792036 # Number of instructions simulated sim_ops 1149086878 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -105,6 +105,14 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -126,6 +134,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 123914 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91355479 # DTB read hits @@ -147,6 +173,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 175957422 # DTB hits system.cpu0.dtb.misses 123914 # DTB misses system.cpu0.dtb.accesses 176081336 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -168,6 +202,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 60226 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 491372488 # ITB inst hits system.cpu0.itb.inst_misses 60226 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -392,15 +444,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 2648971 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. @@ -576,6 +625,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -597,6 +654,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 144852 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 91720002 # DTB read hits @@ -618,6 +693,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 174219015 # DTB hits system.cpu1.dtb.misses 144852 # DTB misses system.cpu1.dtb.accesses 174363867 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -639,6 +722,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 61939 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 485906850 # ITB inst hits system.cpu1.itb.inst_misses 61939 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -861,15 +962,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 2333825 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 09df20817..70b8700c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111151 # Nu sim_ticks 51111150553500 # Number of ticks simulated final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1176583 # Simulator instruction rate (inst/s) -host_op_rate 1382679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61065327647 # Simulator tick rate (ticks/s) -host_mem_usage 656288 # Number of bytes of host memory used -host_seconds 836.99 # Real time elapsed on the host +host_inst_rate 1336104 # Simulator instruction rate (inst/s) +host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69344550867 # Simulator tick rate (ticks/s) +host_mem_usage 712616 # Number of bytes of host memory used +host_seconds 737.06 # Real time elapsed on the host sim_insts 984789519 # Number of instructions simulated sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -74,6 +74,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -95,6 +103,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 265618 # Table walker walks requested +system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 184057973 # DTB read hits @@ -116,6 +142,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 352334273 # DTB hits system.cpu.dtb.misses 265618 # DTB misses system.cpu.dtb.accesses 352599891 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -137,6 +171,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 126829 # Table walker walks requested +system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 985266544 # ITB inst hits system.cpu.itb.inst_misses 126829 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 2d0abc648..cd0cb8f17 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.398431 # Number of seconds simulated -sim_ticks 47398431268500 # Number of ticks simulated -final_tick 47398431268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.410782 # Number of seconds simulated +sim_ticks 47410781652000 # Number of ticks simulated +final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671569 # Simulator instruction rate (inst/s) -host_op_rate 790318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37657329129 # Simulator tick rate (ticks/s) -host_mem_usage 861000 # Number of bytes of host memory used -host_seconds 1258.68 # Real time elapsed on the host -sim_insts 845288376 # Number of instructions simulated -sim_ops 994755388 # Number of ops (including micro ops) simulated +host_inst_rate 787433 # Simulator instruction rate (inst/s) +host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41969003911 # Simulator tick rate (ticks/s) +host_mem_usage 699232 # Number of bytes of host memory used +host_seconds 1129.66 # Real time elapsed on the host +sim_insts 889532971 # Number of instructions simulated +sim_ops 1046714541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 36416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 41984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 768052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7936536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 44723840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 83456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 97984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 589368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8667104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 21031552 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441920 # Number of bytes read from this memory -system.physmem.bytes_read::total 84418212 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 768052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 589368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1357420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65101248 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory +system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 65122064 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 52408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 124030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 698810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 135438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 328618 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6905 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1359566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1017207 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory +system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019810 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 16204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 167443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 943572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 182856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 443718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1781034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 16204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 28639 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1373490 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1373929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1373490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 16204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 167882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 943572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 182856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 443718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3154963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1359566 # Number of read requests accepted -system.physmem.writeReqs 1139623 # Number of write requests accepted -system.physmem.readBursts 1359566 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1139623 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 86962304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49920 # Total number of bytes read from write queue -system.physmem.bytesWritten 72439488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 84418212 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 72790096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 780 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7732 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 85004 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 81504 # Per bank write bursts -system.physmem.perBankRdBursts::1 94599 # Per bank write bursts -system.physmem.perBankRdBursts::2 79086 # Per bank write bursts -system.physmem.perBankRdBursts::3 89082 # Per bank write bursts -system.physmem.perBankRdBursts::4 90127 # Per bank write bursts -system.physmem.perBankRdBursts::5 94039 # Per bank write bursts -system.physmem.perBankRdBursts::6 78740 # Per bank write bursts -system.physmem.perBankRdBursts::7 79772 # Per bank write bursts -system.physmem.perBankRdBursts::8 80197 # Per bank write bursts -system.physmem.perBankRdBursts::9 124149 # Per bank write bursts -system.physmem.perBankRdBursts::10 71869 # Per bank write bursts -system.physmem.perBankRdBursts::11 83577 # Per bank write bursts -system.physmem.perBankRdBursts::12 73174 # Per bank write bursts -system.physmem.perBankRdBursts::13 83519 # Per bank write bursts -system.physmem.perBankRdBursts::14 78794 # Per bank write bursts -system.physmem.perBankRdBursts::15 76558 # Per bank write bursts -system.physmem.perBankWrBursts::0 70549 # Per bank write bursts -system.physmem.perBankWrBursts::1 76959 # Per bank write bursts -system.physmem.perBankWrBursts::2 69527 # Per bank write bursts -system.physmem.perBankWrBursts::3 76268 # Per bank write bursts -system.physmem.perBankWrBursts::4 71760 # Per bank write bursts -system.physmem.perBankWrBursts::5 76111 # Per bank write bursts -system.physmem.perBankWrBursts::6 67646 # Per bank write bursts -system.physmem.perBankWrBursts::7 68141 # Per bank write bursts -system.physmem.perBankWrBursts::8 69345 # Per bank write bursts -system.physmem.perBankWrBursts::9 72887 # Per bank write bursts -system.physmem.perBankWrBursts::10 65485 # Per bank write bursts -system.physmem.perBankWrBursts::11 73987 # Per bank write bursts -system.physmem.perBankWrBursts::12 65828 # Per bank write bursts -system.physmem.perBankWrBursts::13 73935 # Per bank write bursts -system.physmem.perBankWrBursts::14 66021 # Per bank write bursts -system.physmem.perBankWrBursts::15 67418 # Per bank write bursts +system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 921890 # Number of read requests accepted +system.physmem.writeReqs 1829645 # Number of write requests accepted +system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue +system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 54393 # Per bank write bursts +system.physmem.perBankRdBursts::1 56084 # Per bank write bursts +system.physmem.perBankRdBursts::2 54659 # Per bank write bursts +system.physmem.perBankRdBursts::3 58883 # Per bank write bursts +system.physmem.perBankRdBursts::4 54974 # Per bank write bursts +system.physmem.perBankRdBursts::5 58047 # Per bank write bursts +system.physmem.perBankRdBursts::6 51881 # Per bank write bursts +system.physmem.perBankRdBursts::7 58759 # Per bank write bursts +system.physmem.perBankRdBursts::8 52533 # Per bank write bursts +system.physmem.perBankRdBursts::9 95950 # Per bank write bursts +system.physmem.perBankRdBursts::10 53815 # Per bank write bursts +system.physmem.perBankRdBursts::11 56993 # Per bank write bursts +system.physmem.perBankRdBursts::12 52328 # Per bank write bursts +system.physmem.perBankRdBursts::13 55917 # Per bank write bursts +system.physmem.perBankRdBursts::14 52932 # Per bank write bursts +system.physmem.perBankRdBursts::15 53389 # Per bank write bursts +system.physmem.perBankWrBursts::0 113787 # Per bank write bursts +system.physmem.perBankWrBursts::1 117144 # Per bank write bursts +system.physmem.perBankWrBursts::2 115098 # Per bank write bursts +system.physmem.perBankWrBursts::3 118536 # Per bank write bursts +system.physmem.perBankWrBursts::4 116769 # Per bank write bursts +system.physmem.perBankWrBursts::5 120895 # Per bank write bursts +system.physmem.perBankWrBursts::6 109520 # Per bank write bursts +system.physmem.perBankWrBursts::7 112924 # Per bank write bursts +system.physmem.perBankWrBursts::8 111914 # Per bank write bursts +system.physmem.perBankWrBursts::9 117541 # Per bank write bursts +system.physmem.perBankWrBursts::10 111832 # Per bank write bursts +system.physmem.perBankWrBursts::11 116807 # Per bank write bursts +system.physmem.perBankWrBursts::12 108182 # Per bank write bursts +system.physmem.perBankWrBursts::13 109739 # Per bank write bursts +system.physmem.perBankWrBursts::14 110202 # Per bank write bursts +system.physmem.perBankWrBursts::15 111930 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 47398428076000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 47410778671000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1316329 # Read request sizes (log2) +system.physmem.readPktSize::6 878653 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1137020 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 566894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 282234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 134057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 101972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 58693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 53670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 46721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 35916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1827042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,158 +188,182 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 30737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 39170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 50283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 72051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 76579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 78341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 74556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 78312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 75395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.646870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.183985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 295.195613 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 325424 50.15% 50.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 135792 20.93% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50411 7.77% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26706 4.12% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22287 3.43% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16108 2.48% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10950 1.69% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13619 2.10% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 47609 7.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648906 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 58676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.156827 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 139.787244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 58673 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 373 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 58676 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 58676 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.290119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.850822 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.308232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 54948 93.65% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 970 1.65% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 598 1.02% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 219 0.37% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 626 1.07% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 147 0.25% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 195 0.33% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 132 0.22% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 184 0.31% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 81 0.14% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 205 0.35% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 24 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 63 0.11% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 38 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 129 0.22% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 27 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 11 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 19 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 58676 # Writes before turning the bus around for reads -system.physmem.totQLat 69966976258 # Total ticks spent queuing -system.physmem.totMemAccLat 95444213758 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6793930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51492.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads +system.physmem.totQLat 32913462781 # Total ticks spent queuing +system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70242.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 1114788 # Number of row buffer hits during reads -system.physmem.writeRowHits 726958 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.23 # Row buffer hit rate for writes -system.physmem.avgGap 18965523.65 # Average gap between requests -system.physmem.pageHitRate 73.95 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45538400789750 # Time in different power states -system.physmem.memoryStateTime::REF 1582737780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 277292625250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2564850960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2340878400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1399472250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1277265000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5358202200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5240320800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3738707280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3595790880 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1171174509540 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1161726671475 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27411712647750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27420000225000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31691783487660 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31690016249235 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.625157 # Core power per rank (mW) -system.physmem.averagePower::1 668.587872 # Core power per rank (mW) +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing +system.physmem.readRowHits 687654 # Number of row buffer hits during reads +system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes +system.physmem.avgGap 17230665.31 # Average gap between requests +system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.749637 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states +system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.723459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states +system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -373,6 +397,14 @@ system.cf0.dma_write_full_pages 1670 # Nu system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1673 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,27 +426,74 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 107972 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 74706058 # DTB read hits -system.cpu0.dtb.read_misses 64792 # DTB read misses -system.cpu0.dtb.write_hits 67192400 # DTB write hits -system.cpu0.dtb.write_misses 21129 # DTB write misses +system.cpu0.dtb.read_hits 83792624 # DTB read hits +system.cpu0.dtb.read_misses 78614 # DTB read misses +system.cpu0.dtb.write_hits 76883618 # DTB write hits +system.cpu0.dtb.write_misses 29358 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 33482 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3817 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8375 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 74770850 # DTB read accesses -system.cpu0.dtb.write_accesses 67213529 # DTB write accesses +system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83871238 # DTB read accesses +system.cpu0.dtb.write_accesses 76912976 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 141898458 # DTB hits -system.cpu0.dtb.misses 85921 # DTB misses -system.cpu0.dtb.accesses 141984379 # DTB accesses +system.cpu0.dtb.hits 160676242 # DTB hits +system.cpu0.dtb.misses 107972 # DTB misses +system.cpu0.dtb.accesses 160784214 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -436,201 +515,236 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 397874920 # ITB inst hits -system.cpu0.itb.inst_misses 49120 # ITB inst misses +system.cpu0.itb.walker.walks 64255 # Table walker walks requested +system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 448595101 # ITB inst hits +system.cpu0.itb.inst_misses 64255 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 23760 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 397924040 # ITB inst accesses -system.cpu0.itb.hits 397874920 # DTB hits -system.cpu0.itb.misses 49120 # DTB misses -system.cpu0.itb.accesses 397924040 # DTB accesses -system.cpu0.numCycles 94796862537 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses +system.cpu0.itb.hits 448595101 # DTB hits +system.cpu0.itb.misses 64255 # DTB misses +system.cpu0.itb.accesses 448659356 # DTB accesses +system.cpu0.numCycles 94821563304 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 397643174 # Number of instructions committed -system.cpu0.committedOps 466635553 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 429030148 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 322477 # Number of float alu accesses -system.cpu0.num_func_calls 23930039 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 59901605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 429030148 # number of integer instructions -system.cpu0.num_fp_insts 322477 # number of float instructions -system.cpu0.num_int_register_reads 621630892 # number of times the integer registers were read -system.cpu0.num_int_register_writes 340702516 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 547437 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 211832 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 102593685 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 102325899 # number of times the CC registers were written -system.cpu0.num_mem_refs 141893093 # number of memory refs -system.cpu0.num_load_insts 74704433 # Number of load instructions -system.cpu0.num_store_insts 67188660 # Number of store instructions -system.cpu0.num_idle_cycles 93886429062.298019 # Number of idle cycles -system.cpu0.num_busy_cycles 910433474.701981 # Number of busy cycles -system.cpu0.not_idle_fraction 0.009604 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.990396 # Percentage of idle cycles -system.cpu0.Branches 88352328 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 323823287 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1114929 0.24% 69.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 56737 0.01% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 22377 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::MemRead 74704433 16.00% 85.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 67188660 14.39% 100.00% # Class of executed instruction +system.cpu0.committedInsts 448345930 # Number of instructions committed +system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses +system.cpu0.num_func_calls 26890258 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls +system.cpu0.num_int_insts 484594714 # number of integer instructions +system.cpu0.num_fp_insts 558267 # number of float instructions +system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read +system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written +system.cpu0.num_mem_refs 160668093 # number of memory refs +system.cpu0.num_load_insts 83788812 # Number of load instructions +system.cpu0.num_store_insts 76879281 # Number of store instructions +system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles +system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles +system.cpu0.Branches 100174256 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction +system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction +system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 466910423 # Class of executed instruction +system.cpu0.op_class::total 527943731 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 4859280 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.680410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 136835586 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 4859789 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.156693 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.680410 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 9 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 288671468 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 288671468 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 69599952 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 69599952 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 63413457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 63413457 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 173858 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 173858 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1561841 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1561841 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 133013409 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 133013409 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 133187267 # number of overall hits -system.cpu0.dcache.overall_hits::total 133187267 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2622769 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2622769 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1185607 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1185607 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 553155 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 553155 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145021 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 145021 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178721 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 178721 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3808376 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3808376 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4361531 # number of overall misses -system.cpu0.dcache.overall_misses::total 4361531 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 55222501244 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 55222501244 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 72222721 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 72222721 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 64599064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 64599064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 727013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 727013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 831127 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 831127 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027835 # miss rate for demand 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LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5753925 # number of replacements +system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits 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(read+write) hits +system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits +system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 172905 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200615 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 200615 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4518537 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4518537 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5216802 # number of overall misses +system.cpu0.dcache.overall_misses::total 5216802 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45365631768 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 45365631768 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25986134990 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 25986134990 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 26026367891 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 26026367891 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2610218258 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2610218258 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4265500897 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4265500897 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2243000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2243000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 71351766758 # number of demand (read+write) miss cycles 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for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038058 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019454 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.019454 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.794192 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.794192 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.869570 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.869570 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101055 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101055 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029173 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029173 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033491 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.033491 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14731.899328 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.899328 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18056.936792 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18056.936792 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 33249.656203 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15790.900187 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15790.900187 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13677.300146 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,92 +753,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3276433 # number of writebacks -system.cpu0.dcache.writebacks::total 3276433 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 20828 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 20828 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21424 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21424 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 36174 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 36174 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 42252 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 42252 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 42252 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 42252 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2601941 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2601941 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1164183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1164183 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 551435 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 551435 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 697992 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 697992 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108847 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 108847 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178721 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 178721 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 3766124 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 3766124 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4317559 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4317559 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30561578872 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30561578872 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 15647124797 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 15647124797 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 11524265112 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 11524265112 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 10542114896 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 10542114896 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1234908207 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1234908207 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3440508666 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3440508666 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 879000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 879000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 46208703669 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 46208703669 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 57732968781 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 57732968781 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2384094697 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2384094697 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2386757695 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2386757695 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4770852392 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4770852392 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036027 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036027 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018022 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018022 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758494 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758494 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839814 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839814 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102680 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102680 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027526 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027526 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031389 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031389 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3895213 # number of writebacks +system.cpu0.dcache.writebacks::total 3895213 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 35120 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 35120 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21470 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21470 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46933 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46933 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 56590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 56590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 56590 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 56590 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3044295 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3044295 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417652 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1417652 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 692633 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 692633 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 782756 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 782756 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125972 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125972 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200615 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 200615 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4461947 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4461947 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5154580 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5154580 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37795344499 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37795344499 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22579422262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22579422262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14234213672 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14234213672 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24458156109 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24458156109 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564829744 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564829744 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3853276103 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3853276103 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2137000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2137000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60374766761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 60374766761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2244465248 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2244465248 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4532259246 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4532259246 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037624 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037624 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019164 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019164 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.787787 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.787787 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.869570 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.869570 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063415 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063415 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028808 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028808 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033092 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033092 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12415.138644 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12415.138644 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15927.337782 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15927.337782 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20550.874232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20550.874232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31246.207131 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 31246.207131 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12422.044137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.044137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19207.318012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19207.318012 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13531.036286 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13531.036286 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14474.308369 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14474.308369 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -732,59 +846,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4269396 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932974 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 393605012 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4269908 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 92.181146 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 18918806750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932974 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 5166576 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.910022 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 443428013 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5167088 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.817778 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30209622750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.910022 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999824 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999824 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 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-system.cpu0.icache.ReadReq_misses::cpu0.inst 4269908 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4269908 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4269908 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4269908 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4269908 # number of overall misses -system.cpu0.icache.overall_misses::total 4269908 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 37643365597 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 37643365597 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 37643365597 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 37643365597 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 37643365597 # number of overall miss cycles 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overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10391.679717 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,384 +906,383 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4269908 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4269908 # number of ReadReq MSHR misses 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(read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45925261947 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 45925261947 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for demand accesses 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mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency 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WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2085589258 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2085589258 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2284466860 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2284466860 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1713000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1713000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9147060396 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9147060396 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 312733504 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11805310434 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34625863602 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 47071840049 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 312733504 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11805310434 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34625863602 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34882867408 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 81954707457 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2268534801 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5330399551 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2268405055 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2268405055 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2174725243 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5236589993 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129495502 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2129495502 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4536939856 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7598804606 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.265568 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.130853 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4304220745 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7366085495 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253426 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160493 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.070057 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.070057 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.585799 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.585799 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824608 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824608 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.696946 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.696946 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.535384 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.535384 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.828730 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.828730 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.172158 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.172158 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135483 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205407 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205407 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.469001 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22395.109853 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22273.429726 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43752.426923 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 18274.092453 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 18274.092453 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16661.502488 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16661.502488 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13865.687238 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13865.687238 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 687000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 687000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1180,59 +1292,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11465749 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 8074092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3276433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4228803 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 811507 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 696929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 407420 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 328722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 423022 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1108208 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 995011 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 8626066 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14109371 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 260774 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 426575 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 23422786 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 273446612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 532438419 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 912728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1410280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 808208039 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8581549 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 21569506 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.385644 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.486747 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 13251364 61.44% 61.44% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8318142 38.56% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21569506 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 10644176370 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 173370992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 6459583336 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 6973558574 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 146771777 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 250366041 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1254,27 +1374,82 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 99527 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84980512 # DTB read hits -system.cpu1.dtb.read_misses 74547 # DTB read misses -system.cpu1.dtb.write_hits 77969612 # DTB write hits -system.cpu1.dtb.write_misses 26781 # DTB write misses +system.cpu1.dtb.read_hits 83767099 # DTB read hits +system.cpu1.dtb.read_misses 74857 # DTB read misses +system.cpu1.dtb.write_hits 75685520 # DTB write hits +system.cpu1.dtb.write_misses 24670 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37319 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4156 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10210 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 85055059 # DTB read accesses -system.cpu1.dtb.write_accesses 77996393 # DTB write accesses +system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83841956 # DTB read accesses +system.cpu1.dtb.write_accesses 75710190 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162950124 # DTB hits -system.cpu1.dtb.misses 101328 # DTB misses -system.cpu1.dtb.accesses 163051452 # DTB accesses +system.cpu1.dtb.hits 159452619 # DTB hits +system.cpu1.dtb.misses 99527 # DTB misses +system.cpu1.dtb.accesses 159552146 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1296,201 +1471,239 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 447940407 # ITB inst hits -system.cpu1.itb.inst_misses 68561 # ITB inst misses +system.cpu1.itb.walker.walks 55326 # Table walker walks requested +system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 441493680 # ITB inst hits +system.cpu1.itb.inst_misses 55326 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26339 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448008968 # ITB inst accesses -system.cpu1.itb.hits 447940407 # DTB hits -system.cpu1.itb.misses 68561 # DTB misses -system.cpu1.itb.accesses 448008968 # DTB accesses -system.cpu1.numCycles 94796862537 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses +system.cpu1.itb.hits 441493680 # DTB hits +system.cpu1.itb.misses 55326 # DTB misses +system.cpu1.itb.accesses 441549006 # DTB accesses +system.cpu1.numCycles 94821563303 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 447645202 # Number of instructions committed -system.cpu1.committedOps 528119835 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 486291398 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 624474 # Number of float alu accesses -system.cpu1.num_func_calls 27450761 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67545606 # number of instructions that are conditional controls -system.cpu1.num_int_insts 486291398 # number of integer instructions -system.cpu1.num_fp_insts 624474 # number of float instructions -system.cpu1.num_int_register_reads 698728829 # number of times the integer registers were read -system.cpu1.num_int_register_writes 384530758 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 985803 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 576512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 114161169 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113813296 # number of times the CC registers were written -system.cpu1.num_mem_refs 162934099 # number of memory refs -system.cpu1.num_load_insts 84972579 # Number of load instructions -system.cpu1.num_store_insts 77961520 # Number of store instructions -system.cpu1.num_idle_cycles 93770083152.566025 # Number of idle cycles -system.cpu1.num_busy_cycles 1026779384.433978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010831 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989169 # Percentage of idle cycles -system.cpu1.Branches 100081816 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364276895 68.94% 68.94% # Class of executed instruction -system.cpu1.op_class::IntMult 1051011 0.20% 69.14% # Class of executed instruction -system.cpu1.op_class::IntDiv 60606 0.01% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 92495 0.02% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::MemRead 84972579 16.08% 85.25% # Class of executed instruction -system.cpu1.op_class::MemWrite 77961520 14.75% 100.00% # Class of executed instruction +system.cpu1.committedInsts 441187041 # Number of instructions committed +system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses +system.cpu1.num_func_calls 26570520 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls +system.cpu1.num_int_insts 477531543 # number of integer instructions +system.cpu1.num_fp_insts 364386 # number of float instructions +system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read +system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written +system.cpu1.num_mem_refs 159443034 # number of memory refs +system.cpu1.num_load_insts 83763663 # Number of load instructions +system.cpu1.num_store_insts 75679371 # Number of store instructions +system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles +system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles +system.cpu1.Branches 98214896 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction +system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 528415149 # Class of executed instruction +system.cpu1.op_class::total 519369853 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13701 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5194711 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.134068 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 157559099 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5195223 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.327687 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8367548601000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.134068 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 331059949 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 331059949 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79405575 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79405575 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 74066119 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 74066119 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191889 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191889 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1654141 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1654141 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 153471694 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 153471694 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 153663583 # number of overall hits -system.cpu1.dcache.overall_hits::total 153663583 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2946837 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2946837 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1283113 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1283113 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 571898 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 571898 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 171203 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 171203 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185528 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 185528 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4229950 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4229950 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4801848 # number of overall misses -system.cpu1.dcache.overall_misses::total 4801848 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 41215882509 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 41215882509 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19312866378 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 19312866378 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 60528748887 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 60528748887 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82352412 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82352412 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75349232 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75349232 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 763787 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 763787 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 748341 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 748341 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1840883 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1840883 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1839669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1839669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 157701644 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 157701644 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 158465431 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 158465431 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035783 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017029 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.017029 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.748766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.748766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.735906 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.735906 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093000 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093000 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100849 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100849 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026822 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026822 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030302 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030302 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.481950 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13986.481950 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15051.570967 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 15051.570967 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 11976.739247 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 11976.739247 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13922.971916 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13922.971916 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4977655 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 211446 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1712714 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1712714 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1673213 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1673213 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 150096526 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 150096526 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 150288224 # number of overall hits +system.cpu1.dcache.overall_hits::total 150288224 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2870044 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2870044 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1235849 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1235849 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 574884 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 574884 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 468795 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 468795 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 161452 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 161452 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199386 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 199386 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4105893 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4105893 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4680777 # number of overall misses +system.cpu1.dcache.overall_misses::total 4680777 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39400522531 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 39400522531 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20561069776 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 20561069776 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12119187041 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles 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accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1874166 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1874166 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1872599 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1872599 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154202419 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154202419 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 154969001 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 154969001 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035388 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035388 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016906 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.016906 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.749932 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.749932 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.689160 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.689160 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086146 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086146 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106476 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106476 # miss rate for StoreCondReq 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12605.302976 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1499,92 +1712,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed 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overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932101 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2932101 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1282706 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1282706 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 571898 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 571898 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 550709 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 550709 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 122389 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 122389 # number of LoadLockedReq MSHR misses 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number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1037500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51359578044 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 51359578044 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 62972032328 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 62972032328 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3972621225 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3972621225 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3807943973 # number of WriteReq MSHR uncacheable cycles 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-system.cpu1.dcache.overall_mshr_miss_rate::total 0.030207 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3230902 # number of writebacks +system.cpu1.dcache.writebacks::total 3230902 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11797 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11797 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 280 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits 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of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1592,59 +1805,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5786522 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.339295 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 442153368 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5787034 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 76.404142 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367526246000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.339295 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969413 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969413 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 4937125 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. 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+system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 901667853 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 901667853 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 442153368 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 442153368 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 442153368 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 442153368 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 442153368 # number of overall hits -system.cpu1.icache.overall_hits::total 442153368 # number of overall hits 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-system.cpu1.icache.overall_miss_latency::total 50052191468 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 447940407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 447940407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 447940407 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 447940407 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 447940407 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 447940407 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012919 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.012919 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012919 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.012919 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8649.015752 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8649.015752 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8649.015752 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits +system.cpu1.icache.overall_hits::total 436556038 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4937642 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4937642 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4937642 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4937642 # number of overall misses +system.cpu1.icache.overall_misses::total 4937642 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50835870381 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 50835870381 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 50835870381 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 50835870381 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 50835870381 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 50835870381 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 441493680 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 441493680 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 441493680 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 441493680 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 441493680 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 441493680 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011184 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011184 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011184 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011184 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011184 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011184 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10295.576387 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10295.576387 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1653,384 +1866,377 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5787039 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5787039 # number of ReadReq MSHR misses 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overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9075250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9075250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9075250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9075250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012919 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.012919 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.012919 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7148.511456 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4937642 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4937642 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4937642 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 4937642 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4937642 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4937642 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43414323627 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 43414323627 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43414323627 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 43414323627 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43414323627 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 43414323627 # number of overall MSHR miss cycles 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0.011184 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8792.521537 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 55302288 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 976452 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 51578919 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9282 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 584 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2737051 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4557576 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3265247 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13732.593717 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11929802 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3281353 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.635635 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9719592338000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 3548.297662 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 58.425503 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.675774 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 758.406628 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2477.157386 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6824.630764 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.216571 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003566 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004009 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.046289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.151194 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.416542 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.838171 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8592 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7474 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 93 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 541 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2721 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4842 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 395 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 810 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3409 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 229 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.524414 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002441 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.456177 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 249010603 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 249010603 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 204488 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158918 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5602514 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2695724 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8661644 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3397427 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3397427 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 491178 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 491178 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77109 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 77109 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35497 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 35497 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 899510 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 899510 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 204488 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158918 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5602514 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3595234 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9561154 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 204488 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158918 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5602514 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3595234 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9561154 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11072 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9747 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 184525 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 930664 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1136008 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 58187 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 58187 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 111708 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 111708 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 150027 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 150027 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 196006 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 196006 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11072 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9747 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 184525 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1126670 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1332014 # number of demand (read+write) misses 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WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 1715319866 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2196780170 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2196780170 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3055684059 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3055684059 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1008500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1008500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 6932150792 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 6932150792 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 339143470 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 328936960 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4835548618 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 34777443242 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 40281072290 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 339143470 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 328936960 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4835548618 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 34777443242 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 40281072290 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 215560 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168665 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5787039 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3626388 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9797652 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3397427 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3397427 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 549365 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 549365 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 188817 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 188817 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 185524 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 185524 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1095516 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1095516 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 215560 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168665 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5787039 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4721904 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10893168 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 215560 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 168665 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5787039 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4721904 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10893168 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.051364 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057789 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.031886 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.256637 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.115947 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.105917 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.105917 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.591620 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.591620 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.808666 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.808666 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6896094 # number of hwpf issued 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9789299685500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5807.381964 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.245810 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 78.947620 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2946.895146 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3156.020749 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 990.255474 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.354454 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003738 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004819 # Average percentage of cache occupancy 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task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 188 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1044 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1799 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10295 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id 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latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222784 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22345.362493 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22234.428550 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2040,65 +2246,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 13482596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10019474 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3397427 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3948207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 669175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 549365 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 394300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332875 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 429984 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1203009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1101184 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11574298 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14922836 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373561 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 511408 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27382103 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 370370936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 560535931 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349320 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1724480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 933980667 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 8332859 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 23404111 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.344949 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.475352 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15330876 65.51% 65.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8073235 34.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 23404111 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11646725084 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 158989494 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8682146940 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7623277083 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 205120292 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 296049290 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40487 # Transaction distribution -system.iobus.trans_dist::ReadResp 40487 # Transaction distribution -system.iobus.trans_dist::WriteReq 137083 # Transaction distribution -system.iobus.trans_dist::WriteResp 30163 # Transaction distribution +system.iobus.trans_dist::ReadReq 40416 # Transaction distribution +system.iobus.trans_dist::ReadResp 40416 # Transaction distribution +system.iobus.trans_dist::WriteReq 136984 # Transaction distribution +system.iobus.trans_dist::WriteResp 30064 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48390 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2108,18 +2315,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 355140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2129,18 +2336,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156518 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7351088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7509692 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36789000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2160,7 +2367,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2168,71 +2375,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1044839337 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93320000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179372271 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115786 # number of replacements -system.iocache.tags.tagsinuse 11.223287 # Cycle average of tags in use +system.iocache.tags.replacements 115804 # number of replacements +system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115802 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9123835798000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.412555 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.810732 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463285 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.238171 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.701455 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042467 # Number of tag accesses -system.iocache.tags.data_accesses 1042467 # Number of data accesses +system.iocache.tags.tag_accesses 1042755 # Number of tag accesses +system.iocache.tags.data_accesses 1042755 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8870 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8907 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 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8942 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1942659591 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1948366591 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5984000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1958941092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1964925092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5984000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1958941092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1964925092 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8870 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8870 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8910 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8870 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8910 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2246,55 +2453,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220564.510161 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225288 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27401 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.221890 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106886 # number of writebacks -system.iocache.writebacks::total 106886 # number of writebacks +system.iocache.writebacks::writebacks 106887 # number of writebacks +system.iocache.writebacks::total 106887 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8870 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8870 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8910 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8870 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8910 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3703000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1497575112 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1501278112 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1479616613 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1483399613 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23337113496 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23337113496 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3904000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1497575112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1501479112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3904000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1497575112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1501479112 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427435940 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427435940 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1479616613 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2308,567 +2515,560 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166211.706695 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165946.930641 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219111.821362 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219111.821362 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1310456 # number of replacements -system.l2c.tags.tagsinuse 64677.337118 # Cycle average of tags in use -system.l2c.tags.total_refs 7257968 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1373726 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.283418 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 5621833500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9998.305247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 56.991260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 77.146603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 791.679733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4513.780403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.211809 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 222.184258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 784.998757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7219.989726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.152562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000870 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.012080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.363444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002292 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.110168 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.260061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.986898 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 38915 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 205 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 24150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 487 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 8729 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29647 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5282 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18136 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.593796 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003128 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.368500 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74054042 # Number of tag accesses -system.l2c.tags.data_accesses 74054042 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4407 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 131001 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 549137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1653135 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 7096 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6374 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 146834 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 607953 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1853450 # number of ReadReq hits -system.l2c.ReadReq_hits::total 4964901 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2477309 # number of Writeback hits -system.l2c.Writeback_hits::total 2477309 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 3452 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 4029 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 7481 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 31717 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 34608 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 66325 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7299 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8593 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15892 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 45918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59655 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105573 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4407 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 131001 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 595055 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1653135 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 7096 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6374 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 146834 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 667608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1853450 # number of demand (read+write) hits -system.l2c.demand_hits::total 5070474 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5514 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4407 # number of overall hits -system.l2c.overall_hits::cpu0.inst 131001 # number of overall hits -system.l2c.overall_hits::cpu0.data 595055 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1653135 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 7096 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6374 # number of overall hits -system.l2c.overall_hits::cpu1.inst 146834 # number of overall hits -system.l2c.overall_hits::cpu1.data 667608 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1853450 # number of overall hits -system.l2c.overall_hits::total 5070474 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 569 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 656 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9314 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 87213 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 698997 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1531 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9213 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 99987 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 328949 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1237733 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 9435 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 3626 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 13061 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 30881 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 31286 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 62167 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9976 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9599 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 19575 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 38485 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 37338 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 75823 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 569 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 656 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9314 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 125698 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 698997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1304 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1531 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9213 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 137325 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 328949 # number of demand (read+write) misses -system.l2c.demand_misses::total 1313556 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 569 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 656 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9314 # number of overall misses -system.l2c.overall_misses::cpu0.data 125698 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 698997 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1304 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1531 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9213 # number of overall misses -system.l2c.overall_misses::cpu1.data 137325 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 328949 # number of overall misses -system.l2c.overall_misses::total 1313556 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 46419250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 56195000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 845205741 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 7070866945 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 100071825385 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 105377999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 124997499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 812177995 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 7981910698 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 38448513875 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 155563490387 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 1840421 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 2071411 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 3911832 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 134255920 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 141850516 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 276106436 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 49268414 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 49362431 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 98630845 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 2848027798 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2731267565 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5579295363 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 46419250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 56195000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 845205741 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9918894743 # number of demand (read+write) miss cycles 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accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 636350 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2352132 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 8400 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7905 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 156047 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 707940 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2182399 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 6202634 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2477309 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2477309 # number of Writeback accesses(hits+misses) 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-system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2182399 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 6384030 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 6083 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5063 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 140315 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 720753 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2352132 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8400 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7905 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 156047 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 804933 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2182399 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 6384030 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.093539 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.129567 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.066379 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.137052 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.297176 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.155238 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.193675 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.059040 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.141237 # miss rate for ReadReq accesses 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for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.455967 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.384956 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.417997 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.093539 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.129567 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.066379 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.174398 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.297176 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155238 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.193675 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.059040 # miss rate for demand accesses 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0.170604 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.150728 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.205757 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81580.404218 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85663.109756 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 90745.731265 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 81075.836687 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80811.348926 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 81644.349445 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88155.649083 # average ReadReq miss latency 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blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2392.943065 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3574.441825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5977.605096 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.301650 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003482 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004999 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.067191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.199529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217905 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001239 # Average percentage of cache occupancy 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rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.174375 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.297121 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155238 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193675 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.058976 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.170592 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.205710 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.093539 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129567 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.066329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.174375 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.297121 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155238 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193675 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.058976 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.170592 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.205710 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68538.072262 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67290.296268 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 113420.305476 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 19988.031585 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 19972.307777 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 19983.666335 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10132.657589 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.550438 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.518973 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10124.336608 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.007397 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10142.318876 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61378.878992 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60517.887969 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60954.895731 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3786921248 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6014500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6832242748 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12871375746 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.206075 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.154495 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.229677 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.776063 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.521612 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.689229 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584496 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.627511 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.605641 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.632847 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.638128 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.635412 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589079 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.524669 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.562469 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.250858 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.250858 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70801.479758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70176.265391 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 95099.746219 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22466.608046 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20243.971628 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21892.569988 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10081.122986 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10172.643319 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10127.734904 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10094.514924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10170.084593 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10131.367291 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66785.676932 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63285.951301 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65436.965728 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2883,58 +3083,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1327465 # Transaction distribution -system.membus.trans_dist::ReadResp 1327465 # Transaction distribution -system.membus.trans_dist::WriteReq 37863 # Transaction distribution -system.membus.trans_dist::WriteResp 37863 # Transaction distribution -system.membus.trans_dist::Writeback 1017207 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 119813 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 119813 # Transaction distribution -system.membus.trans_dist::UpgradeReq 367379 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 281461 # Transaction distribution -system.membus.trans_dist::UpgradeResp 85028 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 87184 # Transaction distribution -system.membus.trans_dist::ReadExResp 72708 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123480 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 841910 # Transaction distribution +system.membus.trans_dist::ReadResp 841910 # Transaction distribution +system.membus.trans_dist::WriteReq 38471 # Transaction distribution +system.membus.trans_dist::WriteResp 38471 # Transaction distribution +system.membus.trans_dist::Writeback 1161772 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution +system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution +system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 138806 # Transaction distribution +system.membus.trans_dist::ReadExResp 121371 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4395675 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4541961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4878502 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156518 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 45428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143082804 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 143284954 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157410458 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 581037 # Total snoops (count) -system.membus.snoop_fanout::samples 3119395 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 613627 # Total snoops (count) +system.membus.snoop_fanout::samples 3433927 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3119395 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3119395 # Request fanout histogram -system.membus.reqLayer0.occupancy 101251489 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3433927 # Request fanout histogram +system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19693498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11963097483 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12443113804 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187409729 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2978,45 +3178,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 7096727 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7089473 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37863 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37863 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2477309 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 127465 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 20542 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 430421 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 297353 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 727774 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 228196 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 228196 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8832957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8435767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17268724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294458407 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274483891 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 568942298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1532220 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10576474 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010952 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104077 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1593139 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10460641 98.90% 98.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115833 1.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10576474 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 15316484616 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7440499 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 16737915607 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 16438547163 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index e087cdc41..11eb5dd0c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821204 # Number of seconds simulated -sim_ticks 51821203872000 # Number of ticks simulated -final_tick 51821203872000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821157 # Number of seconds simulated +sim_ticks 51821157171000 # Number of ticks simulated +final_tick 51821157171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 797175 # Simulator instruction rate (inst/s) -host_op_rate 936716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46008450754 # Simulator tick rate (ticks/s) -host_mem_usage 656028 # Number of bytes of host memory used -host_seconds 1126.34 # Real time elapsed on the host -sim_insts 897890420 # Number of instructions simulated -sim_ops 1055061464 # Number of ops (including micro ops) simulated +host_inst_rate 734878 # Simulator instruction rate (inst/s) +host_op_rate 863519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42416153440 # Simulator tick rate (ticks/s) +host_mem_usage 712380 # Number of bytes of host memory used +host_seconds 1221.73 # Real time elapsed on the host +sim_insts 897823750 # Number of instructions simulated +sim_ops 1054987960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 274944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 280896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5219828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 52654408 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 402752 # Number of bytes read from this memory -system.physmem.bytes_read::total 58832828 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5219828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5219828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79485888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 267456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 270528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5250612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 52674824 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 383808 # Number of bytes read from this memory +system.physmem.bytes_read::total 58847228 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5250612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5250612 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79637568 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 79506468 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 121967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 822738 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6293 # Number of read requests responded to by this memory -system.physmem.num_reads::total 959683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1241967 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79658148 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 823057 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 5997 # Number of read requests responded to by this memory +system.physmem.num_reads::total 959908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1244337 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1244540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 100728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1016078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1135304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 100728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1533849 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1246910 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1016473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1135583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1536777 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1534246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1533849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 100728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1016476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2669550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 959683 # Number of read requests accepted -system.physmem.writeReqs 1860672 # Number of write requests accepted -system.physmem.readBursts 959683 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1860672 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61376064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43648 # Total number of bytes read from write queue -system.physmem.bytesWritten 118595648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58832828 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 118938916 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 682 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7593 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36288 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56975 # Per bank write bursts -system.physmem.perBankRdBursts::1 58359 # Per bank write bursts -system.physmem.perBankRdBursts::2 58716 # Per bank write bursts -system.physmem.perBankRdBursts::3 57264 # Per bank write bursts -system.physmem.perBankRdBursts::4 61545 # Per bank write bursts -system.physmem.perBankRdBursts::5 66145 # Per bank write bursts -system.physmem.perBankRdBursts::6 57228 # Per bank write bursts -system.physmem.perBankRdBursts::7 52937 # Per bank write bursts -system.physmem.perBankRdBursts::8 52189 # Per bank write bursts -system.physmem.perBankRdBursts::9 99547 # Per bank write bursts -system.physmem.perBankRdBursts::10 57680 # Per bank write bursts -system.physmem.perBankRdBursts::11 61393 # Per bank write bursts -system.physmem.perBankRdBursts::12 54506 # Per bank write bursts -system.physmem.perBankRdBursts::13 60286 # Per bank write bursts -system.physmem.perBankRdBursts::14 51564 # Per bank write bursts -system.physmem.perBankRdBursts::15 52667 # Per bank write bursts -system.physmem.perBankWrBursts::0 114739 # Per bank write bursts -system.physmem.perBankWrBursts::1 115397 # Per bank write bursts -system.physmem.perBankWrBursts::2 117633 # Per bank write bursts -system.physmem.perBankWrBursts::3 119136 # Per bank write bursts -system.physmem.perBankWrBursts::4 120318 # Per bank write bursts -system.physmem.perBankWrBursts::5 121968 # Per bank write bursts -system.physmem.perBankWrBursts::6 116613 # Per bank write bursts -system.physmem.perBankWrBursts::7 113695 # Per bank write bursts -system.physmem.perBankWrBursts::8 109286 # Per bank write bursts -system.physmem.perBankWrBursts::9 116370 # Per bank write bursts -system.physmem.perBankWrBursts::10 115629 # Per bank write bursts -system.physmem.perBankWrBursts::11 118249 # Per bank write bursts -system.physmem.perBankWrBursts::12 111968 # Per bank write bursts -system.physmem.perBankWrBursts::13 117797 # Per bank write bursts -system.physmem.perBankWrBursts::14 110347 # Per bank write bursts -system.physmem.perBankWrBursts::15 113912 # Per bank write bursts +system.physmem.bw_write::total 1537174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1536777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1016870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2672757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 959908 # Number of read requests accepted +system.physmem.writeReqs 1865455 # Number of write requests accepted +system.physmem.readBursts 959908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1865455 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61382336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 51776 # Total number of bytes read from write queue +system.physmem.bytesWritten 118954432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 58847228 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 119245028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 809 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6774 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36275 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 56974 # Per bank write bursts +system.physmem.perBankRdBursts::1 60608 # Per bank write bursts +system.physmem.perBankRdBursts::2 56247 # Per bank write bursts +system.physmem.perBankRdBursts::3 58787 # Per bank write bursts +system.physmem.perBankRdBursts::4 55621 # Per bank write bursts +system.physmem.perBankRdBursts::5 61105 # Per bank write bursts +system.physmem.perBankRdBursts::6 53454 # Per bank write bursts +system.physmem.perBankRdBursts::7 55202 # Per bank write bursts +system.physmem.perBankRdBursts::8 54549 # Per bank write bursts +system.physmem.perBankRdBursts::9 101006 # Per bank write bursts +system.physmem.perBankRdBursts::10 57136 # Per bank write bursts +system.physmem.perBankRdBursts::11 59250 # Per bank write bursts +system.physmem.perBankRdBursts::12 54470 # Per bank write bursts +system.physmem.perBankRdBursts::13 61564 # Per bank write bursts +system.physmem.perBankRdBursts::14 57688 # Per bank write bursts +system.physmem.perBankRdBursts::15 55438 # Per bank write bursts +system.physmem.perBankWrBursts::0 113578 # Per bank write bursts +system.physmem.perBankWrBursts::1 118177 # Per bank write bursts +system.physmem.perBankWrBursts::2 119014 # Per bank write bursts +system.physmem.perBankWrBursts::3 122732 # Per bank write bursts +system.physmem.perBankWrBursts::4 115108 # Per bank write bursts +system.physmem.perBankWrBursts::5 118421 # Per bank write bursts +system.physmem.perBankWrBursts::6 110433 # Per bank write bursts +system.physmem.perBankWrBursts::7 110649 # Per bank write bursts +system.physmem.perBankWrBursts::8 111009 # Per bank write bursts +system.physmem.perBankWrBursts::9 115530 # Per bank write bursts +system.physmem.perBankWrBursts::10 116272 # Per bank write bursts +system.physmem.perBankWrBursts::11 116171 # Per bank write bursts +system.physmem.perBankWrBursts::12 116950 # Per bank write bursts +system.physmem.perBankWrBursts::13 121923 # Per bank write bursts +system.physmem.perBankWrBursts::14 117171 # Per bank write bursts +system.physmem.perBankWrBursts::15 115525 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51821201316000 # Total gap between requests +system.physmem.totGap 51821154615000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 916567 # Read request sizes (log2) +system.physmem.readPktSize::6 916792 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1858099 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 925038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1862882 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 923488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 30071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,120 +159,140 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 58079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 70983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 101652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 104342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 108305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 122410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 126456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 111805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 113098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 110863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 108761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 105735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 102887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 101533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 95973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 95806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 94380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 565 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.physmem.wrQLenPdf::21 127000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 113028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 114051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 111714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 106267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 103051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 101586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 96822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 95736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 95578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 94283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see 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activation -system.physmem.bytesPerActivate::stdev 330.841680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256797 41.58% 41.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 151085 24.46% 66.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51876 8.40% 74.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 29038 4.70% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19766 3.20% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13229 2.14% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10059 1.63% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9064 1.47% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 76697 12.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 617611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 92036 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.419705 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.178395 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 92034 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 618930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.368084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.608476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.498173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 256436 41.43% 41.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 152224 24.59% 66.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51996 8.40% 74.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28892 4.67% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20098 3.25% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13547 2.19% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10018 1.62% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9306 1.50% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 76413 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 618930 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 92468 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.372118 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 105.903641 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 92466 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 92036 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 92036 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.134045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.130429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.695121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 84651 91.98% 91.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 3801 4.13% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1276 1.39% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 446 0.48% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 607 0.66% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 136 0.15% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 198 0.22% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 105 0.11% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 166 0.18% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 53 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 197 0.21% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 35 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 54 0.06% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 56 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 137 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 24 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 33 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 16 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 92036 # Writes before turning the bus around for reads -system.physmem.totQLat 12714966775 # Total ticks spent queuing -system.physmem.totMemAccLat 30696235525 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4795005000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13258.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 92468 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 92468 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.100608 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.118632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.444453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 55053 59.54% 59.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 30512 33.00% 92.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2134 2.31% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1149 1.24% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 862 0.93% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 455 0.49% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 271 0.29% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 154 0.17% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 523 0.57% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 85 0.09% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 63 0.07% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 90 0.10% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 138 0.15% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 53 0.06% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 45 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 77 0.08% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 126 0.14% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 47 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 24 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 42 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 157 0.17% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 21 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 16 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 59 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 9 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 28 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 35 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 128 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 15 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 16 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 15 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 10 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 92468 # Writes before turning the bus around for reads +system.physmem.totQLat 12424177254 # Total ticks spent queuing +system.physmem.totMemAccLat 30407283504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4795495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12954.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32008.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31704.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.29 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.30 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -280,36 +300,41 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.23 # Average write queue length when enqueuing -system.physmem.readRowHits 722338 # Number of row buffer hits during reads -system.physmem.writeRowHits 1472108 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.32 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.29 # Average write queue length when enqueuing +system.physmem.readRowHits 722238 # Number of row buffer hits during reads +system.physmem.writeRowHits 1476593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes -system.physmem.avgGap 18373999.48 # Average gap between requests -system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49686658091000 # Time in different power states -system.physmem.memoryStateTime::REF 1730423760000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 404121645500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2414648880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2254490280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1317516750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1230128625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3659518200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3820650600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6087953520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5919855840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3384708874560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3384708874560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1312804436175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1305168623550 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29941137312000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29947835393250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34652130260085 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34650938016705 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.686370 # Core power per rank (mW) -system.physmem.averagePower::1 668.663363 # Core power per rank (mW) +system.physmem.avgGap 18341414.75 # Average gap between requests +system.physmem.pageHitRate 78.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2336584320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1274922000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3572345400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6014165760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308692927565 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29944715868000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34651312636245 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.671195 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49815023694250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 275710901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2342526480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1278164250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3908587800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6029970480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1310912306640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29942769044250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34651946423100 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.683425 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49811721549250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 279009798250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -333,6 +358,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -354,27 +387,81 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 215397 # Table walker walks requested +system.cpu.dtb.walker.walksLong 215397 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16603 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 166513 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 215383 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.157858 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 54.935133 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 215381 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 215383 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 183130 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 181175 98.93% 98.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 4 0.00% 98.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1496 0.82% 99.75% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 183 0.10% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 74 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 58 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 49 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 36 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 18 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 183130 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 800972760 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 2.488036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -1191876296 -148.80% -148.80% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 1992849056 248.80% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 800972760 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 166514 90.93% 90.93% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16603 9.07% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 183117 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 398514 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168646043 # DTB read hits -system.cpu.dtb.read_misses 158497 # DTB read misses -system.cpu.dtb.write_hits 153371607 # DTB write hits -system.cpu.dtb.write_misses 56347 # DTB write misses +system.cpu.dtb.read_hits 168647599 # DTB read hits +system.cpu.dtb.read_misses 158984 # DTB read misses +system.cpu.dtb.write_hits 153347297 # DTB write hits +system.cpu.dtb.write_misses 56413 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 74830 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 74349 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7977 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8039 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19966 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168804540 # DTB read accesses -system.cpu.dtb.write_accesses 153427954 # DTB write accesses +system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 168806583 # DTB read accesses +system.cpu.dtb.write_accesses 153403710 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 322017650 # DTB hits -system.cpu.dtb.misses 214844 # DTB misses -system.cpu.dtb.accesses 322232494 # DTB accesses +system.cpu.dtb.hits 321994896 # DTB hits +system.cpu.dtb.misses 215397 # DTB misses +system.cpu.dtb.accesses 322210293 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -396,56 +483,91 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 898442559 # ITB inst hits -system.cpu.itb.inst_misses 123457 # ITB inst misses +system.cpu.itb.walker.walks 123370 # Table walker walks requested +system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1120 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 111048 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 112168 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 24898.509379 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109848 97.93% 97.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2031 1.81% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 132 0.12% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 23 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 112168 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -1257598296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -1257598296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -1257598296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 111048 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1120 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 112168 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112168 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 112168 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 235538 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 898375907 # ITB inst hits +system.cpu.itb.inst_misses 123370 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53017 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52826 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 898566016 # ITB inst accesses -system.cpu.itb.hits 898442559 # DTB hits -system.cpu.itb.misses 123457 # DTB misses -system.cpu.itb.accesses 898566016 # DTB accesses -system.cpu.numCycles 103642407744 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 898499277 # ITB inst accesses +system.cpu.itb.hits 898375907 # DTB hits +system.cpu.itb.misses 123370 # DTB misses +system.cpu.itb.accesses 898499277 # DTB accesses +system.cpu.numCycles 103642314342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 897890420 # Number of instructions committed -system.cpu.committedOps 1055061464 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 968615704 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 900077 # Number of float alu accesses -system.cpu.num_func_calls 53165114 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 137212632 # number of instructions that are conditional controls -system.cpu.num_int_insts 968615704 # number of integer instructions -system.cpu.num_fp_insts 900077 # number of float instructions -system.cpu.num_int_register_reads 1413530400 # number of times the integer registers were read -system.cpu.num_int_register_writes 768471074 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1450010 # number of times the floating registers were read -system.cpu.num_fp_register_writes 764580 # number of times the floating registers were written -system.cpu.num_cc_register_reads 236283447 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235682818 # number of times the CC registers were written -system.cpu.num_mem_refs 322001322 # number of memory refs -system.cpu.num_load_insts 168639088 # Number of load instructions -system.cpu.num_store_insts 153362234 # Number of store instructions -system.cpu.num_idle_cycles 100472196154.122070 # Number of idle cycles -system.cpu.num_busy_cycles 3170211589.877939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030588 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969412 # Percentage of idle cycles -system.cpu.Branches 200577010 # Number of branches fetched +system.cpu.committedInsts 897823750 # Number of instructions committed +system.cpu.committedOps 1054987960 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 968534129 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 900653 # Number of float alu accesses +system.cpu.num_func_calls 53156799 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 137185420 # number of instructions that are conditional controls +system.cpu.num_int_insts 968534129 # number of integer instructions +system.cpu.num_fp_insts 900653 # number of float instructions +system.cpu.num_int_register_reads 1413400107 # number of times the integer registers were read +system.cpu.num_int_register_writes 768429309 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1451290 # number of times the floating registers were read +system.cpu.num_fp_register_writes 764324 # number of times the floating registers were written +system.cpu.num_cc_register_reads 236274909 # number of times the CC registers were read +system.cpu.num_cc_register_writes 235673566 # number of times the CC registers were written +system.cpu.num_mem_refs 321978685 # number of memory refs +system.cpu.num_load_insts 168640749 # Number of load instructions +system.cpu.num_store_insts 153337936 # Number of store instructions +system.cpu.num_idle_cycles 100474351324.032059 # Number of idle cycles +system.cpu.num_busy_cycles 3167963017.967939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030566 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969434 # Percentage of idle cycles +system.cpu.Branches 200551202 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 731218910 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2226806 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99223 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 731167173 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2227672 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99245 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -472,122 +594,122 @@ system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 168639088 15.97% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 153362234 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 168640749 15.98% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 153337936 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1055656727 # Class of executed instruction +system.cpu.op_class::total 1055583241 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10282368 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.969706 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 311548704 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10282880 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.297806 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 10281150 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.969700 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 311526777 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10281662 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.299263 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.969706 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.969700 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1298012717 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1298012717 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 157556193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 157556193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145511723 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145511723 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 396994 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 396994 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3698345 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3698345 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4003149 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4003149 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 303067916 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 303067916 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 303464910 # number of overall hits -system.cpu.dcache.overall_hits::total 303464910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5344087 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5344087 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2236666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2236666 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1310162 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1310162 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1231947 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1231947 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 306495 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 306495 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7580753 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7580753 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8890915 # number of overall misses -system.cpu.dcache.overall_misses::total 8890915 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83712196260 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83712196260 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64378240535 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64378240535 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27514486506 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27514486506 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4474608500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4474608500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251501 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 251501 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 148090436795 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 148090436795 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 148090436795 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 148090436795 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162900280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162900280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147748389 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147748389 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707156 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1707156 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568634 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1568634 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4004840 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4004840 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4003153 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4003153 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 310648669 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 310648669 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 312355825 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 312355825 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032806 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032806 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015138 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015138 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767453 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.767453 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.785363 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.785363 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076531 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076531 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024403 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024403 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028464 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028464 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15664.452368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15664.452368 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28783.126553 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28783.126553 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22334.147902 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22334.147902 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14599.287101 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14599.287101 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 62875.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 62875.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19535.056319 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19535.056319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16656.377526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16656.377526 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1297920552 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1297920552 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 157560037 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157560037 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 145486469 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 145486469 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 397138 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 397138 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335387 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 335387 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3699332 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3699332 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4002690 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4002690 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 303046506 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 303046506 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 303443644 # number of overall hits +system.cpu.dcache.overall_hits::total 303443644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5342305 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5342305 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2238545 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238545 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1309963 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1309963 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232790 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1232790 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 305057 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 305057 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 7580850 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7580850 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8890813 # number of overall misses +system.cpu.dcache.overall_misses::total 8890813 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83595802503 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83595802503 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64185055523 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64185055523 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27578524507 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27578524507 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4441396750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4441396750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 147780858026 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 147780858026 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 147780858026 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 147780858026 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 162902342 # number of ReadReq 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17023.064030 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -685,59 +807,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13856298 # number of replacements -system.cpu.icache.tags.tagsinuse 511.892935 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 884585744 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13856810 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63.837618 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31832974250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.892935 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 13791662 # number of replacements +system.cpu.icache.tags.tagsinuse 511.892960 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 884583728 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13792174 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.136642 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31822438250 # Cycle when the warmup percentage was hit. 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-system.cpu.icache.ReadReq_accesses::total 898442559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 898442559 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 898442559 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 898442559 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 898442559 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015423 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015423 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015423 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015423 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015423 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015423 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13370.106441 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13370.106441 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13370.106441 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13370.106441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13370.106441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13370.106441 # average overall miss latency +system.cpu.icache.tags.tag_accesses 912168086 # Number of tag accesses +system.cpu.icache.tags.data_accesses 912168086 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 884583728 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 884583728 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 884583728 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 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0.015352 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015352 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015352 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015352 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015352 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13373.260543 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13373.260543 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13373.260543 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13373.260543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13373.260543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13373.260543 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,208 +868,208 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13856815 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13856815 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13856815 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13856815 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13856815 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13856815 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 157525292015 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 157525292015 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 157525292015 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 157525292015 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 157525292015 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 157525292015 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13792179 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13792179 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13792179 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13792179 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13792179 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13792179 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 156833610274 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 156833610274 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 156833610274 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 156833610274 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 156833610274 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 156833610274 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2831639000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2831639000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2831639000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 2831639000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015423 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015423 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015423 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11368.073545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11368.073545 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11368.073545 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11368.073545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11368.073545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11368.073545 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015352 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for demand accesses 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average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1326931 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65218.833700 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27835482 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1389841 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.027818 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1330655 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65236.148872 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 27755474 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1393687 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 19.915142 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6373825000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 38602.265871 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 305.289253 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 445.157205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6377.971996 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19488.149376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589024 # Average percentage of cache occupancy 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id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5481 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54290 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956177 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 266276553 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 266276553 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 378716 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250963 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 13777936 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6592157 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 20999772 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7918344 # number of Writeback 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-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21568.658213 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.590282 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.590282 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 47500.250000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 47500.250000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61617.263057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61617.263057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246111 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246111 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.038840 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.038840 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61986.826021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63479.273949 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63225.991053 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21565.936570 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21565.936570 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.708273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.708273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61281.495461 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61281.495461 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1067,58 +1189,58 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21819690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21811671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 21752331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21744344 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7918344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1338611 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1231947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2169953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2169953 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27799880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28711563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1010117 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 58145888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 887008660 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1165125804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2042816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3064096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2057241376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 474114 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33215302 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003479 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058876 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 7913457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45727 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2171658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2171658 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27670608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28704497 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624113 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1013195 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 58012413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 882871956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1164737260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2043192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3078296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2052730704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 473368 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 33145716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003486 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058938 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 33099762 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115540 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 33030174 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33215302 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25772593750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 33145716 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25733748000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1282500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1332000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20852498735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20755677476 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14430330552 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14427270036 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 369475750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 369197500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 627605250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 628893000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40402 # Transaction distribution -system.iobus.trans_dist::ReadResp 40402 # Transaction distribution +system.iobus.trans_dist::ReadReq 40403 # Transaction distribution +system.iobus.trans_dist::ReadResp 40403 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1138,11 +1260,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1159,11 +1281,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492838 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1192,71 +1314,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042392405 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042395169 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179042528 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179037771 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115480 # number of replacements -system.iocache.tags.tagsinuse 10.457351 # Cycle average of tags in use +system.iocache.tags.replacements 115482 # number of replacements +system.iocache.tags.tagsinuse 10.457347 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115496 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153949219000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511147 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946204 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434138 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153920852000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510781 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946566 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434160 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039857 # Number of tag accesses -system.iocache.tags.data_accesses 1039857 # Number of data accesses +system.iocache.tags.tag_accesses 1039866 # Number of tag accesses +system.iocache.tags.data_accesses 1039866 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses -system.iocache.demand_misses::total 8876 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8836 # number of overall misses -system.iocache.overall_misses::total 8876 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1916450860 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1921935860 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1901914612 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1907393612 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28823836017 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28823836017 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1916450860 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1922274860 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1916450860 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1922274860 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28843036786 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28843036786 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1901914612 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1907732612 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1901914612 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1907732612 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1270,55 +1392,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 216604.965626 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 214941.808880 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 216569.948175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 216569.948175 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223291 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 214907.357441 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 214907.357441 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 223600 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27526 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.132093 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.123229 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106629 # number of writebacks -system.iocache.writebacks::total 106629 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456881862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1460442862 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1442304112 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1445859112 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23277254071 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23277254071 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1456881862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1460625862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1456881862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1460625862 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23296466828 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23296466828 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3738000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1442304112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1446042112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3738000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1442304112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1446042112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1332,71 +1454,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 462201 # Transaction distribution -system.membus.trans_dist::ReadResp 462201 # Transaction distribution +system.membus.trans_dist::ReadReq 463332 # Transaction distribution +system.membus.trans_dist::ReadResp 463332 # Transaction distribution system.membus.trans_dist::WriteReq 33872 # Transaction distribution system.membus.trans_dist::WriteResp 33872 # Transaction distribution -system.membus.trans_dist::Writeback 1241967 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 616132 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 616132 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36293 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36297 # Transaction distribution -system.membus.trans_dist::ReadExReq 534513 # Transaction distribution -system.membus.trans_dist::ReadExResp 534513 # Transaction distribution +system.membus.trans_dist::Writeback 1244337 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 618545 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 618545 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36281 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36283 # Transaction distribution +system.membus.trans_dist::ReadExReq 533903 # Transaction distribution +system.membus.trans_dist::ReadExResp 533903 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4139437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4269627 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4604753 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4147646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4277836 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 334832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4612668 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163718240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163888576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14053504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14053504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 177942080 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3244 # Total snoops (count) -system.membus.snoop_fanout::samples 2814199 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164057632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164227968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14034624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14034624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 178262592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3539 # Total snoops (count) +system.membus.snoop_fanout::samples 2819489 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2814199 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2819489 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2814199 # Request fanout histogram -system.membus.reqLayer0.occupancy 106092500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2819489 # Request fanout histogram +system.membus.reqLayer0.occupancy 106085000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5680000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5679999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 17856822743 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 17900056737 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9254301682 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9260714451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186599472 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186597229 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 72bc2e01a..5213927ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111151 # Nu sim_ticks 51111150553500 # Number of ticks simulated final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1088550 # Simulator instruction rate (inst/s) -host_op_rate 1279225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56496360239 # Simulator tick rate (ticks/s) -host_mem_usage 672572 # Number of bytes of host memory used -host_seconds 904.68 # Real time elapsed on the host +host_inst_rate 1151312 # Simulator instruction rate (inst/s) +host_op_rate 1352981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59753764865 # Simulator tick rate (ticks/s) +host_mem_usage 728116 # Number of bytes of host memory used +host_seconds 855.36 # Real time elapsed on the host sim_insts 984789519 # Number of instructions simulated sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -92,6 +92,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -113,6 +121,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 144982 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 144982 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 144982 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 108340 85.69% 85.69% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18088 14.31% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126428 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 271410 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91965302 # DTB read hits @@ -134,6 +160,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 176331252 # DTB hits system.cpu0.dtb.misses 144982 # DTB misses system.cpu0.dtb.accesses 176476234 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -155,6 +189,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 70785 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70785 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70785 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62159 96.07% 96.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2545 3.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64704 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135489 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 493804573 # ITB inst hits system.cpu0.itb.inst_misses 70785 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -424,6 +476,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -445,6 +505,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 143312 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143312 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143312 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 106567 85.62% 85.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17903 14.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124470 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 267782 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 92072581 # DTB read hits @@ -466,6 +544,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 175979862 # DTB hits system.cpu1.dtb.misses 143312 # DTB misses system.cpu1.dtb.accesses 176123174 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -487,6 +573,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 69790 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61179 95.99% 95.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2554 4.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63733 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63733 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63733 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133523 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 491448225 # ITB inst hits system.cpu1.itb.inst_misses 69790 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index e0cd774db..806ccbd13 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196466 # Number of seconds simulated -sim_ticks 5196466347000 # Number of ticks simulated -final_tick 5196466347000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.192453 # Number of seconds simulated +sim_ticks 5192452884000 # Number of ticks simulated +final_tick 5192452884000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 596082 # Simulator instruction rate (inst/s) -host_op_rate 1149061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24120553188 # Simulator tick rate (ticks/s) -host_mem_usage 596696 # Number of bytes of host memory used -host_seconds 215.44 # Real time elapsed on the host -sim_insts 128418244 # Number of instructions simulated -sim_ops 247550593 # Number of ops (including micro ops) simulated +host_inst_rate 836744 # Simulator instruction rate (inst/s) +host_op_rate 1613002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33830425760 # Simulator tick rate (ticks/s) +host_mem_usage 654168 # Number of bytes of host memory used +host_seconds 153.48 # Real time elapsed on the host +sim_insts 128427413 # Number of instructions simulated +sim_ops 247571076 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 828416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9035072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9039104 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9892224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 828416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 828416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8113920 # Number of bytes written to this memory -system.physmem.bytes_written::total 8113920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 9895360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8137984 # Number of bytes written to this memory +system.physmem.bytes_written::total 8137984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141173 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141236 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126780 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126780 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 154615 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 127156 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127156 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1903644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1561430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1561430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1561430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1740816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1905720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1567272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1567272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1567272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3465075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154566 # Number of read requests accepted -system.physmem.writeReqs 173500 # Number of write requests accepted -system.physmem.readBursts 154566 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173500 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9886080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 10951744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9892224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11104000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2352 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1595 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9833 # Per bank write bursts -system.physmem.perBankRdBursts::1 9504 # Per bank write bursts -system.physmem.perBankRdBursts::2 9844 # Per bank write bursts -system.physmem.perBankRdBursts::3 9497 # Per bank write bursts -system.physmem.perBankRdBursts::4 9570 # Per bank write bursts -system.physmem.perBankRdBursts::5 9679 # Per bank write bursts -system.physmem.perBankRdBursts::6 9540 # Per bank write bursts -system.physmem.perBankRdBursts::7 9680 # Per bank write bursts -system.physmem.perBankRdBursts::8 9214 # Per bank write bursts -system.physmem.perBankRdBursts::9 9453 # Per bank write bursts -system.physmem.perBankRdBursts::10 9241 # Per bank write bursts -system.physmem.perBankRdBursts::11 9575 # Per bank write bursts -system.physmem.perBankRdBursts::12 9600 # Per bank write bursts -system.physmem.perBankRdBursts::13 10182 # Per bank write bursts -system.physmem.perBankRdBursts::14 10246 # Per bank write bursts -system.physmem.perBankRdBursts::15 9812 # Per bank write bursts -system.physmem.perBankWrBursts::0 10679 # Per bank write bursts -system.physmem.perBankWrBursts::1 10594 # Per bank write bursts -system.physmem.perBankWrBursts::2 10884 # Per bank write bursts -system.physmem.perBankWrBursts::3 10241 # Per bank write bursts -system.physmem.perBankWrBursts::4 10237 # Per bank write bursts -system.physmem.perBankWrBursts::5 10759 # Per bank write bursts -system.physmem.perBankWrBursts::6 10579 # Per bank write bursts -system.physmem.perBankWrBursts::7 10814 # Per bank write bursts -system.physmem.perBankWrBursts::8 10762 # Per bank write bursts -system.physmem.perBankWrBursts::9 11220 # Per bank write bursts -system.physmem.perBankWrBursts::10 10499 # Per bank write bursts -system.physmem.perBankWrBursts::11 10145 # Per bank write bursts -system.physmem.perBankWrBursts::12 11054 # Per bank write bursts -system.physmem.perBankWrBursts::13 11426 # Per bank write bursts -system.physmem.perBankWrBursts::14 10852 # Per bank write bursts -system.physmem.perBankWrBursts::15 10376 # Per bank write bursts +system.physmem.bw_total::cpu.inst 159357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1740816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3472991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154615 # Number of read requests accepted +system.physmem.writeReqs 173876 # Number of write requests accepted +system.physmem.readBursts 154615 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173876 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9886592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 10962560 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9895360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11128064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2557 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1589 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10281 # Per bank write bursts +system.physmem.perBankRdBursts::1 9591 # Per bank write bursts +system.physmem.perBankRdBursts::2 10028 # Per bank write bursts +system.physmem.perBankRdBursts::3 9674 # Per bank write bursts +system.physmem.perBankRdBursts::4 9945 # Per bank write bursts +system.physmem.perBankRdBursts::5 9558 # Per bank write bursts +system.physmem.perBankRdBursts::6 9523 # Per bank write bursts +system.physmem.perBankRdBursts::7 9498 # Per bank write bursts +system.physmem.perBankRdBursts::8 9124 # Per bank write bursts +system.physmem.perBankRdBursts::9 8990 # Per bank write bursts +system.physmem.perBankRdBursts::10 9390 # Per bank write bursts +system.physmem.perBankRdBursts::11 9205 # Per bank write bursts +system.physmem.perBankRdBursts::12 9557 # Per bank write bursts +system.physmem.perBankRdBursts::13 10069 # Per bank write bursts +system.physmem.perBankRdBursts::14 10020 # Per bank write bursts +system.physmem.perBankRdBursts::15 10025 # Per bank write bursts +system.physmem.perBankWrBursts::0 10769 # Per bank write bursts +system.physmem.perBankWrBursts::1 10634 # Per bank write bursts +system.physmem.perBankWrBursts::2 10541 # Per bank write bursts +system.physmem.perBankWrBursts::3 10043 # Per bank write bursts +system.physmem.perBankWrBursts::4 11026 # Per bank write bursts +system.physmem.perBankWrBursts::5 9713 # Per bank write bursts +system.physmem.perBankWrBursts::6 10229 # Per bank write bursts +system.physmem.perBankWrBursts::7 10822 # Per bank write bursts +system.physmem.perBankWrBursts::8 11151 # Per bank write bursts +system.physmem.perBankWrBursts::9 11218 # Per bank write bursts +system.physmem.perBankWrBursts::10 10861 # Per bank write bursts +system.physmem.perBankWrBursts::11 10308 # Per bank write bursts +system.physmem.perBankWrBursts::12 10862 # Per bank write bursts +system.physmem.perBankWrBursts::13 11716 # Per bank write bursts +system.physmem.perBankWrBursts::14 11104 # Per bank write bursts +system.physmem.perBankWrBursts::15 10293 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5196466283500 # Total gap between requests +system.physmem.totGap 5192452820500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154566 # Read request sizes (log2) +system.physmem.readPktSize::6 154615 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173500 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173876 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see @@ -156,377 +156,360 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 11162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8989 # What write queue length does an incoming req see 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does an incoming req see +system.physmem.wrQLenPdf::41 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 356.006287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.370190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.892439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19432 33.20% 33.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13728 23.45% 56.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5812 9.93% 66.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3460 5.91% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2276 3.89% 76.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1654 2.83% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1160 1.98% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1010 1.73% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10000 17.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58532 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.461831 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 602.615488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6313 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 60024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.345862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.231116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.371422 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21054 35.08% 35.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13721 22.86% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5818 9.69% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3428 5.71% 73.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2258 3.76% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1594 2.66% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1149 1.91% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 996 1.66% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10006 16.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60024 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6317 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.452430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 602.471336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6316 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6314 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6314 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.101837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.618222 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.504313 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4900 77.61% 77.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 45 0.71% 78.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 20 0.32% 78.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 269 4.26% 82.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 162 2.57% 85.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 59 0.93% 86.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.49% 86.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 30 0.48% 87.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 184 2.91% 90.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.16% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.21% 90.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.14% 90.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 33 0.52% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 21 0.33% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.27% 91.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 41 0.65% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 96 1.52% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 7 0.11% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 8 0.13% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 18 0.29% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 170 2.69% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.08% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.19% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 20 0.32% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 7 0.11% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 6 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 38 0.60% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.14% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.05% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.11% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.19% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.05% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.11% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 4 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6314 # Writes before turning the bus around for reads -system.physmem.totQLat 1460181000 # Total ticks spent queuing -system.physmem.totMemAccLat 4356493500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9452.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6317 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6317 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.115719 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.572083 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 27.245873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4954 78.42% 78.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 303 4.80% 83.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 227 3.59% 86.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 68 1.08% 87.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 174 2.75% 90.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 37 0.59% 91.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 45 0.71% 91.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 56 0.89% 92.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 90 1.42% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 19 0.30% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 157 2.49% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 22 0.35% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 27 0.43% 97.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 21 0.33% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 36 0.57% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 11 0.17% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 22 0.35% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 8 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 14 0.22% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.09% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6317 # Writes before turning the bus around for reads +system.physmem.totQLat 1525176500 # Total ticks spent queuing +system.physmem.totMemAccLat 4421639000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 772390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9873.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28202.85 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28623.10 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing -system.physmem.readRowHits 127064 # Number of row buffer hits during reads -system.physmem.writeRowHits 139994 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.80 # Row buffer hit rate for writes -system.physmem.avgGap 15839697.75 # Average gap between requests -system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4974958806500 # Time in different power states -system.physmem.memoryStateTime::REF 173521400000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 47986025500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 218272320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224229600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 119097000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122347500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 601746600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 603111600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 549419760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 559444320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 339407858400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 339407858400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 134224004700 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 134453555955 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 3000139025250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2999937664500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3475259424030 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3475308211875 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.773676 # Core power per rank (mW) -system.physmem.averagePower::1 668.783065 # Core power per rank (mW) +system.physmem.avgWrQLen 25.96 # Average write queue length when enqueuing +system.physmem.readRowHits 125716 # Number of row buffer hits during reads +system.physmem.writeRowHits 140027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.73 # Row buffer hit rate for writes +system.physmem.avgGap 15806986.56 # Average gap between requests +system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 224879760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 122702250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 609164400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 542874960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339145441440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 134202799845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2997747003000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3472594865655 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.777986 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4986908920500 # Time in different power states +system.physmem_0.memoryStateTime::REF 173387240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32151782000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 228901680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124896750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595756200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 567084240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339145441440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134282501235 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2997677089500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3472621671045 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.783148 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4986802992250 # Time in different power states +system.physmem_1.memoryStateTime::REF 173387240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32262536750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10392932694 # number of cpu cycles simulated +system.cpu.numCycles 10384905768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128418244 # Number of instructions committed -system.cpu.committedOps 247550593 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232131886 # Number of integer alu accesses +system.cpu.committedInsts 128427413 # Number of instructions committed +system.cpu.committedOps 247571076 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232151918 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2300917 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23183149 # number of instructions that are conditional controls -system.cpu.num_int_insts 232131886 # number of integer instructions +system.cpu.num_func_calls 2302537 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23180236 # number of instructions that are conditional controls +system.cpu.num_int_insts 232151918 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434791523 # number of times the integer registers were read -system.cpu.num_int_register_writes 197987761 # number of times the integer registers were written +system.cpu.num_int_register_reads 434861886 # number of times the integer registers were read +system.cpu.num_int_register_writes 198003963 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132892118 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95599960 # number of times the CC registers were written -system.cpu.num_mem_refs 22255642 # number of memory refs -system.cpu.num_load_insts 13887148 # Number of load instructions -system.cpu.num_store_insts 8368494 # Number of store instructions -system.cpu.num_idle_cycles 9795963958.998116 # Number of idle cycles -system.cpu.num_busy_cycles 596968735.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057440 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942560 # Percentage of idle cycles -system.cpu.Branches 26322824 # Number of branches fetched -system.cpu.op_class::No_OpClass 174818 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 224858584 90.83% 90.90% # Class of executed instruction -system.cpu.op_class::IntMult 140018 0.06% 90.96% # Class of executed instruction -system.cpu.op_class::IntDiv 123105 0.05% 91.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::MemRead 13887148 5.61% 96.62% # Class of executed instruction -system.cpu.op_class::MemWrite 8368494 3.38% 100.00% # Class of executed instruction +system.cpu.num_cc_register_reads 132886732 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95589498 # number of times the CC registers were written +system.cpu.num_mem_refs 22270580 # number of memory refs +system.cpu.num_load_insts 13896035 # Number of load instructions +system.cpu.num_store_insts 8374545 # Number of store instructions +system.cpu.num_idle_cycles 9787798534.998116 # Number of idle cycles +system.cpu.num_busy_cycles 597107233.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057498 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942502 # Percentage of idle cycles +system.cpu.Branches 26321851 # Number of branches fetched +system.cpu.op_class::No_OpClass 175044 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224863247 90.83% 90.90% # Class of executed instruction +system.cpu.op_class::IntMult 140296 0.06% 90.95% # Class of executed instruction +system.cpu.op_class::IntDiv 123429 0.05% 91.00% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::MemRead 13896035 5.61% 96.62% # Class of executed instruction +system.cpu.op_class::MemWrite 8374545 3.38% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247552167 # Class of executed instruction +system.cpu.op_class::total 247572596 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1622836 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996904 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20034858 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623348 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.341690 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1622236 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996968 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20050453 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622748 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.355864 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996904 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996968 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88294796 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88294796 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11940626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11940626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8032822 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8032822 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59222 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59222 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19973448 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19973448 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20032670 # number of overall hits -system.cpu.dcache.overall_hits::total 20032670 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 907502 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 907502 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325247 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325247 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402429 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402429 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1232749 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1232749 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1635178 # number of overall misses -system.cpu.dcache.overall_misses::total 1635178 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12738871000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12738871000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11339051069 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11339051069 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24077922069 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24077922069 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24077922069 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24077922069 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12848128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12848128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8358069 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8358069 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461651 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461651 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21206197 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21206197 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21667848 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21667848 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070633 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070633 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038914 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038914 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871717 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871717 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.058132 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.058132 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075466 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075466 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14037.292480 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14037.292480 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34862.892107 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34862.892107 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19531.893410 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19531.893410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14724.954757 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14724.954757 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6197 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88354150 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88354150 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11949885 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11949885 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8039029 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8039029 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59358 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59358 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19988914 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19988914 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20048272 # number of overall hits +system.cpu.dcache.overall_hits::total 20048272 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907019 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907019 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325091 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325091 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402457 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402457 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232110 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232110 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1634567 # number of overall misses +system.cpu.dcache.overall_misses::total 1634567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12730749000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12730749000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11380492066 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11380492066 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24111241066 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24111241066 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24111241066 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24111241066 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12856904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12856904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8364120 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8364120 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461815 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461815 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21221024 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21221024 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21682839 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21682839 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070547 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070547 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038867 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038867 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871468 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871468 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.058061 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.058061 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075385 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075385 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14035.812921 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14035.812921 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35007.096678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35007.096678 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19569.065316 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19569.065316 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14750.842924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14750.842924 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6388 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 83 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.662651 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.506849 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539435 # number of writebacks -system.cpu.dcache.writebacks::total 1539435 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9259 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9259 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9550 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9550 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9550 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9550 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907211 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907211 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315988 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315988 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402393 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402393 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1223199 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1223199 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625592 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625592 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10916933250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10916933250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10204146879 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10204146879 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337559000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337559000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21121080129 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21121080129 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26458639129 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26458639129 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1539114 # number of writebacks +system.cpu.dcache.writebacks::total 1539114 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9270 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9557 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9557 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9557 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9557 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906732 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906732 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315821 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315821 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402422 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402422 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222553 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222553 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624975 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624975 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10909979000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10909979000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10244477888 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10244477888 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5364351750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5364351750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21154456888 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21154456888 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26518808638 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26518808638 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561805000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561805000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802178000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802178000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037806 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037806 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871639 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871639 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057681 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057681 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075023 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075023 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12033.510672 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12033.510672 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32292.830357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32292.830357 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13264.542375 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13264.542375 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17267.084202 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17267.084202 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16276.309879 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16276.309879 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561567000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561567000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96801940000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96801940000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070525 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070525 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037759 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037759 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871392 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871392 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057610 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057610 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074943 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074943 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.198047 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.198047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.608291 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.608291 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13330.165225 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13330.165225 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17303.509041 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17303.509041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16319.517924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16319.517924 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -534,58 +517,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7764 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.069200 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13087 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7779 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.682350 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5159703878000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.069200 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316825 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316825 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7361 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.061574 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13446 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7376 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.822939 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5159721667000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061574 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316348 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316348 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53125 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53125 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13088 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13088 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13088 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13088 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13088 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13088 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8983 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8983 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8983 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8983 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8983 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8983 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95259000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95259000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95259000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 95259000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95259000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 95259000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22071 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22071 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22071 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22071 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22071 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22071 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10604.363798 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10604.363798 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10604.363798 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 52616 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52616 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13447 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13447 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13447 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13447 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13447 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13447 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8574 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8574 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8574 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8574 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8574 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8574 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 90024000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 90024000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 90024000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 90024000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90024000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 90024000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22021 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22021 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22021 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22021 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22021 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22021 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389356 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389356 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389356 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389356 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389356 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389356 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10499.650105 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10499.650105 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10499.650105 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -594,86 +577,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3015 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3015 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8983 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8983 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8983 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8983 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8983 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8983 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77292500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77292500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77292500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77292500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77292500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77292500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8604.308138 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2787 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2787 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8574 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8574 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8574 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8574 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8574 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8574 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 72875500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 72875500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 72875500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 72875500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 72875500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 72875500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389356 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389356 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389356 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8499.591789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8499.591789 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 791291 # number of replacements -system.cpu.icache.tags.tagsinuse 510.349956 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144673577 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.714106 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 793260 # number of replacements +system.cpu.icache.tags.tagsinuse 510.348682 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144679610 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 793772 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.268473 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.349956 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996777 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.348682 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146257197 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146257197 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144673577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144673577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144673577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144673577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144673577 # number of overall hits -system.cpu.icache.overall_hits::total 144673577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791810 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791810 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791810 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791810 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791810 # number of overall misses -system.cpu.icache.overall_misses::total 791810 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11120002617 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11120002617 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11120002617 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11120002617 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11120002617 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11120002617 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145465387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145465387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145465387 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145465387 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145465387 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145465387 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14043.776432 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14043.776432 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14043.776432 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14043.776432 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146267168 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146267168 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144679610 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144679610 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144679610 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144679610 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144679610 # number of overall hits +system.cpu.icache.overall_hits::total 144679610 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(read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 793779 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 793779 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 793779 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9550046380 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9550046380 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9550046380 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9550046380 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9550046380 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9550046380 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005457 # mshr miss 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12031.114932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.114932 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3671 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.091001 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7743 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3683 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.102362 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161228729000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.091001 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.193188 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.193188 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3392 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.080377 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 8023 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3405 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.356241 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161936228000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.080377 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192524 # Average percentage of cache occupancy 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miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45208750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 45208750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45208750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 45208750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12278 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12278 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8045 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8045 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8045 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8045 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4264 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4264 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4264 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4264 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4264 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4264 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 41583500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 41583500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 41583500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 41583500 # number of demand (read+write) miss cycles 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-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9968.853363 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9968.853363 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12309 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12309 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12309 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12309 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.346469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.346469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,177 +755,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4535 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4535 # number of ReadReq MSHR misses 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# number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4264 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4264 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33053500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33053500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33053500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33053500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33053500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33053500 # number of overall MSHR miss cycles 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Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3492751 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152091 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.964876 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50370.250728 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.007923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141558 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3248.489299 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11128.405530 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768589 # Average percentage of cache occupancy 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id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2777 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4943 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56808 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32220272 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32220272 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6177 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2685 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 780836 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1279767 # number of ReadReq hits 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ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113458 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12930 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28590 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41527 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1330 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1330 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113574 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113574 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12945 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 155054 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12930 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 142164 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 155101 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12945 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142103 # number of overall misses -system.cpu.l2cache.overall_misses::total 155054 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # 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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2394785000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2394785000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89074859500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89074859500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019672 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809495 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809495 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063969 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063969 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60772.428461 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63250.760756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62478.375515 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10692.715789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10692.715789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56990.951072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56990.951072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60772.428461 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58249.834888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.163229 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60772.428461 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58249.834888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.163229 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1042,59 +1025,59 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2697337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2696818 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2698168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2697644 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542614 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313800 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5980523 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8291 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18581 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7591002 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50675008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204057491 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 240384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 614272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255587155 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53212 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4021729 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011827 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108106 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313640 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1587545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5978947 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17540 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7591699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50801024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203997643 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 217792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255590283 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53203 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4021775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011825 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108096 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3974165 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47564 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3974219 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47556 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4021729 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3834985000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4021775 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834392000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 468000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1190158617 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1193119870 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3054984845 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3054097839 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6803250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13474750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 12861250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230264 # Transaction distribution -system.iobus.trans_dist::ReadResp 230264 # Transaction distribution +system.iobus.trans_dist::ReadReq 230256 # Transaction distribution +system.iobus.trans_dist::ReadResp 230256 # Transaction distribution system.iobus.trans_dist::WriteReq 57694 # Transaction distribution system.iobus.trans_dist::WriteResp 10974 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1655 # Transaction distribution -system.iobus.trans_dist::MessageResp 1655 # Transaction distribution +system.iobus.trans_dist::MessageReq 1654 # Transaction distribution +system.iobus.trans_dist::MessageResp 1654 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1114,11 +1097,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579226 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579208 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1138,12 +1121,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280590 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280522 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1179,54 +1162,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448397612 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448430581 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52228501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52212002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47510 # number of replacements -system.iocache.tags.tagsinuse 0.132770 # Cycle average of tags in use +system.iocache.tags.replacements 47501 # number of replacements +system.iocache.tags.tagsinuse 0.119711 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045851378000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.132770 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008298 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.008298 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045856556000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.119711 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007482 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007482 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428076 # Number of tag accesses -system.iocache.tags.data_accesses 428076 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.tags.tag_accesses 428004 # Number of tag accesses +system.iocache.tags.data_accesses 428004 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses -system.iocache.demand_misses::total 844 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses -system.iocache.overall_misses::total 844 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143496186 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143496186 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12353940925 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12353940925 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 143496186 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 143496186 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 143496186 # number of overall miss cycles -system.iocache.overall_miss_latency::total 143496186 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 836 # number of demand (read+write) misses +system.iocache.demand_misses::total 836 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 836 # number of overall misses +system.iocache.overall_misses::total 836 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143698686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143698686 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361223893 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12361223893 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 143698686 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 143698686 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 143698686 # number of overall miss cycles +system.iocache.overall_miss_latency::total 143698686 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 836 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 836 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 836 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 836 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1235,40 +1218,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170019.177725 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264425.105415 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264425.105415 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170019.177725 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170019.177725 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70456 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 171888.380383 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264580.990860 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264580.990860 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 171888.380383 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 171888.380383 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70511 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9155 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9153 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.695904 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.703594 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99583186 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9924498927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9924498927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 99583186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 99583186 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 836 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 836 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 836 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 836 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100200686 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9931779897 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9931779897 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 100200686 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 100200686 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1277,71 +1260,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117989.556872 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212425.062650 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212425.062650 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 119857.279904 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212580.905330 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212580.905330 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 119857.279904 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 119857.279904 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624001 # Transaction distribution -system.membus.trans_dist::ReadResp 624001 # Transaction distribution -system.membus.trans_dist::WriteReq 13890 # Transaction distribution -system.membus.trans_dist::WriteResp 13890 # Transaction distribution -system.membus.trans_dist::Writeback 126780 # Transaction distribution +system.membus.trans_dist::ReadReq 623924 # Transaction distribution +system.membus.trans_dist::ReadResp 623924 # Transaction distribution +system.membus.trans_dist::WriteReq 13888 # Transaction distribution +system.membus.trans_dist::WriteResp 13888 # Transaction distribution +system.membus.trans_dist::Writeback 127156 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1612 # Transaction distribution -system.membus.trans_dist::ReadExReq 113178 # Transaction distribution -system.membus.trans_dist::ReadExResp 113178 # Transaction distribution -system.membus.trans_dist::MessageReq 1655 # Transaction distribution -system.membus.trans_dist::MessageResp 1655 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2158 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1607 # Transaction distribution +system.membus.trans_dist::ReadExReq 113297 # Transaction distribution +system.membus.trans_dist::ReadExResp 113297 # Transaction distribution +system.membus.trans_dist::MessageReq 1654 # Transaction distribution +system.membus.trans_dist::MessageResp 1654 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392754 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1728361 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1728824 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14991040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16657939 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22669743 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1607 # Total snoops (count) -system.membus.snoop_fanout::samples 331268 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15018304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16685195 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22696931 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1614 # Total snoops (count) +system.membus.snoop_fanout::samples 331694 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331268 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331694 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331268 # Request fanout histogram -system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 331694 # Request fanout histogram +system.membus.reqLayer0.occupancy 257197500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358100000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 358100500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1728081500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1731913000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2618580655 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2619410411 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54329499 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54258998 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index c9524dba5..954061e30 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35022500 # Number of ticks simulated -final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 34993500 # Number of ticks simulated +final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71946 # Simulator instruction rate (inst/s) -host_op_rate 71929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 393524726 # Simulator tick rate (ticks/s) -host_mem_usage 237176 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 162128 # Simulator instruction rate (inst/s) +host_op_rate 162075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 885888965 # Simulator tick rate (ticks/s) +host_mem_usage 292456 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34924000 # Total gap between requests +system.physmem.totGap 34895000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,19 +196,19 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3887500 # Total ticks spent queuing -system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3849750 # Total ticks spent queuing +system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.61 # Data bus utilization in percentage -system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.62 # Data bus utilization in percentage +system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -216,31 +216,36 @@ system.physmem.readRowHits 435 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65523.45 # Average gap between requests +system.physmem.avgGap 65469.04 # Average gap between requests system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 1040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 30393500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 140250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 210375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2082600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1677000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ) -system.physmem.averagePower::0 827.295718 # Core power per rank (mW) -system.physmem.averagePower::1 815.785757 # Core power per rank (mW) +system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ) +system.physmem_0.averagePower 827.438306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ) +system.physmem_1.averagePower 815.785757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1972 # Number of BP lookups system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect @@ -284,26 +289,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 70045 # number of cpu cycles simulated +system.cpu.numCycles 69987 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.944531 # CPI: cycles per instruction -system.cpu.ipc 0.091370 # IPC: instructions per cycle -system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped +system.cpu.cpi 10.935469 # CPI: cycles per instruction +system.cpu.ipc 0.091446 # IPC: instructions per cycle +system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 104.036694 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -328,12 +333,12 @@ system.cpu.dcache.overall_misses::cpu.inst 227 # system.cpu.dcache.overall_misses::total 227 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8670250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 16373500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) @@ -352,12 +357,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,12 +389,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 169 system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5119000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12250000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses @@ -400,25 +405,25 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70123.287671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses system.cpu.icache.tags.data_accesses 5649 # Number of data accesses @@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses @@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,37 +477,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.762820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -520,14 +525,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 533 # system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31657000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5044000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36701000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) @@ -544,14 +549,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68819.565217 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.890411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68857.410882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68857.410882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -568,14 +573,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -584,14 +589,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -617,7 +622,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) @@ -642,7 +647,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 533 # Request fanout histogram system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index c9776266f..7064bc28f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20537500 # Number of ticks simulated final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69014 # Simulator instruction rate (inst/s) -host_op_rate 69006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 222388397 # Simulator tick rate (ticks/s) -host_mem_usage 237256 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 92569 # Simulator instruction rate (inst/s) +host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 298254404 # Simulator tick rate (ticks/s) +host_mem_usage 293992 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 80.08 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 41913.76 # Average gap between requests system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15339250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 332640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 181500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1755000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1365000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10809765 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10569510 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 38250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 249000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13982370 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13714770 # Total energy per rank (pJ) -system.physmem.averagePower::0 881.195525 # Core power per rank (mW) -system.physmem.averagePower::1 864.330865 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 415 # Transaction distribution -system.membus.trans_dist::ReadExReq 72 # Transaction distribution -system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 487 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 487 # Request fanout histogram -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) +system.physmem_0.averagePower 881.195525 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) +system.physmem_1.averagePower 864.696352 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2806 # Number of BP lookups system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -605,34 +587,118 @@ system.cpu.fp_regfile_reads 8 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits +system.cpu.dcache.overall_hits::total 2314 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses +system.cpu.dcache.overall_misses::total 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. @@ -854,117 +920,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits -system.cpu.dcache.overall_hits::total 2314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 415 # Transaction distribution +system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadExReq 72 # Transaction distribution +system.membus.trans_dist::ReadExResp 72 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 487 # Request fanout histogram +system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 95f3db4f2..aeda1c330 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138637 # Number of ticks simulated final_tick 138637 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12523 # Simulator instruction rate (inst/s) -host_op_rate 12523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271684 # Simulator tick rate (ticks/s) -host_mem_usage 436940 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host +host_inst_rate 45640 # Simulator instruction rate (inst/s) +host_op_rate 45635 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 990010 # Simulator tick rate (ticks/s) +host_mem_usage 451208 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -237,29 +237,126 @@ system.mem_ctrls.readRowHitRate 81.03 # Ro system.mem_ctrls.writeRowHitRate 75.41 # Row buffer hit rate for writes system.mem_ctrls.avgGap 79.75 # Average gap between requests system.mem_ctrls.pageHitRate 80.50 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 211 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 4420 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 128005 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1103760 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 613200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5828160 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 8112000 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 362880 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 673920 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 75333024 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 89081424 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 13491600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1431600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 104531424 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 109661424 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 788.190677 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 826.872042 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5828160 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 75338496 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 13486800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 104532096 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 788.195744 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 25869 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4420 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 106214 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 8112000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 673920 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 89081424 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1431600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 109661424 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 826.872042 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1728 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4420 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 126488 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 138637 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 138637 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -279,8 +376,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 15.410630 -system.ruby.latency_hist::gmean 5.220511 -system.ruby.latency_hist::stdev 29.550250 +system.ruby.latency_hist::gmean 5.220490 +system.ruby.latency_hist::stdev 29.556532 system.ruby.latency_hist | 7278 86.15% 86.15% | 1151 13.62% 99.78% | 3 0.04% 99.81% | 2 0.02% 99.83% | 6 0.07% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 @@ -294,8 +391,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1490 system.ruby.miss_latency_hist::mean 73.365772 -system.ruby.miss_latency_hist::gmean 69.379008 -system.ruby.miss_latency_hist::stdev 29.545012 +system.ruby.miss_latency_hist::gmean 69.377440 +system.ruby.miss_latency_hist::stdev 29.580633 system.ruby.miss_latency_hist | 320 21.48% 21.48% | 1151 77.25% 98.72% | 3 0.20% 98.93% | 2 0.13% 99.06% | 6 0.40% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1490 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits @@ -304,7 +401,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -314,6 +410,10 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 3.776229 system.ruby.network.routers0.msg_count.Control::0 1490 system.ruby.network.routers0.msg_count.Request_Control::2 1041 @@ -331,9 +431,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6392 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328 -system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 7.332278 system.ruby.network.routers1.msg_count.Control::0 2950 system.ruby.network.routers1.msg_count.Request_Control::2 1041 @@ -387,98 +484,6 @@ system.ruby.network.msg_byte.Response_Data 697032 system.ruby.network.msg_byte.Response_Control 114288 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 6984 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 138637 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 138637 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.369057 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 @@ -609,9 +614,9 @@ system.ruby.LD.miss_latency_hist::total 583 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 17.899422 -system.ruby.ST.latency_hist::gmean 6.261931 -system.ruby.ST.latency_hist::stdev 30.808929 +system.ruby.ST.latency_hist::mean 17.890173 +system.ruby.ST.latency_hist::gmean 6.261514 +system.ruby.ST.latency_hist::stdev 30.772511 system.ruby.ST.latency_hist | 767 88.67% 88.67% | 95 10.98% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 @@ -624,17 +629,17 @@ system.ruby.ST.hit_latency_hist::total 649 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 216 -system.ruby.ST.miss_latency_hist::mean 62.666667 -system.ruby.ST.miss_latency_hist::gmean 57.141141 -system.ruby.ST.miss_latency_hist::stdev 33.628615 +system.ruby.ST.miss_latency_hist::mean 62.629630 +system.ruby.ST.miss_latency_hist::gmean 57.125913 +system.ruby.ST.miss_latency_hist::stdev 33.544027 system.ruby.ST.miss_latency_hist | 118 54.63% 54.63% | 95 43.98% 98.61% | 1 0.46% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 216 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 11.389844 -system.ruby.IFETCH.latency_hist::gmean 4.264766 -system.ruby.IFETCH.latency_hist::stdev 26.115167 +system.ruby.IFETCH.latency_hist::mean 11.391094 +system.ruby.IFETCH.latency_hist::gmean 4.264782 +system.ruby.IFETCH.latency_hist::stdev 26.130654 system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 673 10.52% 99.80% | 1 0.02% 99.81% | 2 0.03% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -647,11 +652,21 @@ system.ruby.IFETCH.hit_latency_hist::total 5709 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 691 -system.ruby.IFETCH.miss_latency_hist::mean 80.706223 -system.ruby.IFETCH.miss_latency_hist::gmean 78.001693 -system.ruby.IFETCH.miss_latency_hist::stdev 30.507480 +system.ruby.IFETCH.miss_latency_hist::mean 80.717800 +system.ruby.IFETCH.miss_latency_hist::gmean 78.004389 +system.ruby.IFETCH.miss_latency_hist::stdev 30.603968 system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 673 97.40% 98.12% | 1 0.14% 98.26% | 2 0.29% 98.55% | 5 0.72% 99.28% | 5 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 691 +system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.Data 277 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -716,15 +731,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data 570 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 799 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% -system.ruby.Directory_Controller.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index a7cf38c09..d5c587675 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000126 # Nu sim_ticks 126195 # Number of ticks simulated final_tick 126195 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17040 # Simulator instruction rate (inst/s) -host_op_rate 17039 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 336486 # Simulator tick rate (ticks/s) -host_mem_usage 440076 # Number of bytes of host memory used -host_seconds 0.38 # Real time elapsed on the host +host_inst_rate 43805 # Simulator instruction rate (inst/s) +host_op_rate 43801 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864948 # Simulator tick rate (ticks/s) +host_mem_usage 454088 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,36 +230,133 @@ system.mem_ctrls.busUtil 4.32 # Da system.mem_ctrls.busUtilRead 4.00 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 22.42 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 799 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 76 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 79.19 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 68.47 # Row buffer hit rate for writes system.mem_ctrls.avgGap 91.66 # Average gap between requests system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 232 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 4160 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 120458 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 551880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 306600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 4992000 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 7450560 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 186624 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 64157832 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 84064968 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 18622800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1160400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 96954696 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 103087560 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 776.656541 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 825.783908 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 186624 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 64142784 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 18636000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 96952848 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 776.641738 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 31414 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 90106 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1035720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 575400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7450560 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 84064968 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1160400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 103087560 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 825.783908 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1262 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 119428 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 126195 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 126195 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -272,8 +369,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 13.937855 -system.ruby.latency_hist::gmean 4.957822 -system.ruby.latency_hist::stdev 28.418252 +system.ruby.latency_hist::gmean 4.957827 +system.ruby.latency_hist::stdev 28.413153 system.ruby.latency_hist | 7438 88.04% 88.04% | 992 11.74% 99.79% | 2 0.02% 99.81% | 1 0.01% 99.82% | 11 0.13% 99.95% | 3 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 @@ -287,8 +384,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1421 system.ruby.miss_latency_hist::mean 68.026742 -system.ruby.miss_latency_hist::gmean 59.451623 -system.ruby.miss_latency_hist::stdev 35.838026 +system.ruby.miss_latency_hist::gmean 59.451968 +system.ruby.miss_latency_hist::stdev 35.813966 system.ruby.miss_latency_hist | 411 28.92% 28.92% | 992 69.81% 98.73% | 2 0.14% 98.87% | 1 0.07% 98.94% | 11 0.77% 99.72% | 3 0.21% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1421 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits @@ -297,7 +394,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.974286 system.ruby.network.routers0.msg_count.Request_Control::0 1421 system.ruby.network.routers0.msg_count.Response_Data::2 1182 @@ -311,9 +411,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736 -system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 8.972820 system.ruby.network.routers1.msg_count.Request_Control::0 1421 system.ruby.network.routers1.msg_count.Request_Control::1 1182 @@ -371,98 +468,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624 system.ruby.network.msg_byte.Writeback_Data 324432 system.ruby.network.msg_byte.Writeback_Control 74304 system.ruby.network.msg_byte.Unblock_Control 63576 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 126195 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 126195 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.603629 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 @@ -553,9 +558,9 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456 system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 29.355030 -system.ruby.LD.latency_hist::gmean 10.774857 -system.ruby.LD.latency_hist::stdev 36.604149 +system.ruby.LD.latency_hist::mean 29.370245 +system.ruby.LD.latency_hist::gmean 10.775321 +system.ruby.LD.latency_hist::stdev 36.738545 system.ruby.LD.latency_hist | 860 72.70% 72.70% | 320 27.05% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 @@ -568,9 +573,9 @@ system.ruby.LD.hit_latency_hist::total 658 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 525 -system.ruby.LD.miss_latency_hist::mean 62.386667 -system.ruby.LD.miss_latency_hist::gmean 53.502649 -system.ruby.LD.miss_latency_hist::stdev 32.511258 +system.ruby.LD.miss_latency_hist::mean 62.420952 +system.ruby.LD.miss_latency_hist::gmean 53.507846 +system.ruby.LD.miss_latency_hist::stdev 32.816863 system.ruby.LD.miss_latency_hist | 202 38.48% 38.48% | 320 60.95% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 525 system.ruby.ST.latency_hist::bucket_size 64 @@ -599,9 +604,9 @@ system.ruby.ST.miss_latency_hist::total 250 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 10.378594 -system.ruby.IFETCH.latency_hist::gmean 4.114908 -system.ruby.IFETCH.latency_hist::stdev 25.040800 +system.ruby.IFETCH.latency_hist::mean 10.375781 +system.ruby.IFETCH.latency_hist::gmean 4.114880 +system.ruby.IFETCH.latency_hist::stdev 24.994631 system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 564 8.81% 99.83% | 0 0.00% 99.83% | 1 0.02% 99.84% | 8 0.12% 99.97% | 1 0.02% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -614,11 +619,33 @@ system.ruby.IFETCH.hit_latency_hist::total 5754 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 646 -system.ruby.IFETCH.miss_latency_hist::mean 76.100619 -system.ruby.IFETCH.miss_latency_hist::gmean 68.669414 -system.ruby.IFETCH.miss_latency_hist::stdev 37.537546 +system.ruby.IFETCH.miss_latency_hist::mean 76.072755 +system.ruby.IFETCH.miss_latency_hist::gmean 68.664868 +system.ruby.IFETCH.miss_latency_hist::stdev 37.280241 system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 564 87.31% 98.30% | 0 0.00% 98.30% | 1 0.15% 98.45% | 8 1.24% 99.69% | 1 0.15% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 646 +system.ruby.Directory_Controller.GETX 198 0.00% 0.00% +system.ruby.Directory_Controller.GETS 984 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -696,27 +723,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 52 0.00% system.ruby.L2Cache_Controller.SS.Unblock 141 0.00% 0.00% system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 46 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.GETX 198 0.00% 0.00% -system.ruby.Directory_Controller.GETS 984 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index abe542f63..23f7e060f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000117 # Nu sim_ticks 116770 # Number of ticks simulated final_tick 116770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 333 # Simulator instruction rate (inst/s) -host_op_rate 333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6085 # Simulator tick rate (ticks/s) -host_mem_usage 436992 # Number of bytes of host memory used -host_seconds 19.19 # Real time elapsed on the host +host_inst_rate 63656 # Simulator instruction rate (inst/s) +host_op_rate 63646 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1162909 # Simulator tick rate (ticks/s) +host_mem_usage 451252 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -236,29 +236,126 @@ system.mem_ctrls.readRowHitRate 79.80 # Ro system.mem_ctrls.writeRowHitRate 77.31 # Row buffer hit rate for writes system.mem_ctrls.avgGap 83.10 # Average gap between requests system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 105625 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 514080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 937440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 285600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 520800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5041920 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 6764160 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 269568 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 725760 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 60929352 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 72381564 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 12117000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 2071200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 86277360 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 90520764 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 789.557896 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 828.390947 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 285600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5041920 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 269568 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 60923196 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 12117000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 86271204 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 789.566591 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 22175 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 85821 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 937440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 520800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 725760 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 72391140 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2062800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 90521940 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 828.401709 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2878 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 102769 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 116770 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 116770 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -271,8 +368,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 12.822206 -system.ruby.latency_hist::gmean 3.506831 -system.ruby.latency_hist::stdev 27.804874 +system.ruby.latency_hist::gmean 3.506830 +system.ruby.latency_hist::stdev 27.805292 system.ruby.latency_hist | 7433 87.99% 87.99% | 995 11.78% 99.76% | 6 0.07% 99.83% | 2 0.02% 99.86% | 8 0.09% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 4 @@ -287,8 +384,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1176 system.ruby.miss_latency_hist::mean 75.774660 -system.ruby.miss_latency_hist::gmean 72.686076 -system.ruby.miss_latency_hist::stdev 29.372665 +system.ruby.miss_latency_hist::gmean 72.686009 +system.ruby.miss_latency_hist::stdev 29.375504 system.ruby.miss_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1176 system.ruby.Directory.incomplete_times 1175 @@ -298,7 +395,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 189 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.578702 system.ruby.network.routers0.msg_count.Request_Control::1 1383 system.ruby.network.routers0.msg_count.Response_Data::4 1176 @@ -312,9 +412,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 320 -system.ruby.l2_cntrl0.L2cache.demand_hits 189 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.210200 system.ruby.network.routers1.msg_count.Request_Control::1 1383 system.ruby.network.routers1.msg_count.Request_Control::2 1194 @@ -372,98 +469,6 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 341712 system.ruby.network.msg_byte.Writeback_Control 23184 system.ruby.network.msg_byte.Persistent_Control 960 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 116770 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 116770 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.338700 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1176 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 207 @@ -585,8 +590,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 system.ruby.IFETCH.latency_hist::mean 9.334062 -system.ruby.IFETCH.latency_hist::gmean 2.862492 -system.ruby.IFETCH.latency_hist::stdev 24.015420 +system.ruby.IFETCH.latency_hist::gmean 2.862491 +system.ruby.IFETCH.latency_hist::stdev 24.016058 system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 573 8.95% 99.81% | 4 0.06% 99.87% | 0 0.00% 99.87% | 7 0.11% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 4 @@ -601,8 +606,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 585 system.ruby.IFETCH.miss_latency_hist::mean 79.849573 -system.ruby.IFETCH.miss_latency_hist::gmean 77.699187 -system.ruby.IFETCH.miss_latency_hist::stdev 27.986383 +system.ruby.IFETCH.miss_latency_hist::gmean 77.699044 +system.ruby.IFETCH.miss_latency_hist::stdev 27.992378 system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 585 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 @@ -624,8 +629,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1176 system.ruby.Directory.miss_mach_latency_hist::mean 75.774660 -system.ruby.Directory.miss_mach_latency_hist::gmean 72.686076 -system.ruby.Directory.miss_mach_latency_hist::stdev 29.372665 +system.ruby.Directory.miss_mach_latency_hist::gmean 72.686009 +system.ruby.Directory.miss_mach_latency_hist::stdev 29.375504 system.ruby.Directory.miss_mach_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1176 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -719,10 +724,37 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 585 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 79.849573 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699187 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.986383 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699044 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.992378 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 585 +system.ruby.Directory_Controller.GETX 209 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 219 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 903 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1176 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 228 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 1008 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 18 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 219 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 903 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 5 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 228 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 9 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 9 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -796,32 +828,5 @@ system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 1122 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETX 1 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 9 0.00% 0.00% -system.ruby.Directory_Controller.GETX 209 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 219 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 903 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1176 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 228 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 1008 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 18 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 219 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 903 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 5 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 228 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 72fcefa3c..4d5f2d93a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000096 # Nu sim_ticks 96381 # Number of ticks simulated final_tick 96381 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32379 # Simulator instruction rate (inst/s) -host_op_rate 32376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 488288 # Simulator tick rate (ticks/s) -host_mem_usage 436896 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 66831 # Simulator instruction rate (inst/s) +host_op_rate 66821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1007748 # Simulator tick rate (ticks/s) +host_mem_usage 449612 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,12 +186,12 @@ system.mem_ctrls.wrQLenPdf::62 0 # Wh system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 194 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 352.659794 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 218.108055 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 333.620332 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 54 27.84% 27.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 26.29% 54.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 19 9.79% 63.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 16 8.25% 72.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 217.534506 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 333.874690 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 55 28.35% 28.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 50 25.77% 54.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 18 9.28% 63.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 8.76% 72.16% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 12 6.19% 78.35% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 7 3.61% 81.96% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 7 3.61% 85.57% # Bytes accessed per row activation @@ -231,138 +231,42 @@ system.mem_ctrls.busUtil 5.65 # Da system.mem_ctrls.busUtilRead 5.20 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.25 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 21.24 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 80.56 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.83 # Average gap between requests system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 90575 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 476280 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 975240 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 264600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 541800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5104320 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 7063680 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 238464 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 54836964 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 61829496 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 8112600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1978800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 75135948 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 79155288 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 801.946249 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 844.845750 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 10.408736 -system.ruby.latency_hist::gmean 3.320045 -system.ruby.latency_hist::stdev 22.997500 -system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 2 -system.ruby.hit_latency_hist::max_bucket 19 -system.ruby.hit_latency_hist::samples 7289 -system.ruby.hit_latency_hist::mean 2.306352 -system.ruby.hit_latency_hist::gmean 2.107025 -system.ruby.hit_latency_hist::stdev 1.810102 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 7289 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1159 -system.ruby.miss_latency_hist::mean 61.364970 -system.ruby.miss_latency_hist::gmean 57.951867 -system.ruby.miss_latency_hist::stdev 28.728264 -system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1159 -system.ruby.Directory.incomplete_times 1158 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54887580 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8068200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 75142164 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 802.012594 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 14237 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 77447 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7063680 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 61908840 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1909200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 79165032 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 844.949750 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2762 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 87824 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 4.652888 -system.ruby.network.routers0.msg_count.Request_Control::2 1159 -system.ruby.network.routers0.msg_count.Response_Data::4 1159 -system.ruby.network.routers0.msg_count.Writeback_Data::5 220 -system.ruby.network.routers0.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers0.msg_count.Writeback_Control::5 923 -system.ruby.network.routers0.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers0.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 4.652888 -system.ruby.network.routers1.msg_count.Request_Control::2 1159 -system.ruby.network.routers1.msg_count.Response_Data::4 1159 -system.ruby.network.routers1.msg_count.Writeback_Data::5 220 -system.ruby.network.routers1.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers1.msg_count.Writeback_Control::5 923 -system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers1.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers2.percent_links_utilized 4.652888 -system.ruby.network.routers2.msg_count.Request_Control::2 1159 -system.ruby.network.routers2.msg_count.Response_Data::4 1159 -system.ruby.network.routers2.msg_count.Writeback_Data::5 220 -system.ruby.network.routers2.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers2.msg_count.Writeback_Control::5 923 -system.ruby.network.routers2.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers2.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.msg_count.Request_Control 3477 -system.ruby.network.msg_count.Response_Data 3477 -system.ruby.network.msg_count.Writeback_Data 660 -system.ruby.network.msg_count.Writeback_Control 9627 -system.ruby.network.msg_count.Unblock_Control 3477 -system.ruby.network.msg_byte.Request_Control 27816 -system.ruby.network.msg_byte.Response_Data 250344 -system.ruby.network.msg_byte.Writeback_Data 47520 -system.ruby.network.msg_byte.Writeback_Control 77016 -system.ruby.network.msg_byte.Unblock_Control 27816 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -454,6 +358,107 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 8449 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8449 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 8448 +system.ruby.latency_hist::mean 10.408736 +system.ruby.latency_hist::gmean 3.320047 +system.ruby.latency_hist::stdev 22.995606 +system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 8448 +system.ruby.hit_latency_hist::bucket_size 2 +system.ruby.hit_latency_hist::max_bucket 19 +system.ruby.hit_latency_hist::samples 7289 +system.ruby.hit_latency_hist::mean 2.306352 +system.ruby.hit_latency_hist::gmean 2.107025 +system.ruby.hit_latency_hist::stdev 1.810102 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 7289 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1159 +system.ruby.miss_latency_hist::mean 61.364970 +system.ruby.miss_latency_hist::gmean 57.952099 +system.ruby.miss_latency_hist::stdev 28.717200 +system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1159 +system.ruby.Directory.incomplete_times 1158 +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 4.652888 +system.ruby.network.routers0.msg_count.Request_Control::2 1159 +system.ruby.network.routers0.msg_count.Response_Data::4 1159 +system.ruby.network.routers0.msg_count.Writeback_Data::5 220 +system.ruby.network.routers0.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers0.msg_count.Writeback_Control::5 923 +system.ruby.network.routers0.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers0.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers0.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers1.percent_links_utilized 4.652888 +system.ruby.network.routers1.msg_count.Request_Control::2 1159 +system.ruby.network.routers1.msg_count.Response_Data::4 1159 +system.ruby.network.routers1.msg_count.Writeback_Data::5 220 +system.ruby.network.routers1.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers1.msg_count.Writeback_Control::5 923 +system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers1.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers1.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers2.percent_links_utilized 4.652888 +system.ruby.network.routers2.msg_count.Request_Control::2 1159 +system.ruby.network.routers2.msg_count.Response_Data::4 1159 +system.ruby.network.routers2.msg_count.Writeback_Data::5 220 +system.ruby.network.routers2.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers2.msg_count.Writeback_Control::5 923 +system.ruby.network.routers2.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers2.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers2.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.msg_count.Request_Control 3477 +system.ruby.network.msg_count.Response_Data 3477 +system.ruby.network.msg_count.Writeback_Data 660 +system.ruby.network.msg_count.Writeback_Control 9627 +system.ruby.network.msg_count.Unblock_Control 3477 +system.ruby.network.msg_byte.Request_Control 27816 +system.ruby.network.msg_byte.Response_Data 250344 +system.ruby.network.msg_byte.Writeback_Data 47520 +system.ruby.network.msg_byte.Writeback_Control 77016 +system.ruby.network.msg_byte.Unblock_Control 27816 system.ruby.network.routers0.throttle0.link_utilization 6.004295 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 @@ -554,9 +559,9 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 system.ruby.IFETCH.latency_hist::mean 7.937812 -system.ruby.IFETCH.latency_hist::gmean 2.788276 -system.ruby.IFETCH.latency_hist::stdev 21.096217 -system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 1 0.02% 99.86% | 4 0.06% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::gmean 2.788278 +system.ruby.IFETCH.latency_hist::stdev 21.093490 +system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 2 system.ruby.IFETCH.hit_latency_hist::max_bucket 19 @@ -570,9 +575,9 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 581 system.ruby.IFETCH.miss_latency_hist::mean 66.177281 -system.ruby.IFETCH.miss_latency_hist::gmean 63.049831 -system.ruby.IFETCH.miss_latency_hist::stdev 34.055805 -system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::gmean 63.050334 +system.ruby.IFETCH.miss_latency_hist::stdev 34.037169 +system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 581 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 @@ -592,9 +597,9 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1159 system.ruby.Directory.miss_mach_latency_hist::mean 61.364970 -system.ruby.Directory.miss_mach_latency_hist::gmean 57.951867 -system.ruby.Directory.miss_mach_latency_hist::stdev 28.728264 -system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::gmean 57.952099 +system.ruby.Directory.miss_mach_latency_hist::stdev 28.717200 +system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1159 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -684,10 +689,28 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.177281 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.049831 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.055805 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.050334 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.037169 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581 +system.ruby.Directory_Controller.GETX 185 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% +system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00% system.ruby.L1Cache_Controller.Store 892 0.00% 0.00% @@ -729,23 +752,5 @@ system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00% -system.ruby.Directory_Controller.GETX 185 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 01d67d280..e18c35fff 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000124 # Nu sim_ticks 123564 # Number of ticks simulated final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 34581 # Simulator instruction rate (inst/s) -host_op_rate 34578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 668563 # Simulator tick rate (ticks/s) -host_mem_usage 436724 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 69668 # Simulator instruction rate (inst/s) +host_op_rate 69633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1346306 # Simulator tick rate (ticks/s) +host_mem_usage 450680 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate 75.06 # Ro system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes system.mem_ctrls.avgGap 35.73 # Average gap between requests system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11701 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3900 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 101465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 771120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1081080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 428400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 600600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 4879680 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 5466240 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 4281984 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 4323456 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 69482088 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 69027912 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 9282000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 9680400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 96753672 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 97808088 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 826.587089 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 835.595188 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 3456 # delay histogram for all message -system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 3456 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.626420 -system.ruby.latency_hist::gmean 5.329740 -system.ruby.latency_hist::stdev 25.242996 -system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6718 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6718 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1730 -system.ruby.miss_latency_hist::mean 54.891329 -system.ruby.miss_latency_hist::gmean 49.648144 -system.ruby.miss_latency_hist::stdev 31.153546 -system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1730 -system.ruby.Directory.incomplete_times 1729 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 771120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 428400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4879680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4281984 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 69480720 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 9282000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 96752304 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 826.589526 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 15125 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 98100 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1081080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 600600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 5466240 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 4323456 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 69027912 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 9680400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 97808088 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 835.595188 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 15368 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 97798 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.992328 -system.ruby.network.routers0.msg_count.Control::2 1730 -system.ruby.network.routers0.msg_count.Data::2 1726 -system.ruby.network.routers0.msg_count.Response_Data::4 1730 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers0.msg_bytes.Control::2 13840 -system.ruby.network.routers0.msg_bytes.Data::2 124272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers1.percent_links_utilized 6.992328 -system.ruby.network.routers1.msg_count.Control::2 1730 -system.ruby.network.routers1.msg_count.Data::2 1726 -system.ruby.network.routers1.msg_count.Response_Data::4 1730 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers1.msg_bytes.Control::2 13840 -system.ruby.network.routers1.msg_bytes.Data::2 124272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.percent_links_utilized 6.992328 -system.ruby.network.routers2.msg_count.Control::2 1730 -system.ruby.network.routers2.msg_count.Data::2 1726 -system.ruby.network.routers2.msg_count.Response_Data::4 1730 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers2.msg_bytes.Control::2 13840 -system.ruby.network.routers2.msg_bytes.Data::2 124272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.msg_count.Control 5190 -system.ruby.network.msg_count.Data 5178 -system.ruby.network.msg_count.Response_Data 5190 -system.ruby.network.msg_count.Writeback_Control 5178 -system.ruby.network.msg_byte.Control 41520 -system.ruby.network.msg_byte.Data 372816 -system.ruby.network.msg_byte.Response_Data 373680 -system.ruby.network.msg_byte.Writeback_Control 41424 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 3456 # delay histogram for all message +system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 3456 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 8449 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8449 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 8448 +system.ruby.latency_hist::mean 13.626420 +system.ruby.latency_hist::gmean 5.329740 +system.ruby.latency_hist::stdev 25.242996 +system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 8448 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 6718 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6718 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1730 +system.ruby.miss_latency_hist::mean 54.891329 +system.ruby.miss_latency_hist::gmean 49.648144 +system.ruby.miss_latency_hist::stdev 31.153546 +system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1730 +system.ruby.Directory.incomplete_times 1729 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.992328 +system.ruby.network.routers0.msg_count.Control::2 1730 +system.ruby.network.routers0.msg_count.Data::2 1726 +system.ruby.network.routers0.msg_count.Response_Data::4 1730 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers0.msg_bytes.Control::2 13840 +system.ruby.network.routers0.msg_bytes.Data::2 124272 +system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.routers1.percent_links_utilized 6.992328 +system.ruby.network.routers1.msg_count.Control::2 1730 +system.ruby.network.routers1.msg_count.Data::2 1726 +system.ruby.network.routers1.msg_count.Response_Data::4 1730 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers1.msg_bytes.Control::2 13840 +system.ruby.network.routers1.msg_bytes.Data::2 124272 +system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.routers2.percent_links_utilized 6.992328 +system.ruby.network.routers2.msg_count.Control::2 1730 +system.ruby.network.routers2.msg_count.Data::2 1726 +system.ruby.network.routers2.msg_count.Response_Data::4 1730 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers2.msg_bytes.Control::2 13840 +system.ruby.network.routers2.msg_bytes.Data::2 124272 +system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.msg_count.Control 5190 +system.ruby.network.msg_count.Data 5178 +system.ruby.network.msg_count.Response_Data 5190 +system.ruby.network.msg_count.Writeback_Control 5178 +system.ruby.network.msg_byte.Control 41520 +system.ruby.network.msg_byte.Data 372816 +system.ruby.network.msg_byte.Response_Data 373680 +system.ruby.network.msg_byte.Writeback_Control 41424 system.ruby.network.routers0.throttle0.link_utilization 6.998802 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 @@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 +system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 0513960dd..8eeabeb60 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18733500 # Number of ticks simulated final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41421 # Simulator instruction rate (inst/s) -host_op_rate 41407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 299977624 # Simulator tick rate (ticks/s) -host_mem_usage 235900 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 81438 # Simulator instruction rate (inst/s) +host_op_rate 81405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 589715743 # Simulator tick rate (ticks/s) +host_mem_usage 292180 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # By system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation -system.physmem.totQLat 1958750 # Total ticks spent queuing -system.physmem.totMemAccLat 7733750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1952250 # Total ticks spent queuing +system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6359.58 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25109.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 83.44 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 60556.82 # Average gap between requests system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15310750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 83160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 45375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1294800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10790100 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12765855 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13440630 # Total energy per rank (pJ) -system.physmem.averagePower::0 806.306964 # Core power per rank (mW) -system.physmem.averagePower::1 848.926575 # Core power per rank (mW) +system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ) +system.physmem_0.averagePower 806.306964 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ) +system.physmem_1.averagePower 848.926575 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 793 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect @@ -296,14 +301,14 @@ system.cpu.ipc 0.068994 # IP system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.468521 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 48.468521 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.011833 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011833 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 48.478730 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id @@ -326,14 +331,14 @@ system.cpu.dcache.demand_misses::cpu.inst 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4636500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4636500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3517500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3517500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 8154000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8154000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 8154000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4644500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3502000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 8146500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses) @@ -350,14 +355,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78403.846154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78403.846154 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76139.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81441.860465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,14 +387,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2086500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6389000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses @@ -398,24 +403,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.426247 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.426247 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057825 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057825 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id @@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst 223 # n system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15431500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15431500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15431500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15431500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15431500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses @@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69199.551570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69199.551570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69199.551570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69199.551570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69163.677130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69163.677130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,34 +477,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14892500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14892500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14884500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66782.511211 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66782.511211 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 146.486275 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 146.534478 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.486275 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.534478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id @@ -516,12 +521,12 @@ system.cpu.l2cache.overall_misses::cpu.inst 308 # system.cpu.l2cache.overall_misses::total 308 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18913000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2059500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2059500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20972500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20972500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20965250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses) @@ -540,12 +545,12 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76277.777778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76277.777778 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68092.532468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68092.532468 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,12 +569,12 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15398500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1725500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1725500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17124000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17124000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -580,12 +585,12 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63907.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63907.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution @@ -613,7 +618,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 154000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 137000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution @@ -636,7 +641,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 308 # Request fanout histogram system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2868500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 15.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index dd62dc740..49b58755c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11765500 # Number of ticks simulated final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35174 # Simulator instruction rate (inst/s) -host_op_rate 35164 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173275234 # Simulator tick rate (ticks/s) -host_mem_usage 235920 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 73154 # Simulator instruction rate (inst/s) +host_op_rate 73124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 360297045 # Simulator tick rate (ticks/s) +host_mem_usage 293708 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 81.99 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 42926.47 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7778000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 68040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 158760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 37125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 86625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 631800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 850200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5478840 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5222340 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 246750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 6746115 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 7073235 # Total energy per rank (pJ) -system.physmem.averagePower::0 838.417275 # Core power per rank (mW) -system.physmem.averagePower::1 879.072239 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 248 # Transaction distribution -system.membus.trans_dist::ReadResp 248 # Transaction distribution -system.membus.trans_dist::ReadExReq 24 # Transaction distribution -system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 272 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 631800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 6746115 # Total energy per rank (pJ) +system.physmem_0.averagePower 838.417275 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206000 # Time in different power states +system.physmem_0.memoryStateTime::REF 260000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7778000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 158760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 86625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 850200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5222340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 7073235 # Total energy per rank (pJ) +system.physmem_1.averagePower 879.072239 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 397500 # Time in different power states +system.physmem_1.memoryStateTime::REF 260000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7402500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1090 # Number of BP lookups system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -603,34 +585,118 @@ system.cpu.int_regfile_writes 2774 # nu system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits +system.cpu.dcache.overall_hits::total 729 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses +system.cpu.dcache.overall_misses::total 198 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. @@ -846,117 +912,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits -system.cpu.dcache.overall_hits::total 729 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses -system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.membus.trans_dist::ReadResp 248 # Transaction distribution +system.membus.trans_dist::ReadExReq 24 # Transaction distribution +system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 272 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 272 # Request fanout histogram +system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index d47845159..84bb9ed03 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52301 # Number of ticks simulated final_tick 52301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 11256 # Simulator instruction rate (inst/s) -host_op_rate 11255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 228406 # Simulator tick rate (ticks/s) -host_mem_usage 435628 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 42059 # Simulator instruction rate (inst/s) +host_op_rate 42050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 853239 # Simulator tick rate (ticks/s) +host_mem_usage 450140 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 79.91 # Ro system.mem_ctrls.writeRowHitRate 30.43 # Row buffer hit rate for writes system.mem_ctrls.avgGap 80.33 # Average gap between requests system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 20 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45410 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 393120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 218400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1971840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2907840 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 31347036 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 31310100 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 688200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 720600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 37328916 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 38767308 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 794.638028 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 825.257749 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 31347036 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 688200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 37328916 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 794.638028 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1179 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 44437 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2907840 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 31309416 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 721200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 38767224 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 825.255960 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1048 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44382 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 52301 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 52301 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -299,7 +396,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -309,6 +405,10 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 3.803943 system.ruby.network.routers0.msg_count.Control::0 572 system.ruby.network.routers0.msg_count.Request_Control::2 431 @@ -326,9 +426,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 -system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 7.327776 system.ruby.network.routers1.msg_count.Control::0 1119 system.ruby.network.routers1.msg_count.Request_Control::2 431 @@ -382,98 +479,6 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 52301 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52301 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.452095 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 @@ -647,6 +652,16 @@ system.ruby.IFETCH.miss_latency_hist::gmean 75.006009 system.ruby.IFETCH.miss_latency_hist::stdev 25.337433 system.ruby.IFETCH.miss_latency_hist | 9 3.00% 3.00% | 0 0.00% 3.00% | 276 92.00% 95.00% | 10 3.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 1 0.33% 99.00% | 1 0.33% 99.33% | 1 0.33% 99.67% | 1 0.33% 100.00% system.ruby.IFETCH.miss_latency_hist::total 300 +system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% +system.ruby.Directory_Controller.Data 103 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -711,15 +726,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data 192 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 291 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 64 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 272 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 2e81c65b5..b603fabdb 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000048 # Nu sim_ticks 48283 # Number of ticks simulated final_tick 48283 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12943 # Simulator instruction rate (inst/s) -host_op_rate 12941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 242448 # Simulator tick rate (ticks/s) -host_mem_usage 437744 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 45603 # Simulator instruction rate (inst/s) +host_op_rate 45593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 854052 # Simulator tick rate (ticks/s) +host_mem_usage 451760 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 77.66 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 88.76 # Average gap between requests system.mem_ctrls.pageHitRate 72.85 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 76 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45412 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 446040 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 247800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1884480 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2808000 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 31539240 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 30693132 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 520800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1263000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 37266360 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 38675220 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 793.272596 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 823.262378 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1884480 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 31537872 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 520800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 37264992 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 793.277248 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 968 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 44716 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 446040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 247800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2808000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 30693132 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1263000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 38675220 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 823.262378 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2007 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 43481 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 48283 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 48283 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -292,7 +389,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.874739 system.ruby.network.routers0.msg_count.Request_Control::0 544 system.ruby.network.routers0.msg_count.Response_Data::2 465 @@ -306,9 +406,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5688 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 -system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 8.967442 system.ruby.network.routers1.msg_count.Request_Control::0 544 system.ruby.network.routers1.msg_count.Request_Control::1 465 @@ -366,98 +463,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 17064 system.ruby.network.msg_byte.Writeback_Data 120960 system.ruby.network.msg_byte.Writeback_Control 27840 system.ruby.network.msg_byte.Unblock_Control 24688 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 48283 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 48283 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.589959 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 465 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 79 @@ -614,6 +619,29 @@ system.ruby.IFETCH.miss_latency_hist::gmean 69.413198 system.ruby.IFETCH.miss_latency_hist::stdev 30.681798 system.ruby.IFETCH.miss_latency_hist | 26 9.63% 9.63% | 239 88.52% 98.15% | 2 0.74% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 270 +system.ruby.Directory_Controller.GETX 80 0.00% 0.00% +system.ruby.Directory_Controller.GETS 385 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -691,28 +719,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 12 0.00% system.ruby.L2Cache_Controller.SS.Unblock 51 0.00% 0.00% system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 16 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.GETX 80 0.00% 0.00% -system.ruby.Directory_Controller.GETS 385 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 69664e25a..166a3264e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu sim_ticks 43869 # Number of ticks simulated final_tick 43869 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 107 # Simulator instruction rate (inst/s) -host_op_rate 107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1826 # Simulator tick rate (ticks/s) -host_mem_usage 435688 # Number of bytes of host memory used -host_seconds 24.02 # Real time elapsed on the host +host_inst_rate 63661 # Simulator instruction rate (inst/s) +host_op_rate 63637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1082971 # Simulator tick rate (ticks/s) +host_mem_usage 449944 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 78.40 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 82.31 # Average gap between requests system.mem_ctrls.pageHitRate 73.40 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 37882 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 158760 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 355320 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 88200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 197400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1697280 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2483520 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 25360668 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 26385300 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1267800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 369000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 31115508 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 32499228 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 793.965501 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 829.273488 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1697280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 25360668 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1267800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 31115508 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 793.965501 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1987 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 35917 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2483520 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 26385300 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 369000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 32499228 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 829.273488 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 583 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 37415 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 43869 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 43869 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -294,7 +391,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.531811 system.ruby.network.routers0.msg_count.Request_Control::1 518 system.ruby.network.routers0.msg_count.Response_Data::4 448 @@ -308,9 +408,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 64 -system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.129340 system.ruby.network.routers1.msg_count.Request_Control::1 518 system.ruby.network.routers1.msg_count.Request_Control::2 454 @@ -368,98 +465,6 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 126576 system.ruby.network.msg_byte.Writeback_Control 8760 system.ruby.network.msg_byte.Persistent_Control 192 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 43869 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 43869 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.319246 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 @@ -718,6 +723,32 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.741160 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.366891 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 1 0.40% 98.79% | 3 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 247 +system.ruby.Directory_Controller.GETX 61 0.00% 0.00% +system.ruby.Directory_Controller.GETS 398 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -786,31 +817,5 @@ system.ruby.L2Cache_Controller.M.L1_GETS 52 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 415 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.GETX 61 0.00% 0.00% -system.ruby.Directory_Controller.GETS 398 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 391ee4c59..2c1a5d0e0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu sim_ticks 36255 # Number of ticks simulated final_tick 36255 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16369 # Simulator instruction rate (inst/s) -host_op_rate 16367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230240 # Simulator tick rate (ticks/s) -host_mem_usage 435584 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 60442 # Simulator instruction rate (inst/s) +host_op_rate 60421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 849780 # Simulator tick rate (ticks/s) +host_mem_usage 449324 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 80.27 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.32 # Average gap between requests system.mem_ctrls.pageHitRate 75.06 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 30367 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 143640 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 79800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 172200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1634880 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2446080 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 20833956 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 21069936 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 567000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 360000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 25293516 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 26558304 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 805.423386 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 845.698128 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1634880 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 20833956 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 567000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 25293516 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 805.423386 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 847 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 29531 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 172200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2446080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 21069936 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 360000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 26558304 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 845.698128 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1450 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 29876 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 36255 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 36255 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -288,7 +385,9 @@ system.ruby.miss_latency_hist::stdev 26.697338 system.ruby.miss_latency_hist | 59 13.38% 13.38% | 290 65.76% 79.14% | 87 19.73% 98.87% | 1 0.23% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 1 0.23% 99.32% | 3 0.68% 100.00% system.ruby.miss_latency_hist::total 441 system.ruby.Directory.incomplete_times 440 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -298,7 +397,7 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 4.670390 system.ruby.network.routers0.msg_count.Request_Control::2 441 system.ruby.network.routers0.msg_count.Response_Data::4 441 @@ -314,9 +413,6 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.670390 system.ruby.network.routers1.msg_count.Request_Control::2 441 system.ruby.network.routers1.msg_count.Response_Data::4 441 @@ -357,97 +453,6 @@ system.ruby.network.msg_byte.Response_Data 95256 system.ruby.network.msg_byte.Writeback_Data 17496 system.ruby.network.msg_byte.Writeback_Control 28656 system.ruby.network.msg_byte.Unblock_Control 10560 -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 36255 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36255 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.059854 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 @@ -682,6 +687,25 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.229629 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 23.299188 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 199 80.24% 80.24% | 46 18.55% 98.79% | 1 0.40% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 2 0.81% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 248 +system.ruby.Directory_Controller.GETX 51 0.00% 0.00% +system.ruby.Directory_Controller.GETS 409 0.00% 0.00% +system.ruby.Directory_Controller.PUT 425 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% system.ruby.L1Cache_Controller.Load 422 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2591 0.00% 0.00% system.ruby.L1Cache_Controller.Store 298 0.00% 0.00% @@ -723,24 +747,5 @@ system.ruby.L1Cache_Controller.MI.Store 4 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 425 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 45 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 24 0.00% 0.00% -system.ruby.Directory_Controller.GETX 51 0.00% 0.00% -system.ruby.Directory_Controller.GETS 409 0.00% 0.00% -system.ruby.Directory_Controller.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 58855671d..19e3fb417 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000048 # Nu sim_ticks 47840 # Number of ticks simulated final_tick 47840 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31483 # Simulator instruction rate (inst/s) -host_op_rate 31473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 584131 # Simulator tick rate (ticks/s) -host_mem_usage 435420 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 35814 # Simulator instruction rate (inst/s) +host_op_rate 35808 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 664620 # Simulator tick rate (ticks/s) +host_mem_usage 449364 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate 74.87 # Ro system.mem_ctrls.writeRowHitRate 87.91 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.30 # Average gap between requests system.mem_ctrls.pageHitRate 81.48 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 140 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45290 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 249480 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 138600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 319200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 2009280 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2758080 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 1575936 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 2208384 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 30369600 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 31087116 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1545600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 916200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 38939856 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 40914900 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 828.930858 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 870.974540 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 1248 # delay histogram for all message -system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1248 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 13.523376 -system.ruby.latency_hist::gmean 5.183572 -system.ruby.latency_hist::stdev 25.409311 -system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 2668 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2668 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 626 -system.ruby.miss_latency_hist::mean 58.373802 -system.ruby.miss_latency_hist::gmean 53.319163 -system.ruby.miss_latency_hist::stdev 30.235728 -system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626 -system.ruby.Directory.incomplete_times 625 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 249480 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 138600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2009280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1575936 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 30369600 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1545600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 38939856 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 828.930858 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 2928 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 43008 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 574560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 319200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2758080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2208384 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 31087116 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 916200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 40914900 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 870.974540 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1359 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44071 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.521739 -system.ruby.network.routers0.msg_count.Control::2 626 -system.ruby.network.routers0.msg_count.Data::2 622 -system.ruby.network.routers0.msg_count.Response_Data::4 626 -system.ruby.network.routers0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers0.msg_bytes.Control::2 5008 -system.ruby.network.routers0.msg_bytes.Data::2 44784 -system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.percent_links_utilized 6.521739 -system.ruby.network.routers1.msg_count.Control::2 626 -system.ruby.network.routers1.msg_count.Data::2 622 -system.ruby.network.routers1.msg_count.Response_Data::4 626 -system.ruby.network.routers1.msg_count.Writeback_Control::3 622 -system.ruby.network.routers1.msg_bytes.Control::2 5008 -system.ruby.network.routers1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.percent_links_utilized 6.521739 -system.ruby.network.routers2.msg_count.Control::2 626 -system.ruby.network.routers2.msg_count.Data::2 622 -system.ruby.network.routers2.msg_count.Response_Data::4 626 -system.ruby.network.routers2.msg_count.Writeback_Control::3 622 -system.ruby.network.routers2.msg_bytes.Control::2 5008 -system.ruby.network.routers2.msg_bytes.Data::2 44784 -system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.msg_count.Control 1878 -system.ruby.network.msg_count.Data 1866 -system.ruby.network.msg_count.Response_Data 1878 -system.ruby.network.msg_count.Writeback_Control 1866 -system.ruby.network.msg_byte.Control 15024 -system.ruby.network.msg_byte.Data 134352 -system.ruby.network.msg_byte.Response_Data 135216 -system.ruby.network.msg_byte.Writeback_Control 14928 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 1248 # delay histogram for all message +system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1248 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 3295 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 3295 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 3294 +system.ruby.latency_hist::mean 13.523376 +system.ruby.latency_hist::gmean 5.183572 +system.ruby.latency_hist::stdev 25.409311 +system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 3294 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 2668 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 2668 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 626 +system.ruby.miss_latency_hist::mean 58.373802 +system.ruby.miss_latency_hist::gmean 53.319163 +system.ruby.miss_latency_hist::stdev 30.235728 +system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 626 +system.ruby.Directory.incomplete_times 625 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.521739 +system.ruby.network.routers0.msg_count.Control::2 626 +system.ruby.network.routers0.msg_count.Data::2 622 +system.ruby.network.routers0.msg_count.Response_Data::4 626 +system.ruby.network.routers0.msg_count.Writeback_Control::3 622 +system.ruby.network.routers0.msg_bytes.Control::2 5008 +system.ruby.network.routers0.msg_bytes.Data::2 44784 +system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers1.percent_links_utilized 6.521739 +system.ruby.network.routers1.msg_count.Control::2 626 +system.ruby.network.routers1.msg_count.Data::2 622 +system.ruby.network.routers1.msg_count.Response_Data::4 626 +system.ruby.network.routers1.msg_count.Writeback_Control::3 622 +system.ruby.network.routers1.msg_bytes.Control::2 5008 +system.ruby.network.routers1.msg_bytes.Data::2 44784 +system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers2.percent_links_utilized 6.521739 +system.ruby.network.routers2.msg_count.Control::2 626 +system.ruby.network.routers2.msg_count.Data::2 622 +system.ruby.network.routers2.msg_count.Response_Data::4 626 +system.ruby.network.routers2.msg_count.Writeback_Control::3 622 +system.ruby.network.routers2.msg_bytes.Control::2 5008 +system.ruby.network.routers2.msg_bytes.Data::2 44784 +system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.msg_count.Control 1878 +system.ruby.network.msg_count.Data 1866 +system.ruby.network.msg_count.Response_Data 1878 +system.ruby.network.msg_count.Writeback_Control 1866 +system.ruby.network.msg_byte.Control 15024 +system.ruby.network.msg_byte.Data 134352 +system.ruby.network.msg_byte.Response_Data 135216 +system.ruby.network.msg_byte.Writeback_Control 14928 system.ruby.network.routers0.throttle0.link_utilization 6.538462 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 @@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.999958 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.587258 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297 +system.ruby.Directory_Controller.GETX 626 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement 622 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 542 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 84 0.00% 0.00% -system.ruby.Directory_Controller.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 1f9a90b5a..58622e09f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27981000 # Number of ticks simulated final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65720 # Simulator instruction rate (inst/s) -host_op_rate 76928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 399296424 # Simulator tick rate (ticks/s) -host_mem_usage 250660 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 95550 # Simulator instruction rate (inst/s) +host_op_rate 111835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 580422337 # Simulator tick rate (ticks/s) +host_mem_usage 309164 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -217,29 +217,34 @@ system.physmem.readRowHitRate 83.14 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 66260.10 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 12000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22840500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ) -system.physmem.averagePower::0 856.107753 # Core power per rank (mW) -system.physmem.averagePower::1 786.272135 # Core power per rank (mW) +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) +system.physmem_0.averagePower 856.107753 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) +system.physmem_1.averagePower 786.272135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1926 # Number of BP lookups system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect @@ -250,6 +255,14 @@ system.cpu.branchPred.BTBHitPct 20.426065 # BT system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -271,6 +284,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -292,6 +313,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -313,6 +342,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 62f6dcd2b..bac015830 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16223000 # Number of ticks simulated final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26356 # Simulator instruction rate (inst/s) -host_op_rate 30865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93111675 # Simulator tick rate (ticks/s) -host_mem_usage 251576 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 54860 # Simulator instruction rate (inst/s) +host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193800024 # Simulator tick rate (ticks/s) +host_mem_usage 308908 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -221,53 +221,34 @@ system.physmem.readRowHitRate 83.38 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 40695.21 # Average gap between requests system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 317520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 151200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 173250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 82500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2238600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 795600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10477170 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 309000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 14571510 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 12832590 # Total energy per rank (pJ) -system.physmem.averagePower::0 920.354334 # Core power per rank (mW) -system.physmem.averagePower::1 810.522027 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 355 # Transaction distribution -system.membus.trans_dist::ReadResp 355 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 397 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) +system.physmem_0.averagePower 920.354334 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) +system.physmem_1.averagePower 810.522027 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2638 # Number of BP lookups system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect @@ -277,6 +258,15 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -298,6 +288,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -319,6 +317,14 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -340,6 +346,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.walks 0 # Table walker walks requested +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -365,6 +379,14 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 5390 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -386,6 +408,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -407,6 +437,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -428,6 +466,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -744,42 +790,136 @@ system.cpu.cc_regfile_reads 28734 # nu system.cpu.cc_regfile_writes 3302 # number of cc regfile writes system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits +system.cpu.dcache.overall_hits::total 2146 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses +system.cpu.dcache.overall_misses::total 521 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. @@ -1010,135 +1150,64 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 355 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.trans_dist::ReadExReq 42 # Transaction distribution +system.membus.trans_dist::ReadExResp 42 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 397 # Request fanout histogram +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 6fc5d6de3..9157ec7b3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11859500 # Number of ticks simulated -final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16487000 # Number of ticks simulated +final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34923 # Simulator instruction rate (inst/s) -host_op_rate 40896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90188816 # Simulator tick rate (ticks/s) -host_mem_usage 248256 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 33036 # Simulator instruction rate (inst/s) +host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118603969 # Simulator tick rate (ticks/s) +host_mem_usage 248576 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory -system.physmem.bytes_read::total 46848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 732 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 733 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory +system.physmem.bytes_read::total 26048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory +system.physmem.num_reads::total 407 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 143 # Per bank write bursts -system.physmem.perBankRdBursts::1 90 # Per bank write bursts -system.physmem.perBankRdBursts::2 40 # Per bank write bursts -system.physmem.perBankRdBursts::3 73 # Per bank write bursts -system.physmem.perBankRdBursts::4 58 # Per bank write bursts -system.physmem.perBankRdBursts::5 88 # Per bank write bursts -system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 18 # Per bank write bursts -system.physmem.perBankRdBursts::8 12 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 34 # Per bank write bursts +system.physmem.perBankRdBursts::0 88 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 19 # Per bank write bursts +system.physmem.perBankRdBursts::3 45 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 32 # Per bank write bursts +system.physmem.perBankRdBursts::6 37 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 26 # Per bank write bursts system.physmem.perBankRdBursts::11 47 # Per bank write bursts system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 19 # Per bank write bursts +system.physmem.perBankRdBursts::13 7 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11846500 # Total gap between requests +system.physmem.totGap 16473500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 733 # Read request sizes (log2) +system.physmem.readPktSize::6 408 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,98 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation -system.physmem.totQLat 17284989 # Total ticks spent queuing -system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 3192729 # Total ticks spent queuing +system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 30.90 # Data bus utilization in percentage -system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads +system.physmem.busUtil 12.37 # Data bus utilization in percentage +system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 662 # Number of row buffer hits during reads +system.physmem.readRowHits 342 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 16161.66 # Average gap between requests -system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 6500 # Time in different power states -system.physmem.memoryStateTime::REF 260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7800750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 249480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 90720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 136125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 49500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3088800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1037400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5483970 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5436945 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 63000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 9488685 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 7186125 # Total energy per rank (pJ) -system.physmem.averagePower::0 1178.169797 # Core power per rank (mW) -system.physmem.averagePower::1 892.270681 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 704 # Transaction distribution -system.membus.trans_dist::ReadResp 702 # Transaction distribution -system.membus.trans_dist::ReadExReq 29 # Transaction distribution -system.membus.trans_dist::ReadExResp 29 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 733 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 733 # Request fanout histogram -system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 55.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2560 # Number of BP lookups -system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups -system.cpu.branchPred.BTBHits 497 # Number of BTB hits +system.physmem.avgGap 40376.23 # Average gap between requests +system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) +system.physmem_0.averagePower 918.403600 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) +system.physmem_1.averagePower 817.101847 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 2361 # Number of BP lookups +system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 473 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -303,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -324,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -345,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -367,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 23720 # number of cpu cycles simulated +system.cpu.numCycles 32975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1063 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5106 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4105 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5035 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4080 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -452,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7242 # Type of FU issued -system.cpu.iq.rate 0.305312 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 7157 # Type of FU issued +system.cpu.iq.rate 0.217043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2449 # number of memory reference insts executed -system.cpu.iew.exec_branches 1283 # Number of branches executed -system.cpu.iew.exec_stores 1021 # Number of stores executed -system.cpu.iew.exec_rate 0.287858 # Inst execution rate -system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6654 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3045 # num instructions producing a value -system.cpu.iew.wb_consumers 5519 # num instructions consuming a value +system.cpu.iew.exec_refs 2417 # number of memory reference insts executed +system.cpu.iew.exec_branches 1277 # Number of branches executed +system.cpu.iew.exec_stores 1017 # Number of stores executed +system.cpu.iew.exec_rate 0.205034 # Inst execution rate +system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6587 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2990 # num instructions producing a value +system.cpu.iew.wb_consumers 5391 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back +system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -640,449 +654,469 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24066 # The number of ROB reads -system.cpu.rob.rob_writes 16750 # The number of ROB writes -system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22003 # The number of ROB reads +system.cpu.rob.rob_writes 16441 # The number of ROB writes +system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads -system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6787 # number of integer regfile reads -system.cpu.int_regfile_writes 3839 # number of integer regfile writes +system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads +system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6737 # number of integer regfile reads +system.cpu.int_regfile_writes 3765 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24301 # number of cc regfile reads -system.cpu.cc_regfile_writes 2919 # number of cc regfile writes -system.cpu.misc_regfile_reads 2642 # number of misc regfile reads +system.cpu.cc_regfile_reads 24010 # number of cc regfile reads +system.cpu.cc_regfile_writes 2910 # number of cc regfile writes +system.cpu.misc_regfile_reads 2599 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1026 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 47 # number of replacements -system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits +system.cpu.dcache.overall_hits::total 1876 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses +system.cpu.dcache.overall_misses::total 369 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 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7484255 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7484255 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7484255 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063697 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063697 # 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Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8536 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits -system.cpu.icache.overall_hits::total 3784 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 332 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 332 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 332 # number of 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-system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.080661 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.080661 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.080661 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.080661 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.080661 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855 # average ReadReq miss latency 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(read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3485 # number of overall hits +system.cpu.icache.overall_hits::total 3485 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses +system.cpu.icache.overall_misses::total 362 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19725741 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19725741 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19725741 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19725741 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19725741 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19725741 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses 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was blocked +system.cpu.icache.blocked::no_mshrs 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 81.297872 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 28 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6489997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6489997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6489997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6489997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6489997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6489997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.073858 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.073858 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.073858 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21348.674342 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21348.674342 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR 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+system.cpu.icache.overall_mshr_miss_latency::total 16894743 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077203 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077203 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077203 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56884.656566 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56884.656566 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 29 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 603 # number of hwpf issued -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 198 # number of hwpf spanning a virtual page -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of 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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits -system.cpu.dcache.overall_hits::total 1873 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses -system.cpu.dcache.overall_misses::total 392 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 67 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 378 # Transaction distribution +system.membus.trans_dist::ReadResp 376 # Transaction distribution +system.membus.trans_dist::ReadExReq 30 # Transaction distribution +system.membus.trans_dist::ReadExResp 30 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 408 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 408 # Request fanout histogram +system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 23.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 398374723..72322cbec 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 582910 # Simulator instruction rate (inst/s) -host_op_rate 681582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 341032781 # Simulator tick rate (ticks/s) -host_mem_usage 293692 # Number of bytes of host memory used +host_inst_rate 396323 # Simulator instruction rate (inst/s) +host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232084410 # Simulator tick rate (ticks/s) +host_mem_usage 298640 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -35,35 +35,15 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -85,6 +65,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -106,6 +94,14 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -127,6 +123,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.walks 0 # Table walker walks requested +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -152,6 +156,14 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 0 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -173,6 +185,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -194,6 +214,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -215,6 +243,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -296,5 +332,33 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index d2d36b722..b8c713e42 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 685428 # Simulator instruction rate (inst/s) -host_op_rate 801222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 400788339 # Simulator tick rate (ticks/s) -host_mem_usage 292412 # Number of bytes of host memory used +host_inst_rate 370272 # Simulator instruction rate (inst/s) +host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216878622 # Simulator tick rate (ticks/s) +host_mem_usage 297624 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -35,35 +35,15 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -85,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -106,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -127,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -209,5 +213,33 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 83a7fcb5f..872a056d2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25815000 # Number of ticks simulated final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 367819 # Simulator instruction rate (inst/s) -host_op_rate 428893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2075494452 # Simulator tick rate (ticks/s) -host_mem_usage 302164 # Number of bytes of host memory used +host_inst_rate 376930 # Simulator instruction rate (inst/s) +host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2127142386 # Simulator tick rate (ticks/s) +host_mem_usage 307352 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 557815224 # In system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 307 # Transaction distribution -system.membus.trans_dist::ReadResp 307 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 350 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,118 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits +system.cpu.dcache.overall_hits::total 1764 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses +system.cpu.dcache.overall_misses::total 141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. @@ -416,118 +537,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits -system.cpu.dcache.overall_hits::total 1764 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -560,5 +569,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 307 # Transaction distribution +system.membus.trans_dist::ReadResp 307 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 350 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 350 # Request fanout histogram +system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1593f969f..a18a67ef2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24417000 # Number of ticks simulated -final_tick 24417000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24407000 # Number of ticks simulated +final_tick 24407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26948 # Simulator instruction rate (inst/s) -host_op_rate 26945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116974890 # Simulator tick rate (ticks/s) -host_mem_usage 277212 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 92117 # Simulator instruction rate (inst/s) +host_op_rate 92097 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 399597243 # Simulator tick rate (ticks/s) +host_mem_usage 289532 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 450 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 820412008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359094074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1179506082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 820412008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 820412008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 820412008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359094074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1179506082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 820748146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359241201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1179989347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 820748146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 820748146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 820748146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359241201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1179989347 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 450 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 450 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24336000 # Total gap between requests +system.physmem.totGap 24326000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 3 2.91% 94.17% # By system.physmem.bytesPerActivate::896-1023 1 0.97% 95.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 4.85% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 4914500 # Total ticks spent queuing -system.physmem.totMemAccLat 13352000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4895500 # Total ticks spent queuing +system.physmem.totMemAccLat 13333000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10921.11 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10878.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29671.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1179.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29628.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1179.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1179.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1179.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.21 # Data bus utilization in percentage -system.physmem.busUtilRead 9.21 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.22 # Data bus utilization in percentage +system.physmem.busUtilRead 9.22 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,55 +220,36 @@ system.physmem.readRowHits 344 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54080.00 # Average gap between requests +system.physmem.avgGap 54057.78 # Average gap between requests system.physmem.pageHitRate 76.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22851000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 181440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 582120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 99000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 317625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 772200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2652000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 14753880 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 16048350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1235250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 99750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 18567450 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 21225525 # Total energy per rank (pJ) -system.physmem.averagePower::0 785.799080 # Core power per rank (mW) -system.physmem.averagePower::1 898.292335 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 400 # Transaction distribution -system.membus.trans_dist::ReadResp 400 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 450 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 450 # Request fanout histogram -system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4210750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 772200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14753880 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1232250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 18564450 # Total energy per rank (pJ) +system.physmem_0.averagePower 785.838404 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1971000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20886000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 582120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 317625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 16041510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 99750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21218685 # Total energy per rank (pJ) +system.physmem_1.averagePower 898.383064 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 96500 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22756000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1124 # Number of BP lookups system.cpu.branchPred.condPredicted 833 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 586 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 38.705882 # BTB Hit Percentage system.cpu.branchPred.usedRAS 84 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -297,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 48835 # number of cpu cycles simulated +system.cpu.numCycles 48815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 421 # Number of Branches Predicted As Taken (True). @@ -322,9 +304,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 9295 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43587 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 43567 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5248 # Number of cycles cpu stages are processed. -system.cpu.activity 10.746391 # Percentage of cycles cpu is active +system.cpu.activity 10.750794 # Percentage of cycles cpu is active system.cpu.comLoads 1132 # Number of Load instructions committed system.cpu.comStores 901 # Number of Store instructions committed system.cpu.comBranches 883 # Number of Branches instructions committed @@ -336,36 +318,148 @@ system.cpu.committedInsts 5624 # Nu system.cpu.committedOps 5624 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5624 # Number of Instructions committed (Total) -system.cpu.cpi 8.683321 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.679765 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.683321 # CPI: Total CPI of All Threads -system.cpu.ipc 0.115163 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.679765 # CPI: Total CPI of All Threads +system.cpu.ipc 0.115210 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.115163 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45291 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.115210 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45271 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3544 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.257090 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46099 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.260064 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46079 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2736 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.602539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46145 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.604835 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46125 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2690 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.508344 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47641 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.510601 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47621 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1194 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.444968 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46041 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.445969 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46021 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2794 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.721306 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 5.723651 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 89.114959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 89.114959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits +system.cpu.dcache.overall_hits::total 1596 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20579000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20579000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60526.470588 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60526.470588 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63951.945080 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63951.945080 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3771500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3771500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10474750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10474750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10474750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10474750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75430 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 147.900639 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.861470 # Cycle average of tags in use system.cpu.icache.tags.total_refs 418 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 315 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.326984 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.900639 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072217 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.861470 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072198 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072198 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -384,12 +478,12 @@ system.cpu.icache.demand_misses::cpu.inst 344 # n system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25151000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25151000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25151000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25151000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25151000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25151000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25136000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25136000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25136000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25136000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25136000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25136000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 762 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 762 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 762 # number of demand (read+write) accesses @@ -402,12 +496,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.451444 system.cpu.icache.demand_miss_rate::total 0.451444 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.451444 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.451444 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73113.372093 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73113.372093 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73113.372093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73113.372093 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73069.767442 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73069.767442 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73069.767442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73069.767442 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -428,64 +522,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22975000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22960000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22960000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.413386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.413386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.413386 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72936.507937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72936.507937 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72888.888889 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72888.888889 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 204.797884 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 204.748410 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.365797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.432088 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004558 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006250 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.325774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.422636 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004557 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006248 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id @@ -509,17 +575,17 @@ system.cpu.l2cache.demand_misses::total 450 # nu system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 450 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22634000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22619000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6609750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29243750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3723500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3723500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10333250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32967250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10333250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32967250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29228750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3718500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3718500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22619000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10328250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32947250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22619000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10328250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32947250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) @@ -542,17 +608,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995575 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993651 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995575 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72313.099042 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72265.175719 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73109.375000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74470 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74470 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72313.099042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75425.182482 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73260.555556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72313.099042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75425.182482 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73260.555556 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73071.875000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74370 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74370 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73216.111111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73216.111111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,17 +638,17 @@ system.cpu.l2cache.demand_mshr_misses::total 450 system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18704000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18689500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5530750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24234750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3093000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3093000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18704000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8623750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27327750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18704000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8623750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27327750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24220250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3088000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3088000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18689500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8618750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27308250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18689500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8618750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27308250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -594,129 +660,68 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995575 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995575 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59757.188498 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59710.862620 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60586.875000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59757.188498 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62947.080292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60728.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59757.188498 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62947.080292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60728.333333 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60550.625000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61760 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61760 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.129655 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.129655 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits -system.cpu.dcache.overall_hits::total 1596 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20584000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27952000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27952000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27952000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60541.176471 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60541.176471 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63963.386728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63963.386728 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10479750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10479750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10479750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10479750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75530 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 400 # Transaction distribution +system.membus.trans_dist::ReadResp 400 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 450 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 450 # Request fanout histogram +system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4210250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 61d4efb5a..ca0260a61 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21163500 # Number of ticks simulated final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24711 # Simulator instruction rate (inst/s) -host_op_rate 24708 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 104867636 # Simulator tick rate (ticks/s) -host_mem_usage 278232 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 81533 # Simulator instruction rate (inst/s) +host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 345921870 # Simulator tick rate (ticks/s) +host_mem_usage 292088 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 75.58 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 44762.21 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 136080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 536760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 74250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 292875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 569400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2285400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 9955620 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10734525 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 766500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 83250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12518970 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14949930 # Total energy per rank (pJ) -system.physmem.averagePower::0 790.713406 # Core power per rank (mW) -system.physmem.averagePower::1 944.255803 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 421 # Transaction distribution -system.membus.trans_dist::ReadResp 421 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 471 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) +system.physmem_0.averagePower 790.660351 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) +system.physmem_1.averagePower 944.255803 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2146 # Number of BP lookups system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -589,34 +571,118 @@ system.cpu.int_regfile_writes 5247 # nu system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 164 # number of misc regfile reads -system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits +system.cpu.dcache.overall_hits::total 2445 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses +system.cpu.dcache.overall_misses::total 515 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. @@ -838,117 +904,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 421 # Transaction distribution +system.membus.trans_dist::ReadResp 421 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 471 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 471 # Request fanout histogram +system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 3a696e5a2..8476aa73a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000116 # Number of seconds simulated -sim_ticks 115508 # Number of ticks simulated -final_tick 115508 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000115 # Number of seconds simulated +sim_ticks 115467 # Number of ticks simulated +final_tick 115467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 2198 # Simulator instruction rate (inst/s) -host_op_rate 2198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45146 # Simulator tick rate (ticks/s) -host_mem_usage 435400 # Number of bytes of host memory used -host_seconds 2.56 # Real time elapsed on the host +host_inst_rate 66709 # Simulator instruction rate (inst/s) +host_op_rate 66698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1369179 # Simulator tick rate (ticks/s) +host_mem_usage 449556 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,41 +21,41 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 814489040 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 814489040 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 812272743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 812272743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1626761783 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1626761783 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 814778248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 814778248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 812561165 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 812561165 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1627339413 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1627339413 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1470 # Number of read requests accepted system.mem_ctrls.writeReqs 1466 # Number of write requests accepted system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 59264 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 34816 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 60672 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 59456 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 34624 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 60800 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 544 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 493 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 491 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 34 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 86 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 65 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 244 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 102 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 43 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 100 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 248 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 103 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 173 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 35 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 36 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts @@ -64,16 +64,16 @@ system.mem_ctrls.perBankWrBursts::5 3 # Pe system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 244 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 249 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 194 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 114 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 182 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 16 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 115437 # Total gap between requests +system.mem_ctrls.totGap 115396 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 926 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 929 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,12 +135,12 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 13 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 17 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 62 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see @@ -184,162 +184,91 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 349 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 341.455587 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 225.575393 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 311.156448 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 80 22.92% 22.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 99 28.37% 51.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 59 16.91% 68.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 25 7.16% 75.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 22 6.30% 81.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 2.58% 84.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 3.44% 87.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 6 1.72% 89.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 37 10.60% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 349 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 362 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 330.077348 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 218.964738 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 303.831296 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 84 23.20% 23.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 104 28.73% 51.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 58 16.02% 67.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 36 9.94% 77.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 5.25% 83.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 2.76% 85.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 2.49% 88.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.38% 89.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 37 10.22% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 362 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.070175 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.908868 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.750712 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 24 42.11% 45.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.105263 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.953786 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.697116 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 1.75% 1.75% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 45.61% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.631579 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.601010 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.045937 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 39 68.42% 68.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 5 8.77% 77.19% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 9 15.79% 92.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.637263 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.023533 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 37 64.91% 64.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 6 10.53% 75.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 11 19.30% 94.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 3.51% 98.25% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12468 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30062 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4630 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.46 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 12340 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 29991 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4645 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.28 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.46 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 513.07 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 525.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 814.49 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 812.27 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.28 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 514.92 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 526.56 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 814.78 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 812.56 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.11 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.01 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.14 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.02 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.51 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 891 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 67.60 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.57 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 39.32 # Average gap between requests -system.mem_ctrls.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 12 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 105626 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 453600 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 2033640 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 252000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 1129800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1547520 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 9409920 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 1213056 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 8107776 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 51518196 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 74359692 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 20367000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 330600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 82471212 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 102491268 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 754.788512 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 938.014973 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2936 # delay histogram for all message -system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2936 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 7659 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 7659 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 14.083312 -system.ruby.latency_hist::gmean 5.240199 -system.ruby.latency_hist::stdev 27.247033 -system.ruby.latency_hist | 7337 95.81% 95.81% | 269 3.51% 99.32% | 34 0.44% 99.76% | 10 0.13% 99.90% | 4 0.05% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 7658 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6188 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6188 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 60.738776 -system.ruby.miss_latency_hist::gmean 54.828482 -system.ruby.miss_latency_hist::stdev 34.263958 -system.ruby.miss_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1470 -system.ruby.Directory.incomplete_times 1469 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.mem_ctrls.avgWrQLen 25.24 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 618 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 892 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 66.52 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.49 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 39.30 # Average gap between requests +system.mem_ctrls.pageHitRate 79.31 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1684800 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1327104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54116712 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 18087600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 83206296 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 761.516108 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 29701 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 76066 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 2079000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1155000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 9372480 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 74259144 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 418800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102397992 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 937.161297 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 278 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 105360 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.354538 -system.ruby.network.routers0.msg_count.Control::2 1470 -system.ruby.network.routers0.msg_count.Data::2 1466 -system.ruby.network.routers0.msg_count.Response_Data::4 1470 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers0.msg_bytes.Control::2 11760 -system.ruby.network.routers0.msg_bytes.Data::2 105552 -system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers1.percent_links_utilized 6.354538 -system.ruby.network.routers1.msg_count.Control::2 1470 -system.ruby.network.routers1.msg_count.Data::2 1466 -system.ruby.network.routers1.msg_count.Response_Data::4 1470 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers1.msg_bytes.Control::2 11760 -system.ruby.network.routers1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 6.354538 -system.ruby.network.routers2.msg_count.Control::2 1470 -system.ruby.network.routers2.msg_count.Data::2 1466 -system.ruby.network.routers2.msg_count.Response_Data::4 1470 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers2.msg_bytes.Control::2 11760 -system.ruby.network.routers2.msg_bytes.Data::2 105552 -system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.msg_count.Control 4410 -system.ruby.network.msg_count.Data 4398 -system.ruby.network.msg_count.Response_Data 4410 -system.ruby.network.msg_count.Writeback_Control 4398 -system.ruby.network.msg_byte.Control 35280 -system.ruby.network.msg_byte.Data 316656 -system.ruby.network.msg_byte.Response_Data 317520 -system.ruby.network.msg_byte.Writeback_Control 35184 system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -359,7 +288,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 115508 # number of cpu cycles simulated +system.cpu.numCycles 115467 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -378,7 +307,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 115508 # Number of busy cycles +system.cpu.num_busy_cycles 115467 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -417,32 +346,108 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 6.361464 +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 2936 # delay histogram for all message +system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 2936 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 7659 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 7659 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 7658 +system.ruby.latency_hist::mean 14.077958 +system.ruby.latency_hist::gmean 5.242569 +system.ruby.latency_hist::stdev 26.858459 +system.ruby.latency_hist | 7322 95.61% 95.61% | 283 3.70% 99.31% | 37 0.48% 99.79% | 6 0.08% 99.87% | 9 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 7658 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 6188 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6188 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1470 +system.ruby.miss_latency_hist::mean 60.710884 +system.ruby.miss_latency_hist::gmean 54.957755 +system.ruby.miss_latency_hist::stdev 32.665540 +system.ruby.miss_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1470 +system.ruby.Directory.incomplete_times 1469 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.356795 +system.ruby.network.routers0.msg_count.Control::2 1470 +system.ruby.network.routers0.msg_count.Data::2 1466 +system.ruby.network.routers0.msg_count.Response_Data::4 1470 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers0.msg_bytes.Control::2 11760 +system.ruby.network.routers0.msg_bytes.Data::2 105552 +system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers1.percent_links_utilized 6.356795 +system.ruby.network.routers1.msg_count.Control::2 1470 +system.ruby.network.routers1.msg_count.Data::2 1466 +system.ruby.network.routers1.msg_count.Response_Data::4 1470 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers1.msg_bytes.Control::2 11760 +system.ruby.network.routers1.msg_bytes.Data::2 105552 +system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers2.percent_links_utilized 6.356795 +system.ruby.network.routers2.msg_count.Control::2 1470 +system.ruby.network.routers2.msg_count.Data::2 1466 +system.ruby.network.routers2.msg_count.Response_Data::4 1470 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers2.msg_bytes.Control::2 11760 +system.ruby.network.routers2.msg_bytes.Data::2 105552 +system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.msg_count.Control 4410 +system.ruby.network.msg_count.Data 4398 +system.ruby.network.msg_count.Response_Data 4410 +system.ruby.network.msg_count.Writeback_Control 4398 +system.ruby.network.msg_byte.Control 35280 +system.ruby.network.msg_byte.Data 316656 +system.ruby.network.msg_byte.Response_Data 317520 +system.ruby.network.msg_byte.Writeback_Control 35184 +system.ruby.network.routers0.throttle0.link_utilization 6.363723 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 6.347612 +system.ruby.network.routers0.throttle1.link_utilization 6.349866 system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 6.347612 +system.ruby.network.routers1.throttle0.link_utilization 6.349866 system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 6.361464 +system.ruby.network.routers1.throttle1.link_utilization 6.363723 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 6.361464 +system.ruby.network.routers2.throttle0.link_utilization 6.363723 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 6.347612 +system.ruby.network.routers2.throttle1.link_utilization 6.349866 system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 @@ -457,13 +462,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 +system.ruby.LD.latency_hist::bucket_size 32 +system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 35.522968 -system.ruby.LD.latency_hist::gmean 16.130611 -system.ruby.LD.latency_hist::stdev 37.257775 -system.ruby.LD.latency_hist | 989 87.37% 87.37% | 116 10.25% 97.61% | 20 1.77% 99.38% | 4 0.35% 99.73% | 2 0.18% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 35.492049 +system.ruby.LD.latency_hist::gmean 16.147834 +system.ruby.LD.latency_hist::stdev 37.303839 +system.ruby.LD.latency_hist | 465 41.08% 41.08% | 518 45.76% 86.84% | 124 10.95% 97.79% | 3 0.27% 98.06% | 3 0.27% 98.32% | 12 1.06% 99.38% | 2 0.18% 99.56% | 0 0.00% 99.56% | 3 0.27% 99.82% | 2 0.18% 100.00% system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -472,21 +477,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 +system.ruby.LD.miss_latency_hist::bucket_size 32 +system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 58.196402 -system.ruby.LD.miss_latency_hist::gmean 52.112336 -system.ruby.LD.miss_latency_hist::stdev 33.226027 -system.ruby.LD.miss_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 58.143928 +system.ruby.LD.miss_latency_hist::gmean 52.206801 +system.ruby.LD.miss_latency_hist::stdev 33.349415 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% system.ruby.LD.miss_latency_hist::total 667 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 +system.ruby.ST.latency_hist::bucket_size 32 +system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 15.558269 -system.ruby.ST.latency_hist::gmean 5.883337 -system.ruby.ST.latency_hist::stdev 27.738104 -system.ruby.ST.latency_hist | 860 95.45% 95.45% | 33 3.66% 99.11% | 6 0.67% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 14.748058 +system.ruby.ST.latency_hist::gmean 5.824702 +system.ruby.ST.latency_hist::stdev 24.783906 +system.ruby.ST.latency_hist | 684 75.92% 75.92% | 183 20.31% 96.23% | 29 3.22% 99.45% | 0 0.00% 99.45% | 2 0.22% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -495,21 +500,21 @@ system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 684 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 +system.ruby.ST.miss_latency_hist::bucket_size 32 +system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 55.142857 -system.ruby.ST.miss_latency_hist::gmean 49.160125 -system.ruby.ST.miss_latency_hist::stdev 33.648687 -system.ruby.ST.miss_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 51.778802 +system.ruby.ST.miss_latency_hist::gmean 47.157588 +system.ruby.ST.miss_latency_hist::stdev 27.288529 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 217 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 9.532444 -system.ruby.IFETCH.latency_hist::gmean 4.102291 -system.ruby.IFETCH.latency_hist::stdev 22.246367 -system.ruby.IFETCH.latency_hist | 5488 97.56% 97.56% | 120 2.13% 99.70% | 8 0.14% 99.84% | 5 0.09% 99.93% | 2 0.04% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.661156 +system.ruby.IFETCH.latency_hist::gmean 4.110524 +system.ruby.IFETCH.latency_hist::stdev 22.183687 +system.ruby.IFETCH.latency_hist | 5472 97.28% 97.28% | 127 2.26% 99.54% | 18 0.32% 99.86% | 4 0.07% 99.93% | 3 0.05% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -521,18 +526,18 @@ system.ruby.IFETCH.hit_latency_hist::total 5039 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 65.704778 -system.ruby.IFETCH.miss_latency_hist::gmean 60.488386 -system.ruby.IFETCH.miss_latency_hist::stdev 35.064530 -system.ruby.IFETCH.miss_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 66.940273 +system.ruby.IFETCH.miss_latency_hist::gmean 61.663848 +system.ruby.IFETCH.miss_latency_hist::stdev 32.593558 +system.ruby.IFETCH.miss_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 586 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 60.738776 -system.ruby.Directory.miss_mach_latency_hist::gmean 54.828482 -system.ruby.Directory.miss_mach_latency_hist::stdev 34.263958 -system.ruby.Directory.miss_mach_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 60.710884 +system.ruby.Directory.miss_mach_latency_hist::gmean 54.957755 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.665540 +system.ruby.Directory.miss_mach_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -560,30 +565,38 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.196402 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.112336 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.226027 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.143928 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.206801 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.349415 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.142857 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.160125 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.648687 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.778802 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.157588 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.288529 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.704778 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 60.488386 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.064530 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.940273 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.663848 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.593558 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 +system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00% system.ruby.L1Cache_Controller.Store 901 0.00% 0.00% @@ -600,13 +613,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index b652069ee..e81ca8aaa 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18857500 # Number of ticks simulated final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71546 # Simulator instruction rate (inst/s) -host_op_rate 71536 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232873039 # Simulator tick rate (ticks/s) -host_mem_usage 233800 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 101158 # Simulator instruction rate (inst/s) +host_op_rate 101133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 329193143 # Simulator tick rate (ticks/s) +host_mem_usage 288984 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 80.18 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 42171.17 # Average gap between requests system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 476280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 68040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 259875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 37125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2644200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 288600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 8055810 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2433000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 15222495 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 11899695 # Total energy per rank (pJ) -system.physmem.averagePower::0 961.471341 # Core power per rank (mW) -system.physmem.averagePower::1 751.599242 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 397 # Transaction distribution -system.membus.trans_dist::ReadResp 397 # Transaction distribution -system.membus.trans_dist::ReadExReq 47 # Transaction distribution -system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 444 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 476280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 259875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2644200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15222495 # Total energy per rank (pJ) +system.physmem_0.averagePower 961.471341 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8055810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2433000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11899695 # Total energy per rank (pJ) +system.physmem_1.averagePower 751.599242 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4725250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 11341250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2332 # Number of BP lookups system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -589,34 +571,118 @@ system.cpu.int_regfile_reads 13744 # nu system.cpu.int_regfile_writes 7176 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits +system.cpu.dcache.overall_hits::total 2261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses +system.cpu.dcache.overall_misses::total 452 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. @@ -841,117 +907,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits -system.cpu.dcache.overall_hits::total 2261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses -system.cpu.dcache.overall_misses::total 452 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 397 # Transaction distribution +system.membus.trans_dist::ReadResp 397 # Transaction distribution +system.membus.trans_dist::ReadExReq 47 # Transaction distribution +system.membus.trans_dist::ReadExResp 47 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 444 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 444 # Request fanout histogram +system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 951c5abaa..33e0e9c43 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20927500 # Number of ticks simulated final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61359 # Simulator instruction rate (inst/s) -host_op_rate 61351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 240990471 # Simulator tick rate (ticks/s) -host_mem_usage 234980 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 82286 # Simulator instruction rate (inst/s) +host_op_rate 82268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 323129777 # Simulator tick rate (ticks/s) +host_mem_usage 289972 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,53 +220,34 @@ system.physmem.readRowHitRate 80.14 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 49309.69 # Average gap between requests system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 13500 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15312750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 196560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 107250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1497600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1107600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10702035 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10576350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 111750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 222000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13784220 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13226880 # Total energy per rank (pJ) -system.physmem.averagePower::0 870.628138 # Core power per rank (mW) -system.physmem.averagePower::1 835.425865 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 342 # Transaction distribution -system.membus.trans_dist::ReadResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 423 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 423 # Request fanout histogram -system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1497600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10702035 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 111750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13784220 # Total energy per rank (pJ) +system.physmem_0.averagePower 870.628138 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 116500 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15209750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 196560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 107250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1107600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10576350 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 222000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13226880 # Total energy per rank (pJ) +system.physmem_1.averagePower 835.425865 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 328000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14998250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -276,6 +257,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 41856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -337,6 +319,118 @@ system.cpu.stage3.utilization 2.329415 # Pe system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits +system.cpu.dcache.overall_hits::total 914 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. @@ -427,34 +521,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 70926.116838 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 169.161112 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. @@ -589,117 +655,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57807.958478 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits -system.cpu.dcache.overall_hits::total 914 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 342 # Transaction distribution +system.membus.trans_dist::ReadResp 342 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 423 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 423 # Request fanout histogram +system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 0a40cf084..51b100b5f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000096 # Number of seconds simulated -sim_ticks 95992 # Number of ticks simulated -final_tick 95992 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 95989 # Number of ticks simulated +final_tick 95989 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28429 # Simulator instruction rate (inst/s) -host_op_rate 28426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 512186 # Simulator tick rate (ticks/s) -host_mem_usage 435856 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 73101 # Simulator instruction rate (inst/s) +host_op_rate 73087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1316740 # Simulator tick rate (ticks/s) +host_mem_usage 448980 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,12 +21,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 859404950 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 859404950 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 856738062 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 856738062 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716143012 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1716143012 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 859431810 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 859431810 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 856764838 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 856764838 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716196648 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1716196648 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1289 # Number of read requests accepted system.mem_ctrls.writeReqs 1285 # Number of write requests accepted system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue @@ -73,7 +73,7 @@ system.mem_ctrls.perBankWrBursts::14 18 # Pe system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 95928 # Total gap between requests +system.mem_ctrls.totGap 95925 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -217,16 +217,16 @@ system.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Wr system.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8746 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22027 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 8743 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 22024 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers system.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 466.04 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 472.04 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 859.40 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 856.74 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgRdBW 466.05 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 472.05 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 859.43 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 856.76 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads @@ -239,29 +239,94 @@ system.mem_ctrls.readRowHitRate 70.96 # Ro system.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes system.mem_ctrls.avgGap 37.27 # Average gap between requests system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 3037 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 87552 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 672840 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 373800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5229120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 3257280 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 4271616 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 2716416 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 59194044 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 56254896 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 4292400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 6870600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 80701020 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 76248552 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 861.316185 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 813.795315 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1035720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 575400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4271616 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 59194044 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 4292400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 80701020 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 861.316185 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 6799 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 83841 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 672840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 373800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 3257280 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2716416 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 56250108 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 6873000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 76246164 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 813.795884 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 11133 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 79453 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 95989 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5327 # Number of instructions committed +system.cpu.committedOps 5327 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 146 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls +system.cpu.num_int_insts 4505 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 10598 # number of times the integer registers were read +system.cpu.num_int_register_writes 4845 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 1401 # number of memory refs +system.cpu.num_load_insts 723 # Number of load instructions +system.cpu.num_store_insts 678 # Number of store instructions +system.cpu.num_idle_cycles 0.999990 # Number of idle cycles +system.cpu.num_busy_cycles 95988.000010 # Number of busy cycles +system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000010 # Percentage of idle cycles +system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -278,9 +343,9 @@ system.ruby.outstanding_req_hist::total 6759 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 6758 -system.ruby.latency_hist::mean 13.204202 -system.ruby.latency_hist::gmean 5.149414 -system.ruby.latency_hist::stdev 25.350800 +system.ruby.latency_hist::mean 13.203759 +system.ruby.latency_hist::gmean 5.149407 +system.ruby.latency_hist::stdev 25.345890 system.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 6758 system.ruby.hit_latency_hist::bucket_size 1 @@ -293,18 +358,17 @@ system.ruby.hit_latency_hist::total 5469 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1289 -system.ruby.miss_latency_hist::mean 56.498836 -system.ruby.miss_latency_hist::gmean 50.965885 -system.ruby.miss_latency_hist::stdev 32.457285 +system.ruby.miss_latency_hist::mean 56.496509 +system.ruby.miss_latency_hist::gmean 50.965481 +system.ruby.miss_latency_hist::stdev 32.440273 system.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1289 system.ruby.Directory.incomplete_times 1288 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.703684 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.703893 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 system.ruby.network.routers0.msg_count.Response_Data::4 1289 @@ -313,7 +377,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.percent_links_utilized 6.703684 +system.ruby.network.routers1.percent_links_utilized 6.703893 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 system.ruby.network.routers1.msg_count.Response_Data::4 1289 @@ -322,7 +386,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.percent_links_utilized 6.703684 +system.ruby.network.routers2.percent_links_utilized 6.703893 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 system.ruby.network.routers2.msg_count.Response_Data::4 1289 @@ -339,91 +403,32 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 95992 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.999990 # Number of idle cycles -system.cpu.num_busy_cycles 95991.000010 # Number of busy cycles -system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000010 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 6.712018 +system.ruby.network.routers0.throttle0.link_utilization 6.712227 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers0.throttle1.link_utilization 6.695350 +system.ruby.network.routers0.throttle1.link_utilization 6.695559 system.ruby.network.routers0.throttle1.msg_count.Control::2 1289 system.ruby.network.routers0.throttle1.msg_count.Data::2 1285 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle0.link_utilization 6.695350 +system.ruby.network.routers1.throttle0.link_utilization 6.695559 system.ruby.network.routers1.throttle0.msg_count.Control::2 1289 system.ruby.network.routers1.throttle0.msg_count.Data::2 1285 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle1.link_utilization 6.712018 +system.ruby.network.routers1.throttle1.link_utilization 6.712227 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle0.link_utilization 6.712018 +system.ruby.network.routers2.throttle0.link_utilization 6.712227 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle1.link_utilization 6.695350 +system.ruby.network.routers2.throttle1.link_utilization 6.695559 system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 @@ -441,9 +446,9 @@ system.ruby.delayVCHist.vnet_2::total 1285 # de system.ruby.LD.latency_hist::bucket_size 32 system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 715 -system.ruby.LD.latency_hist::mean 30.928671 -system.ruby.LD.latency_hist::gmean 13.876476 -system.ruby.LD.latency_hist::stdev 34.808507 +system.ruby.LD.latency_hist::mean 30.924476 +system.ruby.LD.latency_hist::gmean 13.876278 +system.ruby.LD.latency_hist::stdev 34.776798 system.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00% system.ruby.LD.latency_hist::total 715 system.ruby.LD.hit_latency_hist::bucket_size 1 @@ -456,9 +461,9 @@ system.ruby.LD.hit_latency_hist::total 320 system.ruby.LD.miss_latency_hist::bucket_size 32 system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 395 -system.ruby.LD.miss_latency_hist::mean 53.554430 -system.ruby.LD.miss_latency_hist::gmean 47.988958 -system.ruby.LD.miss_latency_hist::stdev 32.387704 +system.ruby.LD.miss_latency_hist::mean 53.546835 +system.ruby.LD.miss_latency_hist::gmean 47.987716 +system.ruby.LD.miss_latency_hist::stdev 32.331244 system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% system.ruby.LD.miss_latency_hist::total 395 system.ruby.ST.latency_hist::bucket_size 32 @@ -510,9 +515,9 @@ system.ruby.IFETCH.miss_latency_hist::total 715 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1289 -system.ruby.Directory.miss_mach_latency_hist::mean 56.498836 -system.ruby.Directory.miss_mach_latency_hist::gmean 50.965885 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.457285 +system.ruby.Directory.miss_mach_latency_hist::mean 56.496509 +system.ruby.Directory.miss_mach_latency_hist::gmean 50.965481 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.440273 system.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1289 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -544,9 +549,9 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.554430 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.988958 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.387704 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.546835 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.987716 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.331244 system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 @@ -565,6 +570,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 +system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% system.ruby.L1Cache_Controller.Load 715 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00% system.ruby.L1Cache_Controller.Store 673 0.00% 0.00% @@ -581,13 +594,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1285 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1285 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1110 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 179 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 83799ecfd..3b4d7b677 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19678000 # Number of ticks simulated final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30596 # Simulator instruction rate (inst/s) -host_op_rate 55428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111894824 # Simulator tick rate (ticks/s) -host_mem_usage 253080 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 46918 # Simulator instruction rate (inst/s) +host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171550123 # Simulator tick rate (ticks/s) +host_mem_usage 309548 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,55 +220,34 @@ system.physmem.readRowHitRate 74.10 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 47073.14 # Average gap between requests system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15318250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 219240 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 446040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 119625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 243375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1084200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1567800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10796085 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10703745 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 112500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13267770 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14090580 # Total energy per rank (pJ) -system.physmem.averagePower::0 837.810088 # Core power per rank (mW) -system.physmem.averagePower::1 889.767464 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 339 # Transaction distribution -system.membus.trans_dist::ReadResp 338 # Transaction distribution -system.membus.trans_dist::ReadExReq 78 # Transaction distribution -system.membus.trans_dist::ReadExResp 78 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 417 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) +system.physmem_0.averagePower 837.810088 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) +system.physmem_1.averagePower 889.816201 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 3423 # Number of BP lookups system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect @@ -278,6 +257,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 39357 # number of cpu cycles simulated @@ -572,36 +552,116 @@ system.cpu.cc_regfile_reads 8069 # nu system.cpu.cc_regfile_writes 5036 # number of cc regfile writes system.cpu.misc_regfile_reads 7491 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits +system.cpu.dcache.overall_hits::total 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses +system.cpu.dcache.overall_misses::total 214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. @@ -823,115 +883,60 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 339 # Transaction distribution +system.membus.trans_dist::ReadResp 338 # Transaction distribution +system.membus.trans_dist::ReadExReq 78 # Transaction distribution +system.membus.trans_dist::ReadExResp 78 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 417 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 417 # Request fanout histogram +system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index f27f9e229..6ad7b9146 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107237 # Number of ticks simulated final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14917 # Simulator instruction rate (inst/s) -host_op_rate 27022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 297251 # Simulator tick rate (ticks/s) -host_mem_usage 452416 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 59170 # Simulator instruction rate (inst/s) +host_op_rate 107175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1178869 # Simulator tick rate (ticks/s) +host_mem_usage 466480 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,29 +238,97 @@ system.mem_ctrls.readRowHitRate 64.11 # Ro system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.96 # Average gap between requests system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 6647 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 91465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 695520 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1270080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 386400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 705600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 3219840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 4605120 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2623104 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 3784320 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 57894444 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 62913636 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 10102200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 5699400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 81532788 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 85589436 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 803.452847 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 843.428487 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3219840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 57895812 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10101000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 81532956 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 803.454502 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 16443 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 81669 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1270080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 705600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4605120 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3784320 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 62916372 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5697000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 85589772 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 843.431798 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 89065 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.apic_clk_domain.clock 16 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 107237 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5381 # Number of instructions committed +system.cpu.committedOps 9748 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 209 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls +system.cpu.num_int_insts 9654 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 18335 # number of times the integer registers were read +system.cpu.num_int_register_writes 7527 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written +system.cpu.num_mem_refs 1988 # number of memory refs +system.cpu.num_load_insts 1053 # Number of load instructions +system.cpu.num_store_insts 935 # Number of store instructions +system.cpu.num_idle_cycles 0.999991 # Number of idle cycles +system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles +system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000009 # Percentage of idle cycles +system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -278,8 +346,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8852 system.ruby.latency_hist::mean 11.114437 -system.ruby.latency_hist::gmean 4.638311 -system.ruby.latency_hist::stdev 22.978637 +system.ruby.latency_hist::gmean 4.638310 +system.ruby.latency_hist::stdev 22.979355 system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8852 system.ruby.hit_latency_hist::bucket_size 1 @@ -293,16 +361,15 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1377 system.ruby.miss_latency_hist::mean 55.163399 -system.ruby.miss_latency_hist::gmean 49.389613 -system.ruby.miss_latency_hist::stdev 33.121212 +system.ruby.miss_latency_hist::gmean 49.389540 +system.ruby.miss_latency_hist::stdev 33.124416 system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 6.411034 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -338,68 +405,6 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 107237 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999991 # Number of idle cycles -system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles -system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000009 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.418494 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -490,8 +495,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6864 system.ruby.IFETCH.latency_hist::mean 8.263112 -system.ruby.IFETCH.latency_hist::gmean 3.900454 -system.ruby.IFETCH.latency_hist::stdev 20.208626 +system.ruby.IFETCH.latency_hist::gmean 3.900453 +system.ruby.IFETCH.latency_hist::stdev 20.209679 system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6864 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -505,8 +510,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 623 system.ruby.IFETCH.miss_latency_hist::mean 60.987159 -system.ruby.IFETCH.miss_latency_hist::gmean 54.083768 -system.ruby.IFETCH.miss_latency_hist::stdev 37.997755 +system.ruby.IFETCH.miss_latency_hist::gmean 54.083593 +system.ruby.IFETCH.miss_latency_hist::stdev 38.003932 system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 623 system.ruby.RMW_Read.latency_hist::bucket_size 4 @@ -536,8 +541,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1377 system.ruby.Directory.miss_mach_latency_hist::mean 55.163399 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.389613 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.121212 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.389540 +system.ruby.Directory.miss_mach_latency_hist::stdev 33.124416 system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1377 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -586,8 +591,8 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083768 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.997755 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083593 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 38.003932 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 @@ -598,6 +603,14 @@ system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 +system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% system.ruby.L1Cache_Controller.Store 943 0.00% 0.00% @@ -614,13 +627,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 390228fe9..752a25834 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23061500 # Number of ticks simulated -final_tick 23061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 23754500 # Number of ticks simulated +final_tick 23754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45645 # Simulator instruction rate (inst/s) -host_op_rate 45641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82586308 # Simulator tick rate (ticks/s) -host_mem_usage 237816 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 70868 # Simulator instruction rate (inst/s) +host_op_rate 70863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132078042 # Simulator tick rate (ticks/s) +host_mem_usage 294344 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22080 # Number of bytes read from this memory -system.physmem.bytes_read::total 62656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40576 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 634 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 345 # Number of read requests responded to by this memory -system.physmem.num_reads::total 979 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1759469245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 957439889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2716909134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1759469245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1759469245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1759469245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 957439889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2716909134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 979 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22336 # Number of bytes read from this memory +system.physmem.bytes_read::total 62400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40064 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 626 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 349 # Number of read requests responded to by this memory +system.physmem.num_reads::total 975 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1686585700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 940284999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2626870698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1686585700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1686585700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1686585700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 940284999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2626870698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 975 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 979 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62656 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62656 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 84 # Per bank write bursts +system.physmem.perBankRdBursts::0 83 # Per bank write bursts system.physmem.perBankRdBursts::1 151 # Per bank write bursts system.physmem.perBankRdBursts::2 78 # Per bank write bursts system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 89 # Per bank write bursts -system.physmem.perBankRdBursts::5 50 # Per bank write bursts -system.physmem.perBankRdBursts::6 33 # Per bank write bursts -system.physmem.perBankRdBursts::7 51 # Per bank write bursts -system.physmem.perBankRdBursts::8 42 # Per bank write bursts -system.physmem.perBankRdBursts::9 39 # Per bank write bursts -system.physmem.perBankRdBursts::10 29 # Per bank write bursts +system.physmem.perBankRdBursts::4 88 # Per bank write bursts +system.physmem.perBankRdBursts::5 49 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 49 # Per bank write bursts +system.physmem.perBankRdBursts::8 41 # Per bank write bursts +system.physmem.perBankRdBursts::9 38 # Per bank write bursts +system.physmem.perBankRdBursts::10 30 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 120 # Per bank write bursts -system.physmem.perBankRdBursts::14 69 # Per bank write bursts +system.physmem.perBankRdBursts::13 122 # Per bank write bursts +system.physmem.perBankRdBursts::14 70 # Per bank write bursts system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22909000 # Total gap between requests +system.physmem.totGap 23342000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 979 # Read request sizes (log2) +system.physmem.readPktSize::6 975 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,118 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.772581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 289.019279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 62 31.63% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 59 30.10% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 22 11.22% 72.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 4.08% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15 7.65% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9 4.59% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 2.04% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 2.04% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13 6.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 196 # Bytes accessed per row activation -system.physmem.totQLat 11811000 # Total ticks spent queuing -system.physmem.totMemAccLat 30167250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4895000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12064.35 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.431280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.087836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.004628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 56 26.54% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25 11.85% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14 6.64% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15 7.11% 84.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9 4.27% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.90% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.84% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13 6.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation +system.physmem.totQLat 12504500 # Total ticks spent queuing +system.physmem.totMemAccLat 30785750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12825.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30814.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2716.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31575.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2626.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2716.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2626.87 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 21.23 # Data bus utilization in percentage -system.physmem.busUtilRead 21.23 # Data bus utilization in percentage for reads +system.physmem.busUtil 20.52 # Data bus utilization in percentage +system.physmem.busUtilRead 20.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 767 # Number of row buffer hits during reads +system.physmem.readRowHits 763 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.35 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23400.41 # Average gap between requests -system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 25750 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15300500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 710640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 438480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 387750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 239250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3798600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1747200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10760175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10602000 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 60750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 199500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 16735035 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14243550 # Total energy per rank (pJ) -system.physmem.averagePower::0 1057.005211 # Core power per rank (mW) -system.physmem.averagePower::1 899.639981 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 833 # Transaction distribution -system.membus.trans_dist::ReadResp 833 # Transaction distribution -system.membus.trans_dist::ReadExReq 146 # Transaction distribution -system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1958 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1958 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 979 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 979 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 979 # Request fanout histogram -system.membus.reqLayer0.occupancy 1210000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 9085500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 39.4 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 6891 # Number of BP lookups -system.cpu.branchPred.condPredicted 3900 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1379 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5156 # Number of BTB lookups -system.cpu.branchPred.BTBHits 960 # Number of BTB hits +system.physmem.avgGap 23940.51 # Average gap between requests +system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4578600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16058610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 84750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 23638155 # Total energy per rank (pJ) +system.physmem_0.averagePower 1000.821593 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 44000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22808500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 695520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 379500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3018600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 15908130 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 216750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21744180 # Total energy per rank (pJ) +system.physmem_1.averagePower 920.632125 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 278750 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22573750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 7608 # Number of BP lookups +system.cpu.branchPred.condPredicted 4258 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1618 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5646 # Number of BTB lookups +system.cpu.branchPred.BTBHits 865 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.619085 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 963 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 15.320581 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1051 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4694 # DTB read hits -system.cpu.dtb.read_misses 106 # DTB read misses +system.cpu.dtb.read_hits 5192 # DTB read hits +system.cpu.dtb.read_misses 102 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4800 # DTB read accesses -system.cpu.dtb.write_hits 2103 # DTB write hits -system.cpu.dtb.write_misses 62 # DTB write misses +system.cpu.dtb.read_accesses 5294 # DTB read accesses +system.cpu.dtb.write_hits 2108 # DTB write hits +system.cpu.dtb.write_misses 66 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2165 # DTB write accesses -system.cpu.dtb.data_hits 6797 # DTB hits +system.cpu.dtb.write_accesses 2174 # DTB write accesses +system.cpu.dtb.data_hits 7300 # DTB hits system.cpu.dtb.data_misses 168 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6965 # DTB accesses -system.cpu.itb.fetch_hits 5123 # ITB hits -system.cpu.itb.fetch_misses 59 # ITB misses +system.cpu.dtb.data_accesses 7468 # DTB accesses +system.cpu.itb.fetch_hits 5663 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5182 # ITB accesses +system.cpu.itb.fetch_accesses 5720 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -312,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 46124 # number of cpu cycles simulated +system.cpu.numCycles 47510 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 38336 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6891 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1923 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10750 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1460 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5123 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 789 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 27999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.369192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.769631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1451 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 41889 # Number of instructions fetch has processed +system.cpu.fetch.Branches 7608 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1916 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 11137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1697 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5663 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 846 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.466188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.843743 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21530 76.90% 76.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 534 1.91% 78.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 415 1.48% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 507 1.81% 82.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 495 1.77% 83.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 425 1.52% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 487 1.74% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 424 1.51% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3182 11.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21551 75.43% 75.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 541 1.89% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 402 1.41% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 607 2.12% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 545 1.91% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 439 1.54% 84.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 542 1.90% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 448 1.57% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3495 12.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 27999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.149402 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.831151 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37351 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11762 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 4916 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 633 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1095 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 569 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 385 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 31322 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 859 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1095 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37970 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4830 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1235 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4957 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5670 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 29386 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 318 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 603 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4545 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 22134 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 36672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 36654 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.160135 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.881688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37575 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12018 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5449 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 625 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1245 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 719 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33794 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 947 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1245 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38261 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5449 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1170 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5378 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5409 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 31549 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 73 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 407 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 458 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4425 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 23766 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 39316 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 39298 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12994 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 62 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2157 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2815 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1467 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2781 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1339 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 14626 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 56 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2199 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3120 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1520 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2933 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1394 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26455 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 22074 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12913 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7569 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 27999 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.788385 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505249 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 28021 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 23357 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14239 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28570 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.817536 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.542788 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19729 70.46% 70.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2607 9.31% 79.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1874 6.69% 86.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1399 5.00% 91.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1239 4.43% 95.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 603 2.15% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 335 1.20% 99.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 163 0.58% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 50 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19963 69.87% 69.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2657 9.30% 79.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1959 6.86% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1384 4.84% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1325 4.64% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 682 2.39% 97.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 348 1.22% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 184 0.64% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 68 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 27999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28570 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 17 5.72% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 196 65.99% 71.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 84 28.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 22 6.04% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 263 72.25% 78.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79 21.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7289 65.97% 65.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2595 23.49% 89.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1160 10.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7749 65.04% 65.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2973 24.95% 90.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1188 9.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11049 # Type of FU issued +system.cpu.iq.FU_type_0::total 11915 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7322 66.41% 66.43% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.44% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2566 23.27% 89.73% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1132 10.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7559 66.06% 66.08% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.09% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2735 23.90% 90.01% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1143 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11025 # Type of FU issued -system.cpu.iq.FU_type::total 22074 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.478579 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 149 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 297 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.006750 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.006705 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.013455 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 72475 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 39437 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19551 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11442 # Type of FU issued +system.cpu.iq.FU_type::total 23357 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.491623 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 183 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 181 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 364 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.007835 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007749 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.015584 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75737 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 42325 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22345 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 23695 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1937 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 655 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 78 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 426 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1598 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 474 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1750 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 529 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 263 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 346 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1095 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 391 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 26654 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 299 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5596 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2806 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 359 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 141 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1219 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20887 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2420 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2389 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4809 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1245 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2860 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 601 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 28216 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 318 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6053 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2914 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 571 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 148 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1270 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1418 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 21922 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2766 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2537 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 5303 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1435 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 73 # number of nop insts executed +system.cpu.iew.exec_nop::0 71 # number of nop insts executed system.cpu.iew.exec_nop::1 73 # number of nop insts executed -system.cpu.iew.exec_nop::total 146 # number of nop insts executed -system.cpu.iew.exec_refs::0 3521 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3470 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6991 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1644 # Number of branches executed -system.cpu.iew.exec_branches::1 1667 # Number of branches executed -system.cpu.iew.exec_branches::total 3311 # Number of branches executed -system.cpu.iew.exec_stores::0 1101 # Number of stores executed -system.cpu.iew.exec_stores::1 1081 # Number of stores executed -system.cpu.iew.exec_stores::total 2182 # Number of stores executed -system.cpu.iew.exec_rate 0.452845 # Inst execution rate -system.cpu.iew.wb_sent::0 9956 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9970 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19926 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9780 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9791 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19571 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5173 # num instructions producing a value -system.cpu.iew.wb_producers::1 5150 # num instructions producing a value -system.cpu.iew.wb_producers::total 10323 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6916 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6837 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13753 # num instructions consuming a value +system.cpu.iew.exec_nop::total 144 # number of nop insts executed +system.cpu.iew.exec_refs::0 3883 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3616 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7499 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1763 # Number of branches executed +system.cpu.iew.exec_branches::1 1733 # Number of branches executed +system.cpu.iew.exec_branches::total 3496 # Number of branches executed +system.cpu.iew.exec_stores::0 1117 # Number of stores executed +system.cpu.iew.exec_stores::1 1079 # Number of stores executed +system.cpu.iew.exec_stores::total 2196 # Number of stores executed +system.cpu.iew.exec_rate 0.461419 # Inst execution rate +system.cpu.iew.wb_sent::0 10477 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 10192 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 20669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 10260 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 10004 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 20264 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5390 # num instructions producing a value +system.cpu.iew.wb_producers::1 5243 # num instructions producing a value +system.cpu.iew.wb_producers::total 10633 # num instructions producing a value +system.cpu.iew.wb_consumers::0 7128 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6992 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 14120 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.212037 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.212276 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.424313 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.747976 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.753254 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.750600 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.215955 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.210566 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.426521 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.756173 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.749857 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.753045 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 13856 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 15441 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1015 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 27930 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.457501 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.335540 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1167 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28457 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.449028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.318063 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22902 82.00% 82.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2402 8.60% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1059 3.79% 94.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 373 1.34% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 324 1.16% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 194 0.69% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 197 0.71% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 141 0.50% 98.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 338 1.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23389 82.19% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2450 8.61% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1057 3.71% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 365 1.28% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 316 1.11% 96.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 193 0.68% 97.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 226 0.79% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 154 0.54% 98.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 307 1.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28457 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12778 # Number of instructions committed @@ -725,232 +707,318 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6389 # Class of committed instruction system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 338 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 307 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 129256 # The number of ROB reads -system.cpu.rob.rob_writes 55848 # The number of ROB writes -system.cpu.timesIdled 409 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18125 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133653 # The number of ROB reads +system.cpu.rob.rob_writes 59305 # The number of ROB writes +system.cpu.timesIdled 412 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18940 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.238544 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.238544 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.619272 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.138149 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.138149 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.276299 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 26325 # number of integer regfile reads -system.cpu.int_regfile_writes 14897 # number of integer regfile writes +system.cpu.cpi::0 7.456058 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.456058 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.728029 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.134119 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.134119 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.268238 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 27427 # number of integer regfile reads +system.cpu.int_regfile_writes 15512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 981 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 981 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 981 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1047000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 4.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 547500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.4 # Layer utilization (%) +system.cpu.dcache.tags.replacements::0 0 # number of replacements +system.cpu.dcache.tags.replacements::1 0 # number of replacements +system.cpu.dcache.tags.replacements::total 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 215.485703 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 5082 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 349 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.561605 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 215.485703 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052609 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052609 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.085205 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 12575 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 12575 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 4060 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 4060 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 5082 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 5082 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 5082 # number of overall hits +system.cpu.dcache.overall_hits::total 5082 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses +system.cpu.dcache.overall_misses::total 1031 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22902750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22902750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 50997162 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 50997162 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 73899912 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 73899912 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 73899912 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 73899912 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 6113 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 6113 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 6113 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 6113 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073694 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073694 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168657 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168657 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168657 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168657 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70906.346749 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70906.346749 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72029.889831 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72029.889831 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71677.897187 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71677.897187 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5816 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.835616 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 682 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 682 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 349 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 349 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16652250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16652250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536240 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28536240 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536240 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28536240 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046543 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046543 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057091 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057091 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81628.676471 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81628.676471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81958.551724 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81958.551724 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 316.469432 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4175 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.564465 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 320.653868 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4726 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.525478 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 316.469432 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.154526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.154526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 629 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.307129 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10870 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10870 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4175 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4175 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4175 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4175 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4175 # number of overall hits -system.cpu.icache.overall_hits::total 4175 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 942 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 942 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 942 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 942 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 942 # number of overall misses -system.cpu.icache.overall_misses::total 942 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64530491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64530491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64530491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64530491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64530491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64530491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5117 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5117 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5117 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5117 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184092 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184092 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184092 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184092 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68503.705945 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68503.705945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68503.705945 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68503.705945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68503.705945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68503.705945 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3163 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 320.653868 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.156569 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.156569 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11936 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11936 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4726 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4726 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4726 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4726 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4726 # number of overall hits +system.cpu.icache.overall_hits::total 4726 # number of overall hits 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blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.051648 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.051648 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.084229 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 11951 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 11951 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits 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MSHR hits -system.cpu.dcache.demand_mshr_hits::total 681 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 681 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 681 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses 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histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 977 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1032000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 4.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 556000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 830 # Transaction distribution +system.membus.trans_dist::ReadResp 830 # Transaction distribution +system.membus.trans_dist::ReadExReq 145 # Transaction distribution +system.membus.trans_dist::ReadExResp 145 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 975 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 975 # Request fanout histogram +system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9051500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 38.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 2e75d917e..766e4c6e5 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27671000 # Number of ticks simulated final_tick 27671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16681 # Simulator instruction rate (inst/s) -host_op_rate 16680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30441710 # Simulator tick rate (ticks/s) -host_mem_usage 234904 # Number of bytes of host memory used -host_seconds 0.91 # Real time elapsed on the host +host_inst_rate 95145 # Simulator instruction rate (inst/s) +host_op_rate 95137 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 173614335 # Simulator tick rate (ticks/s) +host_mem_usage 289900 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -221,53 +221,34 @@ system.physmem.readRowHitRate 83.03 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 63388.76 # Average gap between requests system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1258750 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 21626500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 287280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 204120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 156750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 111375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1786200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1232400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 15269445 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 14648715 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 797250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1341750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 19822605 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 19064040 # Total energy per rank (pJ) -system.physmem.averagePower::0 838.076525 # Core power per rank (mW) -system.physmem.averagePower::1 806.005285 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 351 # Transaction distribution -system.membus.trans_dist::ReadResp 350 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 436 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 436 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 436 # Request fanout histogram -system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.6 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1786200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15269445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 797250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 19822605 # Total energy per rank (pJ) +system.physmem_0.averagePower 838.076525 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1258750 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21626500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 204120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1232400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 14625630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1341750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19040955 # Total energy per rank (pJ) +system.physmem_1.averagePower 806.179624 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4247250 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20686250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect @@ -277,6 +258,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 55343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -338,6 +320,122 @@ system.cpu.stage3.utilization 5.200296 # Pe system.cpu.stage4.idleCycles 46034 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 16.820555 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.529834 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.529834 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024055 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024055 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits +system.cpu.dcache.overall_hits::total 3187 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses +system.cpu.dcache.overall_misses::total 480 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25898250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25898250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30166500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30166500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30166500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30166500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.260664 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.260664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62846.875000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62846.875000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.393939 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6087750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6087750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9837500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9837500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9837500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9837500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71620.588235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71620.588235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 168.877638 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. @@ -428,34 +526,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67971.760797 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67971.760797 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67971.760797 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 439 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 439 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 439 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 500000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 199.907137 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. @@ -587,121 +657,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54914.715719 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.529834 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.529834 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024055 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024055 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits -system.cpu.dcache.overall_hits::total 3187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses -system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25898250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25898250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30166500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30166500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30166500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30166500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.260664 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.260664 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62846.875000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62846.875000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.393939 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6087750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6087750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9837500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9837500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9837500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9837500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71620.588235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71620.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 439 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 439 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 439 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 500000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 222000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution +system.membus.trans_dist::ReadExReq 85 # Transaction distribution +system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 436 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 436 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 436 # Request fanout histogram +system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 9c69b7311..b851aeb29 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25944000 # Number of ticks simulated final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 15615 # Simulator instruction rate (inst/s) -host_op_rate 15615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28062245 # Simulator tick rate (ticks/s) -host_mem_usage 236980 # Number of bytes of host memory used -host_seconds 0.92 # Real time elapsed on the host +host_inst_rate 95549 # Simulator instruction rate (inst/s) +host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171686089 # Simulator tick rate (ticks/s) +host_mem_usage 292480 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 83.54 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 52627.03 # Average gap between requests system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 279250 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22761250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 309960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 226800 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 169125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 123750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2106000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1318200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 16044930 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 14873580 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 96750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1124250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 20252445 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 19192260 # Total energy per rank (pJ) -system.physmem.averagePower::0 857.473194 # Core power per rank (mW) -system.physmem.averagePower::1 812.585763 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 409 # Transaction distribution -system.membus.trans_dist::ReadResp 408 # Transaction distribution -system.membus.trans_dist::ReadExReq 83 # Transaction distribution -system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 492 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 492 # Request fanout histogram -system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.7 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16044930 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20252445 # Total energy per rank (pJ) +system.physmem_0.averagePower 857.473194 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 279250 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22761250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 14873580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19192260 # Total energy per rank (pJ) +system.physmem_1.averagePower 812.585763 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2246250 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21062250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 8578 # Number of BP lookups system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 51889 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -566,34 +548,122 @@ system.cpu.int_regfile_reads 33401 # nu system.cpu.int_regfile_writes 18599 # number of integer regfile writes system.cpu.misc_regfile_reads 7136 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits +system.cpu.dcache.overall_hits::total 4118 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses +system.cpu.dcache.overall_misses::total 548 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. @@ -815,121 +885,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits -system.cpu.dcache.overall_hits::total 4118 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses -system.cpu.dcache.overall_misses::total 548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 409 # Transaction distribution +system.membus.trans_dist::ReadResp 408 # Transaction distribution +system.membus.trans_dist::ReadExReq 83 # Transaction distribution +system.membus.trans_dist::ReadExResp 83 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 492 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 492 # Request fanout histogram +system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 994a2ff39..ffbae61d5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105696000 # Number of ticks simulated -final_tick 105696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 105542000 # Number of ticks simulated +final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145069 # Simulator instruction rate (inst/s) -host_op_rate 145069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15443503 # Simulator tick rate (ticks/s) -host_mem_usage 252160 # Number of bytes of host memory used -host_seconds 6.84 # Real time elapsed on the host -sim_insts 992854 # Number of instructions simulated -sim_ops 992854 # Number of ops (including micro ops) simulated +host_inst_rate 163449 # Simulator instruction rate (inst/s) +host_op_rate 163449 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17392605 # Simulator tick rate (ticks/s) +host_mem_usage 309188 # Number of bytes of host memory used +host_seconds 6.07 # Real time elapsed on the host +sim_insts 991839 # Number of instructions simulated +sim_ops 991839 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 75 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 668 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 218589161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101725704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8477142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7871632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 45413261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 12110203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2422041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7871632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 404480775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 218589161 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8477142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 45413261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2422041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 274901605 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 218589161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101725704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8477142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7871632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 45413261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 12110203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2422041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7871632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 404480775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 669 # Number of read requests accepted +system.physmem.num_reads::total 664 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 665 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 669 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42816 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42816 # Total read bytes from the system interface side +system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 30 # Per bank write bursts +system.physmem.perBankRdBursts::2 27 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts system.physmem.perBankRdBursts::4 65 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts @@ -81,7 +81,7 @@ system.physmem.perBankRdBursts::6 18 # Pe system.physmem.perBankRdBursts::7 24 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts system.physmem.perBankRdBursts::12 65 # Per bank write bursts system.physmem.perBankRdBursts::13 38 # Per bank write bursts @@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 105668000 # Total gap between requests +system.physmem.totGap 105514000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 669 # Read request sizes (log2) +system.physmem.readPktSize::6 665 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,10 +120,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -216,812 +216,319 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.167832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.166692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.214493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42 29.37% 29.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 27.27% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24 16.78% 73.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 9.09% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.20% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.20% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 4.20% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.40% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 143 # Bytes accessed per row activation -system.physmem.totQLat 6392250 # Total ticks spent queuing -system.physmem.totMemAccLat 18936000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9554.93 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation +system.physmem.totQLat 6421750 # Total ticks spent queuing +system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28304.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 405.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 405.09 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 515 # Number of row buffer hits during reads +system.physmem.readRowHits 512 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 157949.18 # Average gap between requests -system.physmem.pageHitRate 76.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 46119750 # Time in different power states -system.physmem.memoryStateTime::REF 3380000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 52590250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 695520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 355320 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 379500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 193875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2776800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2051400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 36176760 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 31269060 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29154750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 33459750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 75794610 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 73940685 # Total energy per rank (pJ) -system.physmem.averagePower::0 746.882897 # Core power per rank (mW) -system.physmem.averagePower::1 728.614251 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 538 # Transaction distribution -system.membus.trans_dist::ReadResp 537 # Transaction distribution -system.membus.trans_dist::UpgradeReq 276 # Transaction distribution -system.membus.trans_dist::UpgradeResp 78 # Transaction distribution -system.membus.trans_dist::ReadExReq 177 # Transaction distribution -system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1737 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 244 # Total snoops (count) -system.membus.snoop_fanout::samples 991 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 991 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 991 # Request fanout histogram -system.membus.reqLayer0.occupancy 940500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 6384422 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 424.241443 # Cycle average of tags in use -system.l2c.tags.total_refs 1667 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 535 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.115888 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.793516 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 289.763968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.233930 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 9.364536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.722908 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 57.054480 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.356180 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.266531 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.685395 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006473 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 535 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008163 # Percentage of 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(read+write) accesses -system.l2c.overall_accesses::total 2348 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.592170 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.034205 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.162272 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.014028 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.248083 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for 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-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.trans_dist::ReadReq 2766 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2765 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 406 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 406 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 353 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5880 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 150272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1022 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3452 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3452 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3452 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1739480 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2819999 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1460516 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2239746 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1188247 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2234243 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1152996 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2246748 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1204495 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) -system.cpu0.branchPred.lookups 81418 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78534 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1187 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78143 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75395 # Number of BTB hits +system.physmem.avgGap 158667.67 # Average gap between requests +system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ) +system.physmem_0.averagePower 738.913691 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states +system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.948851 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states +system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu0.branchPred.lookups 81296 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.483370 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 733 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211393 # number of cpu cycles simulated +system.cpu0.numCycles 211085 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20064 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 481063 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81418 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76128 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 164143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2675 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 658 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 187427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.566669 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.225288 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30149 16.09% 16.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77654 41.43% 57.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823 0.44% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1078 0.58% 58.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 624 0.33% 58.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72980 38.94% 97.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 691 0.37% 98.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 437 0.23% 98.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2991 1.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.385150 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.275681 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15737 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17837 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151841 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 675 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1337 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 469212 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1337 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16355 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2021 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14599 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151852 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1263 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 465757 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 319012 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 928821 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 701999 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 305055 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13957 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 896 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 905 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4572 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148578 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75186 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72446 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72197 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 389771 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 964 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 386457 # Number of instructions issued +system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12213 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11103 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 405 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187427 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.061907 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125198 # Number of insts issued each cycle +system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33106 17.66% 17.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4299 2.29% 19.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73629 39.28% 59.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73187 39.05% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1656 0.88% 99.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 900 0.48% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 407 0.22% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 171 0.09% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 72 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 96 33.92% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 29.68% 63.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 36.40% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163898 42.41% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 148040 38.31% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74519 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 386457 # Type of FU issued -system.cpu0.iq.rate 1.828145 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 283 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000732 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 960647 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 403001 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 384607 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued +system.cpu0.iq.rate 1.826459 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 386740 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71819 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2461 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1337 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1980 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 463607 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148578 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75186 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 843 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 323 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1099 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1422 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 385445 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147736 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72872 # number of nop insts executed -system.cpu0.iew.exec_refs 222117 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76458 # Number of branches executed -system.cpu0.iew.exec_stores 74381 # Number of stores executed -system.cpu0.iew.exec_rate 1.823357 # Inst execution rate -system.cpu0.iew.wb_sent 384977 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 384607 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 228096 # num instructions producing a value -system.cpu0.iew.wb_consumers 231328 # num instructions consuming a value +system.cpu0.iew.exec_nop 72677 # number of nop insts executed +system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76264 # Number of branches executed +system.cpu0.iew.exec_stores 74195 # Number of stores executed +system.cpu0.iew.exec_rate 1.821660 # Inst execution rate +system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 227520 # num instructions producing a value +system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.819393 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986028 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13622 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1187 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 184803 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.434668 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.147538 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33298 18.02% 18.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75556 40.88% 58.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2014 1.09% 59.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 640 0.35% 60.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71511 38.70% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 184803 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 449934 # Number of instructions committed -system.cpu0.commit.committedOps 449934 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 448740 # Number of instructions committed +system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219682 # Number of memory references committed -system.cpu0.commit.loads 146117 # Number of loads committed +system.cpu0.commit.refs 219085 # Number of memory references committed +system.cpu0.commit.loads 145719 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75452 # Number of branches committed +system.cpu0.commit.branches 75253 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303386 # Number of committed integer instructions. +system.cpu0.commit.int_insts 302590 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72184 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157984 35.11% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction @@ -1050,195 +557,104 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146201 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73565 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 449934 # Class of committed instruction -system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction +system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 646710 # The number of ROB reads -system.cpu0.rob.rob_writes 929757 # The number of ROB writes +system.cpu0.rob.rob_reads 645314 # The number of ROB reads +system.cpu0.rob.rob_writes 927635 # The number of ROB writes system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23966 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 377666 # Number of Instructions Simulated -system.cpu0.committedOps 377666 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.559735 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559735 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.786559 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.786559 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 689346 # number of integer regfile reads -system.cpu0.int_regfile_writes 310987 # number of integer regfile writes +system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 376671 # Number of Instructions Simulated +system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 687652 # number of integer regfile reads +system.cpu0.int_regfile_writes 310240 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 224004 # number of misc regfile reads +system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.tags.replacements 322 # number of replacements -system.cpu0.icache.tags.tagsinuse 240.567538 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6326 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 612 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.336601 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.567538 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469858 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.469858 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7735 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7735 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6326 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6326 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6326 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6326 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6326 # number of overall hits -system.cpu0.icache.overall_hits::total 6326 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses -system.cpu0.icache.overall_misses::total 797 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36689746 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 36689746 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 36689746 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 36689746 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 36689746 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 36689746 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7123 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7123 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7123 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7123 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7123 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7123 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111891 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111891 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111891 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111891 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111891 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111891 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46034.813049 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46034.813049 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46034.813049 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46034.813049 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 613 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 613 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 613 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 613 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 613 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 613 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 28185001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 28185001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 28185001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 28185001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 28185001 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 28185001 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45978.794454 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.516453 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148253 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 872.076471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.516453 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276399 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.276399 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 597940 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 597940 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75362 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75362 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72979 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72979 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148341 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148341 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148341 # number of overall hits -system.cpu0.dcache.overall_hits::total 148341 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 480 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits +system.cpu0.dcache.overall_hits::total 147973 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1024 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1024 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1024 # number of overall misses -system.cpu0.dcache.overall_misses::total 1024 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15203420 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15203420 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32866263 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32866263 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 427750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 427750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48069683 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48069683 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48069683 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48069683 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75842 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75842 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73523 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73523 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses +system.cpu0.dcache.overall_misses::total 1026 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149365 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149365 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149365 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149365 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006329 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006329 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007399 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007399 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006856 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006856 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006856 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006856 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31673.791667 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31673.791667 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60415.924632 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60415.924632 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46943.049805 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46943.049805 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -1249,518 +665,519 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 298 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 663 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 663 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6258507 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6258507 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7387727 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7387727 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 382250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 382250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13646234 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13646234 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13646234 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13646234 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002400 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002435 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002435 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002417 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34387.401099 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34387.401099 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41272.217877 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41272.217877 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17375 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17375 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002430 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 35745.961749 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 35745.961749 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41286.184358 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41286.184358 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17420.454545 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17420.454545 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52620 # Number of BP lookups -system.cpu1.branchPred.condPredicted 49209 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1295 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 45306 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 44357 # Number of BTB hits +system.cpu0.icache.tags.replacements 319 # number of replacements +system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6347 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6347 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6347 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6347 # number of overall hits +system.cpu0.icache.overall_hits::total 6347 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 792 # number of overall misses +system.cpu0.icache.overall_misses::total 792 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36432996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 36432996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 36432996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 36432996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 36432996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 36432996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7139 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7139 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7139 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7139 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 48230 # Number of BP lookups +system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.905355 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 875 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 161023 # number of cpu cycles simulated +system.cpu1.numCycles 160735 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 31247 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 289875 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52620 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 45232 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 125550 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2747 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1122 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 22380 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 159305 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.819623 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.179377 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 56744 35.62% 35.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52063 32.68% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6924 4.35% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3540 2.22% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1103 0.69% 75.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 33079 20.76% 96.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1261 0.79% 97.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 757 0.48% 97.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3834 2.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 159305 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.326786 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.800209 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17668 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57241 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 79500 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3513 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1373 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 275603 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1373 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18384 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 26779 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12577 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 80781 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 19401 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 272270 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 17163 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 191050 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 520032 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 405162 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 176680 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14370 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1196 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 24088 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 76067 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 35939 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 36374 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 30769 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 225624 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6666 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 227547 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 18 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11238 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 649 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 159305 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.428373 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.374842 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 60375 37.90% 37.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 22487 14.12% 52.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 35297 22.16% 74.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 34879 21.89% 96.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3406 2.14% 98.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1579 0.99% 99.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 224 0.14% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 159305 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 89 26.49% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 38 11.31% 37.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 62.20% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 111688 49.08% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 80614 35.43% 84.51% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 35245 15.49% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 227547 # Type of FU issued -system.cpu1.iq.rate 1.413134 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 336 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001477 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 614753 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 244854 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 225845 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued +system.cpu1.iq.rate 1.263247 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 227883 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 30551 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2638 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1613 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1373 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7085 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 269526 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 76067 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 35939 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1117 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 476 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1037 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1513 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 226408 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 75003 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1139 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 37236 # number of nop insts executed -system.cpu1.iew.exec_refs 110148 # number of memory reference insts executed -system.cpu1.iew.exec_branches 46633 # Number of branches executed -system.cpu1.iew.exec_stores 35145 # Number of stores executed -system.cpu1.iew.exec_rate 1.406060 # Inst execution rate -system.cpu1.iew.wb_sent 226126 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 225845 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 127804 # num instructions producing a value -system.cpu1.iew.wb_consumers 134338 # num instructions consuming a value +system.cpu1.iew.exec_nop 32947 # number of nop insts executed +system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed +system.cpu1.iew.exec_branches 42219 # Number of branches executed +system.cpu1.iew.exec_stores 29534 # Number of stores executed +system.cpu1.iew.exec_rate 1.256422 # Inst execution rate +system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 112178 # num instructions producing a value +system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.402564 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.951361 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14108 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6017 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1295 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 156709 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.629549 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.048246 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 66028 42.13% 42.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 43411 27.70% 69.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5268 3.36% 73.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6809 4.34% 77.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1543 0.98% 78.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 30606 19.53% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 798 0.51% 98.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 967 0.62% 99.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1279 0.82% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 156709 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 255365 # Number of instructions committed -system.cpu1.commit.committedOps 255365 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 226660 # Number of instructions committed +system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 107755 # Number of memory references committed -system.cpu1.commit.loads 73429 # Number of loads committed -system.cpu1.commit.membars 5300 # Number of memory barriers committed -system.cpu1.commit.branches 45589 # Number of branches committed +system.cpu1.commit.refs 92171 # Number of memory references committed +system.cpu1.commit.loads 63450 # Number of loads committed +system.cpu1.commit.membars 6533 # Number of memory barriers committed +system.cpu1.commit.branches 41215 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 175463 # Number of committed integer instructions. +system.cpu1.commit.int_insts 155506 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 36376 14.24% 14.24% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 105934 41.48% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 78729 30.83% 86.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 34326 13.44% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 255365 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1279 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 424317 # The number of ROB reads -system.cpu1.rob.rob_writes 541540 # The number of ROB writes -system.cpu1.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1718 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43314 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 213689 # Number of Instructions Simulated -system.cpu1.committedOps 213689 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.753539 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.753539 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.327071 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.327071 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 390200 # number of integer regfile reads -system.cpu1.int_regfile_writes 182656 # number of integer regfile writes +system.cpu1.rob.rob_reads 395483 # The number of ROB reads +system.cpu1.rob.rob_writes 484550 # The number of ROB writes +system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 188125 # Number of Instructions Simulated +system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 343348 # number of integer regfile reads +system.cpu1.int_regfile_writes 161358 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 111763 # number of misc regfile reads +system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.tags.replacements 388 # number of replacements -system.cpu1.icache.tags.tagsinuse 78.707719 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21821 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 43.905433 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 78.707719 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.153726 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.153726 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22877 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22877 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21821 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21821 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21821 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21821 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21821 # number of overall hits -system.cpu1.icache.overall_hits::total 21821 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 559 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 559 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 559 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 559 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 559 # number of overall misses -system.cpu1.icache.overall_misses::total 559 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8425746 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8425746 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8425746 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8425746 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8425746 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8425746 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22380 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22380 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22380 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22380 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22380 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22380 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15072.890877 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15072.890877 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15072.890877 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15072.890877 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6648254 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6648254 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6648254 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6648254 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6648254 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6648254 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022207 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022207 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022207 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13376.768612 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.402316 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 40362 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1441.500000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.402316 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.047661 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.047661 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 315306 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 315306 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 43998 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 43998 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 34119 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 34119 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 78117 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 78117 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 78117 # number of overall hits -system.cpu1.dcache.overall_hits::total 78117 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 439 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 439 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 136 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 136 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 575 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 575 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 575 # number of overall misses -system.cpu1.dcache.overall_misses::total 575 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5820038 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5820038 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2819511 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2819511 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 502006 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 502006 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8639549 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8639549 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8639549 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8639549 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 44437 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 44437 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 34255 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 34255 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits +system.cpu1.dcache.overall_hits::total 68186 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses +system.cpu1.dcache.overall_misses::total 559 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 78692 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 78692 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 78692 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 78692 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009879 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009879 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003970 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003970 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007307 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007307 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007307 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007307 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13257.489749 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13257.489749 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20731.698529 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20731.698529 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8655.275862 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 8655.275862 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15025.302609 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15025.302609 # average overall miss latency +system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1769,520 +1186,519 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 276 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 308 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 308 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 308 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 267 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 267 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1085520 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1085520 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1288239 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1288239 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 385994 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 385994 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2373759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2373759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2373759 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2373759 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003668 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003668 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003036 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003036 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003393 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003393 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6659.631902 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6659.631902 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12386.913462 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12386.913462 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6655.068966 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6655.068966 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 52660 # Number of BP lookups -system.cpu2.branchPred.condPredicted 48877 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1286 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45218 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 43881 # Number of BTB hits +system.cpu1.icache.tags.replacements 388 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 25352 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 25352 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 24292 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 24292 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 24292 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 24292 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 24292 # number of overall hits +system.cpu1.icache.overall_hits::total 24292 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 562 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 562 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 562 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 562 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 562 # number of overall misses +system.cpu1.icache.overall_misses::total 562 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.branchPred.lookups 55295 # Number of BP lookups +system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.043213 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 913 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 160663 # number of cpu cycles simulated +system.cpu2.numCycles 160375 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 30584 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 291962 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 52660 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 44794 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 122431 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2729 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1111 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 21169 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 155507 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.877485 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.219728 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 53998 34.72% 34.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51209 32.93% 67.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6210 3.99% 71.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3413 2.19% 73.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 933 0.60% 74.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 33386 21.47% 95.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1293 0.83% 96.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 846 0.54% 97.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4219 2.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155507 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.327767 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.817232 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17863 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 52592 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 80411 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3267 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1364 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 276853 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1364 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18564 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 24147 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12636 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 81735 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 17051 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 273529 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 15090 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 193256 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 525177 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 409210 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 178291 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14965 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1175 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 21746 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 76624 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 36478 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 36325 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31287 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 227715 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6015 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 228842 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13120 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11533 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155507 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.471586 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.386146 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 57410 36.92% 36.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 20565 13.22% 50.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 35759 23.00% 73.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 35374 22.75% 95.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3397 2.18% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1636 1.05% 99.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 896 0.58% 99.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 267 0.17% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 203 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155507 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 89 26.57% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 37 11.04% 37.61% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 112448 49.14% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 80571 35.21% 84.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 35823 15.65% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 228842 # Type of FU issued -system.cpu2.iq.rate 1.424360 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 335 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001464 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 613560 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 246890 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 227101 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued +system.cpu2.iq.rate 1.514600 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 229177 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 31107 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1596 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6807 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 270837 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 190 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 76624 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 36478 # Number of dispatched store instructions +system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1049 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 227700 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 75599 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 37107 # number of nop insts executed -system.cpu2.iew.exec_refs 111310 # number of memory reference insts executed -system.cpu2.iew.exec_branches 46563 # Number of branches executed -system.cpu2.iew.exec_stores 35711 # Number of stores executed -system.cpu2.iew.exec_rate 1.417252 # Inst execution rate -system.cpu2.iew.wb_sent 227402 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 227101 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 129036 # num instructions producing a value -system.cpu2.iew.wb_consumers 135804 # num instructions consuming a value +system.cpu2.iew.exec_nop 39706 # number of nop insts executed +system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed +system.cpu2.iew.exec_branches 49059 # Number of branches executed +system.cpu2.iew.exec_stores 39036 # Number of stores executed +system.cpu2.iew.exec_rate 1.507585 # Inst execution rate +system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 138145 # num instructions producing a value +system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.413524 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.950163 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14614 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5368 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1286 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152859 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.675858 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.068536 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 62472 40.87% 40.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 43239 28.29% 69.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5166 3.38% 72.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6247 4.09% 76.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1528 1.00% 77.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 31073 20.33% 97.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 875 0.57% 98.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 941 0.62% 99.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1318 0.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152859 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 256170 # Number of instructions committed -system.cpu2.commit.committedOps 256170 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 272860 # Number of instructions committed +system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 108804 # Number of memory references committed -system.cpu2.commit.loads 73922 # Number of loads committed -system.cpu2.commit.membars 4659 # Number of memory barriers committed -system.cpu2.commit.branches 45502 # Number of branches committed +system.cpu2.commit.refs 117938 # Number of memory references committed +system.cpu2.commit.loads 79744 # Number of loads committed +system.cpu2.commit.membars 3865 # Number of memory barriers committed +system.cpu2.commit.branches 48024 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 176434 # Number of committed integer instructions. +system.cpu2.commit.int_insts 188084 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 36297 14.17% 14.17% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 106410 41.54% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 78581 30.68% 86.38% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 34882 13.62% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 256170 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1318 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 421739 # The number of ROB reads -system.cpu2.rob.rob_writes 544215 # The number of ROB writes +system.cpu2.rob.rob_reads 438358 # The number of ROB reads +system.cpu2.rob.rob_writes 577962 # The number of ROB writes system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5156 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 43676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 215214 # Number of Instructions Simulated -system.cpu2.committedOps 215214 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.746527 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.746527 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.339537 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.339537 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 394013 # number of integer regfile reads -system.cpu2.int_regfile_writes 184721 # number of integer regfile writes +system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 230180 # Number of Instructions Simulated +system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 421380 # number of integer regfile reads +system.cpu2.int_regfile_writes 197053 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 112958 # number of misc regfile reads +system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.tags.replacements 380 # number of replacements -system.cpu2.icache.tags.tagsinuse 85.367642 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 20592 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 493 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 41.768763 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 85.367642 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.166734 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.166734 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 21662 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 21662 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 20592 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 20592 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 20592 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 20592 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 20592 # number of overall hits -system.cpu2.icache.overall_hits::total 20592 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 577 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 577 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 577 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 577 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 577 # number of overall misses -system.cpu2.icache.overall_misses::total 577 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13065992 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 13065992 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 13065992 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 13065992 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 13065992 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 13065992 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 21169 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 21169 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 21169 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 21169 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 21169 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 21169 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.027257 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.027257 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.027257 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.027257 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.027257 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.027257 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22644.700173 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22644.700173 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22644.700173 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22644.700173 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 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-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1686771 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1686771 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511239 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511239 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 352994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 352994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3198010 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3198010 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3198010 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3198010 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003440 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003440 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003102 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003102 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.777778 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003292 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003292 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11024.647059 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11024.647059 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13992.953704 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13992.953704 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7203.959184 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7203.959184 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 48141 # Number of BP lookups -system.cpu3.branchPred.condPredicted 44605 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1305 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 40897 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 39710 # Number of BTB hits +system.cpu2.icache.tags.replacements 378 # number of replacements +system.cpu2.icache.tags.tagsinuse 84.872672 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 18881 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 38.532653 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.872672 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165767 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.165767 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits +system.cpu2.icache.overall_hits::total 18881 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses +system.cpu2.icache.overall_misses::total 570 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13340243 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 13340243 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 13340243 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 13340243 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 13340243 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 13340243 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19451 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19451 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.branchPred.lookups 49708 # Number of BP lookups +system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.097587 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 884 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 160319 # number of cpu cycles simulated +system.cpu3.numCycles 160031 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 33851 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 260297 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 48141 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 40594 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 122891 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1076 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24972 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 417 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 159213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.634898 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.125574 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 64563 40.55% 40.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 48696 30.59% 71.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8235 5.17% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3504 2.20% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1064 0.67% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 27204 17.09% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1240 0.78% 97.04% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 753 0.47% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3954 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 159213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.300283 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.623619 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17777 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 68157 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 67726 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4161 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1382 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 245360 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1382 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18479 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 33142 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12841 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 69300 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 24059 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 241885 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 21460 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 168616 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 454082 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 355646 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 153987 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14629 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1214 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1272 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 28919 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 65522 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 29976 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31799 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24828 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 198526 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7988 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 201423 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12862 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11999 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 692 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 159213 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.265117 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.367863 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 68514 43.03% 43.03% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 26230 16.47% 59.51% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 29303 18.40% 77.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 28880 18.14% 96.05% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3418 2.15% 98.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1568 0.98% 99.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 871 0.55% 99.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 223 0.14% 99.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 159213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 92 26.36% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 48 13.75% 40.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 59.89% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 100972 50.13% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 71204 35.35% 85.48% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 29247 14.52% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 201423 # Type of FU issued -system.cpu3.iq.rate 1.256389 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 349 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001733 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 562441 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 219414 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 199715 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued +system.cpu3.iq.rate 1.322737 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 201772 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 24567 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2806 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1637 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8523 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 239131 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 65522 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 29976 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1120 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1054 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 200291 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 64311 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1132 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32617 # number of nop insts executed -system.cpu3.iew.exec_refs 93457 # number of memory reference insts executed -system.cpu3.iew.exec_branches 41928 # Number of branches executed -system.cpu3.iew.exec_stores 29146 # Number of stores executed -system.cpu3.iew.exec_rate 1.249328 # Inst execution rate -system.cpu3.iew.wb_sent 200012 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 199715 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 111117 # num instructions producing a value -system.cpu3.iew.wb_consumers 117670 # num instructions consuming a value +system.cpu3.iew.exec_nop 34395 # number of nop insts executed +system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43728 # Number of branches executed +system.cpu3.iew.exec_stores 31474 # Number of stores executed +system.cpu3.iew.exec_rate 1.315601 # Inst execution rate +system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 117676 # num instructions producing a value +system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.245735 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.944310 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14558 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7296 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1305 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156559 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.434092 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.973064 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 75373 48.14% 48.14% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 38673 24.70% 72.85% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5214 3.33% 76.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8076 5.16% 81.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1539 0.98% 82.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24642 15.74% 98.06% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 775 0.50% 98.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1306 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156559 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 224520 # Number of instructions committed -system.cpu3.commit.committedOps 224520 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 236439 # Number of instructions committed +system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 91055 # Number of memory references committed -system.cpu3.commit.loads 62716 # Number of loads committed -system.cpu3.commit.membars 6575 # Number of memory barriers committed -system.cpu3.commit.branches 40877 # Number of branches committed +system.cpu3.commit.refs 97502 # Number of memory references committed +system.cpu3.commit.loads 66856 # Number of loads committed +system.cpu3.commit.membars 6091 # Number of memory barriers committed +system.cpu3.commit.branches 42698 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 154046 # Number of committed integer instructions. +system.cpu3.commit.int_insts 162319 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 31660 14.10% 14.10% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 95230 42.41% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 69291 30.86% 87.38% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 28339 12.62% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 224520 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1306 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 393745 # The number of ROB reads -system.cpu3.rob.rob_writes 480811 # The number of ROB writes -system.cpu3.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1106 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44020 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 186285 # Number of Instructions Simulated -system.cpu3.committedOps 186285 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.860611 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.860611 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.161965 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.161965 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 340113 # number of integer regfile reads -system.cpu3.int_regfile_writes 159981 # number of integer regfile writes +system.cpu3.rob.rob_reads 405464 # The number of ROB reads +system.cpu3.rob.rob_writes 504751 # The number of ROB writes +system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 196863 # Number of Instructions Simulated +system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 359772 # number of integer regfile reads +system.cpu3.int_regfile_writes 168916 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 95078 # number of misc regfile reads +system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.tags.replacements 386 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.771025 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 24411 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 499 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 48.919840 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.771025 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151897 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151897 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 25471 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 25471 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 24411 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 24411 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 24411 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 24411 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 24411 # number of overall hits -system.cpu3.icache.overall_hits::total 24411 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 561 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 561 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 561 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 561 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 561 # number of overall misses -system.cpu3.icache.overall_misses::total 561 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7400997 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7400997 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7400997 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7400997 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7400997 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7400997 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24972 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24972 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24972 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24972 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24972 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24972 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022465 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.022465 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022465 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.022465 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022465 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.022465 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13192.508021 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13192.508021 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13192.508021 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13192.508021 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 499 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 499 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 499 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 499 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 499 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 499 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5888752 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5888752 # number of ReadReq MSHR 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ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.284431 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.284431 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67689.189189 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59065.074906 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58395.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61354.961832 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 534 # Transaction distribution +system.membus.trans_dist::ReadResp 533 # Transaction distribution +system.membus.trans_dist::UpgradeReq 274 # Transaction distribution +system.membus.trans_dist::UpgradeResp 78 # Transaction distribution +system.membus.trans_dist::ReadExReq 179 # Transaction distribution +system.membus.trans_dist::ReadExResp 131 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 244 # Total snoops (count) +system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 987 # Request fanout histogram +system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.0 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1023 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 427faaaab..8156a1abf 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.010189 # Number of seconds simulated -sim_ticks 10189338 # Number of ticks simulated -final_tick 10189338 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.010101 # Number of seconds simulated +sim_ticks 10100518 # Number of ticks simulated +final_tick 10100518 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 78610 # Simulator tick rate (ticks/s) -host_mem_usage 651260 # Number of bytes of host memory used -host_seconds 129.62 # Real time elapsed on the host +host_tick_rate 129349 # Simulator tick rate (ticks/s) +host_mem_usage 663928 # Number of bytes of host memory used +host_seconds 78.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39524800 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39524800 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14139200 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14139200 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 617575 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 617575 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 220925 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 220925 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 3879035125 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 3879035125 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1387646577 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1387646577 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 5266681702 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 5266681702 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 617577 # Number of read requests accepted -system.mem_ctrls.writeReqs 220925 # Number of write requests accepted -system.mem_ctrls.readBursts 617577 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 220925 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39138176 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 386752 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14013696 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39524928 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14139200 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 6043 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 1932 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39550848 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39550848 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14145024 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14145024 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 617982 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 617982 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 221016 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 221016 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 3915724718 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 3915724718 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1400425602 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1400425602 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 5316150320 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 5316150320 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 617983 # Number of read requests accepted +system.mem_ctrls.writeReqs 221016 # Number of write requests accepted +system.mem_ctrls.readBursts 617983 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 221016 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 39163072 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 387840 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14016640 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39550912 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14145024 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 6060 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 1978 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76538 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76571 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76714 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76079 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76086 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76610 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76532 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 76404 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76629 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76171 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76824 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76474 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76756 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76802 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 76042 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27378 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27423 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27424 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27014 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27346 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27635 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27364 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27380 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27421 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27227 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27422 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27319 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27412 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27477 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27095 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27637 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,29 +69,29 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 10189309 # Total gap between requests +system.mem_ctrls.totGap 10100475 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 617577 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 617983 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 220925 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 33272 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 65829 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 105799 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 135981 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 124559 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 85542 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 44255 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 16297 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 221016 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 34398 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 67691 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 107083 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 135966 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 123386 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 83518 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 43655 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 16226 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -131,32 +131,32 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 30 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 83 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 1662 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 5307 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 9467 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 12599 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 14395 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 15324 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 15907 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 16029 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 15907 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 15548 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 15075 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 14795 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 14747 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 14706 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 14783 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 15249 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 4255 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1854 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 778 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 292 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 114 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 118 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 1783 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 5370 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 9528 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 12721 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 14465 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 15565 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 15821 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 16096 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 15783 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 15412 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 15030 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 14722 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 14673 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 14636 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 14779 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 15223 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 4310 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 1845 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 727 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 255 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 87 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 26 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -180,205 +180,174 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 331991 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 160.098220 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 126.076476 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 125.468332 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 134789 40.60% 40.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 125458 37.79% 78.39% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44451 13.39% 91.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 17342 5.22% 97.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6423 1.93% 98.94% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2310 0.70% 99.63% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 840 0.25% 99.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 257 0.08% 99.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 121 0.04% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 331991 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 332523 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 159.925611 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 125.830358 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 125.889032 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 135463 40.74% 40.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 125752 37.82% 78.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 43770 13.16% 91.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17448 5.25% 96.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6543 1.97% 98.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2325 0.70% 99.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 803 0.24% 99.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 286 0.09% 99.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 133 0.04% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 332523 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 13671 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 44.729574 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 43.698245 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 9.605843 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-15 1 0.01% 0.01% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-19 10 0.07% 0.08% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-23 59 0.43% 0.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-27 247 1.81% 2.32% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::28-31 645 4.72% 7.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-35 1323 9.68% 16.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-39 1874 13.71% 30.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-43 2328 17.03% 47.45% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::44-47 2269 16.60% 64.05% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-51 1834 13.42% 77.46% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::52-55 1248 9.13% 86.59% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-59 853 6.24% 92.83% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::60-63 491 3.59% 96.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-67 271 1.98% 98.41% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::68-71 125 0.91% 99.32% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-75 48 0.35% 99.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::76-79 28 0.20% 99.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-83 10 0.07% 99.95% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::84-87 4 0.03% 99.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-91 2 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 44.758833 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 43.734391 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 9.598616 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-19 10 0.07% 0.07% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-23 51 0.37% 0.45% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-27 237 1.73% 2.18% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::28-31 592 4.33% 6.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-35 1395 10.20% 16.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-39 1956 14.31% 31.02% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-43 2298 16.81% 47.83% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::44-47 2196 16.06% 63.89% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-51 1787 13.07% 76.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::52-55 1319 9.65% 86.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-59 876 6.41% 93.02% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::60-63 474 3.47% 96.49% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-67 243 1.78% 98.27% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::68-71 135 0.99% 99.25% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-75 62 0.45% 99.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::76-79 22 0.16% 99.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-83 13 0.10% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::84-87 3 0.02% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::92-95 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::104-107 1 0.01% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 13671 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 13671 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.016678 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.015501 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.206017 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13555 99.15% 99.15% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 48 0.35% 99.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 43 0.31% 99.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 9 0.07% 99.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 13 0.10% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 3 0.02% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.020042 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.018590 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.229581 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13535 99.01% 99.01% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 53 0.39% 99.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 50 0.37% 99.76% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.15% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 6 0.04% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 5 0.04% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 2 0.01% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 13671 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 29899696 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 41518842 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3057670 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 48.89 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 28940521 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 40567058 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3059615 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 47.29 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 67.89 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 3841.09 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1375.33 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 3879.05 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1387.65 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 66.29 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 3877.33 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1387.71 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 3915.73 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1400.43 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 40.75 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 30.01 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 10.74 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 5.53 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.44 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 285563 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 212936 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 46.70 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.23 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 12.15 # Average gap between requests -system.mem_ctrls.pageHitRate 60.02 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 20 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 340080 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 9844307 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 2508483600 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 1393602000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7628000640 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2269057536 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 665196480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 665196480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 6939209412 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 220089312 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 23610000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 5917575000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 21427159668 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 6802860792 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 2103.921134 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.969195 # Core power per rank (mW) +system.mem_ctrls.busUtil 41.13 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 30.29 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 10.84 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 5.49 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 26.46 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 285611 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 212791 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 46.67 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.15 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 12.04 # Average gap between requests +system.mem_ctrls.pageHitRate 59.98 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 2513405160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1396336200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7635376320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2270198016 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 659602320 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 6882629616 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 21843000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 21379390632 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2117.037761 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 20 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 337220 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 9761503 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 659602320 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 218238408 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5867775600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 6745616328 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.969575 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9761482 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 337220 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 98577 # number of read accesses completed +system.cpu0.num_writes 54699 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 98994 # number of read accesses completed +system.cpu1.num_writes 54402 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99663 # number of read accesses completed +system.cpu2.num_writes 54801 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99192 # number of read accesses completed +system.cpu3.num_writes 55310 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 55358 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99170 # number of read accesses completed +system.cpu5.num_writes 54755 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 99605 # number of read accesses completed +system.cpu6.num_writes 54887 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 99434 # number of read accesses completed +system.cpu7.num_writes 55034 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 2048 # delay histogram for all message system.ruby.delayHist::max_bucket 20479 # delay histogram for all message -system.ruby.delayHist::samples 4971489 # delay histogram for all message -system.ruby.delayHist::mean 205.679263 # delay histogram for all message -system.ruby.delayHist::stdev 591.280553 # delay histogram for all message -system.ruby.delayHist | 4825560 97.06% 97.06% | 138459 2.79% 99.85% | 7092 0.14% 99.99% | 343 0.01% 100.00% | 32 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 4971489 # delay histogram for all message +system.ruby.delayHist::samples 4971796 # delay histogram for all message +system.ruby.delayHist::mean 200.857627 # delay histogram for all message +system.ruby.delayHist::stdev 577.801677 # delay histogram for all message +system.ruby.delayHist | 4834086 97.23% 97.23% | 131198 2.64% 99.87% | 6246 0.13% 99.99% | 255 0.01% 100.00% | 8 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 4971796 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 623259 -system.ruby.outstanding_req_hist::mean 15.998457 -system.ruby.outstanding_req_hist::gmean 15.997185 -system.ruby.outstanding_req_hist::stdev 0.126163 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 18 0.00% 0.02% | 623137 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 623259 +system.ruby.outstanding_req_hist::samples 623814 +system.ruby.outstanding_req_hist::mean 15.998459 +system.ruby.outstanding_req_hist::gmean 15.997190 +system.ruby.outstanding_req_hist::stdev 0.126101 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 17 0.00% 0.02% | 623693 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 623814 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 623131 -system.ruby.latency_hist::mean 2092.761496 -system.ruby.latency_hist::gmean 1620.223776 -system.ruby.latency_hist::stdev 1225.208976 -system.ruby.latency_hist | 160408 25.74% 25.74% | 151701 24.34% 50.09% | 148772 23.87% 73.96% | 132419 21.25% 95.21% | 29415 4.72% 99.93% | 416 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 623131 +system.ruby.latency_hist::samples 623686 +system.ruby.latency_hist::mean 2072.612140 +system.ruby.latency_hist::gmean 1591.498940 +system.ruby.latency_hist::stdev 1226.963263 +system.ruby.latency_hist | 164804 26.42% 26.42% | 150821 24.18% 50.61% | 147979 23.73% 74.33% | 131724 21.12% 95.45% | 27974 4.49% 99.94% | 384 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 623686 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 5 +system.ruby.hit_latency_hist::samples 9 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 5 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 9 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 623126 -system.ruby.miss_latency_hist::mean 2092.778265 -system.ruby.miss_latency_hist::gmean 1620.305575 -system.ruby.miss_latency_hist::stdev 1225.199591 -system.ruby.miss_latency_hist | 160403 25.74% 25.74% | 151701 24.35% 50.09% | 148772 23.88% 73.96% | 132419 21.25% 95.21% | 29415 4.72% 99.93% | 416 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 623126 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 77550 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77551 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl4.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl4.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl4.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl4.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl4.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl4.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl5.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 77775 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77776 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl5.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl5.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl5.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl5.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl5.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl6.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 77691 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77692 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl6.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl6.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl6.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl6.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl6.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl7.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 77428 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77428 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl7.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl7.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl7.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl7.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl7.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78352 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78353 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 623677 +system.ruby.miss_latency_hist::mean 2072.642005 +system.ruby.miss_latency_hist::gmean 1591.643032 +system.ruby.miss_latency_hist::stdev 1226.946927 +system.ruby.miss_latency_hist | 164795 26.42% 26.42% | 150821 24.18% 50.61% | 147979 23.73% 74.33% | 131724 21.12% 95.45% | 27974 4.49% 99.94% | 384 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 623677 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 3 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 77823 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 77826 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -391,26 +360,9 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers00.percent_links_utilized 4.017157 -system.ruby.network.routers00.msg_count.Control::0 78352 -system.ruby.network.routers00.msg_count.Request_Control::2 76727 -system.ruby.network.routers00.msg_count.Response_Data::1 78943 -system.ruby.network.routers00.msg_count.Response_Control::1 65296 -system.ruby.network.routers00.msg_count.Response_Control::2 77735 -system.ruby.network.routers00.msg_count.Writeback_Data::0 14723 -system.ruby.network.routers00.msg_count.Writeback_Data::1 52192 -system.ruby.network.routers00.msg_count.Writeback_Control::0 26458 -system.ruby.network.routers00.msg_bytes.Control::0 626816 -system.ruby.network.routers00.msg_bytes.Request_Control::2 613816 -system.ruby.network.routers00.msg_bytes.Response_Data::1 5683896 -system.ruby.network.routers00.msg_bytes.Response_Control::1 522368 -system.ruby.network.routers00.msg_bytes.Response_Control::2 621880 -system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1060056 -system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3757824 -system.ruby.network.routers00.msg_bytes.Writeback_Control::0 211664 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78104 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78104 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 2 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 77422 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77424 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -423,26 +375,9 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers01.percent_links_utilized 4.004745 -system.ruby.network.routers01.msg_count.Control::0 78104 -system.ruby.network.routers01.msg_count.Request_Control::2 76509 -system.ruby.network.routers01.msg_count.Response_Data::1 78659 -system.ruby.network.routers01.msg_count.Response_Control::1 65065 -system.ruby.network.routers01.msg_count.Response_Control::2 77454 -system.ruby.network.routers01.msg_count.Writeback_Data::0 14590 -system.ruby.network.routers01.msg_count.Writeback_Data::1 52150 -system.ruby.network.routers01.msg_count.Writeback_Control::0 26505 -system.ruby.network.routers01.msg_bytes.Control::0 624832 -system.ruby.network.routers01.msg_bytes.Request_Control::2 612072 -system.ruby.network.routers01.msg_bytes.Response_Data::1 5663448 -system.ruby.network.routers01.msg_bytes.Response_Control::1 520520 -system.ruby.network.routers01.msg_bytes.Response_Control::2 619632 -system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1050480 -system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3754800 -system.ruby.network.routers01.msg_bytes.Writeback_Control::0 212040 system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78244 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78245 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_misses 77856 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77857 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -455,26 +390,9 @@ system.ruby.l1_cntrl2.prefetcher.hits 0 # nu system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers02.percent_links_utilized 4.010243 -system.ruby.network.routers02.msg_count.Control::0 78244 -system.ruby.network.routers02.msg_count.Request_Control::2 76806 -system.ruby.network.routers02.msg_count.Response_Data::1 78763 -system.ruby.network.routers02.msg_count.Response_Control::1 65157 -system.ruby.network.routers02.msg_count.Response_Control::2 77588 -system.ruby.network.routers02.msg_count.Writeback_Data::0 14535 -system.ruby.network.routers02.msg_count.Writeback_Data::1 52281 -system.ruby.network.routers02.msg_count.Writeback_Control::0 26463 -system.ruby.network.routers02.msg_bytes.Control::0 625952 -system.ruby.network.routers02.msg_bytes.Request_Control::2 614448 -system.ruby.network.routers02.msg_bytes.Response_Data::1 5670936 -system.ruby.network.routers02.msg_bytes.Response_Control::1 521256 -system.ruby.network.routers02.msg_bytes.Response_Control::2 620704 -system.ruby.network.routers02.msg_bytes.Writeback_Data::0 1046520 -system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3764232 -system.ruby.network.routers02.msg_bytes.Writeback_Control::0 211704 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78003 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78003 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 77999 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78000 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -487,729 +405,819 @@ system.ruby.l1_cntrl3.prefetcher.hits 0 # nu system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers03.percent_links_utilized 3.995461 -system.ruby.network.routers03.msg_count.Control::0 78003 -system.ruby.network.routers03.msg_count.Request_Control::2 76449 -system.ruby.network.routers03.msg_count.Response_Data::1 78486 -system.ruby.network.routers03.msg_count.Response_Control::1 64943 -system.ruby.network.routers03.msg_count.Response_Control::2 77331 -system.ruby.network.routers03.msg_count.Writeback_Data::0 14715 -system.ruby.network.routers03.msg_count.Writeback_Data::1 51879 -system.ruby.network.routers03.msg_count.Writeback_Control::0 25998 -system.ruby.network.routers03.msg_bytes.Control::0 624024 -system.ruby.network.routers03.msg_bytes.Request_Control::2 611592 -system.ruby.network.routers03.msg_bytes.Response_Data::1 5650992 -system.ruby.network.routers03.msg_bytes.Response_Control::1 519544 -system.ruby.network.routers03.msg_bytes.Response_Control::2 618648 -system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1059480 -system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3735288 -system.ruby.network.routers03.msg_bytes.Writeback_Control::0 207984 -system.ruby.network.routers04.percent_links_utilized 3.971652 -system.ruby.network.routers04.msg_count.Control::0 77550 -system.ruby.network.routers04.msg_count.Request_Control::2 76039 -system.ruby.network.routers04.msg_count.Response_Data::1 78047 -system.ruby.network.routers04.msg_count.Response_Control::1 64587 -system.ruby.network.routers04.msg_count.Response_Control::2 76934 -system.ruby.network.routers04.msg_count.Writeback_Data::0 14444 -system.ruby.network.routers04.msg_count.Writeback_Data::1 51674 -system.ruby.network.routers04.msg_count.Writeback_Control::0 26145 -system.ruby.network.routers04.msg_bytes.Control::0 620400 -system.ruby.network.routers04.msg_bytes.Request_Control::2 608312 -system.ruby.network.routers04.msg_bytes.Response_Data::1 5619384 -system.ruby.network.routers04.msg_bytes.Response_Control::1 516696 -system.ruby.network.routers04.msg_bytes.Response_Control::2 615472 -system.ruby.network.routers04.msg_bytes.Writeback_Data::0 1039968 -system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3720528 -system.ruby.network.routers04.msg_bytes.Writeback_Control::0 209160 -system.ruby.network.routers05.percent_links_utilized 3.984903 -system.ruby.network.routers05.msg_count.Control::0 77775 -system.ruby.network.routers05.msg_count.Request_Control::2 76299 -system.ruby.network.routers05.msg_count.Response_Data::1 78272 -system.ruby.network.routers05.msg_count.Response_Control::1 64779 -system.ruby.network.routers05.msg_count.Response_Control::2 77121 -system.ruby.network.routers05.msg_count.Writeback_Data::0 14571 -system.ruby.network.routers05.msg_count.Writeback_Data::1 51833 -system.ruby.network.routers05.msg_count.Writeback_Control::0 26083 -system.ruby.network.routers05.msg_bytes.Control::0 622200 -system.ruby.network.routers05.msg_bytes.Request_Control::2 610392 -system.ruby.network.routers05.msg_bytes.Response_Data::1 5635584 -system.ruby.network.routers05.msg_bytes.Response_Control::1 518232 -system.ruby.network.routers05.msg_bytes.Response_Control::2 616968 -system.ruby.network.routers05.msg_bytes.Writeback_Data::0 1049112 -system.ruby.network.routers05.msg_bytes.Writeback_Data::1 3731976 -system.ruby.network.routers05.msg_bytes.Writeback_Control::0 208664 -system.ruby.network.routers06.percent_links_utilized 3.974939 -system.ruby.network.routers06.msg_count.Control::0 77691 -system.ruby.network.routers06.msg_count.Request_Control::2 76079 -system.ruby.network.routers06.msg_count.Response_Data::1 78230 -system.ruby.network.routers06.msg_count.Response_Control::1 64698 -system.ruby.network.routers06.msg_count.Response_Control::2 77044 -system.ruby.network.routers06.msg_count.Writeback_Data::0 14650 -system.ruby.network.routers06.msg_count.Writeback_Data::1 51429 -system.ruby.network.routers06.msg_count.Writeback_Control::0 25787 -system.ruby.network.routers06.msg_bytes.Control::0 621528 -system.ruby.network.routers06.msg_bytes.Request_Control::2 608632 -system.ruby.network.routers06.msg_bytes.Response_Data::1 5632560 -system.ruby.network.routers06.msg_bytes.Response_Control::1 517584 -system.ruby.network.routers06.msg_bytes.Response_Control::2 616352 -system.ruby.network.routers06.msg_bytes.Writeback_Data::0 1054800 -system.ruby.network.routers06.msg_bytes.Writeback_Data::1 3702888 -system.ruby.network.routers06.msg_bytes.Writeback_Control::0 206296 -system.ruby.network.routers07.percent_links_utilized 3.964826 -system.ruby.network.routers07.msg_count.Control::0 77428 -system.ruby.network.routers07.msg_count.Request_Control::2 75965 -system.ruby.network.routers07.msg_count.Response_Data::1 77944 -system.ruby.network.routers07.msg_count.Response_Control::1 64454 -system.ruby.network.routers07.msg_count.Response_Control::2 76853 -system.ruby.network.routers07.msg_count.Writeback_Data::0 14464 -system.ruby.network.routers07.msg_count.Writeback_Data::1 51520 -system.ruby.network.routers07.msg_count.Writeback_Control::0 25906 -system.ruby.network.routers07.msg_bytes.Control::0 619424 -system.ruby.network.routers07.msg_bytes.Request_Control::2 607720 -system.ruby.network.routers07.msg_bytes.Response_Data::1 5611968 -system.ruby.network.routers07.msg_bytes.Response_Control::1 515632 -system.ruby.network.routers07.msg_bytes.Response_Control::2 614824 -system.ruby.network.routers07.msg_bytes.Writeback_Data::0 1041408 -system.ruby.network.routers07.msg_bytes.Writeback_Data::1 3709440 -system.ruby.network.routers07.msg_bytes.Writeback_Control::0 207248 -system.ruby.l2_cntrl0.L2cache.demand_hits 31 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 623101 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 623132 # Number of cache demand accesses -system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions -system.ruby.network.routers08.percent_links_utilized 54.245833 -system.ruby.network.routers08.msg_count.Control::0 1240723 -system.ruby.network.routers08.msg_count.Request_Control::2 607107 -system.ruby.network.routers08.msg_count.Response_Data::1 1457329 -system.ruby.network.routers08.msg_count.Response_Control::1 1533130 -system.ruby.network.routers08.msg_count.Response_Control::2 618060 -system.ruby.network.routers08.msg_count.Writeback_Data::0 116692 -system.ruby.network.routers08.msg_count.Writeback_Data::1 414958 -system.ruby.network.routers08.msg_count.Writeback_Control::0 209345 -system.ruby.network.routers08.msg_bytes.Control::0 9925784 -system.ruby.network.routers08.msg_bytes.Request_Control::2 4856856 -system.ruby.network.routers08.msg_bytes.Response_Data::1 104927688 -system.ruby.network.routers08.msg_bytes.Response_Control::1 12265040 -system.ruby.network.routers08.msg_bytes.Response_Control::2 4944480 -system.ruby.network.routers08.msg_bytes.Writeback_Data::0 8401824 -system.ruby.network.routers08.msg_bytes.Writeback_Data::1 29876976 -system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1674760 -system.ruby.network.routers09.percent_links_utilized 22.519302 -system.ruby.network.routers09.msg_count.Control::0 617577 -system.ruby.network.routers09.msg_count.Response_Data::1 838498 -system.ruby.network.routers09.msg_count.Response_Control::1 1014212 -system.ruby.network.routers09.msg_bytes.Control::0 4940616 -system.ruby.network.routers09.msg_bytes.Response_Data::1 60371856 -system.ruby.network.routers09.msg_bytes.Response_Control::1 8113696 -system.ruby.network.routers10.percent_links_utilized 10.875421 -system.ruby.network.routers10.msg_count.Control::0 1240723 -system.ruby.network.routers10.msg_count.Request_Control::2 610873 -system.ruby.network.routers10.msg_count.Response_Data::1 1462851 -system.ruby.network.routers10.msg_count.Response_Control::1 1533161 -system.ruby.network.routers10.msg_count.Response_Control::2 618060 -system.ruby.network.routers10.msg_count.Writeback_Data::0 116692 -system.ruby.network.routers10.msg_count.Writeback_Data::1 414958 -system.ruby.network.routers10.msg_count.Writeback_Control::0 209345 -system.ruby.network.routers10.msg_bytes.Control::0 9925784 -system.ruby.network.routers10.msg_bytes.Request_Control::2 4886984 -system.ruby.network.routers10.msg_bytes.Response_Data::1 105325272 -system.ruby.network.routers10.msg_bytes.Response_Control::1 12265288 -system.ruby.network.routers10.msg_bytes.Response_Control::2 4944480 -system.ruby.network.routers10.msg_bytes.Writeback_Data::0 8401824 -system.ruby.network.routers10.msg_bytes.Writeback_Data::1 29876976 -system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1674760 -system.ruby.network.msg_count.Control 3722170 -system.ruby.network.msg_count.Request_Control 1828853 -system.ruby.network.msg_count.Response_Data 4386022 -system.ruby.network.msg_count.Response_Control 6453662 -system.ruby.network.msg_count.Writeback_Data 1594950 -system.ruby.network.msg_count.Writeback_Control 628035 -system.ruby.network.msg_byte.Control 29777360 -system.ruby.network.msg_byte.Request_Control 14630824 -system.ruby.network.msg_byte.Response_Data 315793584 -system.ruby.network.msg_byte.Response_Control 51629296 -system.ruby.network.msg_byte.Writeback_Data 114836400 -system.ruby.network.msg_byte.Writeback_Control 5024280 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78237 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78237 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl4.prefetcher.miss_observed 0 # number of misses observed +system.ruby.l1_cntrl4.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.ruby.l1_cntrl4.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.ruby.l1_cntrl4.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.ruby.l1_cntrl4.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.ruby.l1_cntrl4.prefetcher.hits 0 # number of prefetched blocks accessed +system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages +system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl5.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 77909 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77910 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.prefetcher.miss_observed 0 # number of misses observed +system.ruby.l1_cntrl5.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.ruby.l1_cntrl5.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.ruby.l1_cntrl5.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.ruby.l1_cntrl5.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.ruby.l1_cntrl5.prefetcher.hits 0 # number of prefetched blocks accessed +system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages +system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl6.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 77980 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77980 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.prefetcher.miss_observed 0 # number of misses observed +system.ruby.l1_cntrl6.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.ruby.l1_cntrl6.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.ruby.l1_cntrl6.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.ruby.l1_cntrl6.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.ruby.l1_cntrl6.prefetcher.hits 0 # number of prefetched blocks accessed +system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages +system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl7.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78469 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78470 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.prefetcher.miss_observed 0 # number of misses observed +system.ruby.l1_cntrl7.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.ruby.l1_cntrl7.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.ruby.l1_cntrl7.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.ruby.l1_cntrl7.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.ruby.l1_cntrl7.prefetcher.hits 0 # number of prefetched blocks accessed +system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages +system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 623653 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 623683 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 55724 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99110 # number of read accesses completed -system.cpu1.num_writes 54992 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99577 # number of read accesses completed -system.cpu2.num_writes 54873 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99025 # number of read accesses completed -system.cpu3.num_writes 55120 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98415 # number of read accesses completed -system.cpu4.num_writes 54586 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 98390 # number of read accesses completed -system.cpu5.num_writes 54856 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98374 # number of read accesses completed -system.cpu6.num_writes 54563 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98575 # number of read accesses completed -system.cpu7.num_writes 54585 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers00.throttle0.link_utilization 4.038766 -system.ruby.network.routers00.throttle0.msg_count.Request_Control::2 76727 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::1 78349 -system.ruby.network.routers00.throttle0.msg_count.Response_Control::1 41182 -system.ruby.network.routers00.throttle0.msg_bytes.Request_Control::2 613816 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::1 5641128 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::1 329456 -system.ruby.network.routers00.throttle1.link_utilization 3.995549 -system.ruby.network.routers00.throttle1.msg_count.Control::0 78352 -system.ruby.network.routers00.throttle1.msg_count.Response_Data::1 594 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::1 24114 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::2 77735 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::0 14723 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::1 52192 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Control::0 26458 -system.ruby.network.routers00.throttle1.msg_bytes.Control::0 626816 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::1 42768 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::1 192912 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::2 621880 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::0 1060056 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::1 3757824 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Control::0 211664 -system.ruby.network.routers01.throttle0.link_utilization 4.026415 -system.ruby.network.routers01.throttle0.msg_count.Request_Control::2 76509 -system.ruby.network.routers01.throttle0.msg_count.Response_Data::1 78102 -system.ruby.network.routers01.throttle0.msg_count.Response_Control::1 41103 -system.ruby.network.routers01.throttle0.msg_bytes.Request_Control::2 612072 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::1 5623344 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+system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::1 5609304 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::1 325640 +system.ruby.network.routers10.throttle6.link_utilization 4.053525 +system.ruby.network.routers10.throttle6.msg_count.Request_Control::2 76399 +system.ruby.network.routers10.throttle6.msg_count.Response_Data::1 77977 +system.ruby.network.routers10.throttle6.msg_count.Response_Control::1 40662 +system.ruby.network.routers10.throttle6.msg_bytes.Request_Control::2 611192 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::1 5614344 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::1 325296 +system.ruby.network.routers10.throttle7.link_utilization 4.080023 +system.ruby.network.routers10.throttle7.msg_count.Request_Control::2 76701 +system.ruby.network.routers10.throttle7.msg_count.Response_Data::1 78467 +system.ruby.network.routers10.throttle7.msg_count.Response_Control::1 41303 +system.ruby.network.routers10.throttle7.msg_bytes.Request_Control::2 613608 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::1 5649624 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::1 330424 +system.ruby.network.routers10.throttle8.link_utilization 62.405225 +system.ruby.network.routers10.throttle8.msg_count.Control::0 623695 +system.ruby.network.routers10.throttle8.msg_count.Response_Data::1 619265 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::1 811741 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::2 618595 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::0 116618 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::1 413398 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0 208947 +system.ruby.network.routers10.throttle8.msg_bytes.Control::0 4989560 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::1 44587080 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::1 6493928 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::2 4948760 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::0 8396496 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::1 29764656 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 1671576 +system.ruby.network.routers10.throttle9.link_utilization 14.870950 +system.ruby.network.routers10.throttle9.msg_count.Control::0 617983 +system.ruby.network.routers10.throttle9.msg_count.Response_Data::1 221016 +system.ruby.network.routers10.throttle9.msg_count.Response_Control::1 396959 +system.ruby.network.routers10.throttle9.msg_bytes.Control::0 4943864 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1 15913152 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3175672 system.ruby.delayVCHist.vnet_0::bucket_size 2048 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 20479 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 1567216 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 648.458979 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 907.022632 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1421287 90.69% 90.69% | 138459 8.83% 99.52% | 7092 0.45% 99.98% | 343 0.02% 100.00% | 32 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 1567216 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 1567834 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 632.927856 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 886.561692 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 1430124 91.22% 91.22% | 131198 8.37% 99.58% | 6246 0.40% 99.98% | 255 0.02% 100.00% | 8 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 1567834 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 8 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 79 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 2793400 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 2.237732 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 4.228455 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 2393251 85.68% 85.68% | 334671 11.98% 97.66% | 57246 2.05% 99.71% | 7631 0.27% 99.98% | 583 0.02% 100.00% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 2793400 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 2793654 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 2.252049 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 4.236651 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 2389326 85.53% 85.53% | 338163 12.10% 97.63% | 58171 2.08% 99.71% | 7435 0.27% 99.98% | 537 0.02% 100.00% | 22 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 2793654 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 610873 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.009868 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.140184 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 607860 99.51% 99.51% | 0 0.00% 99.51% | 3012 0.49% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 610873 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 610308 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.009651 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.138784 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 607367 99.52% 99.52% | 0 0.00% 99.52% | 2937 0.48% 100.00% | 0 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 610308 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 1024 system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 401577 -system.ruby.LD.latency_hist::mean 2092.828952 -system.ruby.LD.latency_hist::gmean 1620.627009 -system.ruby.LD.latency_hist::stdev 1225.164807 -system.ruby.LD.latency_hist | 103361 25.74% 25.74% | 97791 24.35% 50.09% | 95926 23.89% 73.98% | 85248 21.23% 95.21% | 18977 4.73% 99.93% | 274 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 401577 +system.ruby.LD.latency_hist::samples 402001 +system.ruby.LD.latency_hist::mean 2073.498317 +system.ruby.LD.latency_hist::gmean 1592.038290 +system.ruby.LD.latency_hist::stdev 1226.855968 +system.ruby.LD.latency_hist | 106152 26.41% 26.41% | 97021 24.13% 50.54% | 95622 23.79% 74.33% | 84872 21.11% 95.44% | 18097 4.50% 99.94% | 237 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 402001 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 3 +system.ruby.LD.hit_latency_hist::samples 6 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 3 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 6 system.ruby.LD.miss_latency_hist::bucket_size 1024 system.ruby.LD.miss_latency_hist::max_bucket 10239 -system.ruby.LD.miss_latency_hist::samples 401574 -system.ruby.LD.miss_latency_hist::mean 2092.844564 -system.ruby.LD.miss_latency_hist::gmean 1620.703188 -system.ruby.LD.miss_latency_hist::stdev 1225.156067 -system.ruby.LD.miss_latency_hist | 103358 25.74% 25.74% | 97791 24.35% 50.09% | 95926 23.89% 73.98% | 85248 21.23% 95.21% | 18977 4.73% 99.93% | 274 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 401574 +system.ruby.LD.miss_latency_hist::samples 401995 +system.ruby.LD.miss_latency_hist::mean 2073.529221 +system.ruby.LD.miss_latency_hist::gmean 1592.187383 +system.ruby.LD.miss_latency_hist::stdev 1226.839046 +system.ruby.LD.miss_latency_hist | 106146 26.40% 26.40% | 97021 24.13% 50.54% | 95622 23.79% 74.33% | 84872 21.11% 95.44% | 18097 4.50% 99.94% | 237 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 401995 system.ruby.ST.latency_hist::bucket_size 1024 system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 221554 -system.ruby.ST.latency_hist::mean 2092.639230 -system.ruby.ST.latency_hist::gmean 1619.493152 -system.ruby.ST.latency_hist::stdev 1225.291787 -system.ruby.ST.latency_hist | 57047 25.75% 25.75% | 53910 24.33% 50.08% | 52846 23.85% 73.93% | 47171 21.29% 95.22% | 10438 4.71% 99.94% | 142 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 221554 +system.ruby.ST.latency_hist::samples 221685 +system.ruby.ST.latency_hist::mean 2071.005156 +system.ruby.ST.latency_hist::gmean 1590.521356 +system.ruby.ST.latency_hist::stdev 1227.158942 +system.ruby.ST.latency_hist | 58652 26.46% 26.46% | 53800 24.27% 50.73% | 52357 23.62% 74.34% | 46852 21.13% 95.48% | 9877 4.46% 99.93% | 147 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 221685 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 2 +system.ruby.ST.hit_latency_hist::samples 3 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 2 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 3 system.ruby.ST.miss_latency_hist::bucket_size 1024 system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 221552 -system.ruby.ST.miss_latency_hist::mean 2092.658094 -system.ruby.ST.miss_latency_hist::gmean 1619.585130 -system.ruby.ST.miss_latency_hist::stdev 1225.281232 -system.ruby.ST.miss_latency_hist | 57045 25.75% 25.75% | 53910 24.33% 50.08% | 52846 23.85% 73.93% | 47171 21.29% 95.22% | 10438 4.71% 99.94% | 142 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 221552 -system.ruby.L1Cache_Controller.Load | 50466 12.57% 12.57% | 50379 12.54% 25.11% | 50567 12.59% 37.70% | 50137 12.48% 50.19% | 50081 12.47% 62.66% | 50104 12.48% 75.13% | 49966 12.44% 87.58% | 49898 12.42% 100.00% -system.ruby.L1Cache_Controller.Load::total 401598 -system.ruby.L1Cache_Controller.Store | 27889 12.59% 12.59% | 27726 12.51% 25.10% | 27680 12.49% 37.59% | 27867 12.58% 50.17% | 27470 12.40% 62.57% | 27674 12.49% 75.06% | 27726 12.51% 87.57% | 27532 12.43% 100.00% -system.ruby.L1Cache_Controller.Store::total 221564 -system.ruby.L1Cache_Controller.Inv | 76306 12.55% 12.55% | 76112 12.52% 25.07% | 76439 12.57% 37.65% | 76103 12.52% 50.17% | 75674 12.45% 62.62% | 75957 12.50% 75.11% | 75688 12.45% 87.56% | 75603 12.44% 100.00% -system.ruby.L1Cache_Controller.Inv::total 607882 -system.ruby.L1Cache_Controller.L1_Replacement | 550362 12.51% 12.51% | 550377 12.51% 25.01% | 551471 12.53% 37.55% | 549961 12.50% 50.05% | 548799 12.47% 62.52% | 549479 12.49% 75.00% | 550759 12.52% 87.52% | 549170 12.48% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 4400378 -system.ruby.L1Cache_Controller.Fwd_GETX | 248 14.06% 14.06% | 237 13.44% 27.49% | 214 12.13% 39.63% | 206 11.68% 51.30% | 229 12.98% 64.29% | 184 10.43% 74.72% | 240 13.61% 88.32% | 206 11.68% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1764 -system.ruby.L1Cache_Controller.Fwd_GETS | 173 14.10% 14.10% | 160 13.04% 27.14% | 153 12.47% 39.61% | 140 11.41% 51.02% | 136 11.08% 62.10% | 158 12.88% 74.98% | 151 12.31% 87.29% | 156 12.71% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 1227 -system.ruby.L1Cache_Controller.Data | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.Data::total 15 -system.ruby.L1Cache_Controller.Data_Exclusive | 49704 12.57% 12.57% | 49580 12.54% 25.12% | 49744 12.58% 37.70% | 49297 12.47% 50.17% | 49326 12.48% 62.65% | 49286 12.47% 75.12% | 49158 12.44% 87.56% | 49187 12.44% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 395282 -system.ruby.L1Cache_Controller.DataS_fromL1 | 145 11.82% 11.82% | 148 12.06% 23.88% | 165 13.45% 37.33% | 168 13.69% 51.02% | 139 11.33% 62.35% | 164 13.37% 75.71% | 161 13.12% 88.83% | 137 11.17% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 1227 -system.ruby.L1Cache_Controller.Data_all_Acks | 28498 12.58% 12.58% | 28369 12.52% 25.10% | 28333 12.50% 37.60% | 28532 12.59% 50.19% | 28081 12.39% 62.58% | 28321 12.50% 75.08% | 28367 12.52% 87.60% | 28101 12.40% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 226602 -system.ruby.L1Cache_Controller.Ack | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.Ack::total 15 -system.ruby.L1Cache_Controller.Ack_all | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 15 -system.ruby.L1Cache_Controller.WB_Ack | 41178 12.63% 12.63% | 41093 12.60% 25.23% | 40997 12.57% 37.81% | 40713 12.49% 50.30% | 40587 12.45% 62.75% | 40653 12.47% 75.22% | 40435 12.40% 87.62% | 40369 12.38% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 326025 -system.ruby.L1Cache_Controller.NP.Load | 50453 12.57% 12.57% | 50369 12.54% 25.11% | 50559 12.59% 37.70% | 50126 12.48% 50.19% | 50072 12.47% 62.66% | 50098 12.48% 75.13% | 49957 12.44% 87.58% | 49889 12.42% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 401523 -system.ruby.L1Cache_Controller.NP.Store | 27884 12.59% 12.59% | 27721 12.51% 25.10% | 27674 12.49% 37.59% | 27863 12.58% 50.17% | 27463 12.40% 62.57% | 27669 12.49% 75.06% | 27720 12.51% 87.57% | 27527 12.43% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 221521 -system.ruby.L1Cache_Controller.NP.Inv | 222 13.54% 13.54% | 219 13.35% 26.89% | 200 12.20% 39.09% | 205 12.50% 51.59% | 183 11.16% 62.74% | 203 12.38% 75.12% | 197 12.01% 87.13% | 211 12.87% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 1640 -system.ruby.L1Cache_Controller.I.Load | 10 15.15% 15.15% | 9 13.64% 28.79% | 6 9.09% 37.88% | 10 15.15% 53.03% | 8 12.12% 65.15% | 6 9.09% 74.24% | 8 12.12% 86.36% | 9 13.64% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 66 -system.ruby.L1Cache_Controller.I.Store | 5 13.51% 13.51% | 5 13.51% 27.03% | 5 13.51% 40.54% | 4 10.81% 51.35% | 7 18.92% 70.27% | 2 5.41% 75.68% | 6 16.22% 91.89% | 3 8.11% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 37 -system.ruby.L1Cache_Controller.I.L1_Replacement | 37007 12.51% 12.51% | 36845 12.45% 24.96% | 37094 12.54% 37.50% | 37122 12.55% 50.05% | 36827 12.45% 62.49% | 36968 12.50% 74.99% | 37098 12.54% 87.53% | 36896 12.47% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 295857 -system.ruby.L1Cache_Controller.S.Inv | 636 11.81% 11.81% | 666 12.37% 24.18% | 704 13.08% 37.26% | 712 13.22% 50.48% | 645 11.98% 62.46% | 708 13.15% 75.61% | 711 13.21% 88.82% | 602 11.18% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 5384 -system.ruby.L1Cache_Controller.S.L1_Replacement | 145 12.97% 12.97% | 146 13.06% 26.03% | 137 12.25% 38.28% | 150 13.42% 51.70% | 115 10.29% 61.99% | 141 12.61% 74.60% | 138 12.34% 86.94% | 146 13.06% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1118 -system.ruby.L1Cache_Controller.E.Load | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 2 -system.ruby.L1Cache_Controller.E.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 2 -system.ruby.L1Cache_Controller.E.Inv | 23183 12.50% 12.50% | 23006 12.41% 24.91% | 23185 12.51% 37.42% | 23247 12.54% 49.96% | 23113 12.47% 62.42% | 23151 12.49% 74.91% | 23303 12.57% 87.48% | 23217 12.52% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 185405 -system.ruby.L1Cache_Controller.E.L1_Replacement | 26458 12.64% 12.64% | 26505 12.66% 25.30% | 26463 12.64% 37.94% | 25998 12.42% 50.36% | 26145 12.49% 62.85% | 26083 12.46% 75.31% | 25787 12.32% 87.63% | 25906 12.37% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 209345 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 55 11.63% 11.63% | 61 12.90% 24.52% | 82 17.34% 41.86% | 45 9.51% 51.37% | 66 13.95% 65.33% | 43 9.09% 74.42% | 62 13.11% 87.53% | 59 12.47% 100.00% +system.ruby.ST.miss_latency_hist::samples 221682 +system.ruby.ST.miss_latency_hist::mean 2071.033142 +system.ruby.ST.miss_latency_hist::gmean 1590.656389 +system.ruby.ST.miss_latency_hist::stdev 1227.143664 +system.ruby.ST.miss_latency_hist | 58649 26.46% 26.46% | 53800 24.27% 50.73% | 52357 23.62% 74.34% | 46852 21.13% 95.48% | 9877 4.46% 99.93% | 147 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 221682 +system.ruby.Directory_Controller.Fetch 617983 0.00% 0.00% +system.ruby.Directory_Controller.Data 221016 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 617980 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 221016 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 396959 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 617983 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 221016 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 396959 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 617980 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 221016 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50178 12.48% 12.48% | 50038 12.45% 24.93% | 50231 12.49% 37.42% | 50088 12.46% 49.88% | 50377 12.53% 62.41% | 50301 12.51% 74.93% | 50175 12.48% 87.41% | 50630 12.59% 100.00% +system.ruby.L1Cache_Controller.Load::total 402018 +system.ruby.L1Cache_Controller.Store | 27650 12.47% 12.47% | 27387 12.35% 24.83% | 27627 12.46% 37.29% | 27913 12.59% 49.88% | 27862 12.57% 62.45% | 27609 12.45% 74.90% | 27807 12.54% 87.44% | 27841 12.56% 100.00% +system.ruby.L1Cache_Controller.Store::total 221696 +system.ruby.L1Cache_Controller.Inv | 75709 12.47% 12.47% | 75402 12.42% 24.89% | 75814 12.49% 37.37% | 75941 12.51% 49.88% | 76137 12.54% 62.42% | 75836 12.49% 74.91% | 76014 12.52% 87.43% | 76329 12.57% 100.00% +system.ruby.L1Cache_Controller.Inv::total 607182 +system.ruby.L1Cache_Controller.L1_Replacement | 551542 12.52% 12.52% | 547463 12.43% 24.96% | 549808 12.48% 37.44% | 549863 12.49% 49.93% | 551618 12.53% 62.45% | 550552 12.50% 74.95% | 550899 12.51% 87.46% | 552114 12.54% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 4403859 +system.ruby.L1Cache_Controller.Fwd_GETX | 227 12.34% 12.34% | 242 13.15% 25.49% | 244 13.26% 38.75% | 236 12.83% 51.58% | 214 11.63% 63.21% | 219 11.90% 75.11% | 224 12.17% 87.28% | 234 12.72% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1840 +system.ruby.L1Cache_Controller.Fwd_GETS | 164 12.75% 12.75% | 163 12.67% 25.43% | 176 13.69% 39.11% | 169 13.14% 52.26% | 153 11.90% 64.15% | 162 12.60% 76.75% | 161 12.52% 89.27% | 138 10.73% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 1286 +system.ruby.L1Cache_Controller.Data | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.Data::total 9 +system.ruby.L1Cache_Controller.Data_Exclusive | 49353 12.47% 12.47% | 49226 12.44% 24.92% | 49455 12.50% 37.42% | 49297 12.46% 49.88% | 49592 12.54% 62.41% | 49499 12.51% 74.92% | 49412 12.49% 87.41% | 49794 12.59% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 395628 +system.ruby.L1Cache_Controller.DataS_fromL1 | 159 12.36% 12.36% | 160 12.44% 24.81% | 147 11.43% 36.24% | 160 12.44% 48.68% | 141 10.96% 59.64% | 142 11.04% 70.68% | 173 13.45% 84.14% | 204 15.86% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 1286 +system.ruby.L1Cache_Controller.Data_all_Acks | 28305 12.48% 12.48% | 28033 12.36% 24.85% | 28250 12.46% 37.30% | 28541 12.59% 49.89% | 28500 12.57% 62.46% | 28265 12.47% 74.92% | 28392 12.52% 87.45% | 28468 12.55% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 226754 +system.ruby.L1Cache_Controller.Ack | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.Ack::total 9 +system.ruby.L1Cache_Controller.Ack_all | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 9 +system.ruby.L1Cache_Controller.WB_Ack | 40511 12.44% 12.44% | 40148 12.33% 24.78% | 40397 12.41% 37.18% | 40704 12.50% 49.69% | 41130 12.63% 62.32% | 40703 12.50% 74.82% | 40662 12.49% 87.31% | 41301 12.69% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 325556 +system.ruby.L1Cache_Controller.NP.Load | 50164 12.48% 12.48% | 50032 12.45% 24.93% | 50223 12.50% 37.42% | 50076 12.46% 49.88% | 50363 12.53% 62.41% | 50292 12.51% 74.93% | 50165 12.48% 87.41% | 50615 12.59% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 401930 +system.ruby.L1Cache_Controller.NP.Store | 27646 12.47% 12.47% | 27381 12.35% 24.83% | 27620 12.46% 37.29% | 27908 12.59% 49.88% | 27857 12.57% 62.45% | 27604 12.45% 74.90% | 27800 12.54% 87.44% | 27836 12.56% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 221652 +system.ruby.L1Cache_Controller.NP.Inv | 222 13.07% 13.07% | 216 12.72% 25.80% | 227 13.37% 39.16% | 217 12.78% 51.94% | 188 11.07% 63.02% | 211 12.43% 75.44% | 216 12.72% 88.16% | 201 11.84% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 1698 +system.ruby.L1Cache_Controller.I.Load | 10 12.99% 12.99% | 5 6.49% 19.48% | 8 10.39% 29.87% | 11 14.29% 44.16% | 13 16.88% 61.04% | 8 10.39% 71.43% | 9 11.69% 83.12% | 13 16.88% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 77 +system.ruby.L1Cache_Controller.I.Store | 3 8.33% 8.33% | 4 11.11% 19.44% | 5 13.89% 33.33% | 4 11.11% 44.44% | 4 11.11% 55.56% | 5 13.89% 69.44% | 6 16.67% 86.11% | 5 13.89% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 36 +system.ruby.L1Cache_Controller.I.L1_Replacement | 37148 12.52% 12.52% | 37103 12.50% 25.02% | 37284 12.56% 37.58% | 37119 12.51% 50.08% | 36952 12.45% 62.53% | 37057 12.48% 75.01% | 37155 12.52% 87.53% | 37007 12.47% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 296825 +system.ruby.L1Cache_Controller.S.Inv | 700 12.82% 12.82% | 698 12.78% 25.60% | 657 12.03% 37.64% | 666 12.20% 49.84% | 683 12.51% 62.34% | 691 12.66% 75.00% | 647 11.85% 86.85% | 718 13.15% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 5460 +system.ruby.L1Cache_Controller.S.L1_Replacement | 145 12.50% 12.50% | 157 13.53% 26.03% | 157 13.53% 39.57% | 156 13.45% 53.02% | 133 11.47% 64.48% | 131 11.29% 75.78% | 143 12.33% 88.10% | 138 11.90% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1160 +system.ruby.L1Cache_Controller.E.Load | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3 +system.ruby.L1Cache_Controller.E.Store | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 3 +system.ruby.L1Cache_Controller.E.Inv | 23165 12.45% 12.45% | 23206 12.47% 24.91% | 23518 12.64% 37.55% | 23248 12.49% 50.04% | 23136 12.43% 62.47% | 23354 12.55% 75.02% | 23312 12.52% 87.54% | 23192 12.46% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 186131 +system.ruby.L1Cache_Controller.E.L1_Replacement | 26108 12.50% 12.50% | 25954 12.42% 24.92% | 25849 12.37% 37.29% | 25977 12.43% 49.72% | 26399 12.63% 62.35% | 26084 12.48% 74.84% | 26041 12.46% 87.30% | 26535 12.70% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 208947 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 70 14.80% 14.80% | 54 11.42% 26.22% | 73 15.43% 41.65% | 64 13.53% 55.18% | 47 9.94% 65.12% | 52 10.99% 76.11% | 52 10.99% 87.10% | 61 12.90% 100.00% system.ruby.L1Cache_Controller.E.Fwd_GETX::total 473 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 7 12.50% 12.50% | 8 14.29% 26.79% | 13 23.21% 50.00% | 7 12.50% 62.50% | 2 3.57% 66.07% | 8 14.29% 80.36% | 6 10.71% 91.07% | 5 8.93% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 56 -system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 1 -system.ruby.L1Cache_Controller.M.Inv | 13073 12.55% 12.55% | 13053 12.53% 25.08% | 13069 12.55% 37.63% | 13057 12.54% 50.17% | 12943 12.43% 62.59% | 13016 12.50% 75.09% | 12973 12.46% 87.55% | 12971 12.45% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 104155 -system.ruby.L1Cache_Controller.M.L1_Replacement | 14723 12.62% 12.62% | 14590 12.50% 25.12% | 14535 12.46% 37.58% | 14715 12.61% 50.19% | 14444 12.38% 62.56% | 14571 12.49% 75.05% | 14650 12.55% 87.60% | 14464 12.40% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 116692 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 32 12.75% 12.75% | 33 13.15% 25.90% | 27 10.76% 36.65% | 34 13.55% 50.20% | 35 13.94% 64.14% | 22 8.76% 72.91% | 37 14.74% 87.65% | 31 12.35% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 251 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 59 12.97% 12.97% | 50 10.99% 23.96% | 49 10.77% 34.73% | 60 13.19% 47.91% | 47 10.33% 58.24% | 63 13.85% 72.09% | 65 14.29% 86.37% | 62 13.63% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 455 -system.ruby.L1Cache_Controller.IS.Inv | 43 14.29% 14.29% | 42 13.95% 28.24% | 41 13.62% 41.86% | 42 13.95% 55.81% | 40 13.29% 69.10% | 37 12.29% 81.40% | 27 8.97% 90.37% | 29 9.63% 100.00% -system.ruby.L1Cache_Controller.IS.Inv::total 301 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 304064 12.49% 12.49% | 304172 12.50% 24.99% | 306684 12.60% 37.59% | 302971 12.45% 50.03% | 304022 12.49% 62.52% | 303629 12.47% 74.99% | 303562 12.47% 87.47% | 305131 12.53% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2434235 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49704 12.57% 12.57% | 49580 12.54% 25.12% | 49744 12.58% 37.70% | 49297 12.47% 50.17% | 49326 12.48% 62.65% | 49286 12.47% 75.12% | 49158 12.44% 87.56% | 49187 12.44% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 395282 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 145 11.82% 11.82% | 148 12.06% 23.88% | 165 13.45% 37.33% | 168 13.69% 51.02% | 139 11.33% 62.35% | 164 13.37% 75.71% | 161 13.12% 88.83% | 137 11.17% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1227 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 570 11.96% 11.96% | 606 12.72% 24.69% | 614 12.89% 37.57% | 627 13.16% 50.73% | 572 12.01% 62.74% | 614 12.89% 75.63% | 617 12.95% 88.58% | 544 11.42% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4764 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 167965 12.51% 12.51% | 168119 12.52% 25.02% | 166558 12.40% 37.42% | 169005 12.58% 50.01% | 167246 12.45% 62.46% | 168087 12.51% 74.97% | 169524 12.62% 87.59% | 166627 12.41% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1343131 -system.ruby.L1Cache_Controller.IM.Data | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 15 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27885 12.59% 12.59% | 27721 12.51% 25.10% | 27678 12.49% 37.59% | 27863 12.58% 50.17% | 27469 12.40% 62.57% | 27670 12.49% 75.06% | 27723 12.51% 87.57% | 27528 12.43% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 221537 -system.ruby.L1Cache_Controller.SM.Ack | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 15 -system.ruby.L1Cache_Controller.SM.Ack_all | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 15 -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 43 14.29% 14.29% | 42 13.95% 28.24% | 41 13.62% 41.86% | 42 13.95% 55.81% | 40 13.29% 69.10% | 37 12.29% 81.40% | 27 8.97% 90.37% | 29 9.63% 100.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 301 -system.ruby.L1Cache_Controller.M_I.Inv | 39119 12.59% 12.59% | 39097 12.58% 25.17% | 39212 12.62% 37.78% | 38822 12.49% 50.27% | 38731 12.46% 62.73% | 38817 12.49% 75.22% | 38456 12.37% 87.60% | 38549 12.40% 100.00% -system.ruby.L1Cache_Controller.M_I.Inv::total 310803 -system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 161 15.48% 15.48% | 143 13.75% 29.23% | 105 10.10% 39.33% | 127 12.21% 51.54% | 128 12.31% 63.85% | 119 11.44% 75.29% | 141 13.56% 88.85% | 116 11.15% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1040 -system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 107 14.94% 14.94% | 102 14.25% 29.19% | 91 12.71% 41.90% | 73 10.20% 52.09% | 87 12.15% 64.25% | 87 12.15% 76.40% | 80 11.17% 87.57% | 89 12.43% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 716 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 1794 13.31% 13.31% | 1753 13.01% 26.32% | 1590 11.80% 38.11% | 1691 12.55% 50.66% | 1643 12.19% 62.85% | 1631 12.10% 74.95% | 1760 13.06% 88.01% | 1616 11.99% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 13478 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 2 33.33% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 6 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 4 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 30 15.46% 15.46% | 29 14.95% 30.41% | 28 14.43% 44.85% | 18 9.28% 54.12% | 19 9.79% 63.92% | 25 12.89% 76.80% | 21 10.82% 87.63% | 24 12.37% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 194 -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 39384 12.60% 12.60% | 39340 12.59% 25.19% | 39407 12.61% 37.80% | 39022 12.49% 50.28% | 38944 12.46% 62.74% | 39022 12.49% 75.23% | 38675 12.37% 87.60% | 38753 12.40% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 312547 -system.ruby.L2Cache_Controller.L1_GETS 403170 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 223814 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 15467 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 317914 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 6156 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 4979199 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 617573 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 617568 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 216108 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 200077 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 3751 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 189142 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 1227 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 616832 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 397804 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 219774 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 308614 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 7 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 15 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX 527 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 1153 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2585 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 4818 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8651 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 1227 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 1764 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 13478 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX_old 808 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 6 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 600357 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETS 25 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETX 20 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 2036 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 617568 0.00% 0.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS | 9 12.50% 12.50% | 10 13.89% 26.39% | 14 19.44% 45.83% | 8 11.11% 56.94% | 9 12.50% 69.44% | 9 12.50% 81.94% | 7 9.72% 91.67% | 6 8.33% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 72 +system.ruby.L1Cache_Controller.M.Load | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 3 +system.ruby.L1Cache_Controller.M.Inv | 13157 12.61% 12.61% | 13076 12.54% 25.15% | 12978 12.44% 37.59% | 13085 12.55% 50.14% | 13028 12.49% 62.63% | 12904 12.37% 75.00% | 13083 12.54% 87.54% | 12992 12.46% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 104303 +system.ruby.L1Cache_Controller.M.L1_Replacement | 14405 12.35% 12.35% | 14195 12.17% 24.52% | 14549 12.48% 37.00% | 14728 12.63% 49.63% | 14732 12.63% 62.26% | 14620 12.54% 74.80% | 14622 12.54% 87.34% | 14767 12.66% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 116618 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 27 9.96% 9.96% | 47 17.34% 27.31% | 32 11.81% 39.11% | 31 11.44% 50.55% | 35 12.92% 63.47% | 32 11.81% 75.28% | 37 13.65% 88.93% | 30 11.07% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 271 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 61 12.37% 12.37% | 67 13.59% 25.96% | 66 13.39% 39.35% | 67 13.59% 52.94% | 66 13.39% 66.33% | 53 10.75% 77.08% | 62 12.58% 89.66% | 51 10.34% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 493 +system.ruby.L1Cache_Controller.IS.Inv | 44 14.10% 14.10% | 32 10.26% 24.36% | 40 12.82% 37.18% | 43 13.78% 50.96% | 40 12.82% 63.78% | 39 12.50% 76.28% | 40 12.82% 89.10% | 34 10.90% 100.00% +system.ruby.L1Cache_Controller.IS.Inv::total 312 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 304930 12.52% 12.52% | 304677 12.51% 25.03% | 304555 12.50% 37.53% | 302791 12.43% 49.96% | 304661 12.51% 62.47% | 304322 12.49% 74.97% | 304505 12.50% 87.47% | 305212 12.53% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2435653 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49353 12.47% 12.47% | 49226 12.44% 24.92% | 49455 12.50% 37.42% | 49297 12.46% 49.88% | 49592 12.54% 62.41% | 49499 12.51% 74.92% | 49412 12.49% 87.41% | 49794 12.59% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 395628 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 159 12.36% 12.36% | 160 12.44% 24.81% | 147 11.43% 36.24% | 160 12.44% 48.68% | 141 10.96% 59.64% | 142 11.04% 70.68% | 173 13.45% 84.14% | 204 15.86% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1286 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 616 12.92% 12.92% | 618 12.96% 25.88% | 587 12.31% 38.18% | 587 12.31% 50.49% | 600 12.58% 63.07% | 618 12.96% 76.03% | 548 11.49% 87.52% | 595 12.48% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4769 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 168806 12.55% 12.55% | 165377 12.30% 24.85% | 167414 12.45% 37.30% | 169092 12.58% 49.88% | 168741 12.55% 62.43% | 168337 12.52% 74.95% | 168433 12.53% 87.47% | 168454 12.53% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1344654 +system.ruby.L1Cache_Controller.IM.Data | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 9 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27645 12.47% 12.47% | 27383 12.35% 24.82% | 27623 12.46% 37.29% | 27911 12.59% 49.88% | 27860 12.57% 62.44% | 27608 12.45% 74.90% | 27804 12.54% 87.44% | 27839 12.56% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 221673 +system.ruby.L1Cache_Controller.SM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.SM.L1_Replacement::total 1 +system.ruby.L1Cache_Controller.SM.Ack | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 9 +system.ruby.L1Cache_Controller.SM.Ack_all | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 9 +system.ruby.L1Cache_Controller.IS_I.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_I.L1_Replacement::total 1 +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 44 14.10% 14.10% | 32 10.26% 24.36% | 40 12.82% 37.18% | 43 13.78% 50.96% | 40 12.82% 63.78% | 39 12.50% 76.28% | 40 12.82% 89.10% | 34 10.90% 100.00% +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 312 +system.ruby.L1Cache_Controller.M_I.Inv | 38404 12.42% 12.42% | 38147 12.34% 24.77% | 38368 12.41% 37.18% | 38649 12.50% 49.68% | 39039 12.63% 62.31% | 38617 12.49% 74.81% | 38697 12.52% 87.33% | 39174 12.67% 100.00% +system.ruby.L1Cache_Controller.M_I.Inv::total 309095 +system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 130 11.86% 11.86% | 141 12.86% 24.73% | 139 12.68% 37.41% | 141 12.86% 50.27% | 132 12.04% 62.32% | 135 12.32% 74.64% | 135 12.32% 86.95% | 143 13.05% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1096 +system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 94 13.04% 13.04% | 86 11.93% 24.97% | 96 13.31% 38.28% | 94 13.04% 51.32% | 78 10.82% 62.14% | 100 13.87% 76.01% | 92 12.76% 88.77% | 81 11.23% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 721 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 1885 12.86% 12.86% | 1775 12.11% 24.98% | 1795 12.25% 37.23% | 1821 12.43% 49.66% | 1882 12.84% 62.50% | 1852 12.64% 75.14% | 1739 11.87% 87.01% | 1904 12.99% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 14653 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 5 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 5 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 17 9.29% 9.29% | 27 14.75% 24.04% | 26 14.21% 38.25% | 33 18.03% 56.28% | 23 12.57% 68.85% | 20 10.93% 79.78% | 19 10.38% 90.16% | 18 9.84% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 183 +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 38626 12.42% 12.42% | 38373 12.34% 24.77% | 38602 12.42% 37.18% | 38883 12.51% 49.69% | 39248 12.62% 62.31% | 38851 12.50% 74.81% | 38923 12.52% 87.33% | 39397 12.67% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 310903 +system.ruby.L2Cache_Controller.L1_GETS 403619 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 224049 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 16718 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 316360 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 6791 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 4927098 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 617978 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 617975 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 215635 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 199049 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 3824 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 189942 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 1286 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 617309 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 398157 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 219826 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_PUTX_old 306767 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 3 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 9 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX 543 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX_old 5 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 1199 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2612 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 10 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 5381 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 9254 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 1286 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 1840 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 14653 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX_old 832 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 7 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 599522 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETS 21 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETX 13 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 2174 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 617975 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.WB_Data 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETS 53 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETX 65 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 5892 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 214948 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 200006 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 185402 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 2592 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 2585 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 1159 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 1153 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETS 2526 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETX 1358 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 290 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2188495 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 395276 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETX 8 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14199 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 2526 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETS 1376 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETX 726 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_PUTX_old 271 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1222032 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 219771 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETS 62 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETX 79 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 5995 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 214429 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 198965 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 186128 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 2623 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 2612 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 1201 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 1199 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETS 2534 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETX 1425 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 281 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2159388 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 395619 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETS 10 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETX 5 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_PUTX_old 1 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14164 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 2534 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETS 1405 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETX 765 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_PUTX_old 299 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1198508 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 219825 0.00% 0.00% system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L2_Replacement 20 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 21 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 15 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 135 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 77 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 875 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 10 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 9 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 129 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 76 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 921 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 939983 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 616817 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 585 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2874 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 956 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 45 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 226 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 940845 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 617300 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 598 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2788 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 1020 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 64 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 202 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.L1_PUTX 1 0.00% 0.00% system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 200 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 26 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 159 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 1001 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 617577 0.00% 0.00% -system.ruby.Directory_Controller.Data 220925 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 617573 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220924 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 396644 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 617577 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 220925 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 396644 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 617573 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 220924 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 182 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 20 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 204 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.L2_Replacement_clean 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 1084 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index f39ff9113..d7e27dd2b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007458 # Number of seconds simulated -sim_ticks 7457946 # Number of ticks simulated -final_tick 7457946 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007401 # Number of seconds simulated +sim_ticks 7400590 # Number of ticks simulated +final_tick 7400590 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 41657 # Simulator tick rate (ticks/s) -host_mem_usage 653376 # Number of bytes of host memory used -host_seconds 179.03 # Real time elapsed on the host +host_tick_rate 58553 # Simulator tick rate (ticks/s) +host_mem_usage 666564 # Number of bytes of host memory used +host_seconds 126.39 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39482368 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39482368 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14237568 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14237568 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 616912 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 616912 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 222462 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 222462 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 5294000252 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 5294000252 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1909046807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1909046807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 7203047059 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 7203047059 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 616927 # Number of read requests accepted -system.mem_ctrls.writeReqs 222462 # Number of write requests accepted -system.mem_ctrls.readBursts 616927 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 222462 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39007104 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 475904 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14151616 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39483328 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14237568 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 7436 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 1325 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39203584 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39203584 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14074880 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14074880 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 612556 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 612556 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 219920 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 219920 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 5297359265 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 5297359265 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1901859176 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1901859176 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 7199218441 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 7199218441 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 612559 # Number of read requests accepted +system.mem_ctrls.writeReqs 219920 # Number of write requests accepted +system.mem_ctrls.readBursts 612559 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 219920 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38724800 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 478976 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 13992640 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39203776 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14074880 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 7484 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 1262 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 75997 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76905 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76170 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76019 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 75858 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76406 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76286 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 75845 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 75565 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 75507 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76076 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 75946 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 75488 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 75399 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 75818 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 75276 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27808 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27927 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27526 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27488 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27638 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27575 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27643 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27514 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27473 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27140 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27430 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27423 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27483 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27208 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27363 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27115 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,53 +69,53 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 7457887 # Total gap between requests +system.mem_ctrls.totGap 7400487 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 616927 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 612559 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 222462 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 30785 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 21417 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 21169 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 21106 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 21067 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 21112 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 21130 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 21129 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 21188 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 21211 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 21220 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 21236 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 21233 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 21196 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 21132 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 21007 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 20933 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 20875 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 21426 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 23339 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 20555 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 20518 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 20705 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 21149 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 19529 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 18708 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 17249 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 14885 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 11036 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 6781 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 2902 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 563 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 219920 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 30831 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 21254 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 20948 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 20951 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 20894 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 20888 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 20929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 20953 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 20953 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 20973 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 20986 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 20998 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 20977 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 20956 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 20940 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 20847 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 20708 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 20691 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 21299 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 23250 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 20406 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 20378 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 20586 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 21073 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 19388 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 18654 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 17262 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 14777 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 11043 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 6825 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 2889 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 568 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -131,47 +131,47 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1529 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1663 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 3055 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 4436 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 5840 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 7225 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 8222 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 9323 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 10222 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 11114 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 12954 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 44895 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 22469 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 13951 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 13809 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 13803 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 13701 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 13656 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1751 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1073 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 890 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 790 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 716 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 641 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 579 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 510 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 451 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 388 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 333 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 278 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 218 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 164 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 108 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 75 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 31 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 10 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1641 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1745 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 3102 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 4476 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 5873 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 7246 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 8278 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9308 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 10171 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 11061 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 12833 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 43856 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 22169 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 13787 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 13661 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 13451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 13517 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 13521 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1702 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 974 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 819 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 750 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 676 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 605 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 553 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 493 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 434 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 386 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 321 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 269 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 227 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 188 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 157 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 119 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 90 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 29 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 18 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -180,1252 +180,1253 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 217842 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 244.021557 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 202.580834 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 149.489115 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 27613 12.68% 12.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 89630 41.14% 53.82% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 57317 26.31% 80.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 26502 12.17% 92.30% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10866 4.99% 97.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3972 1.82% 99.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1352 0.62% 99.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 417 0.19% 99.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 173 0.08% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 217842 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13342 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 45.679808 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 42.663864 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 16.154073 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 18 0.13% 0.13% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 31 0.23% 0.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 117 0.88% 1.24% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 4821 36.13% 37.38% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 1382 10.36% 47.74% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 232 1.74% 49.48% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 691 5.18% 54.65% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 5358 40.16% 94.81% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 326 2.44% 97.26% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 80 0.60% 97.86% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 158 1.18% 99.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 122 0.91% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 3 0.02% 99.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::104-111 1 0.01% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 1 0.01% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::136-143 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13342 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13342 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.573152 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.530670 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.263681 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 10409 78.02% 78.02% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 467 3.50% 81.52% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1126 8.44% 89.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 874 6.55% 96.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 256 1.92% 98.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 115 0.86% 99.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 50 0.37% 99.66% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 22 0.16% 99.83% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 5 0.04% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 5 0.04% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 3 0.02% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 2 0.01% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 2 0.01% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 2 0.01% 99.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 1 0.01% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 2 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13342 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 70548774 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 82129008 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3047430 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 115.75 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 216410 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 243.595398 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 202.266425 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 149.425218 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 27460 12.69% 12.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 89166 41.20% 53.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 57358 26.50% 80.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 25806 11.92% 92.32% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10676 4.93% 97.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3981 1.84% 99.09% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1348 0.62% 99.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 415 0.19% 99.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 200 0.09% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 216410 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13179 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 45.909705 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 42.812250 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 16.207292 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 27 0.20% 0.20% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 28 0.21% 0.42% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 98 0.74% 1.16% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 4703 35.69% 36.85% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 1350 10.24% 47.09% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 197 1.49% 48.58% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 669 5.08% 53.66% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 5402 40.99% 94.65% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 338 2.56% 97.22% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 90 0.68% 97.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 138 1.05% 98.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 137 1.04% 99.98% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::168-175 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 13179 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13179 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.589650 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.545210 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.294736 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 10247 77.75% 77.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 437 3.32% 81.07% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1119 8.49% 89.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 908 6.89% 96.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 245 1.86% 98.31% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 119 0.90% 99.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 43 0.33% 99.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 23 0.17% 99.71% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 15 0.11% 99.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 8 0.06% 99.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 5 0.04% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 4 0.03% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 3 0.02% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 1 0.01% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 1 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13179 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 69321327 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 80817752 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3025375 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 114.57 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 134.75 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 5230.27 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1897.52 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 5294.13 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1909.05 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 133.57 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 5232.66 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1890.75 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 5297.39 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1901.86 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 55.69 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 40.86 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 14.82 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 20.86 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 27.80 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 398151 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 214607 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 65.33 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.05 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 8.88 # Average gap between requests -system.mem_ctrls.pageHitRate 73.77 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 85 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 248820 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 7202571 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1645418880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 914121600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7599408960 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2290332672 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 486691920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 486691920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 5077598076 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 161028648 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 16843800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 4329624000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 18030415908 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 4977344568 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 2419.715206 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.968859 # Core power per rank (mW) +system.mem_ctrls.busUtil 55.65 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 40.88 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 14.77 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 20.94 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 27.75 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 395351 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 211942 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 65.34 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 96.93 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 8.89 # Average gap between requests +system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1635250680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 908472600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7547392320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2265584256 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 483132000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5041113516 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 16166400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 17897111772 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2419.511790 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 159 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 247000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7149848 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 483132000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 159850800 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4297947600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 4940930400 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.968970 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7149960 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 247000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 99122 # number of read accesses completed +system.cpu0.num_writes 55082 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 98934 # number of read accesses completed +system.cpu1.num_writes 54848 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 98977 # number of read accesses completed +system.cpu2.num_writes 54560 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99417 # number of read accesses completed +system.cpu3.num_writes 55431 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 54903 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 98481 # number of read accesses completed +system.cpu5.num_writes 55109 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 98951 # number of read accesses completed +system.cpu6.num_writes 54779 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 98318 # number of read accesses completed +system.cpu7.num_writes 55002 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 628341 -system.ruby.outstanding_req_hist::mean 15.998455 -system.ruby.outstanding_req_hist::gmean 15.997193 -system.ruby.outstanding_req_hist::stdev 0.125709 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 27 0.00% 0.02% | 628210 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 628341 +system.ruby.outstanding_req_hist::samples 623953 +system.ruby.outstanding_req_hist::mean 15.998445 +system.ruby.outstanding_req_hist::gmean 15.997175 +system.ruby.outstanding_req_hist::stdev 0.126144 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 26 0.00% 0.02% | 623823 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 623953 system.ruby.latency_hist::bucket_size 2048 system.ruby.latency_hist::max_bucket 20479 -system.ruby.latency_hist::samples 628213 -system.ruby.latency_hist::mean 1519.280787 -system.ruby.latency_hist::gmean 1022.681311 -system.ruby.latency_hist::stdev 1497.288069 -system.ruby.latency_hist | 474914 75.60% 75.60% | 109593 17.45% 93.04% | 31707 5.05% 98.09% | 9100 1.45% 99.54% | 2263 0.36% 99.90% | 512 0.08% 99.98% | 107 0.02% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 628213 +system.ruby.latency_hist::samples 623825 +system.ruby.latency_hist::mean 1518.158580 +system.ruby.latency_hist::gmean 1023.158557 +system.ruby.latency_hist::stdev 1495.268071 +system.ruby.latency_hist | 471692 75.61% 75.61% | 109137 17.49% 93.11% | 31197 5.00% 98.11% | 8878 1.42% 99.53% | 2243 0.36% 99.89% | 516 0.08% 99.97% | 127 0.02% 99.99% | 29 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.latency_hist::total 623825 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 119 +system.ruby.hit_latency_hist::samples 108 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 119 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 119 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 108 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 108 system.ruby.miss_latency_hist::bucket_size 2048 system.ruby.miss_latency_hist::max_bucket 20479 -system.ruby.miss_latency_hist::samples 628094 -system.ruby.miss_latency_hist::mean 1519.568065 -system.ruby.miss_latency_hist::gmean 1023.811857 -system.ruby.miss_latency_hist::stdev 1497.284420 -system.ruby.miss_latency_hist | 474795 75.59% 75.59% | 109593 17.45% 93.04% | 31707 5.05% 98.09% | 9100 1.45% 99.54% | 2263 0.36% 99.90% | 512 0.08% 99.98% | 107 0.02% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 628094 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78541 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78555 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl5.L1Dcache.demand_hits 10 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78462 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78472 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78462 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78476 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 13 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78239 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78252 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 18 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78680 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78698 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 623717 +system.ruby.miss_latency_hist::mean 1518.420938 +system.ruby.miss_latency_hist::gmean 1024.192315 +system.ruby.miss_latency_hist::stdev 1495.264581 +system.ruby.miss_latency_hist | 471584 75.61% 75.61% | 109137 17.50% 93.11% | 31197 5.00% 98.11% | 8878 1.42% 99.53% | 2243 0.36% 99.89% | 516 0.08% 99.97% | 127 0.02% 99.99% | 29 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.miss_latency_hist::total 623717 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 12 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78021 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78033 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers00.percent_links_utilized 5.803900 -system.ruby.network.routers00.msg_count.Request_Control::0 78680 -system.ruby.network.routers00.msg_count.Response_Data::2 77269 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 563 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 1686 -system.ruby.network.routers00.msg_count.Response_Control::2 613 -system.ruby.network.routers00.msg_count.Writeback_Data::2 77627 -system.ruby.network.routers00.msg_count.Writeback_Control::0 157289 -system.ruby.network.routers00.msg_count.Forwarded_Control::0 842 -system.ruby.network.routers00.msg_count.Invalidate_Control::0 233 -system.ruby.network.routers00.msg_count.Unblock_Control::2 79445 -system.ruby.network.routers00.msg_bytes.Request_Control::0 629440 -system.ruby.network.routers00.msg_bytes.Response_Data::2 5563368 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2 40536 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2 121392 -system.ruby.network.routers00.msg_bytes.Response_Control::2 4904 -system.ruby.network.routers00.msg_bytes.Writeback_Data::2 5589144 -system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1258312 -system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6736 -system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1864 -system.ruby.network.routers00.msg_bytes.Unblock_Control::2 635560 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78726 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78743 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 11 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 77929 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77940 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers01.percent_links_utilized 5.806223 -system.ruby.network.routers01.msg_count.Request_Control::0 78726 -system.ruby.network.routers01.msg_count.Response_Data::2 77263 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 617 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 1711 -system.ruby.network.routers01.msg_count.Response_Control::2 606 -system.ruby.network.routers01.msg_count.Writeback_Data::2 77607 -system.ruby.network.routers01.msg_count.Writeback_Control::0 157340 -system.ruby.network.routers01.msg_count.Forwarded_Control::0 868 -system.ruby.network.routers01.msg_count.Invalidate_Control::0 238 -system.ruby.network.routers01.msg_count.Unblock_Control::2 79540 -system.ruby.network.routers01.msg_bytes.Request_Control::0 629808 -system.ruby.network.routers01.msg_bytes.Response_Data::2 5562936 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 44424 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 123192 -system.ruby.network.routers01.msg_bytes.Response_Control::2 4848 -system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5587704 -system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1258720 -system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 6944 -system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1904 -system.ruby.network.routers01.msg_bytes.Unblock_Control::2 636320 -system.ruby.l1_cntrl2.L1Dcache.demand_hits 13 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78492 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78505 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 11 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 77932 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77943 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers02.percent_links_utilized 5.789942 -system.ruby.network.routers02.msg_count.Request_Control::0 78492 -system.ruby.network.routers02.msg_count.Response_Data::2 77126 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 556 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 1605 -system.ruby.network.routers02.msg_count.Response_Control::2 583 -system.ruby.network.routers02.msg_count.Writeback_Data::2 77494 -system.ruby.network.routers02.msg_count.Writeback_Control::0 156900 -system.ruby.network.routers02.msg_count.Forwarded_Control::0 799 -system.ruby.network.routers02.msg_count.Invalidate_Control::0 212 -system.ruby.network.routers02.msg_count.Unblock_Control::2 79228 -system.ruby.network.routers02.msg_bytes.Request_Control::0 627936 -system.ruby.network.routers02.msg_bytes.Response_Data::2 5553072 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 40032 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 115560 -system.ruby.network.routers02.msg_bytes.Response_Control::2 4664 -system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5579568 -system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1255200 -system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 6392 -system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 1696 -system.ruby.network.routers02.msg_bytes.Unblock_Control::2 633824 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78519 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78539 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 14 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78185 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78199 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers03.percent_links_utilized 5.790190 -system.ruby.network.routers03.msg_count.Request_Control::0 78519 -system.ruby.network.routers03.msg_count.Response_Data::2 77107 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2 585 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::2 1603 -system.ruby.network.routers03.msg_count.Response_Control::2 633 -system.ruby.network.routers03.msg_count.Writeback_Data::2 77472 -system.ruby.network.routers03.msg_count.Writeback_Control::0 156964 -system.ruby.network.routers03.msg_count.Forwarded_Control::0 780 -system.ruby.network.routers03.msg_count.Invalidate_Control::0 230 -system.ruby.network.routers03.msg_count.Unblock_Control::2 79288 -system.ruby.network.routers03.msg_bytes.Request_Control::0 628152 -system.ruby.network.routers03.msg_bytes.Response_Data::2 5551704 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2 42120 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2 115416 -system.ruby.network.routers03.msg_bytes.Response_Control::2 5064 -system.ruby.network.routers03.msg_bytes.Writeback_Data::2 5577984 -system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1255712 -system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 6240 -system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 1840 -system.ruby.network.routers03.msg_bytes.Unblock_Control::2 634304 -system.ruby.network.routers04.percent_links_utilized 5.794310 -system.ruby.network.routers04.msg_count.Request_Control::0 78541 -system.ruby.network.routers04.msg_count.Response_Data::2 77149 -system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2 567 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 1664 -system.ruby.network.routers04.msg_count.Response_Control::2 595 -system.ruby.network.routers04.msg_count.Writeback_Data::2 77514 -system.ruby.network.routers04.msg_count.Writeback_Control::0 157002 -system.ruby.network.routers04.msg_count.Forwarded_Control::0 842 -system.ruby.network.routers04.msg_count.Invalidate_Control::0 213 -system.ruby.network.routers04.msg_count.Unblock_Control::2 79307 -system.ruby.network.routers04.msg_bytes.Request_Control::0 628328 -system.ruby.network.routers04.msg_bytes.Response_Data::2 5554728 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 40824 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 119808 -system.ruby.network.routers04.msg_bytes.Response_Control::2 4760 -system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5581008 -system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1256016 -system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 6736 -system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 1704 -system.ruby.network.routers04.msg_bytes.Unblock_Control::2 634456 -system.ruby.network.routers05.percent_links_utilized 5.786489 -system.ruby.network.routers05.msg_count.Request_Control::0 78462 -system.ruby.network.routers05.msg_count.Response_Data::2 77063 -system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2 543 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::2 1668 -system.ruby.network.routers05.msg_count.Response_Control::2 630 -system.ruby.network.routers05.msg_count.Writeback_Data::2 77392 -system.ruby.network.routers05.msg_count.Writeback_Control::0 156838 -system.ruby.network.routers05.msg_count.Forwarded_Control::0 816 -system.ruby.network.routers05.msg_count.Invalidate_Control::0 227 -system.ruby.network.routers05.msg_count.Unblock_Control::2 79246 -system.ruby.network.routers05.msg_bytes.Request_Control::0 627696 -system.ruby.network.routers05.msg_bytes.Response_Data::2 5548536 -system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2 39096 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2 120096 -system.ruby.network.routers05.msg_bytes.Response_Control::2 5040 -system.ruby.network.routers05.msg_bytes.Writeback_Data::2 5572224 -system.ruby.network.routers05.msg_bytes.Writeback_Control::0 1254704 -system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 6528 -system.ruby.network.routers05.msg_bytes.Invalidate_Control::0 1816 -system.ruby.network.routers05.msg_bytes.Unblock_Control::2 633968 -system.ruby.network.routers06.percent_links_utilized 5.788672 -system.ruby.network.routers06.msg_count.Request_Control::0 78462 -system.ruby.network.routers06.msg_count.Response_Data::2 77081 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2 586 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::2 1642 -system.ruby.network.routers06.msg_count.Response_Control::2 600 -system.ruby.network.routers06.msg_count.Writeback_Data::2 77437 -system.ruby.network.routers06.msg_count.Writeback_Control::0 156820 -system.ruby.network.routers06.msg_count.Forwarded_Control::0 849 -system.ruby.network.routers06.msg_count.Invalidate_Control::0 221 -system.ruby.network.routers06.msg_count.Unblock_Control::2 79201 -system.ruby.network.routers06.msg_bytes.Request_Control::0 627696 -system.ruby.network.routers06.msg_bytes.Response_Data::2 5549832 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2 42192 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2 118224 -system.ruby.network.routers06.msg_bytes.Response_Control::2 4800 -system.ruby.network.routers06.msg_bytes.Writeback_Data::2 5575464 -system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1254560 -system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 6792 -system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 1768 -system.ruby.network.routers06.msg_bytes.Unblock_Control::2 633608 -system.ruby.network.routers07.percent_links_utilized 5.769735 -system.ruby.network.routers07.msg_count.Request_Control::0 78239 -system.ruby.network.routers07.msg_count.Response_Data::2 76843 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2 556 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::2 1661 -system.ruby.network.routers07.msg_count.Response_Control::2 611 -system.ruby.network.routers07.msg_count.Writeback_Data::2 77149 -system.ruby.network.routers07.msg_count.Writeback_Control::0 156380 -system.ruby.network.routers07.msg_count.Forwarded_Control::0 824 -system.ruby.network.routers07.msg_count.Invalidate_Control::0 247 -system.ruby.network.routers07.msg_count.Unblock_Control::2 79033 -system.ruby.network.routers07.msg_bytes.Request_Control::0 625912 -system.ruby.network.routers07.msg_bytes.Response_Data::2 5532696 -system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2 40032 -system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2 119592 -system.ruby.network.routers07.msg_bytes.Response_Control::2 4888 -system.ruby.network.routers07.msg_bytes.Writeback_Data::2 5554728 -system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1251040 -system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 6592 -system.ruby.network.routers07.msg_bytes.Invalidate_Control::0 1976 -system.ruby.network.routers07.msg_bytes.Unblock_Control::2 632264 -system.ruby.l2_cntrl0.L2cache.demand_hits 4573 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 623547 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 628120 # Number of cache demand accesses -system.ruby.network.routers08.percent_links_utilized 76.868118 -system.ruby.network.routers08.msg_count.Request_Control::0 628120 -system.ruby.network.routers08.msg_count.Request_Control::1 616927 -system.ruby.network.routers08.msg_count.Response_Data::2 1233805 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2 4573 -system.ruby.network.routers08.msg_count.Response_Control::2 1229 -system.ruby.network.routers08.msg_count.Writeback_Data::2 842154 -system.ruby.network.routers08.msg_count.Writeback_Control::0 1255532 -system.ruby.network.routers08.msg_count.Writeback_Control::1 444935 -system.ruby.network.routers08.msg_count.Forwarded_Control::0 6620 -system.ruby.network.routers08.msg_count.Invalidate_Control::0 1813 -system.ruby.network.routers08.msg_count.Unblock_Control::2 1251180 -system.ruby.network.routers08.msg_bytes.Request_Control::0 5024960 -system.ruby.network.routers08.msg_bytes.Request_Control::1 4935416 -system.ruby.network.routers08.msg_bytes.Response_Data::2 88833960 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 329256 -system.ruby.network.routers08.msg_bytes.Response_Control::2 9832 -system.ruby.network.routers08.msg_bytes.Writeback_Data::2 60635088 -system.ruby.network.routers08.msg_bytes.Writeback_Control::0 10044256 -system.ruby.network.routers08.msg_bytes.Writeback_Control::1 3559480 -system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 52960 -system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 14504 -system.ruby.network.routers08.msg_bytes.Unblock_Control::2 10009440 -system.ruby.network.routers09.percent_links_utilized 30.950516 -system.ruby.network.routers09.msg_count.Request_Control::1 616927 -system.ruby.network.routers09.msg_count.Response_Data::2 616908 -system.ruby.network.routers09.msg_count.Writeback_Data::2 222462 -system.ruby.network.routers09.msg_count.Writeback_Control::1 444945 -system.ruby.network.routers09.msg_count.Unblock_Control::2 616896 -system.ruby.network.routers09.msg_bytes.Request_Control::1 4935416 -system.ruby.network.routers09.msg_bytes.Response_Data::2 44417376 -system.ruby.network.routers09.msg_bytes.Writeback_Data::2 16017264 -system.ruby.network.routers09.msg_bytes.Writeback_Control::1 3559560 -system.ruby.network.routers09.msg_bytes.Unblock_Control::2 4935168 -system.ruby.network.routers10.percent_links_utilized 15.414795 -system.ruby.network.routers10.msg_count.Request_Control::0 628120 -system.ruby.network.routers10.msg_count.Request_Control::1 616927 -system.ruby.network.routers10.msg_count.Response_Data::2 1233804 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2 4573 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::2 6620 -system.ruby.network.routers10.msg_count.Response_Control::2 3050 -system.ruby.network.routers10.msg_count.Writeback_Data::2 842154 -system.ruby.network.routers10.msg_count.Writeback_Control::0 1255532 -system.ruby.network.routers10.msg_count.Writeback_Control::1 444935 -system.ruby.network.routers10.msg_count.Forwarded_Control::0 6620 -system.ruby.network.routers10.msg_count.Invalidate_Control::0 1821 -system.ruby.network.routers10.msg_count.Unblock_Control::2 1251180 -system.ruby.network.routers10.msg_bytes.Request_Control::0 5024960 -system.ruby.network.routers10.msg_bytes.Request_Control::1 4935416 -system.ruby.network.routers10.msg_bytes.Response_Data::2 88833888 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2 329256 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2 476640 -system.ruby.network.routers10.msg_bytes.Response_Control::2 24400 -system.ruby.network.routers10.msg_bytes.Writeback_Data::2 60635088 -system.ruby.network.routers10.msg_bytes.Writeback_Control::0 10044256 -system.ruby.network.routers10.msg_bytes.Writeback_Control::1 3559480 -system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 52960 -system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 14568 -system.ruby.network.routers10.msg_bytes.Unblock_Control::2 10009440 -system.ruby.network.msg_count.Request_Control 3735142 -system.ruby.network.msg_count.Response_Data 3701418 -system.ruby.network.msg_count.ResponseL2hit_Data 13719 -system.ruby.network.msg_count.ResponseLocal_Data 19860 -system.ruby.network.msg_count.Response_Control 9150 -system.ruby.network.msg_count.Writeback_Data 2526462 -system.ruby.network.msg_count.Writeback_Control 5101412 -system.ruby.network.msg_count.Forwarded_Control 19860 -system.ruby.network.msg_count.Invalidate_Control 5455 -system.ruby.network.msg_count.Unblock_Control 3753544 -system.ruby.network.msg_byte.Request_Control 29881136 -system.ruby.network.msg_byte.Response_Data 266502096 -system.ruby.network.msg_byte.ResponseL2hit_Data 987768 -system.ruby.network.msg_byte.ResponseLocal_Data 1429920 -system.ruby.network.msg_byte.Response_Control 73200 -system.ruby.network.msg_byte.Writeback_Data 181905264 -system.ruby.network.msg_byte.Writeback_Control 40811296 -system.ruby.network.msg_byte.Forwarded_Control 158880 -system.ruby.network.msg_byte.Invalidate_Control 43640 -system.ruby.network.msg_byte.Unblock_Control 30028352 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 10 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78368 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78378 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 77782 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77799 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 10 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 77715 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77725 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 23 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 77805 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77828 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 4560 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 619174 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 623734 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 99943 # number of read accesses completed -system.cpu0.num_writes 55703 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99615 # number of read accesses completed -system.cpu1.num_writes 55561 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98958 # number of read accesses completed -system.cpu2.num_writes 55524 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99879 # number of read accesses completed -system.cpu3.num_writes 55313 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99950 # number of read accesses completed -system.cpu4.num_writes 55567 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99292 # number of read accesses completed -system.cpu5.num_writes 55606 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 55665 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99277 # number of read accesses completed -system.cpu7.num_writes 55190 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers00.throttle0.link_utilization 5.284183 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 77269 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 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-system.ruby.network.routers10.throttle5.msg_count.Forwarded_Control::0 816 -system.ruby.network.routers10.throttle5.msg_count.Invalidate_Control::0 227 -system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::2 5548536 -system.ruby.network.routers10.throttle5.msg_bytes.ResponseL2hit_Data::2 39096 -system.ruby.network.routers10.throttle5.msg_bytes.ResponseLocal_Data::2 61344 -system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::2 3224 -system.ruby.network.routers10.throttle5.msg_bytes.Writeback_Control::0 627352 -system.ruby.network.routers10.throttle5.msg_bytes.Forwarded_Control::0 6528 -system.ruby.network.routers10.throttle5.msg_bytes.Invalidate_Control::0 1816 -system.ruby.network.routers10.throttle6.link_utilization 5.269541 -system.ruby.network.routers10.throttle6.msg_count.Response_Data::2 77081 -system.ruby.network.routers10.throttle6.msg_count.ResponseL2hit_Data::2 586 -system.ruby.network.routers10.throttle6.msg_count.ResponseLocal_Data::2 793 -system.ruby.network.routers10.throttle6.msg_count.Response_Control::2 379 -system.ruby.network.routers10.throttle6.msg_count.Writeback_Control::0 78410 -system.ruby.network.routers10.throttle6.msg_count.Forwarded_Control::0 849 -system.ruby.network.routers10.throttle6.msg_count.Invalidate_Control::0 221 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::2 5549832 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseL2hit_Data::2 42192 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseLocal_Data::2 57096 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::2 3032 -system.ruby.network.routers10.throttle6.msg_bytes.Writeback_Control::0 627280 -system.ruby.network.routers10.throttle6.msg_bytes.Forwarded_Control::0 6792 -system.ruby.network.routers10.throttle6.msg_bytes.Invalidate_Control::0 1768 -system.ruby.network.routers10.throttle7.link_utilization 5.254456 -system.ruby.network.routers10.throttle7.msg_count.Response_Data::2 76843 -system.ruby.network.routers10.throttle7.msg_count.ResponseL2hit_Data::2 556 -system.ruby.network.routers10.throttle7.msg_count.ResponseLocal_Data::2 837 -system.ruby.network.routers10.throttle7.msg_count.Response_Control::2 364 -system.ruby.network.routers10.throttle7.msg_count.Writeback_Control::0 78190 -system.ruby.network.routers10.throttle7.msg_count.Forwarded_Control::0 824 -system.ruby.network.routers10.throttle7.msg_count.Invalidate_Control::0 247 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::2 5532696 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseL2hit_Data::2 40032 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseLocal_Data::2 60264 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::2 2912 -system.ruby.network.routers10.throttle7.msg_bytes.Writeback_Control::0 625520 -system.ruby.network.routers10.throttle7.msg_bytes.Forwarded_Control::0 6592 -system.ruby.network.routers10.throttle7.msg_bytes.Invalidate_Control::0 1976 -system.ruby.network.routers10.throttle8.link_utilization 88.777694 -system.ruby.network.routers10.throttle8.msg_count.Request_Control::0 628120 -system.ruby.network.routers10.throttle8.msg_count.Response_Data::2 616903 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::2 619692 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0 627766 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::1 222462 -system.ruby.network.routers10.throttle8.msg_count.Unblock_Control::2 634284 -system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::0 5024960 -system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::2 44417016 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::2 44617824 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 5022128 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::1 1779696 -system.ruby.network.routers10.throttle8.msg_bytes.Unblock_Control::2 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1242434 +system.ruby.network.routers08.msg_bytes.Request_Control::0 4989872 +system.ruby.network.routers08.msg_bytes.Request_Control::1 4900472 +system.ruby.network.routers08.msg_bytes.Response_Data::2 88206264 +system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 328320 +system.ruby.network.routers08.msg_bytes.Response_Control::2 9632 +system.ruby.network.routers08.msg_bytes.Writeback_Data::2 60134616 +system.ruby.network.routers08.msg_bytes.Writeback_Control::0 9973920 +system.ruby.network.routers08.msg_bytes.Writeback_Control::1 3518776 +system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 52920 +system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 14640 +system.ruby.network.routers08.msg_bytes.Unblock_Control::2 9939472 +system.ruby.network.routers09.percent_links_utilized 30.933959 +system.ruby.network.routers09.msg_count.Request_Control::1 612559 +system.ruby.network.routers09.msg_count.Response_Data::2 612551 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4560 +system.ruby.network.routers08.throttle1.msg_count.Response_Control::2 1204 +system.ruby.network.routers08.throttle1.msg_count.Writeback_Data::2 219920 +system.ruby.network.routers08.throttle1.msg_count.Writeback_Control::0 623370 +system.ruby.network.routers08.throttle1.msg_count.Writeback_Control::1 219927 +system.ruby.network.routers08.throttle1.msg_count.Forwarded_Control::0 6615 +system.ruby.network.routers08.throttle1.msg_count.Invalidate_Control::0 1830 +system.ruby.network.routers08.throttle1.msg_count.Unblock_Control::2 612534 +system.ruby.network.routers08.throttle1.msg_bytes.Request_Control::1 4900472 +system.ruby.network.routers08.throttle1.msg_bytes.Response_Data::2 44103096 +system.ruby.network.routers08.throttle1.msg_bytes.ResponseL2hit_Data::2 328320 +system.ruby.network.routers08.throttle1.msg_bytes.Response_Control::2 9632 +system.ruby.network.routers08.throttle1.msg_bytes.Writeback_Data::2 15834240 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1759416 +system.ruby.network.routers09.throttle0.msg_bytes.Unblock_Control::2 4900264 +system.ruby.network.routers09.throttle1.link_utilization 38.732608 +system.ruby.network.routers09.throttle1.msg_count.Response_Data::2 612551 +system.ruby.network.routers09.throttle1.msg_count.Writeback_Control::1 219927 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::2 44103672 +system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Control::1 1759416 +system.ruby.network.routers10.throttle0.link_utilization 5.280248 +system.ruby.network.routers10.throttle0.msg_count.Response_Data::2 76543 +system.ruby.network.routers10.throttle0.msg_count.ResponseL2hit_Data::2 614 +system.ruby.network.routers10.throttle0.msg_count.ResponseLocal_Data::2 862 +system.ruby.network.routers10.throttle0.msg_count.Response_Control::2 364 +system.ruby.network.routers10.throttle0.msg_count.Writeback_Control::0 77978 +system.ruby.network.routers10.throttle0.msg_count.Forwarded_Control::0 787 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219927 +system.ruby.network.routers10.throttle9.msg_count.Unblock_Control::2 612533 +system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::1 4900472 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::2 15834240 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::1 1759416 +system.ruby.network.routers10.throttle9.msg_bytes.Unblock_Control::2 4900264 system.ruby.LD.latency_hist::bucket_size 2048 system.ruby.LD.latency_hist::max_bucket 20479 -system.ruby.LD.latency_hist::samples 403736 -system.ruby.LD.latency_hist::mean 1517.424765 -system.ruby.LD.latency_hist::gmean 1020.440366 -system.ruby.LD.latency_hist::stdev 1496.326206 -system.ruby.LD.latency_hist | 305362 75.63% 75.63% | 70366 17.43% 93.06% | 20348 5.04% 98.10% | 5804 1.44% 99.54% | 1436 0.36% 99.90% | 342 0.08% 99.98% | 68 0.02% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 403736 +system.ruby.LD.latency_hist::samples 401957 +system.ruby.LD.latency_hist::mean 1517.986374 +system.ruby.LD.latency_hist::gmean 1021.285101 +system.ruby.LD.latency_hist::stdev 1496.687265 +system.ruby.LD.latency_hist | 304009 75.63% 75.63% | 70241 17.47% 93.11% | 20001 4.98% 98.08% | 5818 1.45% 99.53% | 1467 0.36% 99.90% | 321 0.08% 99.98% | 81 0.02% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 401957 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 89 +system.ruby.LD.hit_latency_hist::samples 84 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 89 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 84 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 84 system.ruby.LD.miss_latency_hist::bucket_size 2048 system.ruby.LD.miss_latency_hist::max_bucket 20479 -system.ruby.LD.miss_latency_hist::samples 403647 -system.ruby.LD.miss_latency_hist::mean 1517.758680 -system.ruby.LD.miss_latency_hist::gmean 1021.752799 -system.ruby.LD.miss_latency_hist::stdev 1496.322154 -system.ruby.LD.miss_latency_hist | 305273 75.63% 75.63% | 70366 17.43% 93.06% | 20348 5.04% 98.10% | 5804 1.44% 99.54% | 1436 0.36% 99.90% | 342 0.08% 99.98% | 68 0.02% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 403647 +system.ruby.LD.miss_latency_hist::samples 401873 +system.ruby.LD.miss_latency_hist::mean 1518.303039 +system.ruby.LD.miss_latency_hist::gmean 1022.530435 +system.ruby.LD.miss_latency_hist::stdev 1496.683383 +system.ruby.LD.miss_latency_hist | 303925 75.63% 75.63% | 70241 17.48% 93.11% | 20001 4.98% 98.08% | 5818 1.45% 99.53% | 1467 0.37% 99.90% | 321 0.08% 99.98% | 81 0.02% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 401873 system.ruby.ST.latency_hist::bucket_size 2048 system.ruby.ST.latency_hist::max_bucket 20479 -system.ruby.ST.latency_hist::samples 224477 -system.ruby.ST.latency_hist::mean 1522.618959 -system.ruby.ST.latency_hist::gmean 1026.724184 -system.ruby.ST.latency_hist::stdev 1499.014037 -system.ruby.ST.latency_hist | 169552 75.53% 75.53% | 39227 17.47% 93.01% | 11359 5.06% 98.07% | 3296 1.47% 99.54% | 827 0.37% 99.90% | 170 0.08% 99.98% | 39 0.02% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 224477 +system.ruby.ST.latency_hist::samples 221868 +system.ruby.ST.latency_hist::mean 1518.470564 +system.ruby.ST.latency_hist::gmean 1026.561445 +system.ruby.ST.latency_hist::stdev 1492.696810 +system.ruby.ST.latency_hist | 167683 75.58% 75.58% | 38896 17.53% 93.11% | 11196 5.05% 98.16% | 3060 1.38% 99.53% | 776 0.35% 99.88% | 195 0.09% 99.97% | 46 0.02% 99.99% | 13 0.01% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 221868 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 30 +system.ruby.ST.hit_latency_hist::samples 24 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 30 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 30 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 24 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 24 system.ruby.ST.miss_latency_hist::bucket_size 2048 system.ruby.ST.miss_latency_hist::max_bucket 20479 -system.ruby.ST.miss_latency_hist::samples 224447 -system.ruby.ST.miss_latency_hist::mean 1522.822074 -system.ruby.ST.miss_latency_hist::gmean 1027.525327 -system.ruby.ST.miss_latency_hist::stdev 1499.011250 -system.ruby.ST.miss_latency_hist | 169522 75.53% 75.53% | 39227 17.48% 93.01% | 11359 5.06% 98.07% | 3296 1.47% 99.54% | 827 0.37% 99.90% | 170 0.08% 99.98% | 39 0.02% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 224447 -system.ruby.L1Cache_Controller.Load | 50543 12.52% 12.52% | 50614 12.53% 25.05% | 50311 12.46% 37.51% | 50685 12.55% 50.06% | 50542 12.52% 62.57% | 50424 12.49% 75.06% | 50331 12.46% 87.52% | 50386 12.48% 100.00% -system.ruby.L1Cache_Controller.Load::total 403836 -system.ruby.L1Cache_Controller.Store | 28185 12.55% 12.55% | 28135 12.53% 25.09% | 28201 12.56% 37.65% | 27871 12.41% 50.06% | 28023 12.48% 62.54% | 28050 12.49% 75.04% | 28175 12.55% 87.59% | 27873 12.41% 100.00% -system.ruby.L1Cache_Controller.Store::total 224513 -system.ruby.L1Cache_Controller.L1_Replacement | 9456290 12.50% 12.50% | 9453861 12.49% 24.99% | 9456743 12.50% 37.49% | 9458000 12.50% 49.99% | 9456358 12.50% 62.49% | 9459066 12.50% 74.99% | 9459283 12.50% 87.49% | 9464648 12.51% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 75664249 -system.ruby.L1Cache_Controller.Fwd_GETX | 149 10.92% 10.92% | 197 14.43% 25.35% | 173 12.67% 38.02% | 174 12.75% 50.77% | 167 12.23% 63.00% | 160 11.72% 74.73% | 162 11.87% 86.59% | 183 13.41% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1365 -system.ruby.L1Cache_Controller.Fwd_GETS | 730 13.05% 13.05% | 740 13.23% 26.27% | 652 11.65% 37.93% | 650 11.62% 49.54% | 717 12.82% 62.36% | 700 12.51% 74.87% | 725 12.96% 87.83% | 681 12.17% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 5595 -system.ruby.L1Cache_Controller.Inv | 233 12.80% 12.80% | 238 13.07% 25.86% | 212 11.64% 37.51% | 230 12.63% 50.14% | 213 11.70% 61.83% | 227 12.47% 74.30% | 221 12.14% 86.44% | 247 13.56% 100.00% -system.ruby.L1Cache_Controller.Inv::total 1821 -system.ruby.L1Cache_Controller.Ack | 380 12.46% 12.46% | 368 12.07% 24.52% | 371 12.16% 36.69% | 403 13.21% 49.90% | 382 12.52% 62.43% | 403 13.21% 75.64% | 379 12.43% 88.07% | 364 11.93% 100.00% -system.ruby.L1Cache_Controller.Ack::total 3050 -system.ruby.L1Cache_Controller.Data | 50306 12.51% 12.51% | 50385 12.53% 25.04% | 50094 12.46% 37.50% | 50490 12.56% 50.05% | 50329 12.52% 62.57% | 50235 12.49% 75.06% | 50131 12.47% 87.52% | 50173 12.48% 100.00% -system.ruby.L1Cache_Controller.Data::total 402143 -system.ruby.L1Cache_Controller.Exclusive_Data | 28370 12.56% 12.56% | 28338 12.54% 25.10% | 28394 12.57% 37.66% | 28025 12.40% 50.07% | 28209 12.48% 62.55% | 28223 12.49% 75.04% | 28329 12.54% 87.58% | 28063 12.42% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 225951 -system.ruby.L1Cache_Controller.Writeback_Ack | 646 12.65% 12.65% | 679 13.29% 25.94% | 600 11.75% 37.69% | 633 12.39% 50.08% | 633 12.39% 62.47% | 657 12.86% 75.33% | 612 11.98% 87.31% | 648 12.69% 100.00% +system.ruby.ST.miss_latency_hist::samples 221844 +system.ruby.ST.miss_latency_hist::mean 1518.634513 +system.ruby.ST.miss_latency_hist::gmean 1027.209710 +system.ruby.ST.miss_latency_hist::stdev 1492.694318 +system.ruby.ST.miss_latency_hist | 167659 75.58% 75.58% | 38896 17.53% 93.11% | 11196 5.05% 98.16% | 3060 1.38% 99.53% | 776 0.35% 99.88% | 195 0.09% 99.97% | 46 0.02% 99.99% | 13 0.01% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 221844 +system.ruby.Directory_Controller.GETX 219948 0.00% 0.00% +system.ruby.Directory_Controller.GETS 392622 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 219827 0.00% 0.00% +system.ruby.Directory_Controller.PUTO_SHARERS 100 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 142754 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 249849 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 219930 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 219920 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 612551 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 219920 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 78370 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 142761 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 219658 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 141568 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 249860 0.00% 0.00% +system.ruby.Directory_Controller.S.Memory_Ack 100 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 219827 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTO_SHARERS 100 0.00% 0.00% +system.ruby.Directory_Controller.IS.GETX 1 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 142754 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 142760 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Ack 108 0.00% 0.00% +system.ruby.Directory_Controller.SS.GETX 9 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 249849 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 249856 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 219930 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 219935 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 54 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 219820 0.00% 0.00% +system.ruby.Directory_Controller.MIS.Dirty_Writeback 100 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50198 12.49% 12.49% | 50329 12.52% 25.01% | 50260 12.50% 37.51% | 50323 12.52% 50.03% | 50663 12.60% 62.63% | 49920 12.42% 75.04% | 50235 12.50% 87.54% | 50089 12.46% 100.00% +system.ruby.L1Cache_Controller.Load::total 402017 +system.ruby.L1Cache_Controller.Store | 27854 12.55% 12.55% | 27614 12.45% 25.00% | 27687 12.48% 37.48% | 27880 12.57% 50.04% | 27728 12.50% 62.54% | 27882 12.57% 75.10% | 27494 12.39% 87.49% | 27747 12.51% 100.00% +system.ruby.L1Cache_Controller.Store::total 221886 +system.ruby.L1Cache_Controller.L1_Replacement | 9386167 12.50% 12.50% | 9387429 12.50% 25.00% | 9388272 12.50% 37.51% | 9379351 12.49% 50.00% | 9374313 12.49% 62.48% | 9387856 12.50% 74.99% | 9392579 12.51% 87.50% | 9387972 12.50% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 75083939 +system.ruby.L1Cache_Controller.Fwd_GETX | 167 12.69% 12.69% | 158 12.01% 24.70% | 171 12.99% 37.69% | 153 11.63% 49.32% | 166 12.61% 61.93% | 175 13.30% 75.23% | 168 12.77% 87.99% | 158 12.01% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1316 +system.ruby.L1Cache_Controller.Fwd_GETS | 655 11.67% 11.67% | 742 13.22% 24.90% | 703 12.53% 37.43% | 638 11.37% 48.80% | 733 13.06% 61.86% | 704 12.55% 74.41% | 700 12.48% 86.88% | 736 13.12% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 5611 +system.ruby.L1Cache_Controller.Inv | 242 13.16% 13.16% | 233 12.67% 25.83% | 235 12.78% 38.61% | 199 10.82% 49.43% | 237 12.89% 62.32% | 244 13.27% 75.58% | 205 11.15% 86.73% | 244 13.27% 100.00% +system.ruby.L1Cache_Controller.Inv::total 1839 +system.ruby.L1Cache_Controller.Ack | 364 11.96% 11.96% | 369 12.13% 24.09% | 353 11.60% 35.69% | 394 12.95% 48.64% | 386 12.68% 61.32% | 389 12.78% 74.10% | 371 12.19% 86.30% | 417 13.70% 100.00% +system.ruby.L1Cache_Controller.Ack::total 3043 +system.ruby.L1Cache_Controller.Data | 49948 12.48% 12.48% | 50137 12.52% 25.00% | 50041 12.50% 37.50% | 50122 12.52% 50.02% | 50438 12.60% 62.62% | 49723 12.42% 75.04% | 50036 12.50% 87.54% | 49872 12.46% 100.00% +system.ruby.L1Cache_Controller.Data::total 400317 +system.ruby.L1Cache_Controller.Exclusive_Data | 28070 12.56% 12.56% | 27790 12.44% 25.00% | 27889 12.48% 37.49% | 28061 12.56% 50.05% | 27929 12.50% 62.55% | 28056 12.56% 75.11% | 27675 12.39% 87.50% | 27930 12.50% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 223400 +system.ruby.L1Cache_Controller.Writeback_Ack | 678 13.27% 13.27% | 610 11.94% 25.22% | 601 11.77% 36.98% | 683 13.37% 50.35% | 619 12.12% 62.47% | 623 12.20% 74.67% | 633 12.39% 87.06% | 661 12.94% 100.00% system.ruby.L1Cache_Controller.Writeback_Ack::total 5108 -system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77750 12.52% 12.52% | 77745 12.52% 25.05% | 77634 12.51% 37.55% | 77612 12.50% 50.06% | 77650 12.51% 62.57% | 77523 12.49% 75.05% | 77567 12.50% 87.55% | 77298 12.45% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 620779 -system.ruby.L1Cache_Controller.Writeback_Nack | 248 13.20% 13.20% | 246 13.09% 26.29% | 216 11.50% 37.79% | 237 12.61% 50.40% | 218 11.60% 62.00% | 239 12.72% 74.72% | 231 12.29% 87.01% | 244 12.99% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 1879 -system.ruby.L1Cache_Controller.All_acks | 28178 12.55% 12.55% | 28128 12.53% 25.09% | 28199 12.56% 37.65% | 27860 12.41% 50.06% | 28012 12.48% 62.54% | 28046 12.50% 75.04% | 28156 12.54% 87.58% | 27868 12.42% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 224447 -system.ruby.L1Cache_Controller.Use_Timeout | 28370 12.56% 12.56% | 28338 12.54% 25.10% | 28394 12.57% 37.66% | 28025 12.40% 50.07% | 28209 12.48% 62.55% | 28223 12.49% 75.04% | 28329 12.54% 87.58% | 28063 12.42% 100.00% -system.ruby.L1Cache_Controller.Use_Timeout::total 225951 -system.ruby.L1Cache_Controller.I.Load | 50501 12.51% 12.51% | 50597 12.53% 25.04% | 50292 12.46% 37.50% | 50659 12.55% 50.05% | 50527 12.52% 62.57% | 50416 12.49% 75.06% | 50305 12.46% 87.52% | 50369 12.48% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 403666 -system.ruby.L1Cache_Controller.I.Store | 28175 12.55% 12.55% | 28122 12.53% 25.08% | 28197 12.56% 37.65% | 27859 12.41% 50.06% | 28010 12.48% 62.54% | 28043 12.50% 75.04% | 28155 12.55% 87.58% | 27869 12.42% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 224430 -system.ruby.L1Cache_Controller.I.L1_Replacement | 51 12.35% 12.35% | 56 13.56% 25.91% | 48 11.62% 37.53% | 47 11.38% 48.91% | 45 10.90% 59.81% | 52 12.59% 72.40% | 62 15.01% 87.41% | 52 12.59% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 413 -system.ruby.L1Cache_Controller.S.Load | 6 12.50% 12.50% | 7 14.58% 27.08% | 7 14.58% 41.67% | 9 18.75% 60.42% | 4 8.33% 68.75% | 4 8.33% 77.08% | 5 10.42% 87.50% | 6 12.50% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 48 -system.ruby.L1Cache_Controller.S.Store | 4 16.00% 16.00% | 7 28.00% 44.00% | 3 12.00% 56.00% | 1 4.00% 60.00% | 4 16.00% 76.00% | 3 12.00% 88.00% | 2 8.00% 96.00% | 1 4.00% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 25 -system.ruby.L1Cache_Controller.S.L1_Replacement | 50293 12.51% 12.51% | 50374 12.53% 25.04% | 50080 12.46% 37.49% | 50482 12.56% 50.05% | 50317 12.51% 62.57% | 50228 12.49% 75.06% | 50120 12.47% 87.52% | 50160 12.48% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 402054 -system.ruby.L1Cache_Controller.S.Fwd_GETS | 41 11.26% 11.26% | 43 11.81% 23.08% | 48 13.19% 36.26% | 56 15.38% 51.65% | 46 12.64% 64.29% | 46 12.64% 76.92% | 45 12.36% 89.29% | 39 10.71% 100.00% -system.ruby.L1Cache_Controller.S.Fwd_GETS::total 364 -system.ruby.L1Cache_Controller.S.Inv | 9 15.25% 15.25% | 3 5.08% 20.34% | 11 18.64% 38.98% | 7 11.86% 50.85% | 7 11.86% 62.71% | 4 6.78% 69.49% | 7 11.86% 81.36% | 11 18.64% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 59 -system.ruby.L1Cache_Controller.O.L1_Replacement | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 2 -system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77051 12.50% 12.50% | 77032 12.50% 25.00% | 77045 12.50% 37.50% | 77265 12.54% 50.03% | 77446 12.56% 62.60% | 76863 12.47% 75.07% | 76819 12.46% 87.53% | 76844 12.47% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 616365 +system.ruby.L1Cache_Controller.Writeback_Nack | 249 13.13% 13.13% | 248 13.07% 26.20% | 252 13.28% 39.48% | 203 10.70% 50.18% | 240 12.65% 62.84% | 250 13.18% 76.01% | 210 11.07% 87.08% | 245 12.92% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 1897 +system.ruby.L1Cache_Controller.All_acks | 27848 12.55% 12.55% | 27610 12.45% 25.00% | 27682 12.48% 37.48% | 27874 12.56% 50.04% | 27725 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 221844 +system.ruby.L1Cache_Controller.Use_Timeout | 28069 12.56% 12.56% | 27790 12.44% 25.00% | 27888 12.48% 37.49% | 28061 12.56% 50.05% | 27928 12.50% 62.55% | 28056 12.56% 75.11% | 27675 12.39% 87.50% | 27930 12.50% 100.00% +system.ruby.L1Cache_Controller.Use_Timeout::total 223397 +system.ruby.L1Cache_Controller.I.Load | 50172 12.48% 12.48% | 50319 12.52% 25.00% | 50249 12.50% 37.51% | 50309 12.52% 50.03% | 50643 12.60% 62.63% | 49905 12.42% 75.05% | 50224 12.50% 87.54% | 50066 12.46% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 401887 +system.ruby.L1Cache_Controller.I.Store | 27846 12.55% 12.55% | 27607 12.45% 25.00% | 27681 12.48% 37.48% | 27875 12.57% 50.04% | 27723 12.50% 62.54% | 27875 12.57% 75.11% | 27487 12.39% 87.50% | 27734 12.50% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 221828 +system.ruby.L1Cache_Controller.I.L1_Replacement | 49 11.45% 11.45% | 54 12.62% 24.07% | 52 12.15% 36.21% | 38 8.88% 45.09% | 71 16.59% 61.68% | 55 12.85% 74.53% | 53 12.38% 86.92% | 56 13.08% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 428 +system.ruby.L1Cache_Controller.S.Load | 4 13.33% 13.33% | 4 13.33% 26.67% | 4 13.33% 40.00% | 2 6.67% 46.67% | 1 3.33% 50.00% | 7 23.33% 73.33% | 1 3.33% 76.67% | 7 23.33% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 30 +system.ruby.L1Cache_Controller.S.Store | 3 13.64% 13.64% | 3 13.64% 27.27% | 2 9.09% 36.36% | 1 4.55% 40.91% | 2 9.09% 50.00% | 2 9.09% 59.09% | 4 18.18% 77.27% | 5 22.73% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22 +system.ruby.L1Cache_Controller.S.L1_Replacement | 49939 12.48% 12.48% | 50125 12.52% 25.00% | 50030 12.50% 37.50% | 50115 12.52% 50.02% | 50424 12.60% 62.62% | 49714 12.42% 75.04% | 50028 12.50% 87.54% | 49858 12.46% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 400233 +system.ruby.L1Cache_Controller.S.Fwd_GETS | 43 12.72% 12.72% | 41 12.13% 24.85% | 42 12.43% 37.28% | 41 12.13% 49.41% | 37 10.95% 60.36% | 43 12.72% 73.08% | 48 14.20% 87.28% | 43 12.72% 100.00% +system.ruby.L1Cache_Controller.S.Fwd_GETS::total 338 +system.ruby.L1Cache_Controller.S.Inv | 6 11.11% 11.11% | 7 12.96% 24.07% | 8 14.81% 38.89% | 5 9.26% 48.15% | 10 18.52% 66.67% | 6 11.11% 77.78% | 4 7.41% 85.19% | 8 14.81% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 54 +system.ruby.L1Cache_Controller.O.L1_Replacement | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 5 +system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Store::total 1 -system.ruby.L1Cache_Controller.M.L1_Replacement | 191 12.77% 12.77% | 210 14.04% 26.80% | 195 13.03% 39.84% | 163 10.90% 50.74% | 196 13.10% 63.84% | 177 11.83% 75.67% | 169 11.30% 86.97% | 195 13.03% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 1496 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 4 80.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 5 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 2 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 395 10.57% 10.57% | 427 11.43% 22.00% | 786 21.03% 43.03% | 434 11.61% 54.64% | 301 8.05% 62.70% | 536 14.34% 77.04% | 484 12.95% 89.99% | 374 10.01% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 3737 -system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 22.22% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 7 77.78% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 9 -system.ruby.L1Cache_Controller.M_W.Use_Timeout | 192 12.77% 12.77% | 210 13.96% 26.73% | 195 12.97% 39.69% | 165 10.97% 50.66% | 197 13.10% 63.76% | 177 11.77% 75.53% | 173 11.50% 87.03% | 195 12.97% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1504 -system.ruby.L1Cache_Controller.MM.Load | 1 7.69% 7.69% | 3 23.08% 30.77% | 2 15.38% 46.15% | 1 7.69% 53.85% | 0 0.00% 53.85% | 0 0.00% 53.85% | 3 23.08% 76.92% | 3 23.08% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 13 -system.ruby.L1Cache_Controller.MM.Store | 2 25.00% 25.00% | 1 12.50% 37.50% | 1 12.50% 50.00% | 1 12.50% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 8 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 28136 12.56% 12.56% | 28075 12.53% 25.08% | 28162 12.57% 37.65% | 27822 12.42% 50.06% | 27974 12.48% 62.55% | 27998 12.49% 75.04% | 28105 12.54% 87.58% | 27827 12.42% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 224099 -system.ruby.L1Cache_Controller.MM.Fwd_GETX | 13 9.85% 9.85% | 25 18.94% 28.79% | 20 15.15% 43.94% | 16 12.12% 56.06% | 15 11.36% 67.42% | 12 9.09% 76.52% | 16 12.12% 88.64% | 15 11.36% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 132 -system.ruby.L1Cache_Controller.MM.Fwd_GETS | 29 13.36% 13.36% | 28 12.90% 26.27% | 17 7.83% 34.10% | 23 10.60% 44.70% | 23 10.60% 55.30% | 36 16.59% 71.89% | 35 16.13% 88.02% | 26 11.98% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 217 -system.ruby.L1Cache_Controller.MM_W.Load | 6 21.43% 21.43% | 4 14.29% 35.71% | 3 10.71% 46.43% | 3 10.71% 57.14% | 6 21.43% 78.57% | 3 10.71% 89.29% | 1 3.57% 92.86% | 2 7.14% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 28 -system.ruby.L1Cache_Controller.MM_W.Store | 3 14.29% 14.29% | 2 9.52% 23.81% | 0 0.00% 23.81% | 5 23.81% 47.62% | 4 19.05% 66.67% | 2 9.52% 76.19% | 4 19.05% 95.24% | 1 4.76% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 21 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 621119 12.62% 12.62% | 613463 12.47% 25.09% | 615369 12.51% 37.60% | 613454 12.47% 50.06% | 615301 12.50% 62.57% | 615852 12.52% 75.08% | 613919 12.48% 87.56% | 612169 12.44% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4920646 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 12 9.45% 9.45% | 34 26.77% 36.22% | 11 8.66% 44.88% | 15 11.81% 56.69% | 15 11.81% 68.50% | 17 13.39% 81.89% | 4 3.15% 85.04% | 19 14.96% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 127 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 25 12.25% 12.25% | 35 17.16% 29.41% | 15 7.35% 36.76% | 27 13.24% 50.00% | 27 13.24% 63.24% | 27 13.24% 76.47% | 27 13.24% 89.71% | 21 10.29% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 204 -system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 28178 12.55% 12.55% | 28128 12.53% 25.09% | 28199 12.56% 37.65% | 27860 12.41% 50.06% | 28012 12.48% 62.54% | 28046 12.50% 75.04% | 28156 12.54% 87.58% | 27868 12.42% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 224447 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 3178623 12.60% 12.60% | 3133531 12.42% 25.02% | 3166168 12.55% 37.57% | 3128956 12.40% 49.97% | 3171906 12.57% 62.54% | 3132218 12.41% 74.96% | 3164131 12.54% 87.50% | 3154429 12.50% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 25229962 -system.ruby.L1Cache_Controller.IM.Ack | 163 13.27% 13.27% | 155 12.62% 25.90% | 149 12.13% 38.03% | 163 13.27% 51.30% | 150 12.21% 63.52% | 156 12.70% 76.22% | 152 12.38% 88.60% | 140 11.40% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1228 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 28174 12.55% 12.55% | 28121 12.53% 25.08% | 28196 12.56% 37.65% | 27859 12.41% 50.06% | 28009 12.48% 62.54% | 28043 12.50% 75.04% | 28154 12.55% 87.58% | 27867 12.42% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 224423 -system.ruby.L1Cache_Controller.SM.L1_Replacement | 1133 22.51% 22.51% | 986 19.59% 42.09% | 762 15.14% 57.23% | 192 3.81% 61.04% | 902 17.92% 78.96% | 385 7.65% 86.61% | 473 9.40% 96.01% | 201 3.99% 100.00% -system.ruby.L1Cache_Controller.SM.L1_Replacement::total 5034 -system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Inv::total 1 -system.ruby.L1Cache_Controller.SM.Exclusive_Data | 4 16.67% 16.67% | 7 29.17% 45.83% | 3 12.50% 58.33% | 1 4.17% 62.50% | 3 12.50% 75.00% | 3 12.50% 87.50% | 2 8.33% 95.83% | 1 4.17% 100.00% -system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 24 -system.ruby.L1Cache_Controller.OM.L1_Replacement | 21441 12.36% 12.36% | 21531 12.41% 24.77% | 22013 12.69% 37.46% | 22555 13.00% 50.46% | 22104 12.74% 63.20% | 20567 11.85% 75.05% | 21301 12.28% 87.33% | 21980 12.67% 100.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement::total 173492 -system.ruby.L1Cache_Controller.OM.Ack | 217 11.91% 11.91% | 213 11.69% 23.60% | 222 12.18% 35.78% | 240 13.17% 48.96% | 232 12.73% 61.69% | 247 13.56% 75.25% | 227 12.46% 87.71% | 224 12.29% 100.00% -system.ruby.L1Cache_Controller.OM.Ack::total 1822 -system.ruby.L1Cache_Controller.OM.All_acks | 28178 12.55% 12.55% | 28128 12.53% 25.09% | 28199 12.56% 37.65% | 27860 12.41% 50.06% | 28012 12.48% 62.54% | 28046 12.50% 75.04% | 28156 12.54% 87.58% | 27868 12.42% 100.00% -system.ruby.L1Cache_Controller.OM.All_acks::total 224447 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 5554907 12.43% 12.43% | 5605208 12.54% 24.96% | 5573160 12.47% 37.43% | 5613895 12.56% 49.99% | 5567311 12.45% 62.44% | 5611053 12.55% 75.00% | 5580519 12.48% 87.48% | 5597261 12.52% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44703314 -system.ruby.L1Cache_Controller.IS.Data | 50306 12.51% 12.51% | 50385 12.53% 25.04% | 50094 12.46% 37.50% | 50490 12.56% 50.05% | 50329 12.52% 62.57% | 50235 12.49% 75.06% | 50131 12.47% 87.52% | 50173 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 402143 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 192 12.77% 12.77% | 210 13.96% 26.73% | 195 12.97% 39.69% | 165 10.97% 50.66% | 197 13.10% 63.76% | 177 11.77% 75.53% | 173 11.50% 87.03% | 195 12.97% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1504 -system.ruby.L1Cache_Controller.SI.Load | 14 21.54% 21.54% | 2 3.08% 24.62% | 7 10.77% 35.38% | 13 20.00% 55.38% | 5 7.69% 63.08% | 1 1.54% 64.62% | 17 26.15% 90.77% | 6 9.23% 100.00% -system.ruby.L1Cache_Controller.SI.Load::total 65 -system.ruby.L1Cache_Controller.SI.Store | 1 3.57% 3.57% | 3 10.71% 14.29% | 0 0.00% 14.29% | 4 14.29% 28.57% | 5 17.86% 46.43% | 1 3.57% 50.00% | 13 46.43% 96.43% | 1 3.57% 100.00% -system.ruby.L1Cache_Controller.SI.Store::total 28 -system.ruby.L1Cache_Controller.SI.Fwd_GETS | 374 12.94% 12.94% | 385 13.32% 26.26% | 338 11.70% 37.96% | 361 12.49% 50.45% | 369 12.77% 63.22% | 354 12.25% 75.47% | 375 12.98% 88.44% | 334 11.56% 100.00% -system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2890 -system.ruby.L1Cache_Controller.SI.Inv | 224 12.72% 12.72% | 235 13.34% 26.06% | 201 11.41% 37.48% | 223 12.66% 50.14% | 205 11.64% 61.78% | 223 12.66% 74.45% | 214 12.15% 86.60% | 236 13.40% 100.00% -system.ruby.L1Cache_Controller.SI.Inv::total 1761 -system.ruby.L1Cache_Controller.SI.Writeback_Ack | 645 12.63% 12.63% | 679 13.30% 25.94% | 600 11.75% 37.69% | 632 12.38% 50.07% | 632 12.38% 62.45% | 657 12.87% 75.32% | 612 11.99% 87.31% | 648 12.69% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5105 -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49424 12.51% 12.51% | 49460 12.52% 25.02% | 49279 12.47% 37.49% | 49627 12.56% 50.05% | 49480 12.52% 62.57% | 49348 12.49% 75.06% | 49294 12.47% 87.53% | 49276 12.47% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 395188 -system.ruby.L1Cache_Controller.OI.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 1 -system.ruby.L1Cache_Controller.OI.Fwd_GETS | 0 0.00% 0.00% | 1 11.11% 11.11% | 0 0.00% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 3 33.33% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 9 -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 261 13.66% 13.66% | 248 12.98% 26.65% | 233 12.20% 38.85% | 182 9.53% 48.38% | 250 13.09% 61.47% | 234 12.25% 73.72% | 242 12.67% 86.39% | 260 13.61% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1910 -system.ruby.L1Cache_Controller.OI.Writeback_Nack | 24 20.69% 20.69% | 11 9.48% 30.17% | 13 11.21% 41.38% | 15 12.93% 54.31% | 13 11.21% 65.52% | 16 13.79% 79.31% | 16 13.79% 93.10% | 8 6.90% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 116 -system.ruby.L1Cache_Controller.MI.Load | 15 93.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 16 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 124 11.37% 11.37% | 138 12.65% 24.01% | 141 12.92% 36.94% | 140 12.83% 49.77% | 137 12.56% 62.33% | 131 12.01% 74.34% | 131 12.01% 86.34% | 149 13.66% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1091 -system.ruby.L1Cache_Controller.MI.Fwd_GETS | 260 13.62% 13.62% | 248 12.99% 26.61% | 234 12.26% 38.87% | 182 9.53% 48.40% | 249 13.04% 61.45% | 234 12.26% 73.70% | 242 12.68% 86.38% | 260 13.62% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1909 -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27942 12.55% 12.55% | 27899 12.53% 25.09% | 27982 12.57% 37.66% | 27663 12.43% 50.08% | 27784 12.48% 62.57% | 27810 12.49% 75.06% | 27901 12.53% 87.59% | 27613 12.41% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 222594 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 3 -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 123 11.32% 11.32% | 138 12.70% 24.01% | 140 12.88% 36.89% | 140 12.88% 49.77% | 136 12.51% 62.28% | 131 12.05% 74.33% | 130 11.96% 86.29% | 149 13.71% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1087 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 224 12.71% 12.71% | 235 13.33% 26.04% | 203 11.51% 37.55% | 222 12.59% 50.14% | 205 11.63% 61.77% | 223 12.65% 74.42% | 215 12.20% 86.61% | 236 13.39% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1763 -system.ruby.L2Cache_Controller.L1_GETS 501706 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 280108 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTO 131 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 260500 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 476451 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS 25484 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 222478 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 616903 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 395188 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 224504 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 222462 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 408333 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 225951 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 690870 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 394442 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 219255 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETS 3254 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETX 1820 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 391949 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS 3239 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETS 2128 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETX 1228 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 223680 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTS 1753 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement | 221 14.26% 14.26% | 179 11.55% 25.81% | 205 13.23% 39.03% | 187 12.06% 51.10% | 204 13.16% 64.26% | 181 11.68% 75.94% | 182 11.74% 87.68% | 191 12.32% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 1550 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 5 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 591 14.10% 14.10% | 590 14.08% 28.18% | 722 17.23% 45.41% | 352 8.40% 53.81% | 599 14.29% 68.10% | 348 8.30% 76.40% | 686 16.37% 92.77% | 303 7.23% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 4191 +system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 2 +system.ruby.L1Cache_Controller.M_W.Use_Timeout | 222 14.27% 14.27% | 180 11.57% 25.84% | 207 13.30% 39.14% | 187 12.02% 51.16% | 204 13.11% 64.27% | 181 11.63% 75.90% | 184 11.83% 87.72% | 191 12.28% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1556 +system.ruby.L1Cache_Controller.MM.Load | 2 8.70% 8.70% | 2 8.70% 17.39% | 3 13.04% 30.43% | 5 21.74% 52.17% | 3 13.04% 65.22% | 2 8.70% 73.91% | 2 8.70% 82.61% | 4 17.39% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 23 +system.ruby.L1Cache_Controller.MM.Store | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 2 28.57% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 7 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 27804 12.55% 12.55% | 27563 12.45% 25.00% | 27637 12.48% 37.48% | 27840 12.57% 50.05% | 27663 12.49% 62.54% | 27826 12.56% 75.11% | 27443 12.39% 87.50% | 27691 12.50% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 221467 +system.ruby.L1Cache_Controller.MM.Fwd_GETX | 17 14.41% 14.41% | 16 13.56% 27.97% | 14 11.86% 39.83% | 14 11.86% 51.69% | 20 16.95% 68.64% | 11 9.32% 77.97% | 15 12.71% 90.68% | 11 9.32% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 118 +system.ruby.L1Cache_Controller.MM.Fwd_GETS | 26 10.16% 10.16% | 31 12.11% 22.27% | 30 11.72% 33.98% | 19 7.42% 41.41% | 41 16.02% 57.42% | 38 14.84% 72.27% | 34 13.28% 85.55% | 37 14.45% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 256 +system.ruby.L1Cache_Controller.MM_W.Load | 3 9.68% 9.68% | 4 12.90% 22.58% | 2 6.45% 29.03% | 4 12.90% 41.94% | 5 16.13% 58.06% | 3 9.68% 67.74% | 4 12.90% 80.65% | 6 19.35% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 31 +system.ruby.L1Cache_Controller.MM_W.Store | 2 12.50% 12.50% | 1 6.25% 18.75% | 2 12.50% 31.25% | 1 6.25% 37.50% | 0 0.00% 37.50% | 4 25.00% 62.50% | 2 12.50% 75.00% | 4 25.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 16 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 611213 12.52% 12.52% | 604769 12.39% 24.91% | 614347 12.59% 37.50% | 608910 12.48% 49.98% | 611746 12.53% 62.51% | 610049 12.50% 75.01% | 610144 12.50% 87.51% | 609423 12.49% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4880601 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 13 11.61% 11.61% | 15 13.39% 25.00% | 19 16.96% 41.96% | 10 8.93% 50.89% | 18 16.07% 66.96% | 16 14.29% 81.25% | 11 9.82% 91.07% | 10 8.93% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 112 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 20 10.10% 10.10% | 22 11.11% 21.21% | 21 10.61% 31.82% | 20 10.10% 41.92% | 29 14.65% 56.57% | 28 14.14% 70.71% | 32 16.16% 86.87% | 26 13.13% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 198 +system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27847 12.55% 12.55% | 27610 12.45% 25.00% | 27681 12.48% 37.48% | 27874 12.56% 50.04% | 27724 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 221841 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 3117685 12.52% 12.52% | 3071171 12.34% 24.86% | 3120650 12.54% 37.40% | 3140383 12.62% 50.02% | 3099421 12.45% 62.47% | 3146089 12.64% 75.11% | 3088522 12.41% 87.51% | 3108221 12.49% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 24892142 +system.ruby.L1Cache_Controller.IM.Ack | 144 12.04% 12.04% | 147 12.29% 24.33% | 138 11.54% 35.87% | 150 12.54% 48.41% | 150 12.54% 60.95% | 142 11.87% 72.83% | 153 12.79% 85.62% | 172 14.38% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1196 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27845 12.55% 12.55% | 27607 12.45% 25.00% | 27680 12.48% 37.48% | 27873 12.57% 50.04% | 27723 12.50% 62.54% | 27873 12.57% 75.11% | 27487 12.39% 87.50% | 27734 12.50% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 221822 +system.ruby.L1Cache_Controller.SM.L1_Replacement | 733 19.03% 19.03% | 966 25.08% 44.11% | 395 10.25% 54.36% | 251 6.52% 60.88% | 202 5.24% 66.12% | 281 7.29% 73.42% | 679 17.63% 91.04% | 345 8.96% 100.00% +system.ruby.L1Cache_Controller.SM.L1_Replacement::total 3852 +system.ruby.L1Cache_Controller.SM.Exclusive_Data | 3 13.64% 13.64% | 3 13.64% 27.27% | 2 9.09% 36.36% | 1 4.55% 40.91% | 2 9.09% 50.00% | 2 9.09% 59.09% | 4 18.18% 77.27% | 5 22.73% 100.00% +system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 22 +system.ruby.L1Cache_Controller.OM.L1_Replacement | 22520 12.98% 12.98% | 21779 12.56% 25.54% | 21024 12.12% 37.66% | 21826 12.58% 50.25% | 21159 12.20% 62.45% | 22530 12.99% 75.44% | 21258 12.26% 87.70% | 21336 12.30% 100.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement::total 173432 +system.ruby.L1Cache_Controller.OM.Ack | 220 11.91% 11.91% | 222 12.02% 23.93% | 215 11.64% 35.57% | 244 13.21% 48.78% | 236 12.78% 61.56% | 247 13.37% 74.93% | 218 11.80% 86.74% | 245 13.26% 100.00% +system.ruby.L1Cache_Controller.OM.Ack::total 1847 +system.ruby.L1Cache_Controller.OM.All_acks | 27848 12.55% 12.55% | 27610 12.45% 25.00% | 27682 12.48% 37.48% | 27874 12.56% 50.04% | 27725 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks::total 221844 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 5555411 12.48% 12.48% | 5610232 12.61% 25.09% | 5553208 12.48% 37.57% | 5529449 12.42% 49.99% | 5562824 12.50% 62.49% | 5530783 12.43% 74.92% | 5593583 12.57% 87.48% | 5570548 12.52% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44506038 +system.ruby.L1Cache_Controller.IS.Data | 49948 12.48% 12.48% | 50137 12.52% 25.00% | 50041 12.50% 37.50% | 50122 12.52% 50.02% | 50438 12.60% 62.62% | 49723 12.42% 75.04% | 50036 12.50% 87.54% | 49872 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 400317 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 222 14.27% 14.27% | 180 11.57% 25.84% | 207 13.30% 39.14% | 187 12.02% 51.16% | 204 13.11% 64.27% | 181 11.63% 75.90% | 184 11.83% 87.72% | 191 12.28% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1556 +system.ruby.L1Cache_Controller.SI.Load | 12 37.50% 37.50% | 0 0.00% 37.50% | 2 6.25% 43.75% | 0 0.00% 43.75% | 11 34.38% 78.12% | 3 9.38% 87.50% | 3 9.38% 96.88% | 1 3.12% 100.00% +system.ruby.L1Cache_Controller.SI.Load::total 32 +system.ruby.L1Cache_Controller.SI.Store | 0 0.00% 0.00% | 3 42.86% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.SI.Store::total 7 +system.ruby.L1Cache_Controller.SI.Fwd_GETS | 329 11.65% 11.65% | 363 12.85% 24.50% | 347 12.29% 36.79% | 329 11.65% 48.44% | 389 13.77% 62.22% | 358 12.68% 74.89% | 337 11.93% 86.83% | 372 13.17% 100.00% +system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2824 +system.ruby.L1Cache_Controller.SI.Inv | 236 13.22% 13.22% | 226 12.66% 25.88% | 227 12.72% 38.60% | 194 10.87% 49.47% | 227 12.72% 62.18% | 238 13.33% 75.52% | 201 11.26% 86.78% | 236 13.22% 100.00% +system.ruby.L1Cache_Controller.SI.Inv::total 1785 +system.ruby.L1Cache_Controller.SI.Writeback_Ack | 675 13.24% 13.24% | 609 11.95% 25.19% | 601 11.79% 36.98% | 683 13.40% 50.37% | 618 12.12% 62.50% | 620 12.16% 74.66% | 632 12.40% 87.05% | 660 12.95% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5098 +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49027 12.46% 12.46% | 49290 12.53% 24.99% | 49202 12.51% 37.50% | 49238 12.52% 50.02% | 49579 12.60% 62.63% | 48856 12.42% 75.05% | 49193 12.51% 87.55% | 48962 12.45% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 393347 +system.ruby.L1Cache_Controller.OI.Fwd_GETX | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 6 +system.ruby.L1Cache_Controller.OI.Fwd_GETS | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 6 +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 233 11.76% 11.76% | 285 14.39% 26.15% | 263 13.28% 39.42% | 227 11.46% 50.88% | 236 11.91% 62.80% | 234 11.81% 74.61% | 247 12.47% 87.08% | 256 12.92% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1981 +system.ruby.L1Cache_Controller.OI.Writeback_Nack | 14 11.86% 11.86% | 22 18.64% 30.51% | 24 20.34% 50.85% | 9 7.63% 58.47% | 14 11.86% 70.34% | 15 12.71% 83.05% | 10 8.47% 91.53% | 10 8.47% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 118 +system.ruby.L1Cache_Controller.MI.Load | 5 35.71% 35.71% | 0 0.00% 35.71% | 0 0.00% 35.71% | 3 21.43% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 1 7.14% 64.29% | 5 35.71% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 14 +system.ruby.L1Cache_Controller.MI.Store | 2 50.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 4 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 136 12.59% 12.59% | 127 11.76% 24.35% | 138 12.78% 37.13% | 128 11.85% 48.98% | 128 11.85% 60.83% | 147 13.61% 74.44% | 141 13.06% 87.50% | 135 12.50% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1080 +system.ruby.L1Cache_Controller.MI.Fwd_GETS | 233 11.76% 11.76% | 284 14.33% 26.08% | 261 13.17% 39.25% | 228 11.50% 50.76% | 236 11.91% 62.66% | 235 11.86% 74.52% | 247 12.46% 86.98% | 258 13.02% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1982 +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27656 12.57% 12.57% | 27331 12.43% 25.00% | 27443 12.48% 37.48% | 27671 12.58% 50.06% | 27503 12.50% 62.56% | 27625 12.56% 75.12% | 27237 12.38% 87.50% | 27489 12.50% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 219955 +system.ruby.L1Cache_Controller.II.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.II.Store::total 1 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 3 30.00% 30.00% | 1 10.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 10 +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 135 12.48% 12.48% | 126 11.65% 24.12% | 137 12.66% 36.78% | 129 11.92% 48.71% | 128 11.83% 60.54% | 148 13.68% 74.21% | 142 13.12% 87.34% | 137 12.66% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1082 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 235 13.21% 13.21% | 226 12.70% 25.91% | 228 12.82% 38.73% | 194 10.91% 49.63% | 226 12.70% 62.34% | 235 13.21% 75.55% | 200 11.24% 86.79% | 235 13.21% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1779 +system.ruby.L2Cache_Controller.L1_GETS 499463 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 277459 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTO 132 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 259037 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS_only 475631 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS 24927 0.00% 0.00% +system.ruby.L2Cache_Controller.All_Acks 219934 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 612544 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 393347 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 221936 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Ack 219920 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 406502 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 223397 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 683777 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 392621 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 216702 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_GETS 3162 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_GETX 1833 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 390198 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS 3149 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETS 2243 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETX 1198 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTX 221036 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTS 1768 0.00% 0.00% system.ruby.L2Cache_Controller.ILOX.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTO 117 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTX 116 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETS 8 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1793 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 118 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS 2517 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1396 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 391275 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_GETS 10 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1700 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS 15 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L2_Replacement 91 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTO 119 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTX 118 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTS 1 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETS 5 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETX 4 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 4 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1859 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 122 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 12 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS 2531 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETX 1394 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 389456 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_GETS 4 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_GETX 6 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1756 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS 7 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L2_Replacement 100 0.00% 0.00% system.ruby.L2Cache_Controller.SLS.L1_GETS 18 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETX 14 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3244 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS 26 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L2_Replacement 2498 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1287 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 739 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_GETX 9 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3189 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS 22 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L2_Replacement 2482 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1300 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 701 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_PUTX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_PUTS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 222382 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 11 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1580 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 117 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.Unblock 118 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 82 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 11 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 60 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4226 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 49 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1793 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.Unblock 6 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.L1_PUTS 119 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.Unblock 26 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.L2_Replacement 177 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_GETS 108 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_GETX 105 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_PUTS 11967 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3239 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETS 16149 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETX 9267 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 391949 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L1_GETS 61 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L1_GETX 40 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.Unblock 3244 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L2_Replacement 22454 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETS 68 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETX 42 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.Unblock 1700 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L2_Replacement 9730 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L1_PUTS_only 2 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 56 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.Unblock 15 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 148 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETS 5812 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETX 3784 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1588 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTS 58 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 222594 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.Unblock 1086 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_GETS 256 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_GETX 135 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28230 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS 202 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.Unblock 3254 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTO 2 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 7 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_PUTS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 219827 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETS 17 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETX 29 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 9 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1686 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTS 13 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 119 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.Unblock 122 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 50 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 26 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 86 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4049 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 30 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1862 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.Unblock 13 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.L1_PUTS 112 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.Unblock 22 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.L2_Replacement 161 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_GETS 182 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_GETX 82 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_PUTS 11381 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3149 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETS 16447 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETX 9062 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 390198 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L1_GETS 110 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L1_GETX 77 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.Unblock 3189 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L2_Replacement 21395 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETS 57 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETX 14 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_PUTS 9 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.Unblock 1756 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L2_Replacement 8852 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 4 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.Unblock 7 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 25 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETS 6054 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETX 3511 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1623 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTS 74 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 219955 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.Unblock 1081 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_GETS 208 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_GETX 115 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28820 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_PUTS 125 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.Unblock 3162 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 10 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 58 0.00% 0.00% system.ruby.L2Cache_Controller.IFLOX.Unblock 1 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 2 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 214 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 37 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 31465 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 104 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Unblock 1911 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1445 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 109 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 80 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.Unblock 8 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 1 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETS 48255 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETX 26567 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_PUTS 7485 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 394425 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 394419 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETS 20782 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETX 12166 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 220644 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_GETS 103 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_GETX 166 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 29804 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 248 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.Data 1834 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETS 5289 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETX 2899 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTX 94 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16694 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS 119 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 222478 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 222477 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 6 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 110 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 197 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 32397 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 242 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Unblock 1987 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1456 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 63 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 56 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.Unblock 5 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 34 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 4 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETS 46072 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETX 26880 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_PUTS 7566 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data 392610 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Unblock 392604 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETS 21372 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETX 11875 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.Data 218092 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_GETS 349 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_GETX 222 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 30376 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 232 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.Data 1842 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETS 5603 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETX 3146 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTX 121 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16651 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTS 147 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.All_Acks 219934 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 219930 0.00% 0.00% system.ruby.L2Cache_Controller.MM.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_GETX 31 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 739 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 40 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 20 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTS 14 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.Unblock 2517 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 29818 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETS 14 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETX 19 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_PUTX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1287 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L2_Replacement 12281 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 46 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.Unblock 10 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.L2_Replacement 9 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 36 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_GETX 4 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 701 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 52 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 25 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTS 27 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.Unblock 2531 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 30081 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_GETS 46 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1300 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L2_Replacement 11341 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 14 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.Unblock 4 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 74 0.00% 0.00% system.ruby.L2Cache_Controller.SLSS.Unblock 18 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.L2_Replacement 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETS 798 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETX 364 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 222371 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 315 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.L1_PUTS 15 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 91 0.00% 0.00% -system.ruby.Directory_Controller.GETX 222490 0.00% 0.00% -system.ruby.Directory_Controller.GETS 394442 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 222382 0.00% 0.00% -system.ruby.Directory_Controller.PUTO_SHARERS 91 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 143648 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 250771 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 222477 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 222462 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 616908 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 222462 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 80054 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 143652 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 222199 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 142431 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 250790 0.00% 0.00% -system.ruby.Directory_Controller.S.Memory_Ack 91 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 222382 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTO_SHARERS 91 0.00% 0.00% -system.ruby.Directory_Controller.IS.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 143648 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 143651 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Ack 105 0.00% 0.00% -system.ruby.Directory_Controller.SS.GETX 2 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 250771 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 250778 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 222477 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 222479 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 67 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 222371 0.00% 0.00% -system.ruby.Directory_Controller.MIS.Dirty_Writeback 91 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.L2_Replacement 57 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETS 845 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETX 345 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.Writeback_Ack 219820 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 268 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 100 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 02ba8cb28..cdc9c6487 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.005903 # Number of seconds simulated -sim_ticks 5903349 # Number of ticks simulated -final_tick 5903349 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.005881 # Number of seconds simulated +sim_ticks 5881067 # Number of ticks simulated +final_tick 5881067 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 47205 # Simulator tick rate (ticks/s) -host_mem_usage 653496 # Number of bytes of host memory used -host_seconds 125.06 # Real time elapsed on the host +host_tick_rate 67797 # Simulator tick rate (ticks/s) +host_mem_usage 666544 # Number of bytes of host memory used +host_seconds 86.75 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39803968 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39803968 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 15577920 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 15577920 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 621937 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 621937 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 243405 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 243405 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 6742607967 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 6742607967 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 2638827554 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 2638827554 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 9381435521 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 9381435521 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 621943 # Number of read requests accepted -system.mem_ctrls.writeReqs 243405 # Number of write requests accepted -system.mem_ctrls.readBursts 621943 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 243405 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39194112 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 610176 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 15379392 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39804352 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 15577920 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 9534 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 3050 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39867264 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39867264 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 15562240 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 15562240 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 622926 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 622926 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 243160 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 243160 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 6778916819 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 6778916819 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 2646159277 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 2646159277 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 9425076096 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 9425076096 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 622939 # Number of read requests accepted +system.mem_ctrls.writeReqs 243160 # Number of write requests accepted +system.mem_ctrls.readBursts 622939 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 243160 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 39257856 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 609920 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 15368000 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39868096 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 15562240 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 9530 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 2992 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76347 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76777 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76688 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76481 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76573 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76421 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76863 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 76258 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76660 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76752 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 77051 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76487 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76654 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76502 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 77074 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 29810 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 29890 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 29935 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 30014 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 30230 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 29983 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 30326 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 30115 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 30175 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 29930 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 29913 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 29922 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 30021 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 29908 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 29847 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 30409 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,54 +68,54 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 1 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5903324 # Total gap between requests +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 5881040 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 621943 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 622939 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 243405 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 8798 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 12225 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 15673 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 18982 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 23894 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 29950 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 36090 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 39516 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 38914 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 35099 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 30974 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 28275 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 27328 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 26531 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 25465 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 24154 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 22659 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 21094 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 19924 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 19151 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 18313 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 17650 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 16767 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 15495 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 13609 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 10848 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 7634 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 4446 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 2074 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 710 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 152 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 15 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 243160 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 9491 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 13045 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 16471 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 19836 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 24397 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 30683 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 37010 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 40313 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 38781 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 34536 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 30013 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 27811 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 26580 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 25824 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 24841 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 23671 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 22442 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 21076 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 19903 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 19289 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 18444 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 17751 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 16931 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 15536 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 13465 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 10656 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 7404 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 4341 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 2023 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 670 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 154 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 21 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -131,992 +131,1025 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 54 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 129 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 509 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 1379 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2637 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 4325 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 6267 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8313 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 10420 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 12108 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 14158 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 15771 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 14672 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 15436 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 15890 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 16068 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 16476 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 16926 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 9332 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 7861 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 6772 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 5940 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 5146 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 4440 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 3847 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 3410 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 2960 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 2737 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 2369 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 2177 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 1926 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 1729 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 1554 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 1310 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 1089 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 996 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 831 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 739 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 600 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 548 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 304 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 115 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 37 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 248467 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 219.637505 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 176.904831 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 149.844178 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 48636 19.57% 19.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 105540 42.48% 62.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 54258 21.84% 83.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 23672 9.53% 93.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10163 4.09% 97.51% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3955 1.59% 99.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1444 0.58% 99.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 531 0.21% 99.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 268 0.11% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 248467 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 14728 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 41.574756 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 37.550094 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 18.264182 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 348 2.36% 2.36% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 39 0.26% 2.63% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 43 0.29% 2.92% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 3310 22.47% 25.39% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 6215 42.20% 67.59% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 1541 10.46% 78.06% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 179 1.22% 79.27% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 857 5.82% 85.09% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 1087 7.38% 92.47% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 557 3.78% 96.25% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 134 0.91% 97.16% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 122 0.83% 97.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 118 0.80% 98.79% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::104-111 93 0.63% 99.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::112-119 42 0.29% 99.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 26 0.18% 99.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::128-135 7 0.05% 99.93% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::136-143 8 0.05% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::144-151 2 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 14728 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 14728 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.316065 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.277150 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.251161 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13454 91.35% 91.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 270 1.83% 93.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 233 1.58% 94.77% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 212 1.44% 96.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 167 1.13% 97.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 127 0.86% 98.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 100 0.68% 98.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 65 0.44% 99.32% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 45 0.31% 99.63% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 22 0.15% 99.78% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 11 0.07% 99.85% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 12 0.08% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 7 0.05% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 1 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 2 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 14728 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 63789979 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 75425731 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3062040 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 104.16 # Average queueing delay per DRAM burst +system.mem_ctrls.wrQLenPdf::15 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 156 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 556 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 1531 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2889 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 4720 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 6835 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9004 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 11039 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 13141 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 14827 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 16745 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 15642 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 15986 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 16671 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 16977 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 17135 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 17397 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 9213 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 7556 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 6269 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 5389 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 4612 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 3842 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 3246 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 2810 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 2318 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 2106 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 1851 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 1567 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 1379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 1186 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 1027 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 894 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 732 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 636 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 584 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 504 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 429 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 350 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 182 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 34 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 251857 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 216.889807 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 174.913465 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 147.987384 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 50106 19.89% 19.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 108175 42.95% 62.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 54326 21.57% 84.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 23433 9.30% 93.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 9848 3.91% 97.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3794 1.51% 99.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1414 0.56% 99.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 496 0.20% 99.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 265 0.11% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 251857 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 14692 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 41.747345 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 38.046520 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 17.572329 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 293 1.99% 1.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 32 0.22% 2.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 40 0.27% 2.48% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 3171 21.58% 24.07% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 6167 41.98% 66.04% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 1682 11.45% 77.49% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 182 1.24% 78.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 909 6.19% 84.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 1233 8.39% 93.31% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 536 3.65% 96.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 119 0.81% 97.77% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 74 0.50% 98.27% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-103 108 0.74% 99.01% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::104-111 74 0.50% 99.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 42 0.29% 99.80% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::120-127 16 0.11% 99.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-135 8 0.05% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::136-143 4 0.03% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::144-151 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::152-159 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 14692 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 14692 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.343929 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.300692 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.322873 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13317 90.64% 90.64% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 342 2.33% 92.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 211 1.44% 94.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 210 1.43% 95.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 177 1.20% 97.04% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 136 0.93% 97.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 103 0.70% 98.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 66 0.45% 99.12% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 56 0.38% 99.50% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 38 0.26% 99.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 17 0.12% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 7 0.05% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 6 0.04% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 3 0.02% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 14692 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 62376294 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 74030970 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3067020 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 101.69 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 123.16 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 6639.30 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 2605.20 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 6742.67 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 2638.83 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 120.69 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 6675.29 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 2613.13 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 6779.06 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 2646.16 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 72.22 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 51.87 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 20.35 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 15.52 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 30.69 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 368879 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 235357 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 60.23 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.92 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 6.82 # Average gap between requests -system.mem_ctrls.pageHitRate 70.86 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 197080 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 5704995 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1877972040 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 1043317800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7640929920 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2491129728 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 385488480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 385488480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 4021690860 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 127544112 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 13450800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 3429369000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 17473979628 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 3942401592 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 2960.646204 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.967833 # Core power per rank (mW) +system.mem_ctrls.busUtil 72.57 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 52.15 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 20.42 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 15.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 29.97 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 367104 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 234563 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 59.85 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.67 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 6.79 # Average gap between requests +system.mem_ctrls.pageHitRate 70.49 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1903252680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1057362600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7652062080 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2488610304 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 383962800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 4006574460 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 12703200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 17504528124 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2977.600142 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 196300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 5682429 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 383962800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 127039320 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3415767600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3926769720 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.968386 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5682390 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 196300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 99830 # number of read accesses completed +system.cpu0.num_writes 55806 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 99618 # number of read accesses completed +system.cpu1.num_writes 55383 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99329 # number of read accesses completed +system.cpu2.num_writes 55521 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99531 # number of read accesses completed +system.cpu3.num_writes 55301 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 99485 # number of read accesses completed +system.cpu4.num_writes 55398 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99702 # number of read accesses completed +system.cpu5.num_writes 55198 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 99965 # number of read accesses completed +system.cpu6.num_writes 55754 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 54827 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 626379 -system.ruby.outstanding_req_hist::mean 15.998463 -system.ruby.outstanding_req_hist::gmean 15.997198 -system.ruby.outstanding_req_hist::stdev 0.125855 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 19 0.00% 0.02% | 626256 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 626379 +system.ruby.outstanding_req_hist::samples 627379 +system.ruby.outstanding_req_hist::mean 15.998465 +system.ruby.outstanding_req_hist::gmean 15.997202 +system.ruby.outstanding_req_hist::stdev 0.125755 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 19 0.00% 0.02% | 627256 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 627379 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 626251 -system.ruby.latency_hist::mean 1206.428296 -system.ruby.latency_hist::gmean 904.745732 -system.ruby.latency_hist::stdev 768.364731 -system.ruby.latency_hist | 168539 26.91% 26.91% | 118080 18.86% 45.77% | 109951 17.56% 63.32% | 120505 19.24% 82.57% | 86642 13.84% 96.40% | 20968 3.35% 99.75% | 1529 0.24% 99.99% | 37 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 626251 +system.ruby.latency_hist::samples 627251 +system.ruby.latency_hist::mean 1199.957633 +system.ruby.latency_hist::gmean 899.316988 +system.ruby.latency_hist::stdev 764.936546 +system.ruby.latency_hist | 169441 27.01% 27.01% | 117906 18.80% 45.81% | 113026 18.02% 63.83% | 119501 19.05% 82.88% | 85523 13.63% 96.52% | 20392 3.25% 99.77% | 1432 0.23% 100.00% | 30 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 627251 system.ruby.hit_latency_hist::bucket_size 512 system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 2807 -system.ruby.hit_latency_hist::mean 1092.408621 -system.ruby.hit_latency_hist::gmean 552.825422 -system.ruby.hit_latency_hist::stdev 803.774497 -system.ruby.hit_latency_hist | 930 33.13% 33.13% | 469 16.71% 49.84% | 481 17.14% 66.98% | 503 17.92% 84.89% | 338 12.04% 96.94% | 81 2.89% 99.82% | 4 0.14% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2807 +system.ruby.hit_latency_hist::samples 2844 +system.ruby.hit_latency_hist::mean 1057.367440 +system.ruby.hit_latency_hist::gmean 516.362786 +system.ruby.hit_latency_hist::stdev 803.056004 +system.ruby.hit_latency_hist | 983 34.56% 34.56% | 524 18.42% 52.99% | 459 16.14% 69.13% | 465 16.35% 85.48% | 334 11.74% 97.22% | 70 2.46% 99.68% | 8 0.28% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 2844 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 623444 -system.ruby.miss_latency_hist::mean 1206.941660 -system.ruby.miss_latency_hist::gmean 906.754630 -system.ruby.miss_latency_hist::stdev 768.164015 -system.ruby.miss_latency_hist | 167609 26.88% 26.88% | 117611 18.86% 45.75% | 109470 17.56% 63.31% | 120002 19.25% 82.56% | 86304 13.84% 96.40% | 20887 3.35% 99.75% | 1525 0.24% 99.99% | 36 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 623444 -system.ruby.L1Cache.incomplete_times 1328 -system.ruby.Directory.incomplete_times 622112 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 77927 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77944 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl5.L1Dcache.demand_hits 21 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78444 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78465 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 77976 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77993 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 19 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 77954 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77973 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 29 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78780 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78809 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 624407 +system.ruby.miss_latency_hist::mean 1200.607091 +system.ruby.miss_latency_hist::gmean 901.592507 +system.ruby.miss_latency_hist::stdev 764.698426 +system.ruby.miss_latency_hist | 168458 26.98% 26.98% | 117382 18.80% 45.78% | 112567 18.03% 63.81% | 119036 19.06% 82.87% | 85189 13.64% 96.51% | 20322 3.25% 99.77% | 1424 0.23% 100.00% | 29 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 624407 +system.ruby.L1Cache.incomplete_times 1293 +system.ruby.Directory.incomplete_times 623110 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 21 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78749 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78770 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers00.percent_links_utilized 9.742411 -system.ruby.network.routers00.msg_count.Request_Control::1 78780 -system.ruby.network.routers00.msg_count.Response_Data::4 80165 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 245 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 173 -system.ruby.network.routers00.msg_count.Response_Control::4 76 -system.ruby.network.routers00.msg_count.Writeback_Data::4 85320 -system.ruby.network.routers00.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers00.msg_count.Persistent_Control::3 102424 -system.ruby.network.routers00.msg_bytes.Request_Control::1 630240 -system.ruby.network.routers00.msg_bytes.Response_Data::4 5771880 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 17640 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 12456 -system.ruby.network.routers00.msg_bytes.Response_Control::4 608 -system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6143040 -system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers00.msg_bytes.Persistent_Control::3 819392 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 22 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78342 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78364 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78393 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78412 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers01.percent_links_utilized 9.710031 -system.ruby.network.routers01.msg_count.Request_Control::1 78342 -system.ruby.network.routers01.msg_count.Response_Data::4 79850 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 247 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 189 -system.ruby.network.routers01.msg_count.Response_Control::4 93 -system.ruby.network.routers01.msg_count.Writeback_Data::4 84812 -system.ruby.network.routers01.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers01.msg_count.Persistent_Control::3 102444 -system.ruby.network.routers01.msg_bytes.Request_Control::1 626736 -system.ruby.network.routers01.msg_bytes.Response_Data::4 5749200 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 17784 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 13608 -system.ruby.network.routers01.msg_bytes.Response_Control::4 744 -system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6106464 -system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers01.msg_bytes.Persistent_Control::3 819552 -system.ruby.l1_cntrl2.L1Dcache.demand_hits 15 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78430 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78445 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 27 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78544 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78571 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers02.percent_links_utilized 9.719589 -system.ruby.network.routers02.msg_count.Request_Control::1 78430 -system.ruby.network.routers02.msg_count.Response_Data::4 80036 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 234 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 212 -system.ruby.network.routers02.msg_count.Response_Control::4 106 -system.ruby.network.routers02.msg_count.Writeback_Data::4 84849 -system.ruby.network.routers02.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers02.msg_count.Persistent_Control::3 102504 -system.ruby.network.routers02.msg_bytes.Request_Control::1 627440 -system.ruby.network.routers02.msg_bytes.Response_Data::4 5762592 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 16848 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 15264 -system.ruby.network.routers02.msg_bytes.Response_Control::4 848 -system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6109128 -system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers02.msg_bytes.Persistent_Control::3 820032 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 23 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78256 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78279 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 24 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78065 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78089 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers03.percent_links_utilized 9.695103 -system.ruby.network.routers03.msg_count.Request_Control::1 78256 -system.ruby.network.routers03.msg_count.Response_Data::4 79763 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 209 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 161 -system.ruby.network.routers03.msg_count.Response_Control::4 98 -system.ruby.network.routers03.msg_count.Writeback_Data::4 84605 -system.ruby.network.routers03.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers03.msg_count.Persistent_Control::3 102240 -system.ruby.network.routers03.msg_bytes.Request_Control::1 626048 -system.ruby.network.routers03.msg_bytes.Response_Data::4 5742936 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 15048 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 11592 -system.ruby.network.routers03.msg_bytes.Response_Control::4 784 -system.ruby.network.routers03.msg_bytes.Writeback_Data::4 6091560 -system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers03.msg_bytes.Persistent_Control::3 817920 -system.ruby.network.routers04.percent_links_utilized 9.671218 -system.ruby.network.routers04.msg_count.Request_Control::1 77927 -system.ruby.network.routers04.msg_count.Response_Data::4 79373 -system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 240 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 191 -system.ruby.network.routers04.msg_count.Response_Control::4 96 -system.ruby.network.routers04.msg_count.Writeback_Data::4 84339 -system.ruby.network.routers04.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers04.msg_count.Persistent_Control::3 102286 -system.ruby.network.routers04.msg_bytes.Request_Control::1 623416 -system.ruby.network.routers04.msg_bytes.Response_Data::4 5714856 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 17280 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 13752 -system.ruby.network.routers04.msg_bytes.Response_Control::4 768 -system.ruby.network.routers04.msg_bytes.Writeback_Data::4 6072408 -system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers04.msg_bytes.Persistent_Control::3 818288 -system.ruby.network.routers05.percent_links_utilized 9.714227 -system.ruby.network.routers05.msg_count.Request_Control::1 78443 -system.ruby.network.routers05.msg_count.Response_Data::4 79833 -system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 223 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 191 -system.ruby.network.routers05.msg_count.Response_Control::4 88 -system.ruby.network.routers05.msg_count.Writeback_Data::4 84971 -system.ruby.network.routers05.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers05.msg_count.Persistent_Control::3 102260 -system.ruby.network.routers05.msg_bytes.Request_Control::1 627544 -system.ruby.network.routers05.msg_bytes.Response_Data::4 5747976 -system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 16056 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 13752 -system.ruby.network.routers05.msg_bytes.Response_Control::4 704 -system.ruby.network.routers05.msg_bytes.Writeback_Data::4 6117912 -system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers05.msg_bytes.Persistent_Control::3 818080 -system.ruby.network.routers06.percent_links_utilized 9.677168 -system.ruby.network.routers06.msg_count.Request_Control::1 77976 -system.ruby.network.routers06.msg_count.Response_Data::4 79371 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 225 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 160 -system.ruby.network.routers06.msg_count.Response_Control::4 78 -system.ruby.network.routers06.msg_count.Writeback_Data::4 84535 -system.ruby.network.routers06.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers06.msg_count.Persistent_Control::3 102328 -system.ruby.network.routers06.msg_bytes.Request_Control::1 623808 -system.ruby.network.routers06.msg_bytes.Response_Data::4 5714712 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 16200 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 11520 -system.ruby.network.routers06.msg_bytes.Response_Control::4 624 -system.ruby.network.routers06.msg_bytes.Writeback_Data::4 6086520 -system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers06.msg_bytes.Persistent_Control::3 818624 -system.ruby.network.routers07.percent_links_utilized 9.675588 -system.ruby.network.routers07.msg_count.Request_Control::1 77953 -system.ruby.network.routers07.msg_count.Response_Data::4 79349 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 241 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 187 -system.ruby.network.routers07.msg_count.Response_Control::4 91 -system.ruby.network.routers07.msg_count.Writeback_Data::4 84477 -system.ruby.network.routers07.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers07.msg_count.Persistent_Control::3 102298 -system.ruby.network.routers07.msg_bytes.Request_Control::1 623624 -system.ruby.network.routers07.msg_bytes.Response_Data::4 5713128 -system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 17352 -system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 13464 -system.ruby.network.routers07.msg_bytes.Response_Control::4 728 -system.ruby.network.routers07.msg_bytes.Writeback_Data::4 6082344 -system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers07.msg_bytes.Persistent_Control::3 818384 -system.ruby.l2_cntrl0.L2cache.demand_hits 1784 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 624319 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 626103 # Number of cache demand accesses -system.ruby.network.routers08.percent_links_utilized 40.519928 -system.ruby.network.routers08.msg_count.Request_Control::1 626105 -system.ruby.network.routers08.msg_count.Request_Control::2 624315 -system.ruby.network.routers08.msg_count.Response_Data::4 7830 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1784 -system.ruby.network.routers08.msg_count.Response_Control::4 713 -system.ruby.network.routers08.msg_count.Writeback_Data::4 862238 -system.ruby.network.routers08.msg_count.Writeback_Control::4 379354 -system.ruby.network.routers08.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers08.msg_bytes.Request_Control::1 5008840 -system.ruby.network.routers08.msg_bytes.Request_Control::2 4994520 -system.ruby.network.routers08.msg_bytes.Response_Data::4 563760 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 128448 -system.ruby.network.routers08.msg_bytes.Response_Control::4 5704 -system.ruby.network.routers08.msg_bytes.Writeback_Data::4 62081136 -system.ruby.network.routers08.msg_bytes.Writeback_Control::4 3034832 -system.ruby.network.routers08.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers09.percent_links_utilized 37.644894 -system.ruby.network.routers09.msg_count.Request_Control::2 624315 -system.ruby.network.routers09.msg_count.Response_Data::4 628897 -system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 80 -system.ruby.network.routers09.msg_count.Response_Control::4 3 -system.ruby.network.routers09.msg_count.Writeback_Data::4 237089 -system.ruby.network.routers09.msg_count.Writeback_Control::4 379353 -system.ruby.network.routers09.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers09.msg_bytes.Request_Control::2 4994520 -system.ruby.network.routers09.msg_bytes.Response_Data::4 45280584 -system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 5760 -system.ruby.network.routers09.msg_bytes.Response_Control::4 24 -system.ruby.network.routers09.msg_bytes.Writeback_Data::4 17070408 -system.ruby.network.routers09.msg_bytes.Writeback_Control::4 3034824 -system.ruby.network.routers09.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers10.percent_links_utilized 17.437599 -system.ruby.network.routers10.msg_count.Request_Control::1 626105 -system.ruby.network.routers10.msg_count.Request_Control::2 624315 -system.ruby.network.routers10.msg_count.Response_Data::4 637234 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1864 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 732 -system.ruby.network.routers10.msg_count.Response_Control::4 721 -system.ruby.network.routers10.msg_count.Writeback_Data::4 888618 -system.ruby.network.routers10.msg_count.Writeback_Control::4 379353 -system.ruby.network.routers10.msg_count.Broadcast_Control::1 4382749 -system.ruby.network.routers10.msg_count.Persistent_Control::3 818784 -system.ruby.network.routers10.msg_bytes.Request_Control::1 5008840 -system.ruby.network.routers10.msg_bytes.Request_Control::2 4994520 -system.ruby.network.routers10.msg_bytes.Response_Data::4 45880848 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 134208 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 52704 -system.ruby.network.routers10.msg_bytes.Response_Control::4 5768 -system.ruby.network.routers10.msg_bytes.Writeback_Data::4 63980496 -system.ruby.network.routers10.msg_bytes.Writeback_Control::4 3034824 -system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35061992 -system.ruby.network.routers10.msg_bytes.Persistent_Control::3 6550272 -system.ruby.network.msg_count.Request_Control 3751262 -system.ruby.network.msg_count.Response_Data 1911701 -system.ruby.network.msg_count.ResponseL2hit_Data 5592 -system.ruby.network.msg_count.ResponseLocal_Data 2196 -system.ruby.network.msg_count.Response_Control 2163 -system.ruby.network.msg_count.Writeback_Data 2665853 -system.ruby.network.msg_count.Writeback_Control 1138060 -system.ruby.network.msg_count.Broadcast_Control 9391605 -system.ruby.network.msg_count.Persistent_Control 1819520 -system.ruby.network.msg_byte.Request_Control 30010096 -system.ruby.network.msg_byte.Response_Data 137642472 -system.ruby.network.msg_byte.ResponseL2hit_Data 402624 -system.ruby.network.msg_byte.ResponseLocal_Data 158112 -system.ruby.network.msg_byte.Response_Control 17304 -system.ruby.network.msg_byte.Writeback_Data 191941416 -system.ruby.network.msg_byte.Writeback_Control 9104480 -system.ruby.network.msg_byte.Broadcast_Control 75132840 -system.ruby.network.msg_byte.Persistent_Control 14556160 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 24 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78237 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78261 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 25 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78351 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78376 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78471 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78490 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 27 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78277 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78304 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 1846 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 625240 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 627086 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 99493 # number of read accesses completed -system.cpu0.num_writes 55749 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99510 # number of read accesses completed -system.cpu1.num_writes 55185 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 55529 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99207 # number of read accesses completed -system.cpu3.num_writes 55624 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99506 # number of read accesses completed -system.cpu4.num_writes 55147 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99763 # number of read accesses completed -system.cpu5.num_writes 55468 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98903 # number of read accesses completed -system.cpu6.num_writes 54921 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99232 # number of read accesses completed -system.cpu7.num_writes 54585 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers00.throttle0.link_utilization 11.727792 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 79274 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 233 -system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4 95 -system.ruby.network.routers00.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4 3327 -system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1 547327 -system.ruby.network.routers00.throttle0.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::4 5707728 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::4 16776 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::4 6840 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Data::4 239544 -system.ruby.network.routers00.throttle0.msg_bytes.Broadcast_Control::1 4378616 -system.ruby.network.routers00.throttle0.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers00.throttle1.link_utilization 7.757029 -system.ruby.network.routers00.throttle1.msg_count.Request_Control::1 78780 -system.ruby.network.routers00.throttle1.msg_count.Response_Data::4 891 -system.ruby.network.routers00.throttle1.msg_count.ResponseL2hit_Data::4 12 -system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::4 78 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::4 75 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::4 81993 -system.ruby.network.routers00.throttle1.msg_count.Broadcast_Control::1 78780 -system.ruby.network.routers00.throttle1.msg_count.Persistent_Control::3 11448 -system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::1 630240 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::4 64152 -system.ruby.network.routers00.throttle1.msg_bytes.ResponseL2hit_Data::4 864 -system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::4 5616 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::4 600 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::4 5903496 -system.ruby.network.routers00.throttle1.msg_bytes.Broadcast_Control::1 630240 -system.ruby.network.routers00.throttle1.msg_bytes.Persistent_Control::3 91584 -system.ruby.network.routers01.throttle0.link_utilization 11.700088 -system.ruby.network.routers01.throttle0.msg_count.Response_Data::4 78881 -system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::4 231 -system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::4 99 -system.ruby.network.routers01.throttle0.msg_count.Writeback_Data::4 3306 -system.ruby.network.routers01.throttle0.msg_count.Broadcast_Control::1 547765 -system.ruby.network.routers01.throttle0.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::4 5679432 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::4 16632 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::4 7128 -system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Data::4 238032 -system.ruby.network.routers01.throttle0.msg_bytes.Broadcast_Control::1 4382120 -system.ruby.network.routers01.throttle0.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers01.throttle1.link_utilization 7.719974 -system.ruby.network.routers01.throttle1.msg_count.Request_Control::1 78342 +system.ruby.network.routers00.percent_links_utilized 9.769549 +system.ruby.network.routers00.msg_count.Request_Control::1 78749 +system.ruby.network.routers00.msg_count.Response_Data::4 80262 +system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 229 +system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 199 +system.ruby.network.routers00.msg_count.Response_Control::4 85 +system.ruby.network.routers00.msg_count.Writeback_Data::4 85149 +system.ruby.network.routers00.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers00.msg_count.Persistent_Control::3 99744 +system.ruby.network.routers00.msg_bytes.Request_Control::1 629992 +system.ruby.network.routers00.msg_bytes.Response_Data::4 5778864 +system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 16488 +system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 14328 +system.ruby.network.routers00.msg_bytes.Response_Control::4 680 +system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6130728 +system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers00.msg_bytes.Persistent_Control::3 797952 +system.ruby.network.routers01.percent_links_utilized 9.734067 +system.ruby.network.routers01.msg_count.Request_Control::1 78393 +system.ruby.network.routers01.msg_count.Response_Data::4 79915 +system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 248 +system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 173 +system.ruby.network.routers01.msg_count.Response_Control::4 88 +system.ruby.network.routers01.msg_count.Writeback_Data::4 84641 +system.ruby.network.routers01.msg_count.Writeback_Control::4 2 +system.ruby.network.routers01.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers01.msg_count.Persistent_Control::3 99506 +system.ruby.network.routers01.msg_bytes.Request_Control::1 627144 +system.ruby.network.routers01.msg_bytes.Response_Data::4 5753880 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 17856 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 12456 +system.ruby.network.routers01.msg_bytes.Response_Control::4 704 +system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6094152 +system.ruby.network.routers01.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers01.msg_bytes.Persistent_Control::3 796048 +system.ruby.network.routers02.percent_links_utilized 9.751836 +system.ruby.network.routers02.msg_count.Request_Control::1 78544 +system.ruby.network.routers02.msg_count.Response_Data::4 80094 +system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 265 +system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 179 +system.ruby.network.routers02.msg_count.Response_Control::4 92 +system.ruby.network.routers02.msg_count.Writeback_Data::4 84876 +system.ruby.network.routers02.msg_count.Writeback_Control::4 2 +system.ruby.network.routers02.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers02.msg_count.Persistent_Control::3 99598 +system.ruby.network.routers02.msg_bytes.Request_Control::1 628352 +system.ruby.network.routers02.msg_bytes.Response_Data::4 5766768 +system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 19080 +system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 12888 +system.ruby.network.routers02.msg_bytes.Response_Control::4 736 +system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6111072 +system.ruby.network.routers02.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers02.msg_bytes.Persistent_Control::3 796784 +system.ruby.network.routers03.percent_links_utilized 9.705650 +system.ruby.network.routers03.msg_count.Request_Control::1 78065 +system.ruby.network.routers03.msg_count.Response_Data::4 79606 +system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 252 +system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 181 +system.ruby.network.routers03.msg_count.Response_Control::4 73 +system.ruby.network.routers03.msg_count.Writeback_Data::4 84239 +system.ruby.network.routers03.msg_count.Broadcast_Control::1 627087 +system.ruby.network.routers03.msg_count.Persistent_Control::3 99456 +system.ruby.network.routers03.msg_bytes.Request_Control::1 624520 +system.ruby.network.routers03.msg_bytes.Response_Data::4 5731632 +system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 18144 +system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 13032 +system.ruby.network.routers03.msg_bytes.Response_Control::4 584 +system.ruby.network.routers03.msg_bytes.Writeback_Data::4 6065208 +system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5016696 +system.ruby.network.routers03.msg_bytes.Persistent_Control::3 795648 +system.ruby.network.routers04.percent_links_utilized 9.729195 +system.ruby.network.routers04.msg_count.Request_Control::1 78237 +system.ruby.network.routers04.msg_count.Response_Data::4 79812 +system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 252 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 208 +system.ruby.network.routers04.msg_count.Response_Control::4 89 +system.ruby.network.routers04.msg_count.Writeback_Data::4 84584 +system.ruby.network.routers04.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers04.msg_count.Persistent_Control::3 99606 +system.ruby.network.routers04.msg_bytes.Request_Control::1 625896 +system.ruby.network.routers04.msg_bytes.Response_Data::4 5746464 +system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 18144 +system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 14976 +system.ruby.network.routers04.msg_bytes.Response_Control::4 712 +system.ruby.network.routers04.msg_bytes.Writeback_Data::4 6090048 +system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers04.msg_bytes.Persistent_Control::3 796848 +system.ruby.network.routers05.percent_links_utilized 9.733064 +system.ruby.network.routers05.msg_count.Request_Control::1 78351 +system.ruby.network.routers05.msg_count.Response_Data::4 79847 +system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 229 +system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 176 +system.ruby.network.routers05.msg_count.Response_Control::4 95 +system.ruby.network.routers05.msg_count.Writeback_Data::4 84692 +system.ruby.network.routers05.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers05.msg_count.Persistent_Control::3 99604 +system.ruby.network.routers05.msg_bytes.Request_Control::1 626808 +system.ruby.network.routers05.msg_bytes.Response_Data::4 5748984 +system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 16488 +system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 12672 +system.ruby.network.routers05.msg_bytes.Response_Control::4 760 +system.ruby.network.routers05.msg_bytes.Writeback_Data::4 6097824 +system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers05.msg_bytes.Persistent_Control::3 796832 +system.ruby.network.routers06.percent_links_utilized 9.739151 +system.ruby.network.routers06.msg_count.Request_Control::1 78471 +system.ruby.network.routers06.msg_count.Response_Data::4 80021 +system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 245 +system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 162 +system.ruby.network.routers06.msg_count.Response_Control::4 76 +system.ruby.network.routers06.msg_count.Writeback_Data::4 84699 +system.ruby.network.routers06.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers06.msg_count.Persistent_Control::3 99288 +system.ruby.network.routers06.msg_bytes.Request_Control::1 627768 +system.ruby.network.routers06.msg_bytes.Response_Data::4 5761512 +system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 17640 +system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 11664 +system.ruby.network.routers06.msg_bytes.Response_Control::4 608 +system.ruby.network.routers06.msg_bytes.Writeback_Data::4 6098328 +system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers06.msg_bytes.Persistent_Control::3 794304 +system.ruby.network.routers07.percent_links_utilized 9.723397 +system.ruby.network.routers07.msg_count.Request_Control::1 78277 +system.ruby.network.routers07.msg_count.Response_Data::4 79832 +system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 226 +system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 190 +system.ruby.network.routers07.msg_count.Response_Control::4 90 +system.ruby.network.routers07.msg_count.Writeback_Data::4 84486 +system.ruby.network.routers07.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers07.msg_count.Persistent_Control::3 99302 +system.ruby.network.routers07.msg_bytes.Request_Control::1 626216 +system.ruby.network.routers07.msg_bytes.Response_Data::4 5747904 +system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 16272 +system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 13680 +system.ruby.network.routers07.msg_bytes.Response_Control::4 720 +system.ruby.network.routers07.msg_bytes.Writeback_Data::4 6082992 +system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers07.msg_bytes.Persistent_Control::3 794416 +system.ruby.network.routers08.percent_links_utilized 40.706771 +system.ruby.network.routers08.msg_count.Request_Control::1 627086 +system.ruby.network.routers08.msg_count.Request_Control::2 625240 +system.ruby.network.routers08.msg_count.Response_Data::4 8185 +system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1849 +system.ruby.network.routers08.msg_count.Response_Control::4 670 +system.ruby.network.routers08.msg_count.Writeback_Data::4 862628 +system.ruby.network.routers08.msg_count.Writeback_Control::4 380561 +system.ruby.network.routers08.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers08.msg_bytes.Request_Control::1 5016688 +system.ruby.network.routers08.msg_bytes.Request_Control::2 5001920 +system.ruby.network.routers08.msg_bytes.Response_Data::4 589320 +system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 133128 +system.ruby.network.routers08.msg_bytes.Response_Control::4 5360 +system.ruby.network.routers08.msg_bytes.Writeback_Data::4 62109216 +system.ruby.network.routers08.msg_bytes.Writeback_Control::4 3044488 +system.ruby.network.routers08.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers09.percent_links_utilized 37.815867 +system.ruby.network.routers09.msg_count.Request_Control::2 625238 +system.ruby.network.routers09.msg_count.Response_Data::4 630263 +system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 97 +system.ruby.network.routers09.msg_count.Response_Control::4 4 +system.ruby.network.routers09.msg_count.Writeback_Data::4 236490 +system.ruby.network.routers09.msg_count.Writeback_Control::4 380565 +system.ruby.network.routers09.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers09.msg_bytes.Request_Control::2 5001904 +system.ruby.network.routers09.msg_bytes.Response_Data::4 45378936 +system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 6984 +system.ruby.network.routers09.msg_bytes.Response_Control::4 32 +system.ruby.network.routers09.msg_bytes.Writeback_Data::4 17027280 +system.ruby.network.routers09.msg_bytes.Writeback_Control::4 3044520 +system.ruby.network.routers09.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers10.percent_links_utilized 17.503496 +system.ruby.network.routers10.msg_count.Request_Control::1 627087 +system.ruby.network.routers10.msg_count.Request_Control::2 625240 +system.ruby.network.routers10.msg_count.Response_Data::4 638918 +system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1946 +system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 734 +system.ruby.network.routers10.msg_count.Response_Control::4 681 +system.ruby.network.routers10.msg_count.Writeback_Data::4 888242 +system.ruby.network.routers10.msg_count.Writeback_Control::4 380565 +system.ruby.network.routers10.msg_count.Broadcast_Control::1 4389609 +system.ruby.network.routers10.msg_count.Persistent_Control::3 796104 +system.ruby.network.routers10.msg_bytes.Request_Control::1 5016696 +system.ruby.network.routers10.msg_bytes.Request_Control::2 5001920 +system.ruby.network.routers10.msg_bytes.Response_Data::4 46002096 +system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 140112 +system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 52848 +system.ruby.network.routers10.msg_bytes.Response_Control::4 5448 +system.ruby.network.routers10.msg_bytes.Writeback_Data::4 63953424 +system.ruby.network.routers10.msg_bytes.Writeback_Control::4 3044520 +system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35116872 +system.ruby.network.routers10.msg_bytes.Persistent_Control::3 6368832 +system.ruby.network.msg_count.Request_Control 3756978 +system.ruby.network.msg_count.Response_Data 1916755 +system.ruby.network.msg_count.ResponseL2hit_Data 5838 +system.ruby.network.msg_count.ResponseLocal_Data 2202 +system.ruby.network.msg_count.Response_Control 2043 +system.ruby.network.msg_count.Writeback_Data 2664726 +system.ruby.network.msg_count.Writeback_Control 1141695 +system.ruby.network.msg_count.Broadcast_Control 9406298 +system.ruby.network.msg_count.Persistent_Control 1769120 +system.ruby.network.msg_byte.Request_Control 30055824 +system.ruby.network.msg_byte.Response_Data 138006360 +system.ruby.network.msg_byte.ResponseL2hit_Data 420336 +system.ruby.network.msg_byte.ResponseLocal_Data 158544 +system.ruby.network.msg_byte.Response_Control 16344 +system.ruby.network.msg_byte.Writeback_Data 191860272 +system.ruby.network.msg_byte.Writeback_Control 9133560 +system.ruby.network.msg_byte.Broadcast_Control 75250384 +system.ruby.network.msg_byte.Persistent_Control 14152960 +system.ruby.network.routers00.throttle0.link_utilization 11.756719 +system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 79304 +system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 218 +system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4 108 +system.ruby.network.routers00.throttle0.msg_count.Response_Control::4 2 +system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4 3264 +system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1 548337 +system.ruby.network.routers00.throttle0.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::4 5709888 +system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::4 15696 +system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::4 7776 +system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::4 16 +system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Data::4 235008 +system.ruby.network.routers00.throttle0.msg_bytes.Broadcast_Control::1 4386696 +system.ruby.network.routers00.throttle0.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers00.throttle1.link_utilization 7.782380 +system.ruby.network.routers00.throttle1.msg_count.Request_Control::1 78749 +system.ruby.network.routers00.throttle1.msg_count.Response_Data::4 958 +system.ruby.network.routers00.throttle1.msg_count.ResponseL2hit_Data::4 11 +system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::4 91 +system.ruby.network.routers00.throttle1.msg_count.Response_Control::4 83 +system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::4 81885 +system.ruby.network.routers00.throttle1.msg_count.Broadcast_Control::1 78749 +system.ruby.network.routers00.throttle1.msg_count.Persistent_Control::3 11288 +system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::1 629992 +system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::4 68976 +system.ruby.network.routers00.throttle1.msg_bytes.ResponseL2hit_Data::4 792 +system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::4 6552 +system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::4 664 +system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::4 5895720 +system.ruby.network.routers00.throttle1.msg_bytes.Broadcast_Control::1 629992 +system.ruby.network.routers00.throttle1.msg_bytes.Persistent_Control::3 90304 +system.ruby.network.routers01.throttle0.link_utilization 11.725925 +system.ruby.network.routers01.throttle0.msg_count.Response_Data::4 78946 +system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::4 242 +system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::4 74 +system.ruby.network.routers01.throttle0.msg_count.Response_Control::4 1 +system.ruby.network.routers01.throttle0.msg_count.Writeback_Data::4 3190 +system.ruby.network.routers01.throttle0.msg_count.Writeback_Control::4 1 +system.ruby.network.routers01.throttle0.msg_count.Broadcast_Control::1 548693 +system.ruby.network.routers01.throttle0.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::4 5684112 +system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::4 17424 +system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::4 5328 +system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::4 8 +system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Data::4 229680 +system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers01.throttle0.msg_bytes.Broadcast_Control::1 4389544 +system.ruby.network.routers01.throttle0.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers01.throttle1.link_utilization 7.742209 +system.ruby.network.routers01.throttle1.msg_count.Request_Control::1 78393 system.ruby.network.routers01.throttle1.msg_count.Response_Data::4 969 -system.ruby.network.routers01.throttle1.msg_count.ResponseL2hit_Data::4 16 -system.ruby.network.routers01.throttle1.msg_count.ResponseLocal_Data::4 90 -system.ruby.network.routers01.throttle1.msg_count.Response_Control::4 93 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::4 81506 -system.ruby.network.routers01.throttle1.msg_count.Broadcast_Control::1 78342 -system.ruby.network.routers01.throttle1.msg_count.Persistent_Control::3 11468 -system.ruby.network.routers01.throttle1.msg_bytes.Request_Control::1 626736 +system.ruby.network.routers01.throttle1.msg_count.ResponseL2hit_Data::4 6 +system.ruby.network.routers01.throttle1.msg_count.ResponseLocal_Data::4 99 +system.ruby.network.routers01.throttle1.msg_count.Response_Control::4 87 +system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::4 81451 +system.ruby.network.routers01.throttle1.msg_count.Writeback_Control::4 1 +system.ruby.network.routers01.throttle1.msg_count.Broadcast_Control::1 78393 +system.ruby.network.routers01.throttle1.msg_count.Persistent_Control::3 11050 +system.ruby.network.routers01.throttle1.msg_bytes.Request_Control::1 627144 system.ruby.network.routers01.throttle1.msg_bytes.Response_Data::4 69768 -system.ruby.network.routers01.throttle1.msg_bytes.ResponseL2hit_Data::4 1152 -system.ruby.network.routers01.throttle1.msg_bytes.ResponseLocal_Data::4 6480 -system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::4 744 -system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::4 5868432 -system.ruby.network.routers01.throttle1.msg_bytes.Broadcast_Control::1 626736 -system.ruby.network.routers01.throttle1.msg_bytes.Persistent_Control::3 91744 -system.ruby.network.routers02.throttle0.link_utilization 11.707871 -system.ruby.network.routers02.throttle0.msg_count.Response_Data::4 79034 -system.ruby.network.routers02.throttle0.msg_count.ResponseL2hit_Data::4 225 -system.ruby.network.routers02.throttle0.msg_count.ResponseLocal_Data::4 89 -system.ruby.network.routers02.throttle0.msg_count.Writeback_Data::4 3281 -system.ruby.network.routers02.throttle0.msg_count.Broadcast_Control::1 547677 -system.ruby.network.routers02.throttle0.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers02.throttle0.msg_bytes.Response_Data::4 5690448 -system.ruby.network.routers02.throttle0.msg_bytes.ResponseL2hit_Data::4 16200 -system.ruby.network.routers02.throttle0.msg_bytes.ResponseLocal_Data::4 6408 -system.ruby.network.routers02.throttle0.msg_bytes.Writeback_Data::4 236232 -system.ruby.network.routers02.throttle0.msg_bytes.Broadcast_Control::1 4381416 -system.ruby.network.routers02.throttle0.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers02.throttle1.link_utilization 7.731306 -system.ruby.network.routers02.throttle1.msg_count.Request_Control::1 78430 -system.ruby.network.routers02.throttle1.msg_count.Response_Data::4 1002 -system.ruby.network.routers02.throttle1.msg_count.ResponseL2hit_Data::4 9 -system.ruby.network.routers02.throttle1.msg_count.ResponseLocal_Data::4 123 -system.ruby.network.routers02.throttle1.msg_count.Response_Control::4 106 -system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::4 81568 -system.ruby.network.routers02.throttle1.msg_count.Broadcast_Control::1 78430 -system.ruby.network.routers02.throttle1.msg_count.Persistent_Control::3 11528 -system.ruby.network.routers02.throttle1.msg_bytes.Request_Control::1 627440 -system.ruby.network.routers02.throttle1.msg_bytes.Response_Data::4 72144 -system.ruby.network.routers02.throttle1.msg_bytes.ResponseL2hit_Data::4 648 -system.ruby.network.routers02.throttle1.msg_bytes.ResponseLocal_Data::4 8856 -system.ruby.network.routers02.throttle1.msg_bytes.Response_Control::4 848 -system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::4 5872896 -system.ruby.network.routers02.throttle1.msg_bytes.Broadcast_Control::1 627440 -system.ruby.network.routers02.throttle1.msg_bytes.Persistent_Control::3 92224 -system.ruby.network.routers03.throttle0.link_utilization 11.687942 -system.ruby.network.routers03.throttle0.msg_count.Response_Data::4 78824 -system.ruby.network.routers03.throttle0.msg_count.ResponseL2hit_Data::4 200 -system.ruby.network.routers03.throttle0.msg_count.ResponseLocal_Data::4 76 +system.ruby.network.routers01.throttle1.msg_bytes.ResponseL2hit_Data::4 432 +system.ruby.network.routers01.throttle1.msg_bytes.ResponseLocal_Data::4 7128 +system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::4 696 +system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::4 5864472 +system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers01.throttle1.msg_bytes.Broadcast_Control::1 627144 +system.ruby.network.routers01.throttle1.msg_bytes.Persistent_Control::3 88400 +system.ruby.network.routers02.throttle0.link_utilization 11.742087 +system.ruby.network.routers02.throttle0.msg_count.Response_Data::4 79112 +system.ruby.network.routers02.throttle0.msg_count.ResponseL2hit_Data::4 252 +system.ruby.network.routers02.throttle0.msg_count.ResponseLocal_Data::4 80 +system.ruby.network.routers02.throttle0.msg_count.Response_Control::4 1 +system.ruby.network.routers02.throttle0.msg_count.Writeback_Data::4 3236 +system.ruby.network.routers02.throttle0.msg_count.Writeback_Control::4 1 +system.ruby.network.routers02.throttle0.msg_count.Broadcast_Control::1 548542 +system.ruby.network.routers02.throttle0.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers02.throttle0.msg_bytes.Response_Data::4 5696064 +system.ruby.network.routers02.throttle0.msg_bytes.ResponseL2hit_Data::4 18144 +system.ruby.network.routers02.throttle0.msg_bytes.ResponseLocal_Data::4 5760 +system.ruby.network.routers02.throttle0.msg_bytes.Response_Control::4 8 +system.ruby.network.routers02.throttle0.msg_bytes.Writeback_Data::4 232992 +system.ruby.network.routers02.throttle0.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers02.throttle0.msg_bytes.Broadcast_Control::1 4388336 +system.ruby.network.routers02.throttle0.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers02.throttle1.link_utilization 7.761585 +system.ruby.network.routers02.throttle1.msg_count.Request_Control::1 78544 +system.ruby.network.routers02.throttle1.msg_count.Response_Data::4 982 +system.ruby.network.routers02.throttle1.msg_count.ResponseL2hit_Data::4 13 +system.ruby.network.routers02.throttle1.msg_count.ResponseLocal_Data::4 99 +system.ruby.network.routers02.throttle1.msg_count.Response_Control::4 91 +system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::4 81640 +system.ruby.network.routers02.throttle1.msg_count.Writeback_Control::4 1 +system.ruby.network.routers02.throttle1.msg_count.Broadcast_Control::1 78544 +system.ruby.network.routers02.throttle1.msg_count.Persistent_Control::3 11142 +system.ruby.network.routers02.throttle1.msg_bytes.Request_Control::1 628352 +system.ruby.network.routers02.throttle1.msg_bytes.Response_Data::4 70704 +system.ruby.network.routers02.throttle1.msg_bytes.ResponseL2hit_Data::4 936 +system.ruby.network.routers02.throttle1.msg_bytes.ResponseLocal_Data::4 7128 +system.ruby.network.routers02.throttle1.msg_bytes.Response_Control::4 728 +system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::4 5878080 +system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers02.throttle1.msg_bytes.Broadcast_Control::1 628352 +system.ruby.network.routers02.throttle1.msg_bytes.Persistent_Control::3 89136 +system.ruby.network.routers03.throttle0.link_utilization 11.702315 +system.ruby.network.routers03.throttle0.msg_count.Response_Data::4 78622 +system.ruby.network.routers03.throttle0.msg_count.ResponseL2hit_Data::4 241 +system.ruby.network.routers03.throttle0.msg_count.ResponseLocal_Data::4 92 system.ruby.network.routers03.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers03.throttle0.msg_count.Writeback_Data::4 3248 -system.ruby.network.routers03.throttle0.msg_count.Broadcast_Control::1 547851 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+system.ruby.network.routers07.throttle1.msg_bytes.ResponseL2hit_Data::4 792 +system.ruby.network.routers07.throttle1.msg_bytes.ResponseLocal_Data::4 6624 +system.ruby.network.routers07.throttle1.msg_bytes.Response_Control::4 696 +system.ruby.network.routers07.throttle1.msg_bytes.Writeback_Data::4 5854536 +system.ruby.network.routers07.throttle1.msg_bytes.Broadcast_Control::1 626216 +system.ruby.network.routers07.throttle1.msg_bytes.Persistent_Control::3 86768 +system.ruby.network.routers08.throttle0.link_utilization 54.018344 +system.ruby.network.routers08.throttle0.msg_count.Request_Control::1 627086 +system.ruby.network.routers08.throttle0.msg_count.Response_Control::4 668 +system.ruby.network.routers08.throttle0.msg_count.Writeback_Data::4 626389 +system.ruby.network.routers08.throttle0.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers08.throttle0.msg_bytes.Request_Control::1 5016688 +system.ruby.network.routers08.throttle0.msg_bytes.Response_Control::4 5344 +system.ruby.network.routers08.throttle0.msg_bytes.Writeback_Data::4 45100008 +system.ruby.network.routers08.throttle0.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers08.throttle1.link_utilization 27.395199 +system.ruby.network.routers08.throttle1.msg_count.Request_Control::2 625240 +system.ruby.network.routers08.throttle1.msg_count.Response_Data::4 8185 +system.ruby.network.routers08.throttle1.msg_count.ResponseL2hit_Data::4 1849 +system.ruby.network.routers08.throttle1.msg_count.Response_Control::4 2 +system.ruby.network.routers08.throttle1.msg_count.Writeback_Data::4 236239 +system.ruby.network.routers08.throttle1.msg_count.Writeback_Control::4 380561 +system.ruby.network.routers08.throttle1.msg_bytes.Request_Control::2 5001920 +system.ruby.network.routers08.throttle1.msg_bytes.Response_Data::4 589320 +system.ruby.network.routers08.throttle1.msg_bytes.ResponseL2hit_Data::4 133128 +system.ruby.network.routers08.throttle1.msg_bytes.Response_Control::4 16 +system.ruby.network.routers08.throttle1.msg_bytes.Writeback_Data::4 17009208 +system.ruby.network.routers08.throttle1.msg_bytes.Writeback_Control::4 3044488 +system.ruby.network.routers09.throttle0.link_utilization 27.943399 +system.ruby.network.routers09.throttle0.msg_count.Request_Control::2 625238 +system.ruby.network.routers09.throttle0.msg_count.Response_Data::4 7338 +system.ruby.network.routers09.throttle0.msg_count.ResponseL2hit_Data::4 97 system.ruby.network.routers09.throttle0.msg_count.Response_Control::4 2 -system.ruby.network.routers09.throttle0.msg_count.Writeback_Data::4 236789 -system.ruby.network.routers09.throttle0.msg_count.Writeback_Control::4 379353 -system.ruby.network.routers09.throttle0.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers09.throttle0.msg_bytes.Request_Control::2 4994520 -system.ruby.network.routers09.throttle0.msg_bytes.Response_Data::4 501048 -system.ruby.network.routers09.throttle0.msg_bytes.ResponseL2hit_Data::4 5760 +system.ruby.network.routers09.throttle0.msg_count.Writeback_Data::4 236174 +system.ruby.network.routers09.throttle0.msg_count.Writeback_Control::4 380563 +system.ruby.network.routers09.throttle0.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers09.throttle0.msg_bytes.Request_Control::2 5001904 +system.ruby.network.routers09.throttle0.msg_bytes.Response_Data::4 528336 +system.ruby.network.routers09.throttle0.msg_bytes.ResponseL2hit_Data::4 6984 system.ruby.network.routers09.throttle0.msg_bytes.Response_Control::4 16 -system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Data::4 17048808 -system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Control::4 3034824 -system.ruby.network.routers09.throttle0.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers09.throttle1.link_utilization 47.431890 -system.ruby.network.routers09.throttle1.msg_count.Response_Data::4 621938 -system.ruby.network.routers09.throttle1.msg_count.Response_Control::4 1 -system.ruby.network.routers09.throttle1.msg_count.Writeback_Data::4 300 -system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::4 44779536 -system.ruby.network.routers09.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Data::4 21600 -system.ruby.network.routers10.throttle0.link_utilization 11.630830 -system.ruby.network.routers10.throttle0.msg_count.Response_Data::4 79274 -system.ruby.network.routers10.throttle0.msg_count.ResponseL2hit_Data::4 233 -system.ruby.network.routers10.throttle0.msg_count.ResponseLocal_Data::4 95 -system.ruby.network.routers10.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle0.msg_count.Writeback_Data::4 3327 -system.ruby.network.routers10.throttle0.msg_count.Broadcast_Control::1 547327 -system.ruby.network.routers10.throttle0.msg_count.Persistent_Control::3 79528 -system.ruby.network.routers10.throttle0.msg_bytes.Response_Data::4 5707728 -system.ruby.network.routers10.throttle0.msg_bytes.ResponseL2hit_Data::4 16776 -system.ruby.network.routers10.throttle0.msg_bytes.ResponseLocal_Data::4 6840 -system.ruby.network.routers10.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle0.msg_bytes.Writeback_Data::4 239544 -system.ruby.network.routers10.throttle0.msg_bytes.Broadcast_Control::1 4378616 -system.ruby.network.routers10.throttle0.msg_bytes.Persistent_Control::3 636224 -system.ruby.network.routers10.throttle1.link_utilization 11.602973 -system.ruby.network.routers10.throttle1.msg_count.Response_Data::4 78882 -system.ruby.network.routers10.throttle1.msg_count.ResponseL2hit_Data::4 231 -system.ruby.network.routers10.throttle1.msg_count.ResponseLocal_Data::4 99 -system.ruby.network.routers10.throttle1.msg_count.Writeback_Data::4 3306 -system.ruby.network.routers10.throttle1.msg_count.Broadcast_Control::1 547765 -system.ruby.network.routers10.throttle1.msg_count.Persistent_Control::3 79508 -system.ruby.network.routers10.throttle1.msg_bytes.Response_Data::4 5679504 -system.ruby.network.routers10.throttle1.msg_bytes.ResponseL2hit_Data::4 16632 -system.ruby.network.routers10.throttle1.msg_bytes.ResponseLocal_Data::4 7128 -system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Data::4 238032 -system.ruby.network.routers10.throttle1.msg_bytes.Broadcast_Control::1 4382120 -system.ruby.network.routers10.throttle1.msg_bytes.Persistent_Control::3 636064 -system.ruby.network.routers10.throttle2.link_utilization 11.610240 -system.ruby.network.routers10.throttle2.msg_count.Response_Data::4 79034 -system.ruby.network.routers10.throttle2.msg_count.ResponseL2hit_Data::4 225 -system.ruby.network.routers10.throttle2.msg_count.ResponseLocal_Data::4 89 -system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 3281 -system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 547677 -system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 79448 -system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5690448 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 16200 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 6408 -system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 236232 -system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4381416 -system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 635584 -system.ruby.network.routers10.throttle3.link_utilization 11.592538 -system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 78824 -system.ruby.network.routers10.throttle3.msg_count.ResponseL2hit_Data::4 200 -system.ruby.network.routers10.throttle3.msg_count.ResponseLocal_Data::4 76 +system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Data::4 17004528 +system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Control::4 3044504 +system.ruby.network.routers09.throttle0.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers09.throttle1.link_utilization 47.688336 +system.ruby.network.routers09.throttle1.msg_count.Response_Data::4 622925 +system.ruby.network.routers09.throttle1.msg_count.Response_Control::4 2 +system.ruby.network.routers09.throttle1.msg_count.Writeback_Data::4 316 +system.ruby.network.routers09.throttle1.msg_count.Writeback_Control::4 2 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::4 44850600 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Control::4 16 +system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Data::4 22752 +system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers10.throttle0.link_utilization 11.660758 +system.ruby.network.routers10.throttle0.msg_count.Response_Data::4 79304 +system.ruby.network.routers10.throttle0.msg_count.ResponseL2hit_Data::4 218 +system.ruby.network.routers10.throttle0.msg_count.ResponseLocal_Data::4 108 +system.ruby.network.routers10.throttle0.msg_count.Response_Control::4 2 +system.ruby.network.routers10.throttle0.msg_count.Writeback_Data::4 3264 +system.ruby.network.routers10.throttle0.msg_count.Broadcast_Control::1 548338 +system.ruby.network.routers10.throttle0.msg_count.Persistent_Control::3 77168 +system.ruby.network.routers10.throttle0.msg_bytes.Response_Data::4 5709888 +system.ruby.network.routers10.throttle0.msg_bytes.ResponseL2hit_Data::4 15696 +system.ruby.network.routers10.throttle0.msg_bytes.ResponseLocal_Data::4 7776 +system.ruby.network.routers10.throttle0.msg_bytes.Response_Control::4 16 +system.ruby.network.routers10.throttle0.msg_bytes.Writeback_Data::4 235008 +system.ruby.network.routers10.throttle0.msg_bytes.Broadcast_Control::1 4386704 +system.ruby.network.routers10.throttle0.msg_bytes.Persistent_Control::3 617344 +system.ruby.network.routers10.throttle1.link_utilization 11.631988 +system.ruby.network.routers10.throttle1.msg_count.Response_Data::4 78946 +system.ruby.network.routers10.throttle1.msg_count.ResponseL2hit_Data::4 242 +system.ruby.network.routers10.throttle1.msg_count.ResponseLocal_Data::4 74 +system.ruby.network.routers10.throttle1.msg_count.Response_Control::4 1 +system.ruby.network.routers10.throttle1.msg_count.Writeback_Data::4 3190 +system.ruby.network.routers10.throttle1.msg_count.Writeback_Control::4 1 +system.ruby.network.routers10.throttle1.msg_count.Broadcast_Control::1 548694 +system.ruby.network.routers10.throttle1.msg_count.Persistent_Control::3 77406 +system.ruby.network.routers10.throttle1.msg_bytes.Response_Data::4 5684112 +system.ruby.network.routers10.throttle1.msg_bytes.ResponseL2hit_Data::4 17424 +system.ruby.network.routers10.throttle1.msg_bytes.ResponseLocal_Data::4 5328 +system.ruby.network.routers10.throttle1.msg_bytes.Response_Control::4 8 +system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Data::4 229680 +system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers10.throttle1.msg_bytes.Broadcast_Control::1 4389552 +system.ruby.network.routers10.throttle1.msg_bytes.Persistent_Control::3 619248 +system.ruby.network.routers10.throttle2.link_utilization 11.647368 +system.ruby.network.routers10.throttle2.msg_count.Response_Data::4 79112 +system.ruby.network.routers10.throttle2.msg_count.ResponseL2hit_Data::4 252 +system.ruby.network.routers10.throttle2.msg_count.ResponseLocal_Data::4 80 +system.ruby.network.routers10.throttle2.msg_count.Response_Control::4 1 +system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 3236 +system.ruby.network.routers10.throttle2.msg_count.Writeback_Control::4 1 +system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 548543 +system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 77314 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5696064 +system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 18144 +system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 5760 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Control::4 8 +system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 232992 +system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4388344 +system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 618512 +system.ruby.network.routers10.throttle3.link_utilization 11.608795 +system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 78622 +system.ruby.network.routers10.throttle3.msg_count.ResponseL2hit_Data::4 241 +system.ruby.network.routers10.throttle3.msg_count.ResponseLocal_Data::4 92 system.ruby.network.routers10.throttle3.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle3.msg_count.Writeback_Data::4 3248 -system.ruby.network.routers10.throttle3.msg_count.Broadcast_Control::1 547851 -system.ruby.network.routers10.throttle3.msg_count.Persistent_Control::3 79712 -system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::4 5675328 -system.ruby.network.routers10.throttle3.msg_bytes.ResponseL2hit_Data::4 14400 -system.ruby.network.routers10.throttle3.msg_bytes.ResponseLocal_Data::4 5472 +system.ruby.network.routers10.throttle3.msg_count.Writeback_Data::4 3152 +system.ruby.network.routers10.throttle3.msg_count.Broadcast_Control::1 549022 +system.ruby.network.routers10.throttle3.msg_count.Persistent_Control::3 77456 +system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::4 5660784 +system.ruby.network.routers10.throttle3.msg_bytes.ResponseL2hit_Data::4 17352 +system.ruby.network.routers10.throttle3.msg_bytes.ResponseLocal_Data::4 6624 system.ruby.network.routers10.throttle3.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle3.msg_bytes.Writeback_Data::4 233856 -system.ruby.network.routers10.throttle3.msg_bytes.Broadcast_Control::1 4382808 -system.ruby.network.routers10.throttle3.msg_bytes.Persistent_Control::3 637696 -system.ruby.network.routers10.throttle4.link_utilization 11.571152 -system.ruby.network.routers10.throttle4.msg_count.Response_Data::4 78435 -system.ruby.network.routers10.throttle4.msg_count.ResponseL2hit_Data::4 234 -system.ruby.network.routers10.throttle4.msg_count.ResponseLocal_Data::4 86 +system.ruby.network.routers10.throttle3.msg_bytes.Writeback_Data::4 226944 +system.ruby.network.routers10.throttle3.msg_bytes.Broadcast_Control::1 4392176 +system.ruby.network.routers10.throttle3.msg_bytes.Persistent_Control::3 619648 +system.ruby.network.routers10.throttle4.link_utilization 11.628094 +system.ruby.network.routers10.throttle4.msg_count.Response_Data::4 78811 +system.ruby.network.routers10.throttle4.msg_count.ResponseL2hit_Data::4 236 +system.ruby.network.routers10.throttle4.msg_count.ResponseLocal_Data::4 108 system.ruby.network.routers10.throttle4.msg_count.Response_Control::4 1 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system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 403201 -system.ruby.LD.latency_hist::mean 1206.626358 -system.ruby.LD.latency_hist::gmean 905.407177 -system.ruby.LD.latency_hist::stdev 767.970224 -system.ruby.LD.latency_hist | 108278 26.85% 26.85% | 76136 18.88% 45.74% | 71035 17.62% 63.36% | 77557 19.24% 82.59% | 55661 13.80% 96.40% | 13496 3.35% 99.74% | 1015 0.25% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 403201 +system.ruby.LD.latency_hist::samples 404123 +system.ruby.LD.latency_hist::mean 1200.999864 +system.ruby.LD.latency_hist::gmean 900.477274 +system.ruby.LD.latency_hist::stdev 765.116325 +system.ruby.LD.latency_hist | 108804 26.92% 26.92% | 76257 18.87% 45.79% | 72846 18.03% 63.82% | 76798 19.00% 82.82% | 55254 13.67% 96.50% | 13218 3.27% 99.77% | 927 0.23% 100.00% | 19 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 404123 system.ruby.LD.hit_latency_hist::bucket_size 512 system.ruby.LD.hit_latency_hist::max_bucket 5119 -system.ruby.LD.hit_latency_hist::samples 1791 -system.ruby.LD.hit_latency_hist::mean 1104.213289 -system.ruby.LD.hit_latency_hist::gmean 581.141844 -system.ruby.LD.hit_latency_hist::stdev 800.023547 -system.ruby.LD.hit_latency_hist | 581 32.44% 32.44% | 303 16.92% 49.36% | 306 17.09% 66.44% | 322 17.98% 84.42% | 222 12.40% 96.82% | 55 3.07% 99.89% | 2 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 1791 +system.ruby.LD.hit_latency_hist::samples 1804 +system.ruby.LD.hit_latency_hist::mean 1046.163525 +system.ruby.LD.hit_latency_hist::gmean 506.824473 +system.ruby.LD.hit_latency_hist::stdev 796.666251 +system.ruby.LD.hit_latency_hist | 637 35.31% 35.31% | 327 18.13% 53.44% | 292 16.19% 69.62% | 287 15.91% 85.53% | 222 12.31% 97.84% | 33 1.83% 99.67% | 6 0.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 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3.28% 99.77% | 921 0.23% 100.00% | 19 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 402319 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223050 -system.ruby.ST.latency_hist::mean 1206.070267 -system.ruby.ST.latency_hist::gmean 903.551282 -system.ruby.ST.latency_hist::stdev 769.078949 -system.ruby.ST.latency_hist | 60261 27.02% 27.02% | 41944 18.80% 45.82% | 38916 17.45% 63.27% | 42948 19.25% 82.52% | 30981 13.89% 96.41% | 7472 3.35% 99.76% | 514 0.23% 99.99% | 14 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223050 +system.ruby.ST.latency_hist::samples 223128 +system.ruby.ST.latency_hist::mean 1198.069973 +system.ruby.ST.latency_hist::gmean 897.219318 +system.ruby.ST.latency_hist::stdev 764.608926 +system.ruby.ST.latency_hist | 60637 27.18% 27.18% | 41649 18.67% 45.84% | 40180 18.01% 63.85% | 42703 19.14% 82.99% | 30269 13.57% 96.55% | 7174 3.22% 99.77% | 505 0.23% 100.00% | 11 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 223128 system.ruby.ST.hit_latency_hist::bucket_size 512 system.ruby.ST.hit_latency_hist::max_bucket 5119 -system.ruby.ST.hit_latency_hist::samples 1016 -system.ruby.ST.hit_latency_hist::mean 1071.599409 -system.ruby.ST.hit_latency_hist::gmean 506.227433 -system.ruby.ST.hit_latency_hist::stdev 810.320737 -system.ruby.ST.hit_latency_hist | 349 34.35% 34.35% | 166 16.34% 50.69% | 175 17.22% 67.91% | 181 17.81% 85.73% | 116 11.42% 97.15% | 26 2.56% 99.70% | 2 0.20% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 1016 +system.ruby.ST.hit_latency_hist::samples 1040 +system.ruby.ST.hit_latency_hist::mean 1076.801923 +system.ruby.ST.hit_latency_hist::gmean 533.335801 +system.ruby.ST.hit_latency_hist::stdev 814.040414 +system.ruby.ST.hit_latency_hist | 346 33.27% 33.27% | 197 18.94% 52.21% | 167 16.06% 68.27% | 178 17.12% 85.38% | 112 10.77% 96.15% | 37 3.56% 99.71% | 2 0.19% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 1040 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 222034 -system.ruby.ST.miss_latency_hist::mean 1206.685589 -system.ruby.ST.miss_latency_hist::gmean 905.949792 -system.ruby.ST.miss_latency_hist::stdev 768.833014 -system.ruby.ST.miss_latency_hist | 59912 26.98% 26.98% | 41778 18.82% 45.80% | 38741 17.45% 63.25% | 42767 19.26% 82.51% | 30865 13.90% 96.41% | 7446 3.35% 99.76% | 512 0.23% 99.99% | 13 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 222034 +system.ruby.ST.miss_latency_hist::samples 222088 +system.ruby.ST.miss_latency_hist::mean 1198.637851 +system.ruby.ST.miss_latency_hist::gmean 899.407401 +system.ruby.ST.miss_latency_hist::stdev 764.326618 +system.ruby.ST.miss_latency_hist | 60291 27.15% 27.15% | 41452 18.66% 45.81% | 40013 18.02% 63.83% | 42525 19.15% 82.98% | 30157 13.58% 96.56% | 7137 3.21% 99.77% | 503 0.23% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 222088 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 163 +system.ruby.L1Cache.hit_mach_latency_hist::samples 186 system.ruby.L1Cache.hit_mach_latency_hist::mean 2 system.ruby.L1Cache.hit_mach_latency_hist::gmean 2 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 163 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 163 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 186 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 186 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 1328 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1160.911145 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 748.217806 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 787.446867 -system.ruby.L1Cache.miss_mach_latency_hist | 383 28.84% 28.84% | 234 17.62% 46.46% | 247 18.60% 65.06% | 238 17.92% 82.98% | 181 13.63% 96.61% | 42 3.16% 99.77% | 3 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 1328 +system.ruby.L1Cache.miss_mach_latency_hist::samples 1293 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1158.235886 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 728.356932 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 802.482863 +system.ruby.L1Cache.miss_mach_latency_hist | 388 30.01% 30.01% | 232 17.94% 47.95% | 204 15.78% 63.73% | 256 19.80% 83.53% | 162 12.53% 96.06% | 48 3.71% 99.77% | 2 0.15% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 1293 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 512 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L2Cache.hit_mach_latency_hist::samples 2644 -system.ruby.L2Cache.hit_mach_latency_hist::mean 1159.631241 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 781.821585 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 779.774726 -system.ruby.L2Cache.hit_mach_latency_hist | 767 29.01% 29.01% | 469 17.74% 46.75% | 481 18.19% 64.94% | 503 19.02% 83.96% | 338 12.78% 96.75% | 81 3.06% 99.81% | 4 0.15% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 2644 +system.ruby.L2Cache.hit_mach_latency_hist::samples 2658 +system.ruby.L2Cache.hit_mach_latency_hist::mean 1131.219338 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 761.614557 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 778.856804 +system.ruby.L2Cache.hit_mach_latency_hist | 797 29.98% 29.98% | 524 19.71% 49.70% | 459 17.27% 66.97% | 465 17.49% 84.46% | 334 12.57% 97.03% | 70 2.63% 99.66% | 8 0.30% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 2658 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 622116 -system.ruby.Directory.miss_mach_latency_hist::mean 1207.039919 -system.ruby.Directory.miss_mach_latency_hist::gmean 907.126686 -system.ruby.Directory.miss_mach_latency_hist::stdev 768.120033 -system.ruby.Directory.miss_mach_latency_hist | 167226 26.88% 26.88% | 117377 18.87% 45.75% | 109223 17.56% 63.30% | 119764 19.25% 82.56% | 86123 13.84% 96.40% | 20845 3.35% 99.75% | 1522 0.24% 99.99% | 36 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 622116 +system.ruby.Directory.miss_mach_latency_hist::samples 623114 +system.ruby.Directory.miss_mach_latency_hist::mean 1200.695014 +system.ruby.Directory.miss_mach_latency_hist::gmean 901.991783 +system.ruby.Directory.miss_mach_latency_hist::stdev 764.616314 +system.ruby.Directory.miss_mach_latency_hist | 168070 26.97% 26.97% | 117150 18.80% 45.77% | 112363 18.03% 63.81% | 118780 19.06% 82.87% | 85027 13.65% 96.51% | 20274 3.25% 99.77% | 1422 0.23% 100.00% | 28 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 623114 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 4 @@ -1142,436 +1175,449 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion | system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 4 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 92 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 120 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 92 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 120 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 120 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 863 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1168.529548 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 753.386461 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 798.015329 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 249 28.85% 28.85% | 159 18.42% 47.28% | 146 16.92% 64.19% | 150 17.38% 81.58% | 132 15.30% 96.87% | 25 2.90% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 863 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 858 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1181.020979 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 749.467450 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 801.452334 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 252 29.37% 29.37% | 147 17.13% 46.50% | 133 15.50% 62.00% | 180 20.98% 82.98% | 113 13.17% 96.15% | 32 3.73% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 858 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1699 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1163.897587 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 790.070814 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 778.028229 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 489 28.78% 28.78% | 303 17.83% 46.62% | 306 18.01% 64.63% | 322 18.95% 83.58% | 222 13.07% 96.65% | 55 3.24% 99.88% | 2 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1699 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1684 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1120.569477 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 751.885491 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 772.432979 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 517 30.70% 30.70% | 327 19.42% 50.12% | 292 17.34% 67.46% | 287 17.04% 84.50% | 222 13.18% 97.68% | 33 1.96% 99.64% | 6 0.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1684 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 400547 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1207.166367 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 907.563331 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 767.727188 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 107448 26.83% 26.83% | 75674 18.89% 45.72% | 70583 17.62% 63.34% | 77085 19.24% 82.58% | 55307 13.81% 96.39% | 13416 3.35% 99.74% | 1011 0.25% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 400547 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 401461 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1201.738333 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 903.160221 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 764.822834 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 107915 26.88% 26.88% | 75783 18.88% 45.76% | 72421 18.04% 63.80% | 76331 19.01% 82.81% | 54919 13.68% 96.49% | 13153 3.28% 99.77% | 921 0.23% 100.00% | 18 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 401461 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 71 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 66 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 71 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 71 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 66 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 66 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 465 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1146.772043 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 738.719018 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 768.096494 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 134 28.82% 28.82% | 75 16.13% 44.95% | 101 21.72% 66.67% | 88 18.92% 85.59% | 49 10.54% 96.13% | 17 3.66% 99.78% | 1 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 465 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 435 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1113.294253 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 688.445437 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 803.539492 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 136 31.26% 31.26% | 85 19.54% 50.80% | 71 16.32% 67.13% | 76 17.47% 84.60% | 49 11.26% 95.86% | 16 3.68% 99.54% | 2 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 435 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 945 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1151.960847 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 767.206460 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 783.259144 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 278 29.42% 29.42% | 166 17.57% 46.98% | 175 18.52% 65.50% | 181 19.15% 84.66% | 116 12.28% 96.93% | 26 2.75% 99.68% | 2 0.21% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 945 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 974 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1149.632444 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 778.733573 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 789.900332 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 280 28.75% 28.75% | 197 20.23% 48.97% | 167 17.15% 66.12% | 178 18.28% 84.39% | 112 11.50% 95.89% | 37 3.80% 99.69% | 2 0.21% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 974 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221569 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1206.811327 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 906.337864 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 768.831381 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 59778 26.98% 26.98% | 41703 18.82% 45.80% | 38640 17.44% 63.24% | 42679 19.26% 82.50% | 30816 13.91% 96.41% | 7429 3.35% 99.76% | 511 0.23% 99.99% | 13 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221569 -system.ruby.L1Cache_Controller.Load | 50436 12.51% 12.51% | 50559 12.54% 25.05% | 50756 12.59% 37.64% | 50222 12.46% 50.09% | 50228 12.46% 62.55% | 50377 12.49% 75.04% | 50328 12.48% 87.52% | 50307 12.48% 100.00% -system.ruby.L1Cache_Controller.Load::total 403213 -system.ruby.L1Cache_Controller.Store | 28373 12.72% 12.72% | 27805 12.47% 25.19% | 27689 12.41% 37.60% | 28057 12.58% 50.18% | 27716 12.43% 62.60% | 28088 12.59% 75.19% | 27665 12.40% 87.60% | 27666 12.40% 100.00% -system.ruby.L1Cache_Controller.Store::total 223059 -system.ruby.L1Cache_Controller.L1_Replacement | 1481354 12.58% 12.58% | 1470664 12.49% 25.07% | 1475652 12.53% 37.60% | 1470559 12.49% 50.09% | 1467129 12.46% 62.55% | 1474661 12.52% 75.08% | 1468637 12.47% 87.55% | 1465817 12.45% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 11774473 -system.ruby.L1Cache_Controller.Data_Shared | 208 13.68% 13.68% | 189 12.43% 26.10% | 189 12.43% 38.53% | 157 10.32% 48.85% | 185 12.16% 61.01% | 194 12.75% 73.77% | 182 11.97% 85.73% | 217 14.27% 100.00% -system.ruby.L1Cache_Controller.Data_Shared::total 1521 -system.ruby.L1Cache_Controller.Data_Owner | 41 13.58% 13.58% | 38 12.58% 26.16% | 45 14.90% 41.06% | 30 9.93% 50.99% | 35 11.59% 62.58% | 31 10.26% 72.85% | 25 8.28% 81.13% | 57 18.87% 100.00% -system.ruby.L1Cache_Controller.Data_Owner::total 302 -system.ruby.L1Cache_Controller.Data_All_Tokens | 82680 12.58% 12.58% | 82290 12.52% 25.09% | 82395 12.53% 37.63% | 82161 12.50% 50.12% | 81816 12.44% 62.57% | 82348 12.53% 75.09% | 81909 12.46% 87.55% | 81830 12.45% 100.00% -system.ruby.L1Cache_Controller.Data_All_Tokens::total 657429 -system.ruby.L1Cache_Controller.Ack | 1 11.11% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 1 11.11% 22.22% | 1 11.11% 33.33% | 3 33.33% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.Ack::total 9 -system.ruby.L1Cache_Controller.Transient_Local_GETX | 194624 12.47% 12.47% | 195190 12.50% 24.97% | 195307 12.51% 37.49% | 194941 12.49% 49.97% | 195278 12.51% 62.49% | 194913 12.49% 74.97% | 195327 12.51% 87.49% | 195329 12.51% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1560909 -system.ruby.L1Cache_Controller.Transient_Local_GETS | 352702 12.50% 12.50% | 352574 12.49% 24.99% | 352370 12.49% 37.48% | 352910 12.51% 49.99% | 352902 12.51% 62.49% | 352750 12.50% 74.99% | 352804 12.50% 87.50% | 352825 12.50% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2821837 -system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 3 -system.ruby.L1Cache_Controller.Persistent_GETX | 14113 12.48% 12.48% | 14154 12.51% 24.99% | 14109 12.47% 37.46% | 14130 12.49% 49.95% | 14118 12.48% 62.43% | 14160 12.52% 74.95% | 14203 12.56% 87.51% | 14134 12.49% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETX::total 113121 -system.ruby.L1Cache_Controller.Persistent_GETS | 25808 12.49% 12.49% | 25766 12.47% 24.95% | 25783 12.47% 37.42% | 25890 12.53% 49.95% | 25893 12.53% 62.48% | 25876 12.52% 74.99% | 25799 12.48% 87.48% | 25889 12.52% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETS::total 206704 -system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 2 50.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221653 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1198.805340 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 899.879339 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 764.240219 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 60155 27.14% 27.14% | 41367 18.66% 45.80% | 39942 18.02% 63.82% | 42449 19.15% 82.97% | 30108 13.58% 96.56% | 7121 3.21% 99.77% | 501 0.23% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221653 +system.ruby.Directory_Controller.GETX 237437 0.00% 0.00% +system.ruby.Directory_Controller.GETS 430203 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 44403 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 44053 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 298 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 243274 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 529 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 379211 0.00% 0.00% +system.ruby.Directory_Controller.Tokens 147 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 777 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 622922 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 243159 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 220129 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 398579 0.00% 0.00% +system.ruby.Directory_Controller.O.Lockdown 3733 0.00% 0.00% +system.ruby.Directory_Controller.O.Data_All_Tokens 60 0.00% 0.00% +system.ruby.Directory_Controller.O.Tokens 5 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 747 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 2154 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 4044 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 17540 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 298 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 242862 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 529 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 378819 0.00% 0.00% +system.ruby.Directory_Controller.NO.Tokens 139 0.00% 0.00% +system.ruby.Directory_Controller.L.GETX 127 0.00% 0.00% +system.ruby.Directory_Controller.L.GETS 205 0.00% 0.00% +system.ruby.Directory_Controller.L.Lockdown 318 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 44051 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_All_Tokens 321 0.00% 0.00% +system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 392 0.00% 0.00% +system.ruby.Directory_Controller.L.Tokens 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 72 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 89 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Lockdown 106 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Data_All_Tokens 31 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Tokens 1 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Data 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 243053 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETX 48 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETS 63 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Lockdown 4 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Data 4229 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Ack 106 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETX 466 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETS 814 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Lockdown 28 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 22674 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETX 14441 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETS 26409 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 22674 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 596017 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50549 12.51% 12.51% | 50655 12.53% 25.04% | 50543 12.51% 37.55% | 50433 12.48% 50.03% | 50597 12.52% 62.55% | 50378 12.47% 75.01% | 50321 12.45% 87.46% | 50661 12.54% 100.00% +system.ruby.L1Cache_Controller.Load::total 404137 +system.ruby.L1Cache_Controller.Store | 28221 12.65% 12.65% | 27757 12.44% 25.09% | 28028 12.56% 37.65% | 27656 12.39% 50.04% | 27664 12.40% 62.44% | 27998 12.55% 74.99% | 28169 12.62% 87.61% | 27643 12.39% 100.00% +system.ruby.L1Cache_Controller.Store::total 223136 +system.ruby.L1Cache_Controller.L1_Replacement | 1480088 12.55% 12.55% | 1475888 12.52% 25.07% | 1476913 12.53% 37.60% | 1470392 12.47% 50.07% | 1471389 12.48% 62.55% | 1471572 12.48% 75.03% | 1471675 12.48% 87.51% | 1472167 12.49% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 11790084 +system.ruby.L1Cache_Controller.Data_Shared | 197 12.48% 12.48% | 200 12.67% 25.14% | 199 12.60% 37.75% | 194 12.29% 50.03% | 203 12.86% 62.89% | 182 11.53% 74.41% | 203 12.86% 87.27% | 201 12.73% 100.00% +system.ruby.L1Cache_Controller.Data_Shared::total 1579 +system.ruby.L1Cache_Controller.Data_Owner | 29 10.03% 10.03% | 45 15.57% 25.61% | 42 14.53% 40.14% | 29 10.03% 50.17% | 39 13.49% 63.67% | 26 9.00% 72.66% | 40 13.84% 86.51% | 39 13.49% 100.00% +system.ruby.L1Cache_Controller.Data_Owner::total 289 +system.ruby.L1Cache_Controller.Data_All_Tokens | 82668 12.56% 12.56% | 82207 12.49% 25.06% | 82439 12.53% 37.59% | 81884 12.44% 50.03% | 82153 12.49% 62.52% | 82236 12.50% 75.02% | 82293 12.51% 87.52% | 82094 12.48% 100.00% +system.ruby.L1Cache_Controller.Data_All_Tokens::total 657974 +system.ruby.L1Cache_Controller.Ack | 2 20.00% 20.00% | 2 20.00% 40.00% | 1 10.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% +system.ruby.L1Cache_Controller.Ack::total 10 +system.ruby.L1Cache_Controller.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.Ack_All_Tokens::total 3 +system.ruby.L1Cache_Controller.Transient_Local_GETX | 194854 12.48% 12.48% | 195320 12.51% 24.99% | 195053 12.49% 37.48% | 195420 12.52% 49.99% | 195412 12.51% 62.51% | 195080 12.49% 75.00% | 194909 12.48% 87.48% | 195435 12.52% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1561483 +system.ruby.L1Cache_Controller.Transient_Local_GETS | 353483 12.50% 12.50% | 353371 12.49% 24.99% | 353489 12.50% 37.49% | 353602 12.50% 50.00% | 353436 12.50% 62.49% | 353654 12.50% 75.00% | 353706 12.51% 87.50% | 353373 12.50% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2828114 +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 5 +system.ruby.L1Cache_Controller.Persistent_GETX | 13783 12.49% 12.49% | 13801 12.51% 25.00% | 13756 12.47% 37.47% | 13761 12.47% 49.95% | 13777 12.49% 62.43% | 13755 12.47% 74.90% | 13894 12.59% 87.49% | 13796 12.51% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETX::total 110323 +system.ruby.L1Cache_Controller.Persistent_GETS | 24943 12.44% 12.44% | 25035 12.49% 24.93% | 25044 12.49% 37.42% | 25123 12.53% 49.95% | 25028 12.48% 62.43% | 25059 12.50% 74.93% | 25085 12.51% 87.44% | 25178 12.56% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETS::total 200495 +system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 4 -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 51053 12.51% 12.51% | 51056 12.51% 25.03% | 51083 12.52% 37.55% | 50956 12.49% 50.04% | 50965 12.49% 62.53% | 50940 12.49% 75.02% | 50973 12.49% 87.51% | 50953 12.49% 100.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 407979 -system.ruby.L1Cache_Controller.Request_Timeout | 35893 12.78% 12.78% | 35498 12.64% 25.42% | 35407 12.61% 38.02% | 34645 12.33% 50.36% | 35410 12.61% 62.97% | 34897 12.42% 75.39% | 34128 12.15% 87.54% | 34991 12.46% 100.00% -system.ruby.L1Cache_Controller.Request_Timeout::total 280869 -system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 8 10.00% 10.00% | 6 7.50% 17.50% | 11 13.75% 31.25% | 11 13.75% 45.00% | 11 13.75% 58.75% | 6 7.50% 66.25% | 11 13.75% 80.00% | 16 20.00% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 80 -system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 7 5.79% 5.79% | 23 19.01% 24.79% | 14 11.57% 36.36% | 9 7.44% 43.80% | 20 16.53% 60.33% | 18 14.88% 75.21% | 14 11.57% 86.78% | 16 13.22% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 121 -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78546 12.58% 12.58% | 78110 12.51% 25.09% | 78198 12.53% 37.62% | 78066 12.50% 50.12% | 77695 12.45% 62.57% | 78214 12.53% 75.10% | 77757 12.46% 87.55% | 77697 12.45% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 624283 -system.ruby.L1Cache_Controller.NP.Load | 50396 12.51% 12.51% | 50523 12.54% 25.05% | 50724 12.59% 37.63% | 50182 12.45% 50.09% | 50190 12.46% 62.54% | 50352 12.50% 75.04% | 50293 12.48% 87.52% | 50276 12.48% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 402936 -system.ruby.L1Cache_Controller.NP.Store | 28349 12.72% 12.72% | 27783 12.47% 25.18% | 27674 12.42% 37.60% | 28036 12.58% 50.18% | 27695 12.43% 62.61% | 28060 12.59% 75.19% | 27646 12.40% 87.60% | 27641 12.40% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 222884 -system.ruby.L1Cache_Controller.NP.Data_Shared | 17 14.53% 14.53% | 16 13.68% 28.21% | 15 12.82% 41.03% | 12 10.26% 51.28% | 12 10.26% 61.54% | 11 9.40% 70.94% | 9 7.69% 78.63% | 25 21.37% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Shared::total 117 -system.ruby.L1Cache_Controller.NP.Data_Owner | 11 11.46% 11.46% | 10 10.42% 21.88% | 13 13.54% 35.42% | 7 7.29% 42.71% | 11 11.46% 54.17% | 11 11.46% 65.62% | 8 8.33% 73.96% | 25 26.04% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Owner::total 96 -system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 4088 12.46% 12.46% | 4134 12.60% 25.06% | 4147 12.64% 37.70% | 4054 12.35% 50.05% | 4073 12.41% 62.46% | 4098 12.49% 74.95% | 4120 12.56% 87.51% | 4099 12.49% 100.00% -system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 32813 -system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.NP.Ack::total 2 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194161 12.47% 12.47% | 194721 12.50% 24.97% | 194841 12.51% 37.49% | 194462 12.49% 49.97% | 194791 12.51% 62.48% | 194446 12.49% 74.97% | 194881 12.51% 87.48% | 194886 12.52% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1557189 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 351907 12.50% 12.50% | 351775 12.50% 25.00% | 351496 12.49% 37.48% | 352130 12.51% 49.99% | 352083 12.51% 62.50% | 351871 12.50% 74.99% | 351944 12.50% 87.50% | 352019 12.50% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2815225 -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 44647 12.50% 12.50% | 44658 12.50% 25.00% | 44641 12.50% 37.50% | 44692 12.51% 50.01% | 44586 12.48% 62.50% | 44684 12.51% 75.01% | 44620 12.49% 87.50% | 44656 12.50% 100.00% -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 357184 -system.ruby.L1Cache_Controller.I.L1_Replacement | 75 10.58% 10.58% | 92 12.98% 23.55% | 106 14.95% 38.50% | 95 13.40% 51.90% | 95 13.40% 65.30% | 81 11.42% 76.73% | 76 10.72% 87.45% | 89 12.55% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 709 -system.ruby.L1Cache_Controller.I.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 1 -system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 1 -system.ruby.L1Cache_Controller.S.L1_Replacement | 205 12.97% 12.97% | 201 12.71% 25.68% | 201 12.71% 38.39% | 162 10.25% 48.64% | 198 12.52% 61.16% | 208 13.16% 74.32% | 199 12.59% 86.91% | 207 13.09% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1581 -system.ruby.L1Cache_Controller.S.Data_Shared | 4 26.67% 26.67% | 2 13.33% 40.00% | 3 20.00% 60.00% | 2 13.33% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 0 0.00% 80.00% | 3 20.00% 100.00% -system.ruby.L1Cache_Controller.S.Data_Shared::total 15 -system.ruby.L1Cache_Controller.S.Data_Owner | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Data_Owner::total 1 -system.ruby.L1Cache_Controller.S.Data_All_Tokens | 2 40.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 49729 12.53% 12.53% | 49620 12.50% 25.04% | 49656 12.51% 37.55% | 49571 12.49% 50.04% | 49651 12.51% 62.55% | 49641 12.51% 75.06% | 49476 12.47% 87.53% | 49482 12.47% 100.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 396826 +system.ruby.L1Cache_Controller.Request_Timeout | 33619 12.37% 12.37% | 34306 12.62% 24.99% | 34435 12.67% 37.65% | 33457 12.31% 49.96% | 34654 12.75% 62.71% | 33427 12.30% 75.00% | 34346 12.63% 87.64% | 33609 12.36% 100.00% +system.ruby.L1Cache_Controller.Request_Timeout::total 271853 +system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 6 10.71% 10.71% | 5 8.93% 19.64% | 6 10.71% 30.36% | 7 12.50% 42.86% | 8 14.29% 57.14% | 6 10.71% 67.86% | 8 14.29% 82.14% | 10 17.86% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 56 +system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 7 5.15% 5.15% | 17 12.50% 17.65% | 15 11.03% 28.68% | 13 9.56% 38.24% | 12 8.82% 47.06% | 25 18.38% 65.44% | 23 16.91% 82.35% | 24 17.65% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 136 +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78528 12.56% 12.56% | 78156 12.50% 25.06% | 78311 12.53% 37.59% | 77846 12.45% 50.04% | 78001 12.48% 62.51% | 78123 12.50% 75.01% | 78233 12.51% 87.52% | 78034 12.48% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 625232 +system.ruby.L1Cache_Controller.NP.Load | 50509 12.51% 12.51% | 50627 12.54% 25.04% | 50510 12.51% 37.55% | 50389 12.48% 50.03% | 50551 12.52% 62.55% | 50342 12.47% 75.02% | 50285 12.45% 87.47% | 50606 12.53% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 403819 +system.ruby.L1Cache_Controller.NP.Store | 28202 12.65% 12.65% | 27742 12.44% 25.09% | 28001 12.56% 37.65% | 27633 12.39% 50.04% | 27642 12.40% 62.44% | 27971 12.55% 74.99% | 28144 12.62% 87.61% | 27623 12.39% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 222958 +system.ruby.L1Cache_Controller.NP.Data_Shared | 11 8.59% 8.59% | 18 14.06% 22.66% | 19 14.84% 37.50% | 14 10.94% 48.44% | 16 12.50% 60.94% | 8 6.25% 67.19% | 23 17.97% 85.16% | 19 14.84% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Shared::total 128 +system.ruby.L1Cache_Controller.NP.Data_Owner | 6 7.14% 7.14% | 14 16.67% 23.81% | 11 13.10% 36.90% | 10 11.90% 48.81% | 12 14.29% 63.10% | 5 5.95% 69.05% | 13 15.48% 84.52% | 13 15.48% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Owner::total 84 +system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 4108 12.67% 12.67% | 4005 12.35% 25.02% | 4095 12.63% 37.64% | 3999 12.33% 49.97% | 4120 12.70% 62.68% | 4067 12.54% 75.22% | 4023 12.40% 87.62% | 4014 12.38% 100.00% +system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 32431 +system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 2 50.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.NP.Ack::total 4 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194378 12.48% 12.48% | 194859 12.51% 24.99% | 194607 12.49% 37.48% | 194968 12.52% 49.99% | 194930 12.51% 62.51% | 194649 12.49% 75.00% | 194495 12.48% 87.48% | 194975 12.52% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1557861 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 352691 12.50% 12.50% | 352515 12.49% 24.99% | 352621 12.50% 37.49% | 352784 12.50% 50.00% | 352579 12.50% 62.49% | 352819 12.50% 75.00% | 352925 12.51% 87.51% | 352525 12.49% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2821459 +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 43402 12.49% 12.49% | 43438 12.50% 24.98% | 43495 12.51% 37.49% | 43450 12.50% 49.99% | 43468 12.50% 62.50% | 43442 12.50% 75.00% | 43468 12.50% 87.50% | 43449 12.50% 100.00% +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 347612 +system.ruby.L1Cache_Controller.I.L1_Replacement | 83 12.46% 12.46% | 85 12.76% 25.23% | 90 13.51% 38.74% | 71 10.66% 49.40% | 86 12.91% 62.31% | 92 13.81% 76.13% | 74 11.11% 87.24% | 85 12.76% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 666 +system.ruby.L1Cache_Controller.I.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 2 +system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 2 +system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 2 +system.ruby.L1Cache_Controller.I.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Persistent_GETX::total 2 +system.ruby.L1Cache_Controller.S.L1_Replacement | 197 12.19% 12.19% | 208 12.87% 25.06% | 195 12.07% 37.13% | 202 12.50% 49.63% | 209 12.93% 62.56% | 196 12.13% 74.69% | 206 12.75% 87.44% | 203 12.56% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1616 +system.ruby.L1Cache_Controller.S.Data_Shared | 4 21.05% 21.05% | 2 10.53% 31.58% | 2 10.53% 42.11% | 4 21.05% 63.16% | 2 10.53% 73.68% | 2 10.53% 84.21% | 1 5.26% 89.47% | 2 10.53% 100.00% +system.ruby.L1Cache_Controller.S.Data_Shared::total 19 +system.ruby.L1Cache_Controller.S.Data_All_Tokens | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 2 40.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 5 -system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 3 -system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETX::total 3 -system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 2 50.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 3 +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 5 +system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Persistent_GETX::total 1 +system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 4 -system.ruby.L1Cache_Controller.O.L1_Replacement | 62 12.16% 12.16% | 62 12.16% 24.31% | 81 15.88% 40.20% | 49 9.61% 49.80% | 71 13.92% 63.73% | 67 13.14% 76.86% | 53 10.39% 87.25% | 65 12.75% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 510 +system.ruby.L1Cache_Controller.O.L1_Replacement | 63 11.98% 11.98% | 79 15.02% 27.00% | 69 13.12% 40.11% | 63 11.98% 52.09% | 69 13.12% 65.21% | 55 10.46% 75.67% | 56 10.65% 86.31% | 72 13.69% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 526 system.ruby.L1Cache_Controller.O.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 2 -system.ruby.L1Cache_Controller.O.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Ack | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.O.Ack::total 1 -system.ruby.L1Cache_Controller.O.Persistent_GETS | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Persistent_GETS::total 3 -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 6 13.95% 13.95% | 5 11.63% 25.58% | 6 13.95% 39.53% | 7 16.28% 55.81% | 5 11.63% 67.44% | 5 11.63% 79.07% | 2 4.65% 83.72% | 7 16.28% 100.00% -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 43 -system.ruby.L1Cache_Controller.M.Load | 3 12.50% 12.50% | 3 12.50% 25.00% | 3 12.50% 37.50% | 2 8.33% 45.83% | 4 16.67% 62.50% | 3 12.50% 75.00% | 2 8.33% 83.33% | 4 16.67% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 24 -system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 1 10.00% 10.00% | 2 20.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 3 30.00% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10 -system.ruby.L1Cache_Controller.M.L1_Replacement | 50107 12.51% 12.51% | 50235 12.54% 25.04% | 50417 12.58% 37.63% | 49956 12.47% 50.09% | 49910 12.46% 62.55% | 50054 12.49% 75.04% | 50028 12.49% 87.53% | 49970 12.47% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 400677 -system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 18 10.98% 10.98% | 21 12.80% 23.78% | 33 20.12% 43.90% | 21 12.80% 56.71% | 20 12.20% 68.90% | 19 11.59% 80.49% | 12 7.32% 87.80% | 20 12.20% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 164 -system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 33 10.68% 10.68% | 36 11.65% 22.33% | 50 16.18% 38.51% | 26 8.41% 46.93% | 47 15.21% 62.14% | 48 15.53% 77.67% | 36 11.65% 89.32% | 33 10.68% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 309 -system.ruby.L1Cache_Controller.M.Persistent_GETX | 10 14.71% 14.71% | 14 20.59% 35.29% | 4 5.88% 41.18% | 5 7.35% 48.53% | 7 10.29% 58.82% | 8 11.76% 70.59% | 9 13.24% 83.82% | 11 16.18% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETX::total 68 -system.ruby.L1Cache_Controller.M.Persistent_GETS | 16 12.70% 12.70% | 16 12.70% 25.40% | 20 15.87% 41.27% | 17 13.49% 54.76% | 14 11.11% 65.87% | 15 11.90% 77.78% | 19 15.08% 92.86% | 9 7.14% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETS::total 126 -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 336 13.03% 13.03% | 302 11.71% 24.75% | 322 12.49% 37.24% | 314 12.18% 49.42% | 336 13.03% 62.45% | 318 12.34% 74.79% | 350 13.58% 88.36% | 300 11.64% 100.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 2578 -system.ruby.L1Cache_Controller.MM.Load | 3 30.00% 30.00% | 2 20.00% 50.00% | 0 0.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 10 -system.ruby.L1Cache_Controller.MM.Store | 2 22.22% 22.22% | 1 11.11% 33.33% | 1 11.11% 44.44% | 3 33.33% 77.78% | 0 0.00% 77.78% | 0 0.00% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 9 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 28327 12.73% 12.73% | 27748 12.47% 25.19% | 27621 12.41% 37.60% | 27990 12.57% 50.17% | 27649 12.42% 62.59% | 28030 12.59% 75.19% | 27616 12.41% 87.59% | 27619 12.41% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222600 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 13 15.29% 15.29% | 10 11.76% 27.06% | 14 16.47% 43.53% | 15 17.65% 61.18% | 11 12.94% 74.12% | 12 14.12% 88.24% | 2 2.35% 90.59% | 8 9.41% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 85 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 14 8.05% 8.05% | 23 13.22% 21.26% | 26 14.94% 36.21% | 23 13.22% 49.43% | 27 15.52% 64.94% | 22 12.64% 77.59% | 18 10.34% 87.93% | 21 12.07% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 174 -system.ruby.L1Cache_Controller.MM.Persistent_GETX | 4 15.38% 15.38% | 1 3.85% 19.23% | 5 19.23% 38.46% | 5 19.23% 57.69% | 3 11.54% 69.23% | 2 7.69% 76.92% | 3 11.54% 88.46% | 3 11.54% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 26 -system.ruby.L1Cache_Controller.MM.Persistent_GETS | 5 8.20% 8.20% | 7 11.48% 19.67% | 9 14.75% 34.43% | 8 13.11% 47.54% | 8 13.11% 60.66% | 6 9.84% 70.49% | 14 22.95% 93.44% | 4 6.56% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 61 -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 179 12.77% 12.77% | 171 12.20% 24.96% | 180 12.84% 37.80% | 144 10.27% 48.07% | 206 14.69% 62.77% | 162 11.55% 74.32% | 172 12.27% 86.59% | 188 13.41% 100.00% -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 1402 -system.ruby.L1Cache_Controller.M_W.Load | 10 23.81% 23.81% | 8 19.05% 42.86% | 3 7.14% 50.00% | 6 14.29% 64.29% | 1 2.38% 66.67% | 4 9.52% 76.19% | 6 14.29% 90.48% | 4 9.52% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 42 -system.ruby.L1Cache_Controller.M_W.Store | 6 17.65% 17.65% | 3 8.82% 26.47% | 2 5.88% 32.35% | 6 17.65% 50.00% | 3 8.82% 58.82% | 9 26.47% 85.29% | 2 5.88% 91.18% | 3 8.82% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 34 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 368409 12.51% 12.51% | 366891 12.46% 24.97% | 370081 12.57% 37.54% | 369093 12.53% 50.07% | 366788 12.45% 62.52% | 368135 12.50% 75.02% | 368286 12.51% 87.53% | 367236 12.47% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2944919 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 65 13.08% 13.08% | 59 11.87% 24.95% | 55 11.07% 36.02% | 71 14.29% 50.30% | 68 13.68% 63.98% | 64 12.88% 76.86% | 59 11.87% 88.73% | 56 11.27% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 497 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 100 11.92% 11.92% | 107 12.75% 24.67% | 105 12.51% 37.19% | 92 10.97% 48.15% | 98 11.68% 59.83% | 104 12.40% 72.23% | 121 14.42% 86.65% | 112 13.35% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 839 -system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 6 12.24% 12.24% | 4 8.16% 20.41% | 7 14.29% 34.69% | 6 12.24% 46.94% | 5 10.20% 57.14% | 2 4.08% 61.22% | 8 16.33% 77.55% | 11 22.45% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 49 -system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 4 5.97% 5.97% | 12 17.91% 23.88% | 9 13.43% 37.31% | 3 4.48% 41.79% | 12 17.91% 59.70% | 11 16.42% 76.12% | 7 10.45% 86.57% | 9 13.43% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 67 -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 482 13.53% 13.53% | 458 12.85% 26.38% | 499 14.01% 40.39% | 442 12.41% 52.79% | 426 11.96% 64.75% | 429 12.04% 76.79% | 409 11.48% 88.27% | 418 11.73% 100.00% -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3563 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 6 11.32% 11.32% | 4 7.55% 18.87% | 8 15.09% 33.96% | 6 11.32% 45.28% | 6 11.32% 56.60% | 2 3.77% 60.38% | 9 16.98% 77.36% | 12 22.64% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 53 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 4 5.41% 5.41% | 14 18.92% 24.32% | 10 13.51% 37.84% | 4 5.41% 43.24% | 12 16.22% 59.46% | 12 16.22% 75.68% | 7 9.46% 85.14% | 11 14.86% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 74 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50183 12.50% 12.50% | 50322 12.54% 25.04% | 50525 12.59% 37.63% | 50026 12.46% 50.10% | 49998 12.46% 62.55% | 50143 12.49% 75.05% | 50105 12.48% 87.53% | 50045 12.47% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 401347 -system.ruby.L1Cache_Controller.MM_W.Load | 3 18.75% 18.75% | 1 6.25% 25.00% | 0 0.00% 25.00% | 3 18.75% 43.75% | 4 25.00% 68.75% | 0 0.00% 68.75% | 3 18.75% 87.50% | 2 12.50% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 16 -system.ruby.L1Cache_Controller.MM_W.Store | 2 11.11% 11.11% | 3 16.67% 27.78% | 4 22.22% 50.00% | 1 5.56% 55.56% | 3 16.67% 72.22% | 3 16.67% 88.89% | 1 5.56% 94.44% | 1 5.56% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 18 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 207903 12.76% 12.76% | 199705 12.26% 25.02% | 201929 12.40% 37.42% | 203693 12.50% 49.92% | 204500 12.55% 62.48% | 205369 12.61% 75.09% | 204273 12.54% 87.63% | 201565 12.37% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1628937 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 19 7.72% 7.72% | 26 10.57% 18.29% | 31 12.60% 30.89% | 38 15.45% 46.34% | 41 16.67% 63.01% | 32 13.01% 76.02% | 29 11.79% 87.80% | 30 12.20% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 246 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 45 9.98% 9.98% | 51 11.31% 21.29% | 67 14.86% 36.14% | 58 12.86% 49.00% | 59 13.08% 62.08% | 58 12.86% 74.94% | 62 13.75% 88.69% | 51 11.31% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 451 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 1 4.17% 4.17% | 2 8.33% 12.50% | 3 12.50% 25.00% | 4 16.67% 41.67% | 4 16.67% 58.33% | 4 16.67% 75.00% | 2 8.33% 83.33% | 4 16.67% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 24 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 3 6.98% 6.98% | 9 20.93% 27.91% | 4 9.30% 37.21% | 5 11.63% 48.84% | 7 16.28% 65.12% | 6 13.95% 79.07% | 6 13.95% 93.02% | 3 6.98% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 43 -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 263 13.34% 13.34% | 245 12.43% 25.77% | 253 12.84% 38.61% | 264 13.39% 52.00% | 260 13.19% 65.20% | 223 11.31% 76.51% | 217 11.01% 87.52% | 246 12.48% 100.00% -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 1971 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 2 7.41% 7.41% | 2 7.41% 14.81% | 3 11.11% 25.93% | 5 18.52% 44.44% | 5 18.52% 62.96% | 4 14.81% 77.78% | 2 7.41% 85.19% | 4 14.81% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 27 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 3 6.38% 6.38% | 9 19.15% 25.53% | 4 8.51% 34.04% | 5 10.64% 44.68% | 8 17.02% 61.70% | 6 12.77% 74.47% | 7 14.89% 89.36% | 5 10.64% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 47 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 28363 12.72% 12.72% | 27788 12.46% 25.19% | 27673 12.41% 37.60% | 28040 12.58% 50.18% | 27697 12.42% 62.60% | 28071 12.59% 75.19% | 27652 12.40% 87.60% | 27652 12.40% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 222936 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 299163 12.81% 12.81% | 291113 12.46% 25.27% | 289146 12.38% 37.65% | 289625 12.40% 50.04% | 292483 12.52% 62.56% | 295149 12.63% 75.20% | 289912 12.41% 87.61% | 289481 12.39% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2336072 -system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 28362 12.72% 12.72% | 27796 12.47% 25.19% | 27679 12.41% 37.60% | 28044 12.58% 50.18% | 27705 12.43% 62.60% | 28071 12.59% 75.19% | 27657 12.40% 87.60% | 27656 12.40% 100.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 222970 -system.ruby.L1Cache_Controller.IM.Ack | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 6 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 99 13.08% 13.08% | 90 11.89% 24.97% | 77 10.17% 35.14% | 92 12.15% 47.29% | 115 15.19% 62.48% | 103 13.61% 76.09% | 87 11.49% 87.58% | 94 12.42% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 757 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 156 11.69% 11.69% | 161 12.06% 23.75% | 159 11.91% 35.66% | 156 11.69% 47.34% | 170 12.73% 60.07% | 202 15.13% 75.21% | 176 13.18% 88.39% | 155 11.61% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1335 -system.ruby.L1Cache_Controller.IM.Persistent_GETX | 9 13.24% 13.24% | 13 19.12% 32.35% | 10 14.71% 47.06% | 8 11.76% 58.82% | 7 10.29% 69.12% | 8 11.76% 80.88% | 7 10.29% 91.18% | 6 8.82% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 68 -system.ruby.L1Cache_Controller.IM.Persistent_GETS | 12 8.39% 8.39% | 20 13.99% 22.38% | 15 10.49% 32.87% | 14 9.79% 42.66% | 21 14.69% 57.34% | 18 12.59% 69.93% | 21 14.69% 84.62% | 22 15.38% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 143 -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 1777 12.60% 12.60% | 1748 12.40% 25.00% | 1787 12.67% 37.67% | 1755 12.45% 50.11% | 1772 12.57% 62.68% | 1769 12.54% 75.22% | 1726 12.24% 87.46% | 1768 12.54% 100.00% -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 14102 -system.ruby.L1Cache_Controller.IM.Request_Timeout | 12748 12.91% 12.91% | 12072 12.23% 25.14% | 12469 12.63% 37.77% | 12565 12.73% 50.50% | 12512 12.67% 63.17% | 12178 12.34% 75.51% | 12291 12.45% 87.96% | 11887 12.04% 100.00% -system.ruby.L1Cache_Controller.IM.Request_Timeout::total 98722 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 526465 12.44% 12.44% | 533733 12.61% 25.05% | 535335 12.65% 37.70% | 529186 12.50% 50.20% | 524621 12.39% 62.59% | 526992 12.45% 75.04% | 527555 12.46% 87.51% | 528820 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4232707 -system.ruby.L1Cache_Controller.IS.Data_Shared | 187 13.47% 13.47% | 171 12.32% 25.79% | 171 12.32% 38.11% | 142 10.23% 48.34% | 173 12.46% 60.81% | 182 13.11% 73.92% | 173 12.46% 86.38% | 189 13.62% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Shared::total 1388 -system.ruby.L1Cache_Controller.IS.Data_Owner | 29 14.15% 14.15% | 28 13.66% 27.80% | 32 15.61% 43.41% | 23 11.22% 54.63% | 24 11.71% 66.34% | 20 9.76% 76.10% | 17 8.29% 84.39% | 32 15.61% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Owner::total 205 -system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50199 12.50% 12.50% | 50340 12.54% 25.04% | 50545 12.59% 37.63% | 50041 12.46% 50.09% | 50019 12.46% 62.55% | 50165 12.49% 75.05% | 50124 12.48% 87.53% | 50069 12.47% 100.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 401502 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 174 12.95% 12.95% | 188 13.99% 26.93% | 170 12.65% 39.58% | 160 11.90% 51.49% | 156 11.61% 63.10% | 158 11.76% 74.85% | 179 13.32% 88.17% | 159 11.83% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1344 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 308 12.65% 12.65% | 287 11.79% 24.45% | 338 13.89% 38.33% | 293 12.04% 50.37% | 296 12.16% 62.53% | 297 12.20% 74.73% | 315 12.94% 87.67% | 300 12.33% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2434 -system.ruby.L1Cache_Controller.IS.Persistent_GETX | 12 8.96% 8.96% | 22 16.42% 25.37% | 16 11.94% 37.31% | 16 11.94% 49.25% | 22 16.42% 65.67% | 10 7.46% 73.13% | 20 14.93% 88.06% | 16 11.94% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 134 -system.ruby.L1Cache_Controller.IS.Persistent_GETS | 23 10.36% 10.36% | 27 12.16% 22.52% | 31 13.96% 36.49% | 27 12.16% 48.65% | 30 13.51% 62.16% | 27 12.16% 74.32% | 23 10.36% 84.68% | 34 15.32% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 222 -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 3220 12.48% 12.48% | 3284 12.72% 25.20% | 3229 12.51% 37.71% | 3182 12.33% 50.04% | 3192 12.37% 62.41% | 3201 12.40% 74.81% | 3302 12.79% 87.60% | 3200 12.40% 100.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 25810 -system.ruby.L1Cache_Controller.IS.Request_Timeout | 23004 12.71% 12.71% | 23289 12.87% 25.58% | 22739 12.57% 38.15% | 21960 12.14% 50.28% | 22817 12.61% 62.89% | 22505 12.44% 75.33% | 21709 12.00% 87.32% | 22937 12.68% 100.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout::total 180960 -system.ruby.L1Cache_Controller.I_L.Load | 21 11.35% 11.35% | 22 11.89% 23.24% | 26 14.05% 37.30% | 28 15.14% 52.43% | 28 15.14% 67.57% | 17 9.19% 76.76% | 23 12.43% 89.19% | 20 10.81% 100.00% -system.ruby.L1Cache_Controller.I_L.Load::total 185 -system.ruby.L1Cache_Controller.I_L.Store | 14 13.46% 13.46% | 14 13.46% 26.92% | 6 5.77% 32.69% | 10 9.62% 42.31% | 14 13.46% 55.77% | 15 14.42% 70.19% | 14 13.46% 83.65% | 17 16.35% 100.00% -system.ruby.L1Cache_Controller.I_L.Store::total 104 -system.ruby.L1Cache_Controller.I_L.L1_Replacement | 114 9.60% 9.60% | 190 16.01% 25.61% | 113 9.52% 35.13% | 133 11.20% 46.34% | 115 9.69% 56.02% | 141 11.88% 67.90% | 177 14.91% 82.81% | 204 17.19% 100.00% -system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1187 -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 28 24.56% 24.56% | 16 14.04% 38.60% | 21 18.42% 57.02% | 20 17.54% 74.56% | 15 13.16% 87.72% | 10 8.77% 96.49% | 4 3.51% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 114 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 74 11.86% 11.86% | 75 12.02% 23.88% | 86 13.78% 37.66% | 80 12.82% 50.48% | 76 12.18% 62.66% | 79 12.66% 75.32% | 78 12.50% 87.82% | 76 12.18% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 624 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 139 13.03% 13.03% | 133 12.46% 25.49% | 129 12.09% 37.58% | 132 12.37% 49.95% | 122 11.43% 61.39% | 148 13.87% 75.26% | 130 12.18% 87.44% | 134 12.56% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 1067 -system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 14071 12.48% 12.48% | 14096 12.51% 24.99% | 14063 12.48% 37.47% | 14085 12.50% 49.96% | 14063 12.48% 62.44% | 14120 12.53% 74.97% | 14143 12.55% 87.51% | 14075 12.49% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 112716 -system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 25744 12.50% 12.50% | 25668 12.46% 24.97% | 25687 12.47% 37.44% | 25805 12.53% 49.97% | 25786 12.52% 62.49% | 25771 12.51% 75.01% | 25691 12.48% 87.48% | 25777 12.52% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 205929 -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 30 10.49% 10.49% | 38 13.29% 23.78% | 33 11.54% 35.31% | 35 12.24% 47.55% | 37 12.94% 60.49% | 29 10.14% 70.63% | 44 15.38% 86.01% | 40 13.99% 100.00% -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 286 -system.ruby.L1Cache_Controller.S_L.L1_Replacement | 39 12.79% 12.79% | 51 16.72% 29.51% | 22 7.21% 36.72% | 46 15.08% 51.80% | 26 8.52% 60.33% | 23 7.54% 67.87% | 43 14.10% 81.97% | 55 18.03% 100.00% -system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 305 -system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 12.00% 12.00% | 2 8.00% 20.00% | 3 12.00% 32.00% | 7 28.00% 60.00% | 3 12.00% 72.00% | 7 28.00% 100.00% -system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 25 -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 23 11.11% 11.11% | 32 15.46% 26.57% | 31 14.98% 41.55% | 21 10.14% 51.69% | 26 12.56% 64.25% | 27 13.04% 77.29% | 27 13.04% 90.34% | 20 9.66% 100.00% -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 207 -system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 185 11.08% 11.08% | 258 15.45% 26.53% | 235 14.07% 40.60% | 170 10.18% 50.78% | 277 16.59% 67.37% | 192 11.50% 78.86% | 184 11.02% 89.88% | 169 10.12% 100.00% -system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 1670 -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 1 11.11% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 1 11.11% 55.56% | 2 22.22% 77.78% | 2 22.22% 100.00% -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 9 -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total 1 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 9.09% 9.09% | 0 0.00% 9.09% | 2 18.18% 27.27% | 2 18.18% 45.45% | 4 36.36% 81.82% | 2 18.18% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 11 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 1 2.86% 2.86% | 1 2.86% 5.71% | 5 14.29% 20.00% | 6 17.14% 37.14% | 5 14.29% 51.43% | 9 25.71% 77.14% | 8 22.86% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 35 -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 34 11.11% 11.11% | 47 15.36% 26.47% | 31 10.13% 36.60% | 31 10.13% 46.73% | 40 13.07% 59.80% | 40 13.07% 72.88% | 40 13.07% 85.95% | 43 14.05% 100.00% -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 306 -system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 33 7.88% 7.88% | 43 10.26% 18.14% | 55 13.13% 31.26% | 25 5.97% 37.23% | 31 7.40% 44.63% | 116 27.68% 72.32% | 63 15.04% 87.35% | 53 12.65% 100.00% -system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 419 -system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 300 11.54% 11.54% | 385 14.81% 26.36% | 365 14.04% 40.40% | 361 13.89% 54.29% | 396 15.24% 69.53% | 220 8.46% 77.99% | 235 9.04% 87.03% | 337 12.97% 100.00% -system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 2599 -system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 1 -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 0 0.00% 0.00% | 3 23.08% 23.08% | 2 15.38% 38.46% | 1 7.69% 46.15% | 1 7.69% 53.85% | 1 7.69% 61.54% | 2 15.38% 76.92% | 3 23.08% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 13 -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 1 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 1 4.55% 4.55% | 0 0.00% 4.55% | 1 4.55% 9.09% | 5 22.73% 31.82% | 3 13.64% 45.45% | 7 31.82% 77.27% | 5 22.73% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 22 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 4 8.00% 8.00% | 4 8.00% 16.00% | 4 8.00% 24.00% | 6 12.00% 36.00% | 10 20.00% 56.00% | 6 12.00% 68.00% | 16 32.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 50 -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 56 10.63% 10.63% | 68 12.90% 23.53% | 71 13.47% 37.00% | 69 13.09% 50.09% | 79 14.99% 65.09% | 53 10.06% 75.14% | 64 12.14% 87.29% | 67 12.71% 100.00% -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 527 -system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 108 14.06% 14.06% | 94 12.24% 26.30% | 144 18.75% 45.05% | 95 12.37% 57.42% | 50 6.51% 63.93% | 98 12.76% 76.69% | 65 8.46% 85.16% | 114 14.84% 100.00% -system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 768 -system.ruby.L2Cache_Controller.L1_GETS 403094 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS_Last_Token 23 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 222986 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_INV 710 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 598155 0.00% 0.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 1 +system.ruby.L1Cache_Controller.O.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Persistent_GETX::total 1 +system.ruby.L1Cache_Controller.O.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Persistent_GETS::total 4 +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 8 14.81% 14.81% | 7 12.96% 27.78% | 7 12.96% 40.74% | 2 3.70% 44.44% | 5 9.26% 53.70% | 9 16.67% 70.37% | 7 12.96% 83.33% | 9 16.67% 100.00% +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 54 +system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 2 6.90% 6.90% | 7 24.14% 31.03% | 5 17.24% 48.28% | 5 17.24% 65.52% | 3 10.34% 75.86% | 2 6.90% 82.76% | 5 17.24% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 29 +system.ruby.L1Cache_Controller.M.Store | 1 6.67% 6.67% | 2 13.33% 20.00% | 3 20.00% 40.00% | 2 13.33% 53.33% | 1 6.67% 60.00% | 3 20.00% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 15 +system.ruby.L1Cache_Controller.M.L1_Replacement | 50241 12.51% 12.51% | 50317 12.53% 25.04% | 50222 12.51% 37.55% | 50111 12.48% 50.03% | 50241 12.51% 62.54% | 50069 12.47% 75.01% | 50018 12.46% 87.46% | 50338 12.54% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 401557 +system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 17 11.18% 11.18% | 18 11.84% 23.03% | 22 14.47% 37.50% | 20 13.16% 50.66% | 33 21.71% 72.37% | 19 12.50% 84.87% | 8 5.26% 90.13% | 15 9.87% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 152 +system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 41 12.39% 12.39% | 48 14.50% 26.89% | 41 12.39% 39.27% | 44 13.29% 52.57% | 45 13.60% 66.16% | 35 10.57% 76.74% | 30 9.06% 85.80% | 47 14.20% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 331 +system.ruby.L1Cache_Controller.M.Persistent_GETX | 8 12.12% 12.12% | 9 13.64% 25.76% | 6 9.09% 34.85% | 10 15.15% 50.00% | 11 16.67% 66.67% | 9 13.64% 80.30% | 7 10.61% 90.91% | 6 9.09% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETX::total 66 +system.ruby.L1Cache_Controller.M.Persistent_GETS | 14 13.86% 13.86% | 18 17.82% 31.68% | 6 5.94% 37.62% | 18 17.82% 55.45% | 15 14.85% 70.30% | 10 9.90% 80.20% | 10 9.90% 90.10% | 10 9.90% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETS::total 101 +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 348 14.36% 14.36% | 327 13.50% 27.86% | 305 12.59% 40.45% | 299 12.34% 52.79% | 285 11.76% 64.55% | 303 12.51% 77.05% | 293 12.09% 89.15% | 263 10.85% 100.00% +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 2423 +system.ruby.L1Cache_Controller.MM.Load | 5 31.25% 31.25% | 1 6.25% 37.50% | 1 6.25% 43.75% | 4 25.00% 68.75% | 2 12.50% 81.25% | 0 0.00% 81.25% | 1 6.25% 87.50% | 2 12.50% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 16 +system.ruby.L1Cache_Controller.MM.Store | 2 25.00% 25.00% | 0 0.00% 25.00% | 3 37.50% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 8 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 28161 12.65% 12.65% | 27700 12.44% 25.08% | 27964 12.56% 37.64% | 27614 12.40% 50.04% | 27628 12.41% 62.45% | 27935 12.54% 74.99% | 28113 12.62% 87.62% | 27575 12.38% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222690 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 8 9.20% 9.20% | 11 12.64% 21.84% | 14 16.09% 37.93% | 8 9.20% 47.13% | 6 6.90% 54.02% | 14 16.09% 70.11% | 14 16.09% 86.21% | 12 13.79% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 87 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 25 15.34% 15.34% | 22 13.50% 28.83% | 22 13.50% 42.33% | 17 10.43% 52.76% | 16 9.82% 62.58% | 25 15.34% 77.91% | 18 11.04% 88.96% | 18 11.04% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 163 +system.ruby.L1Cache_Controller.MM.Persistent_GETX | 5 13.16% 13.16% | 5 13.16% 26.32% | 8 21.05% 47.37% | 2 5.26% 52.63% | 3 7.89% 60.53% | 2 5.26% 65.79% | 5 13.16% 78.95% | 8 21.05% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 38 +system.ruby.L1Cache_Controller.MM.Persistent_GETS | 8 15.09% 15.09% | 8 15.09% 30.19% | 7 13.21% 43.40% | 4 7.55% 50.94% | 4 7.55% 58.49% | 7 13.21% 71.70% | 8 15.09% 86.79% | 7 13.21% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 53 +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 173 13.08% 13.08% | 166 12.55% 25.62% | 133 10.05% 35.68% | 184 13.91% 49.58% | 170 12.85% 62.43% | 162 12.24% 74.68% | 142 10.73% 85.41% | 193 14.59% 100.00% +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 1323 +system.ruby.L1Cache_Controller.M_W.Load | 5 10.87% 10.87% | 4 8.70% 19.57% | 5 10.87% 30.43% | 6 13.04% 43.48% | 8 17.39% 60.87% | 7 15.22% 76.09% | 5 10.87% 86.96% | 6 13.04% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 46 +system.ruby.L1Cache_Controller.M_W.Store | 1 3.45% 3.45% | 4 13.79% 17.24% | 3 10.34% 27.59% | 3 10.34% 37.93% | 5 17.24% 55.17% | 4 13.79% 68.97% | 6 20.69% 89.66% | 3 10.34% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 29 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 370210 12.51% 12.51% | 372575 12.59% 25.10% | 370139 12.51% 37.61% | 371169 12.54% 50.15% | 368462 12.45% 62.61% | 368601 12.46% 75.06% | 366548 12.39% 87.45% | 371410 12.55% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2959114 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 56 12.70% 12.70% | 55 12.47% 25.17% | 58 13.15% 38.32% | 57 12.93% 51.25% | 61 13.83% 65.08% | 53 12.02% 77.10% | 46 10.43% 87.53% | 55 12.47% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 441 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 84 9.81% 9.81% | 131 15.30% 25.12% | 119 13.90% 39.02% | 124 14.49% 53.50% | 103 12.03% 65.54% | 97 11.33% 76.87% | 96 11.21% 88.08% | 102 11.92% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 856 +system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 3 10.00% 10.00% | 2 6.67% 16.67% | 4 13.33% 30.00% | 3 10.00% 40.00% | 7 23.33% 63.33% | 4 13.33% 76.67% | 5 16.67% 93.33% | 2 6.67% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 30 +system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 2 2.38% 2.38% | 11 13.10% 15.48% | 11 13.10% 28.57% | 10 11.90% 40.48% | 7 8.33% 48.81% | 13 15.48% 64.29% | 17 20.24% 84.52% | 13 15.48% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 84 +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 440 12.63% 12.63% | 415 11.91% 24.53% | 440 12.63% 37.16% | 413 11.85% 49.01% | 428 12.28% 61.29% | 446 12.80% 74.09% | 472 13.54% 87.63% | 431 12.37% 100.00% +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3485 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 3 10.00% 10.00% | 2 6.67% 16.67% | 4 13.33% 30.00% | 3 10.00% 40.00% | 7 23.33% 63.33% | 4 13.33% 76.67% | 5 16.67% 93.33% | 2 6.67% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 30 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 2 2.20% 2.20% | 11 12.09% 14.29% | 11 12.09% 26.37% | 10 10.99% 37.36% | 9 9.89% 47.25% | 15 16.48% 63.74% | 18 19.78% 83.52% | 15 16.48% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 91 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50321 12.51% 12.51% | 50412 12.53% 25.04% | 50299 12.51% 37.55% | 50203 12.48% 50.03% | 50345 12.52% 62.55% | 50143 12.47% 75.02% | 50076 12.45% 87.47% | 50415 12.53% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 402214 +system.ruby.L1Cache_Controller.MM_W.Load | 5 17.24% 17.24% | 4 13.79% 31.03% | 2 6.90% 37.93% | 3 10.34% 48.28% | 2 6.90% 55.17% | 6 20.69% 75.86% | 2 6.90% 82.76% | 5 17.24% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 29 +system.ruby.L1Cache_Controller.MM_W.Store | 2 14.29% 14.29% | 2 14.29% 28.57% | 3 21.43% 50.00% | 0 0.00% 50.00% | 1 7.14% 57.14% | 2 14.29% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 14 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 204288 12.51% 12.51% | 203606 12.47% 24.97% | 204500 12.52% 37.50% | 202849 12.42% 49.92% | 203274 12.45% 62.36% | 204548 12.52% 74.89% | 207925 12.73% 87.62% | 202241 12.38% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1633231 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 35 12.82% 12.82% | 24 8.79% 21.61% | 38 13.92% 35.53% | 36 13.19% 48.72% | 33 12.09% 60.81% | 33 12.09% 72.89% | 35 12.82% 85.71% | 39 14.29% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 273 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 50 10.35% 10.35% | 55 11.39% 21.74% | 62 12.84% 34.58% | 55 11.39% 45.96% | 64 13.25% 59.21% | 69 14.29% 73.50% | 61 12.63% 86.13% | 67 13.87% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 483 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 3 12.00% 12.00% | 3 12.00% 24.00% | 2 8.00% 32.00% | 4 16.00% 48.00% | 1 4.00% 52.00% | 2 8.00% 60.00% | 3 12.00% 72.00% | 7 28.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 25 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 5 11.36% 11.36% | 5 11.36% 22.73% | 4 9.09% 31.82% | 3 6.82% 38.64% | 3 6.82% 45.45% | 10 22.73% 68.18% | 5 11.36% 79.55% | 9 20.45% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 44 +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 266 13.73% 13.73% | 227 11.72% 25.45% | 273 14.09% 39.55% | 235 12.13% 51.68% | 237 12.24% 63.91% | 234 12.08% 75.99% | 225 11.62% 87.61% | 240 12.39% 100.00% +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 1937 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 3 11.54% 11.54% | 3 11.54% 23.08% | 2 7.69% 30.77% | 4 15.38% 46.15% | 1 3.85% 50.00% | 2 7.69% 57.69% | 3 11.54% 69.23% | 8 30.77% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 26 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 5 11.11% 11.11% | 6 13.33% 24.44% | 4 8.89% 33.33% | 3 6.67% 40.00% | 3 6.67% 46.67% | 10 22.22% 68.89% | 5 11.11% 80.00% | 9 20.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 45 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 28207 12.65% 12.65% | 27744 12.44% 25.09% | 28012 12.56% 37.65% | 27643 12.39% 50.04% | 27656 12.40% 62.44% | 27980 12.55% 74.99% | 28157 12.63% 87.62% | 27619 12.38% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223018 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 297233 12.73% 12.73% | 289886 12.42% 25.15% | 289674 12.41% 37.56% | 288888 12.37% 49.93% | 292575 12.53% 62.46% | 292468 12.53% 74.99% | 295557 12.66% 87.65% | 288386 12.35% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2334667 +system.ruby.L1Cache_Controller.IM.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.IM.Data_Owner::total 3 +system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 28214 12.65% 12.65% | 27748 12.44% 25.09% | 28014 12.56% 37.65% | 27648 12.40% 50.04% | 27655 12.40% 62.44% | 27988 12.55% 74.99% | 28158 12.62% 87.61% | 27632 12.39% 100.00% +system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223057 +system.ruby.L1Cache_Controller.IM.Ack | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 5 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 97 13.80% 13.80% | 99 14.08% 27.88% | 72 10.24% 38.12% | 102 14.51% 52.63% | 79 11.24% 63.87% | 86 12.23% 76.10% | 72 10.24% 86.34% | 96 13.66% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 703 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 157 12.07% 12.07% | 146 11.22% 23.29% | 173 13.30% 36.59% | 141 10.84% 47.43% | 168 12.91% 60.34% | 186 14.30% 74.63% | 157 12.07% 86.70% | 173 13.30% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1301 +system.ruby.L1Cache_Controller.IM.Persistent_GETX | 6 12.00% 12.00% | 5 10.00% 22.00% | 5 10.00% 32.00% | 5 10.00% 42.00% | 6 12.00% 54.00% | 9 18.00% 72.00% | 9 18.00% 90.00% | 5 10.00% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 50 +system.ruby.L1Cache_Controller.IM.Persistent_GETS | 11 10.48% 10.48% | 13 12.38% 22.86% | 17 16.19% 39.05% | 10 9.52% 48.57% | 13 12.38% 60.95% | 15 14.29% 75.24% | 13 12.38% 87.62% | 13 12.38% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 105 +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 1706 12.40% 12.40% | 1723 12.52% 24.92% | 1721 12.51% 37.43% | 1759 12.78% 50.21% | 1740 12.65% 62.86% | 1764 12.82% 75.68% | 1632 11.86% 87.54% | 1715 12.46% 100.00% +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 13760 +system.ruby.L1Cache_Controller.IM.Request_Timeout | 11760 12.12% 12.12% | 12506 12.89% 25.02% | 12482 12.87% 37.89% | 12270 12.65% 50.54% | 11911 12.28% 62.82% | 11774 12.14% 74.96% | 11971 12.34% 87.30% | 12321 12.70% 100.00% +system.ruby.L1Cache_Controller.IM.Request_Timeout::total 96995 +system.ruby.L1Cache_Controller.OM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 24 63.16% 63.16% | 0 0.00% 63.16% | 0 0.00% 63.16% | 0 0.00% 63.16% | 2 5.26% 68.42% | 12 31.58% 100.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement::total 38 +system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total 3 +system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock::total 2 +system.ruby.L1Cache_Controller.OM.Request_Timeout | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.OM.Request_Timeout::total 2 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 529103 12.51% 12.51% | 530672 12.54% 25.05% | 533381 12.61% 37.66% | 528913 12.50% 50.16% | 528203 12.49% 62.65% | 526767 12.45% 75.10% | 522401 12.35% 87.45% | 531078 12.55% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4230518 +system.ruby.L1Cache_Controller.IS.Data_Shared | 182 12.74% 12.74% | 180 12.60% 25.33% | 177 12.39% 37.72% | 176 12.32% 50.03% | 184 12.88% 62.91% | 172 12.04% 74.95% | 179 12.53% 87.47% | 179 12.53% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Shared::total 1429 +system.ruby.L1Cache_Controller.IS.Data_Owner | 23 11.39% 11.39% | 31 15.35% 26.73% | 30 14.85% 41.58% | 19 9.41% 50.99% | 27 13.37% 64.36% | 21 10.40% 74.75% | 26 12.87% 87.62% | 25 12.38% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Owner::total 202 +system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50326 12.51% 12.51% | 50430 12.53% 25.04% | 50318 12.51% 37.55% | 50220 12.48% 50.03% | 50365 12.52% 62.55% | 50164 12.47% 75.01% | 50104 12.45% 87.47% | 50434 12.53% 100.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 402361 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 166 13.17% 13.17% | 158 12.54% 25.71% | 158 12.54% 38.25% | 143 11.35% 49.60% | 183 14.52% 64.13% | 147 11.67% 75.79% | 148 11.75% 87.54% | 157 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1260 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 290 12.11% 12.11% | 316 13.19% 25.30% | 302 12.61% 37.91% | 301 12.57% 50.48% | 323 13.49% 63.97% | 281 11.73% 75.70% | 277 11.57% 87.27% | 305 12.73% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2395 +system.ruby.L1Cache_Controller.IS.Persistent_GETX | 7 6.93% 6.93% | 24 23.76% 30.69% | 15 14.85% 45.54% | 11 10.89% 56.44% | 13 12.87% 69.31% | 15 14.85% 84.16% | 9 8.91% 93.07% | 7 6.93% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 101 +system.ruby.L1Cache_Controller.IS.Persistent_GETS | 30 13.39% 13.39% | 30 13.39% 26.79% | 30 13.39% 40.18% | 19 8.48% 48.66% | 28 12.50% 61.16% | 24 10.71% 71.88% | 31 13.84% 85.71% | 32 14.29% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 224 +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 3245 12.99% 12.99% | 3160 12.65% 25.63% | 3132 12.53% 38.17% | 3085 12.35% 50.51% | 3159 12.64% 63.15% | 3121 12.49% 75.64% | 3072 12.29% 87.94% | 3014 12.06% 100.00% +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 24988 +system.ruby.L1Cache_Controller.IS.Request_Timeout | 21713 12.50% 12.50% | 21677 12.48% 24.98% | 21741 12.52% 37.50% | 21122 12.16% 49.66% | 22600 13.01% 62.67% | 21444 12.35% 75.02% | 22164 12.76% 87.78% | 21223 12.22% 100.00% +system.ruby.L1Cache_Controller.IS.Request_Timeout::total 173684 +system.ruby.L1Cache_Controller.I_L.Load | 25 12.63% 12.63% | 17 8.59% 21.21% | 18 9.09% 30.30% | 26 13.13% 43.43% | 29 14.65% 58.08% | 20 10.10% 68.18% | 26 13.13% 81.31% | 37 18.69% 100.00% +system.ruby.L1Cache_Controller.I_L.Load::total 198 +system.ruby.L1Cache_Controller.I_L.Store | 13 11.61% 11.61% | 7 6.25% 17.86% | 15 13.39% 31.25% | 17 15.18% 46.43% | 15 13.39% 59.82% | 18 16.07% 75.89% | 16 14.29% 90.18% | 11 9.82% 100.00% +system.ruby.L1Cache_Controller.I_L.Store::total 112 +system.ruby.L1Cache_Controller.I_L.L1_Replacement | 95 7.85% 7.85% | 180 14.88% 22.73% | 131 10.83% 33.55% | 79 6.53% 40.08% | 151 12.48% 52.56% | 218 18.02% 70.58% | 150 12.40% 82.98% | 206 17.02% 100.00% +system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1210 +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 18 17.14% 17.14% | 23 21.90% 39.05% | 11 10.48% 49.52% | 15 14.29% 63.81% | 10 9.52% 73.33% | 12 11.43% 84.76% | 7 6.67% 91.43% | 9 8.57% 100.00% +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 105 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 97 13.84% 13.84% | 95 13.55% 27.39% | 83 11.84% 39.23% | 85 12.13% 51.36% | 87 12.41% 63.77% | 78 11.13% 74.89% | 90 12.84% 87.73% | 86 12.27% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 701 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 144 12.85% 12.85% | 138 12.31% 25.16% | 149 13.29% 38.45% | 135 12.04% 50.49% | 137 12.22% 62.71% | 142 12.67% 75.38% | 140 12.49% 87.87% | 136 12.13% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 1121 +system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 13750 12.50% 12.50% | 13751 12.50% 25.01% | 13711 12.47% 37.47% | 13722 12.48% 49.95% | 13734 12.49% 62.44% | 13710 12.47% 74.90% | 13851 12.59% 87.50% | 13752 12.50% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 109981 +system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 24873 12.45% 12.45% | 24947 12.49% 24.94% | 24964 12.50% 37.43% | 25049 12.54% 49.97% | 24936 12.48% 62.45% | 24961 12.49% 74.95% | 24980 12.50% 87.45% | 25073 12.55% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 199783 +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 33 12.45% 12.45% | 33 12.45% 24.91% | 32 12.08% 36.98% | 27 10.19% 47.17% | 31 11.70% 58.87% | 35 13.21% 72.08% | 33 12.45% 84.53% | 41 15.47% 100.00% +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 265 +system.ruby.L1Cache_Controller.S_L.L1_Replacement | 38 11.55% 11.55% | 61 18.54% 30.09% | 26 7.90% 37.99% | 51 15.50% 53.50% | 62 18.84% 72.34% | 10 3.04% 75.38% | 62 18.84% 94.22% | 19 5.78% 100.00% +system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 329 +system.ruby.L1Cache_Controller.S_L.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S_L.Data_All_Tokens::total 1 +system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 1 2.94% 2.94% | 2 5.88% 8.82% | 1 2.94% 11.76% | 7 20.59% 32.35% | 8 23.53% 55.88% | 9 26.47% 82.35% | 6 17.65% 100.00% +system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 34 +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 17 8.50% 8.50% | 29 14.50% 23.00% | 18 9.00% 32.00% | 29 14.50% 46.50% | 27 13.50% 60.00% | 26 13.00% 73.00% | 29 14.50% 87.50% | 25 12.50% 100.00% +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 200 +system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 166 11.01% 11.01% | 156 10.34% 21.35% | 235 15.58% 36.94% | 157 10.41% 47.35% | 147 9.75% 57.10% | 250 16.58% 73.67% | 227 15.05% 88.73% | 170 11.27% 100.00% +system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 1508 +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 2 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 4 57.14% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 7 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 1 4.55% 4.55% | 1 4.55% 9.09% | 4 18.18% 27.27% | 1 4.55% 31.82% | 6 27.27% 59.09% | 3 13.64% 72.73% | 6 27.27% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 22 +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 30 11.32% 11.32% | 24 9.06% 20.38% | 37 13.96% 34.34% | 32 12.08% 46.42% | 34 12.83% 59.25% | 42 15.85% 75.09% | 38 14.34% 89.43% | 28 10.57% 100.00% +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 265 +system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 24 6.11% 6.11% | 43 10.94% 17.05% | 48 12.21% 29.26% | 26 6.62% 35.88% | 18 4.58% 40.46% | 66 16.79% 57.25% | 138 35.11% 92.37% | 30 7.63% 100.00% +system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 393 +system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 210 8.70% 8.70% | 363 15.04% 23.74% | 263 10.89% 34.63% | 225 9.32% 43.95% | 282 11.68% 55.63% | 363 15.04% 70.67% | 336 13.92% 84.59% | 372 15.41% 100.00% +system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 2414 +system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 3 +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 1 12.50% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 2 25.00% 37.50% | 2 25.00% 62.50% | 1 12.50% 75.00% | 2 25.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 8 +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 2 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 2 9.52% 9.52% | 4 19.05% 28.57% | 3 14.29% 42.86% | 1 4.76% 47.62% | 3 14.29% 61.90% | 1 4.76% 66.67% | 7 33.33% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 21 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 1 2.44% 2.44% | 1 2.44% 4.88% | 5 12.20% 17.07% | 11 26.83% 43.90% | 5 12.20% 56.10% | 9 21.95% 78.05% | 9 21.95% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 41 +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 61 11.91% 11.91% | 71 13.87% 25.78% | 62 12.11% 37.89% | 56 10.94% 48.83% | 67 13.09% 61.91% | 57 11.13% 73.05% | 65 12.70% 85.74% | 73 14.26% 100.00% +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 512 +system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 122 15.66% 15.66% | 80 10.27% 25.93% | 163 20.92% 46.85% | 39 5.01% 51.86% | 125 16.05% 67.91% | 143 18.36% 86.26% | 73 9.37% 95.64% | 34 4.36% 100.00% +system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 779 +system.ruby.L2Cache_Controller.L1_GETS 403983 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS_Last_Token 34 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 223069 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_INV 668 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 599911 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_Shared_Data 988 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 623923 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_All_Tokens 624946 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_Owned 455 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETX 16161 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 29526 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token 3 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 45286 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 401858 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 222292 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_INV 514 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 918 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 596876 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Owned 369 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 38185 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETS 48 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETX 20 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 7228 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 471 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Owned 6 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Persistent_GETX 15 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Persistent_GETS 24 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 23 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 848 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 3 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 55 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Owned 2 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETS 3 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETS_Last_Token 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETS 19 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 879 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 3 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 593 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETS 11 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1108 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 634 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 588428 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETX 2726 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETS 5091 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETS 61 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETX 40 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_INV 196 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L2_Replacement 771 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 64 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 25928 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Owned 78 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 13418 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 24397 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 7087 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.L2_Replacement 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Persistent_GETS_Last_Token 2 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 14 0.00% 0.00% -system.ruby.Directory_Controller.GETX 238416 0.00% 0.00% -system.ruby.Directory_Controller.GETS 430906 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 45690 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 45286 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 310 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 243497 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 539 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 377964 0.00% 0.00% -system.ruby.Directory_Controller.Tokens 139 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 778 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 621933 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 243403 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 219960 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 397659 0.00% 0.00% -system.ruby.Directory_Controller.O.Lockdown 3830 0.00% 0.00% -system.ruby.Directory_Controller.O.Data_All_Tokens 61 0.00% 0.00% -system.ruby.Directory_Controller.O.Tokens 9 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 769 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 2247 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 4060 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 17747 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 309 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 243096 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 538 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 377582 0.00% 0.00% -system.ruby.Directory_Controller.NO.Tokens 129 0.00% 0.00% -system.ruby.Directory_Controller.L.GETX 143 0.00% 0.00% -system.ruby.Directory_Controller.L.GETS 246 0.00% 0.00% -system.ruby.Directory_Controller.L.Lockdown 355 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 45285 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_All_Tokens 305 0.00% 0.00% -system.ruby.Directory_Controller.L.Ack_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 382 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 63 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 106 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Lockdown 111 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Data_All_Tokens 35 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Tokens 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Data 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 243292 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETX 54 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETS 94 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Lockdown 12 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Unlockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Data 4323 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Ack 111 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETX 508 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETS 910 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Lockdown 37 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 23598 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETX 15441 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETS 27831 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 23598 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 594011 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETX 15761 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS 28642 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 44053 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 402707 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 222334 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_INV 488 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 916 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 598635 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Owned 368 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 36593 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETS 55 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETX 24 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_INV 2 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L2_Replacement 7638 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 4 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 472 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_Owned 15 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETS 16 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 34 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 821 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 5 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 71 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Owned 1 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Persistent_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Persistent_GETS 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETS 21 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L2_Replacement 877 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 628 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Persistent_GETS 8 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1132 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 659 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 589830 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETX 2834 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETS 5343 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETS 68 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETX 49 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_INV 178 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L2_Replacement 745 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 62 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 25140 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Owned 71 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETX 12924 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETS 23274 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 7451 0.00% 0.00% +system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 9 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 03a62fad6..c6e069465 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.004762 # Number of seconds simulated -sim_ticks 4761781 # Number of ticks simulated -final_tick 4761781 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.004718 # Number of seconds simulated +sim_ticks 4717737 # Number of ticks simulated +final_tick 4717737 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 26949 # Simulator tick rate (ticks/s) -host_mem_usage 651208 # Number of bytes of host memory used -host_seconds 176.70 # Real time elapsed on the host +host_tick_rate 46146 # Simulator tick rate (ticks/s) +host_mem_usage 663608 # Number of bytes of host memory used +host_seconds 102.24 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38848448 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 38848448 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14135424 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14135424 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 607007 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 607007 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 220866 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 220866 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 8158386116 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 8158386116 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 2968516192 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 2968516192 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 11126902308 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 11126902308 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 607023 # Number of read requests accepted -system.mem_ctrls.writeReqs 220866 # Number of write requests accepted -system.mem_ctrls.readBursts 607023 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 220866 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 37843264 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 1005824 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 13945792 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 38849472 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14135424 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 15716 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 2913 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38891008 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 38891008 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14178496 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14178496 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 607672 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 607672 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 221539 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 221539 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 8243572713 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 8243572713 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 3005359561 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 3005359561 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 11248932274 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 11248932274 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 607686 # Number of read requests accepted +system.mem_ctrls.writeReqs 221539 # Number of write requests accepted +system.mem_ctrls.readBursts 607686 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 221539 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 37901760 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 989888 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 13990016 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 38891904 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14178496 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 15467 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 2896 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 73725 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 74070 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 73899 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 74128 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 73783 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 73790 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 73969 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 73937 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 74248 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 73965 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 74362 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 73718 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 73629 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 74182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 74198 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 73913 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27482 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27277 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27210 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27258 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27255 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27079 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27033 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27309 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27580 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27153 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27465 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27217 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27251 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27223 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27298 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27407 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,54 +68,54 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 342 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 4761762 # Total gap between requests +system.mem_ctrls.numWrRetry 341 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 4717717 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 607023 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 607686 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 220866 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 181 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 455 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 845 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 1380 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 2033 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 2935 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 3979 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 5130 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 6504 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 8329 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 11310 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 15935 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 23242 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 33896 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 47467 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 60476 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 68838 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 70112 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 62885 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 49064 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 34859 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 23771 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 16687 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 12606 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 9780 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 7459 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 5197 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 3229 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 1706 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 751 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 231 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 35 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 221539 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 173 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 425 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 892 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1471 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 2214 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3131 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 4313 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 5653 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 7328 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 9462 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 12392 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 16826 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 24221 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 34718 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 47678 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 60525 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 68415 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 69451 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 61971 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 48773 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 34538 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 23158 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 15821 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 11733 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 9215 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 7008 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 4874 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 3036 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 1729 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 772 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 260 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 43 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -140,992 +140,996 @@ system.mem_ctrls.wrQLenPdf::20 1 # Wh system.mem_ctrls.wrQLenPdf::21 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 9 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 31 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 75 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 107 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 167 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 222 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 301 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 426 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 602 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 1418 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 3050 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 5274 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 7692 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 9880 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 11429 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 12821 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 13884 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 14674 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 15391 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 16299 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 16813 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 16410 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 16033 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 16244 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 17262 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 12153 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 4599 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 1544 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 860 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 596 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 368 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 307 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 271 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 637 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 214623 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 241.295295 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 191.288039 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 173.301221 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 35466 16.52% 16.52% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 90893 42.35% 58.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 45716 21.30% 80.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 21225 9.89% 90.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10997 5.12% 95.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5731 2.67% 97.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2748 1.28% 99.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1136 0.53% 99.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 711 0.33% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 214623 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13609 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 43.445147 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 31.477862 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 25.391105 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-15 3000 22.04% 22.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-31 1539 11.31% 33.35% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-47 2539 18.66% 52.01% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-63 3040 22.34% 74.35% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-79 2614 19.21% 93.56% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-95 821 6.03% 99.59% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-111 53 0.39% 99.98% # Reads before turning the bus around for writes +system.mem_ctrls.wrQLenPdf::30 24 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 90 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 196 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 295 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 386 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 531 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 677 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 1545 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 3338 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 5862 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 8353 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 10675 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 12511 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 13693 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 14394 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 15002 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 15530 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 16080 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 16988 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 16432 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 15907 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 15871 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 16756 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 10206 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 3495 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 1016 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 632 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 462 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 337 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 300 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 230 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 585 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 217832 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 238.215138 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 188.366987 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 172.557799 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 37638 17.28% 17.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 92585 42.50% 59.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45398 20.84% 80.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 21076 9.68% 90.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10973 5.04% 95.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 5549 2.55% 97.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 2719 1.25% 99.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1199 0.55% 99.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 695 0.32% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 217832 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13655 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 43.367704 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 31.670415 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 25.872524 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-15 3074 22.51% 22.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-31 1792 13.12% 35.64% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-47 2254 16.51% 52.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-63 2805 20.54% 72.68% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-79 2763 20.23% 92.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-95 909 6.66% 99.58% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-111 55 0.40% 99.98% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::112-127 2 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::256-271 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13609 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13609 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.011683 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.009721 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.292863 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13571 99.72% 99.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 11 0.08% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 8 0.06% 99.86% # Writes before turning the bus around for reads +system.mem_ctrls.rdPerTurnAround::total 13655 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13655 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.008349 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.007193 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.215662 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13627 99.79% 99.79% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 6 0.04% 99.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 0.02% 99.86% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::19 5 0.04% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 3 0.02% 99.92% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 2 0.01% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 1 0.01% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 2 0.01% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 3 0.02% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 2 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13609 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 76204752 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 87439471 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 2956505 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 128.88 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::20 2 0.01% 99.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 4 0.03% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 1 0.01% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 4 0.03% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13655 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 74136636 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 85388721 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 2961075 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 125.18 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 147.87 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 7947.29 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 2928.69 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 8158.60 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 2968.52 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 144.18 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 8033.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 2965.41 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 8243.76 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 3005.36 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 84.97 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 62.09 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 22.88 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 19.97 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 50.51 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 383126 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 211448 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 64.79 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.02 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 5.75 # Average gap between requests -system.mem_ctrls.pageHitRate 73.47 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 158860 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 4598696 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1621105920 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 900614400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7372759680 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2257061760 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 310730160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 310730160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 3241151100 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 102809304 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 11416800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 2764348200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 15714839820 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 3177887664 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 3303.134998 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.966844 # Core power per rank (mW) +system.mem_ctrls.busUtil 85.93 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 62.76 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 23.17 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 19.65 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 50.35 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 380729 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 212242 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 64.29 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.07 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 5.69 # Average gap between requests +system.mem_ctrls.pageHitRate 73.13 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1644443640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 913579800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7379698560 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2262898944 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 307678800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3210618024 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10162200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 15729079968 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 3338.923999 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 157300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4553526 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 307678800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 101799720 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2737167600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3146646120 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.967681 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 4553490 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 157300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 98877 # number of read accesses completed +system.cpu0.num_writes 55675 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 99785 # number of read accesses completed +system.cpu1.num_writes 55900 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99496 # number of read accesses completed +system.cpu2.num_writes 55477 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 98960 # number of read accesses completed +system.cpu3.num_writes 55077 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 99813 # number of read accesses completed +system.cpu4.num_writes 56095 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99616 # number of read accesses completed +system.cpu5.num_writes 55503 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 98898 # number of read accesses completed +system.cpu6.num_writes 55431 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 55483 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 628111 -system.ruby.outstanding_req_hist::mean 15.998456 -system.ruby.outstanding_req_hist::gmean 15.997194 -system.ruby.outstanding_req_hist::stdev 0.125726 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 26 0.00% 0.02% | 627981 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 628111 +system.ruby.outstanding_req_hist::samples 628930 +system.ruby.outstanding_req_hist::mean 15.998458 +system.ruby.outstanding_req_hist::gmean 15.997198 +system.ruby.outstanding_req_hist::stdev 0.125644 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 26 0.00% 0.02% | 628800 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 628930 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 627983 -system.ruby.latency_hist::mean 970.449089 -system.ruby.latency_hist::gmean 693.046339 -system.ruby.latency_hist::stdev 679.084515 -system.ruby.latency_hist | 234051 37.27% 37.27% | 116033 18.48% 55.75% | 114404 18.22% 73.97% | 122030 19.43% 93.40% | 38244 6.09% 99.49% | 3110 0.50% 99.98% | 106 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 627983 +system.ruby.latency_hist::samples 628802 +system.ruby.latency_hist::mean 960.194053 +system.ruby.latency_hist::gmean 685.947832 +system.ruby.latency_hist::stdev 670.704695 +system.ruby.latency_hist | 235493 37.45% 37.45% | 115985 18.45% 55.90% | 117829 18.74% 74.64% | 122332 19.45% 94.09% | 34636 5.51% 99.60% | 2468 0.39% 99.99% | 59 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 628802 system.ruby.hit_latency_hist::bucket_size 128 system.ruby.hit_latency_hist::max_bucket 1279 -system.ruby.hit_latency_hist::samples 674 -system.ruby.hit_latency_hist::mean 113.305638 -system.ruby.hit_latency_hist::gmean 38.452852 -system.ruby.hit_latency_hist::stdev 152.633110 -system.ruby.hit_latency_hist | 461 68.40% 68.40% | 126 18.69% 87.09% | 48 7.12% 94.21% | 22 3.26% 97.48% | 8 1.19% 98.66% | 3 0.45% 99.11% | 3 0.45% 99.55% | 0 0.00% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% -system.ruby.hit_latency_hist::total 674 +system.ruby.hit_latency_hist::samples 688 +system.ruby.hit_latency_hist::mean 97.577035 +system.ruby.hit_latency_hist::gmean 32.486686 +system.ruby.hit_latency_hist::stdev 126.810521 +system.ruby.hit_latency_hist | 485 70.49% 70.49% | 131 19.04% 89.53% | 50 7.27% 96.80% | 10 1.45% 98.26% | 5 0.73% 98.98% | 4 0.58% 99.56% | 3 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 688 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 627309 -system.ruby.miss_latency_hist::mean 971.370030 -system.ruby.miss_latency_hist::gmean 695.202908 -system.ruby.miss_latency_hist::stdev 678.849054 -system.ruby.miss_latency_hist | 233394 37.21% 37.21% | 116019 18.49% 55.70% | 114401 18.24% 73.94% | 122030 19.45% 93.39% | 38244 6.10% 99.49% | 3110 0.50% 99.98% | 106 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 627309 -system.ruby.L1Cache.incomplete_times 991 -system.ruby.Directory.incomplete_times 155619 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78343 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78360 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.L2cache.demand_hits 72 # Number of cache demand hits -system.ruby.l1_cntrl4.L2cache.demand_misses 78271 # Number of cache demand misses -system.ruby.l1_cntrl4.L2cache.demand_accesses 78343 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl5.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78394 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78406 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l1_cntrl5.L2cache.demand_misses 78330 # Number of cache demand misses -system.ruby.l1_cntrl5.L2cache.demand_accesses 78394 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78610 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78627 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L2cache.demand_hits 68 # Number of cache demand hits -system.ruby.l1_cntrl6.L2cache.demand_misses 78542 # Number of cache demand misses -system.ruby.l1_cntrl6.L2cache.demand_accesses 78610 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78278 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78292 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L2cache.demand_hits 56 # Number of cache demand hits -system.ruby.l1_cntrl7.L2cache.demand_misses 78222 # Number of cache demand misses -system.ruby.l1_cntrl7.L2cache.demand_accesses 78278 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78739 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78753 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 628114 +system.ruby.miss_latency_hist::mean 961.138914 +system.ruby.miss_latency_hist::gmean 688.243254 +system.ruby.miss_latency_hist::stdev 670.450585 +system.ruby.miss_latency_hist | 234817 37.38% 37.38% | 115973 18.46% 55.85% | 117829 18.76% 74.61% | 122332 19.48% 94.08% | 34636 5.51% 99.60% | 2468 0.39% 99.99% | 59 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 628114 +system.ruby.L1Cache.incomplete_times 1076 +system.ruby.Directory.incomplete_times 174126 +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78377 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78396 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 78659 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 78739 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 15.611459 -system.ruby.network.routers0.msg_count.Request_Control::2 78659 -system.ruby.network.routers0.msg_count.Request_Control::3 126 -system.ruby.network.routers0.msg_count.Response_Data::4 81155 -system.ruby.network.routers0.msg_count.Response_Control::4 1092655 -system.ruby.network.routers0.msg_count.Writeback_Data::5 27808 -system.ruby.network.routers0.msg_count.Writeback_Control::2 74263 -system.ruby.network.routers0.msg_count.Writeback_Control::3 74259 -system.ruby.network.routers0.msg_count.Writeback_Control::5 46285 -system.ruby.network.routers0.msg_count.Broadcast_Control::3 547799 -system.ruby.network.routers0.msg_count.Unblock_Control::5 78821 -system.ruby.network.routers0.msg_bytes.Request_Control::2 629272 -system.ruby.network.routers0.msg_bytes.Request_Control::3 1008 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5843160 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8741240 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 2002176 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 594104 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 594072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 370280 -system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4382392 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 630568 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78406 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78420 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 65 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 78312 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 78377 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78839 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78851 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L2cache.demand_hits 79 # Number of cache demand hits -system.ruby.l1_cntrl1.L2cache.demand_misses 78327 # Number of cache demand misses -system.ruby.l1_cntrl1.L2cache.demand_accesses 78406 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 15.566439 -system.ruby.network.routers1.msg_count.Request_Control::2 78327 -system.ruby.network.routers1.msg_count.Request_Control::3 117 -system.ruby.network.routers1.msg_count.Response_Data::4 80869 -system.ruby.network.routers1.msg_count.Response_Control::4 1090742 -system.ruby.network.routers1.msg_count.Writeback_Data::5 27485 -system.ruby.network.routers1.msg_count.Writeback_Control::2 73881 -system.ruby.network.routers1.msg_count.Writeback_Control::3 73878 -system.ruby.network.routers1.msg_count.Writeback_Control::5 46209 -system.ruby.network.routers1.msg_count.Broadcast_Control::3 548111 -system.ruby.network.routers1.msg_count.Unblock_Control::5 78508 -system.ruby.network.routers1.msg_bytes.Request_Control::2 626616 -system.ruby.network.routers1.msg_bytes.Request_Control::3 936 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5822568 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8725936 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 1978920 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 591048 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 591024 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 369672 -system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4384888 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 628064 -system.ruby.l1_cntrl2.L1Dcache.demand_hits 18 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78504 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78522 # Number of cache demand accesses +system.ruby.l1_cntrl1.L2cache.demand_hits 60 # Number of cache demand hits +system.ruby.l1_cntrl1.L2cache.demand_misses 78779 # Number of cache demand misses +system.ruby.l1_cntrl1.L2cache.demand_accesses 78839 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78721 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78741 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L2cache.demand_hits 59 # Number of cache demand hits -system.ruby.l1_cntrl2.L2cache.demand_misses 78445 # Number of cache demand misses -system.ruby.l1_cntrl2.L2cache.demand_accesses 78504 # Number of cache demand accesses -system.ruby.network.routers2.percent_links_utilized 15.582589 -system.ruby.network.routers2.msg_count.Request_Control::2 78445 -system.ruby.network.routers2.msg_count.Request_Control::3 123 -system.ruby.network.routers2.msg_count.Response_Data::4 80995 -system.ruby.network.routers2.msg_count.Response_Control::4 1091483 -system.ruby.network.routers2.msg_count.Writeback_Data::5 27579 -system.ruby.network.routers2.msg_count.Writeback_Control::2 73989 -system.ruby.network.routers2.msg_count.Writeback_Control::3 73986 -system.ruby.network.routers2.msg_count.Writeback_Control::5 46222 -system.ruby.network.routers2.msg_count.Broadcast_Control::3 547994 -system.ruby.network.routers2.msg_count.Unblock_Control::5 78627 -system.ruby.network.routers2.msg_bytes.Request_Control::2 627560 -system.ruby.network.routers2.msg_bytes.Request_Control::3 984 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5831640 -system.ruby.network.routers2.msg_bytes.Response_Control::4 8731864 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 1985688 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 591912 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 591888 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 369776 -system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4383952 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 629016 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78610 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78627 # Number of cache demand accesses +system.ruby.l1_cntrl2.L2cache.demand_hits 62 # Number of cache demand hits +system.ruby.l1_cntrl2.L2cache.demand_misses 78659 # Number of cache demand misses +system.ruby.l1_cntrl2.L2cache.demand_accesses 78721 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78291 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78311 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L2cache.demand_hits 73 # Number of cache demand hits -system.ruby.l1_cntrl3.L2cache.demand_misses 78537 # Number of cache demand misses -system.ruby.l1_cntrl3.L2cache.demand_accesses 78610 # Number of cache demand accesses -system.ruby.network.routers3.percent_links_utilized 15.594811 -system.ruby.network.routers3.msg_count.Request_Control::2 78537 -system.ruby.network.routers3.msg_count.Request_Control::3 103 -system.ruby.network.routers3.msg_count.Response_Data::4 81093 -system.ruby.network.routers3.msg_count.Response_Control::4 1091782 -system.ruby.network.routers3.msg_count.Writeback_Data::5 27685 -system.ruby.network.routers3.msg_count.Writeback_Control::2 74059 -system.ruby.network.routers3.msg_count.Writeback_Control::3 74056 -system.ruby.network.routers3.msg_count.Writeback_Control::5 46186 -system.ruby.network.routers3.msg_count.Broadcast_Control::3 547920 -system.ruby.network.routers3.msg_count.Unblock_Control::5 78718 -system.ruby.network.routers3.msg_bytes.Request_Control::2 628296 -system.ruby.network.routers3.msg_bytes.Request_Control::3 824 -system.ruby.network.routers3.msg_bytes.Response_Data::4 5838696 -system.ruby.network.routers3.msg_bytes.Response_Control::4 8734256 -system.ruby.network.routers3.msg_bytes.Writeback_Data::5 1993320 -system.ruby.network.routers3.msg_bytes.Writeback_Control::2 592472 -system.ruby.network.routers3.msg_bytes.Writeback_Control::3 592448 -system.ruby.network.routers3.msg_bytes.Writeback_Control::5 369488 -system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4383360 -system.ruby.network.routers3.msg_bytes.Unblock_Control::5 629744 -system.ruby.network.routers4.percent_links_utilized 15.571973 -system.ruby.network.routers4.msg_count.Request_Control::2 78271 -system.ruby.network.routers4.msg_count.Request_Control::3 145 -system.ruby.network.routers4.msg_count.Response_Data::4 80771 -system.ruby.network.routers4.msg_count.Response_Control::4 1090522 -system.ruby.network.routers4.msg_count.Writeback_Data::5 27786 -system.ruby.network.routers4.msg_count.Writeback_Control::2 73811 -system.ruby.network.routers4.msg_count.Writeback_Control::3 73807 -system.ruby.network.routers4.msg_count.Writeback_Control::5 45834 -system.ruby.network.routers4.msg_count.Broadcast_Control::3 548156 -system.ruby.network.routers4.msg_count.Unblock_Control::5 78454 -system.ruby.network.routers4.msg_bytes.Request_Control::2 626168 -system.ruby.network.routers4.msg_bytes.Request_Control::3 1160 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5815512 -system.ruby.network.routers4.msg_bytes.Response_Control::4 8724176 -system.ruby.network.routers4.msg_bytes.Writeback_Data::5 2000592 -system.ruby.network.routers4.msg_bytes.Writeback_Control::2 590488 -system.ruby.network.routers4.msg_bytes.Writeback_Control::3 590456 -system.ruby.network.routers4.msg_bytes.Writeback_Control::5 366672 -system.ruby.network.routers4.msg_bytes.Broadcast_Control::3 4385248 -system.ruby.network.routers4.msg_bytes.Unblock_Control::5 627632 -system.ruby.network.routers5.percent_links_utilized 15.557021 -system.ruby.network.routers5.msg_count.Request_Control::2 78330 -system.ruby.network.routers5.msg_count.Request_Control::3 113 -system.ruby.network.routers5.msg_count.Response_Data::4 80870 -system.ruby.network.routers5.msg_count.Response_Control::4 1090637 -system.ruby.network.routers5.msg_count.Writeback_Data::5 27326 -system.ruby.network.routers5.msg_count.Writeback_Control::2 73739 -system.ruby.network.routers5.msg_count.Writeback_Control::3 73737 -system.ruby.network.routers5.msg_count.Writeback_Control::5 46227 -system.ruby.network.routers5.msg_count.Broadcast_Control::3 548107 -system.ruby.network.routers5.msg_count.Unblock_Control::5 78511 -system.ruby.network.routers5.msg_bytes.Request_Control::2 626640 -system.ruby.network.routers5.msg_bytes.Request_Control::3 904 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5822640 -system.ruby.network.routers5.msg_bytes.Response_Control::4 8725096 -system.ruby.network.routers5.msg_bytes.Writeback_Data::5 1967472 -system.ruby.network.routers5.msg_bytes.Writeback_Control::2 589912 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 589896 -system.ruby.network.routers5.msg_bytes.Writeback_Control::5 369816 -system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4384856 -system.ruby.network.routers5.msg_bytes.Unblock_Control::5 628088 -system.ruby.network.routers6.percent_links_utilized 15.603526 -system.ruby.network.routers6.msg_count.Request_Control::2 78540 -system.ruby.network.routers6.msg_count.Request_Control::3 143 -system.ruby.network.routers6.msg_count.Response_Data::4 81105 -system.ruby.network.routers6.msg_count.Response_Control::4 1091896 -system.ruby.network.routers6.msg_count.Writeback_Data::5 27859 -system.ruby.network.routers6.msg_count.Writeback_Control::2 74064 -system.ruby.network.routers6.msg_count.Writeback_Control::3 74061 -system.ruby.network.routers6.msg_count.Writeback_Control::5 46043 -system.ruby.network.routers6.msg_count.Broadcast_Control::3 547908 -system.ruby.network.routers6.msg_count.Unblock_Control::5 78695 -system.ruby.network.routers6.msg_bytes.Request_Control::2 628320 -system.ruby.network.routers6.msg_bytes.Request_Control::3 1144 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5839560 -system.ruby.network.routers6.msg_bytes.Response_Control::4 8735168 -system.ruby.network.routers6.msg_bytes.Writeback_Data::5 2005848 -system.ruby.network.routers6.msg_bytes.Writeback_Control::2 592512 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 592488 -system.ruby.network.routers6.msg_bytes.Writeback_Control::5 368344 -system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4383264 -system.ruby.network.routers6.msg_bytes.Unblock_Control::5 629560 -system.ruby.network.routers7.percent_links_utilized 15.548248 -system.ruby.network.routers7.msg_count.Request_Control::2 78222 -system.ruby.network.routers7.msg_count.Request_Control::3 120 -system.ruby.network.routers7.msg_count.Response_Data::4 80754 -system.ruby.network.routers7.msg_count.Response_Control::4 1090091 -system.ruby.network.routers7.msg_count.Writeback_Data::5 27338 -system.ruby.network.routers7.msg_count.Writeback_Control::2 73710 -system.ruby.network.routers7.msg_count.Writeback_Control::3 73709 -system.ruby.network.routers7.msg_count.Writeback_Control::5 46180 -system.ruby.network.routers7.msg_count.Broadcast_Control::3 548224 -system.ruby.network.routers7.msg_count.Unblock_Control::5 78410 -system.ruby.network.routers7.msg_bytes.Request_Control::2 625776 -system.ruby.network.routers7.msg_bytes.Request_Control::3 960 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5814288 -system.ruby.network.routers7.msg_bytes.Response_Control::4 8720728 -system.ruby.network.routers7.msg_bytes.Writeback_Data::5 1968336 -system.ruby.network.routers7.msg_bytes.Writeback_Control::2 589680 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 589672 -system.ruby.network.routers7.msg_bytes.Writeback_Control::5 369440 -system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4385792 -system.ruby.network.routers7.msg_bytes.Unblock_Control::5 627280 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers8.percent_links_utilized 57.155007 -system.ruby.network.routers8.msg_count.Request_Control::2 627331 -system.ruby.network.routers8.msg_count.Request_Control::3 990 -system.ruby.network.routers8.msg_count.Response_Data::4 607002 -system.ruby.network.routers8.msg_count.Writeback_Data::5 220866 -system.ruby.network.routers8.msg_count.Writeback_Control::2 591516 -system.ruby.network.routers8.msg_count.Writeback_Control::3 591493 -system.ruby.network.routers8.msg_count.Writeback_Control::5 369186 -system.ruby.network.routers8.msg_count.Broadcast_Control::3 626317 -system.ruby.network.routers8.msg_count.Unblock_Control::5 628744 -system.ruby.network.routers8.msg_bytes.Request_Control::2 5018648 -system.ruby.network.routers8.msg_bytes.Request_Control::3 7920 -system.ruby.network.routers8.msg_bytes.Response_Data::4 43704144 -system.ruby.network.routers8.msg_bytes.Writeback_Data::5 15902352 -system.ruby.network.routers8.msg_bytes.Writeback_Control::2 4732128 -system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4731944 -system.ruby.network.routers8.msg_bytes.Writeback_Control::5 2953488 -system.ruby.network.routers8.msg_bytes.Broadcast_Control::3 5010536 -system.ruby.network.routers8.msg_bytes.Unblock_Control::5 5029952 -system.ruby.network.routers9.percent_links_utilized 22.391181 -system.ruby.network.routers9.msg_count.Request_Control::2 627331 -system.ruby.network.routers9.msg_count.Request_Control::3 990 -system.ruby.network.routers9.msg_count.Response_Data::4 627308 -system.ruby.network.routers9.msg_count.Response_Control::4 4364904 -system.ruby.network.routers9.msg_count.Writeback_Data::5 220866 -system.ruby.network.routers9.msg_count.Writeback_Control::2 591516 -system.ruby.network.routers9.msg_count.Writeback_Control::3 591493 -system.ruby.network.routers9.msg_count.Writeback_Control::5 369186 -system.ruby.network.routers9.msg_count.Broadcast_Control::3 4384219 -system.ruby.network.routers9.msg_count.Unblock_Control::5 628744 -system.ruby.network.routers9.msg_bytes.Request_Control::2 5018648 -system.ruby.network.routers9.msg_bytes.Request_Control::3 7920 -system.ruby.network.routers9.msg_bytes.Response_Data::4 45166176 -system.ruby.network.routers9.msg_bytes.Response_Control::4 34919232 -system.ruby.network.routers9.msg_bytes.Writeback_Data::5 15902352 -system.ruby.network.routers9.msg_bytes.Writeback_Control::2 4732128 -system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4731944 -system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2953488 -system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 35073752 -system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5029952 -system.ruby.network.msg_count.Request_Control 1884963 -system.ruby.network.msg_count.Response_Data 1881922 -system.ruby.network.msg_count.Response_Control 13094712 -system.ruby.network.msg_count.Writeback_Data 662598 -system.ruby.network.msg_count.Writeback_Control 4656585 -system.ruby.network.msg_count.Broadcast_Control 9394755 -system.ruby.network.msg_count.Unblock_Control 1886232 -system.ruby.network.msg_byte.Request_Control 15079704 -system.ruby.network.msg_byte.Response_Data 135498384 -system.ruby.network.msg_byte.Response_Control 104757696 -system.ruby.network.msg_byte.Writeback_Data 47707056 -system.ruby.network.msg_byte.Writeback_Control 37252680 -system.ruby.network.msg_byte.Broadcast_Control 75158040 -system.ruby.network.msg_byte.Unblock_Control 15089856 +system.ruby.l1_cntrl3.L2cache.demand_hits 68 # Number of cache demand hits +system.ruby.l1_cntrl3.L2cache.demand_misses 78223 # Number of cache demand misses +system.ruby.l1_cntrl3.L2cache.demand_accesses 78291 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Dcache.demand_hits 28 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78804 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78832 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl4.L2cache.demand_hits 69 # Number of cache demand hits +system.ruby.l1_cntrl4.L2cache.demand_misses 78735 # Number of cache demand misses +system.ruby.l1_cntrl4.L2cache.demand_accesses 78804 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78597 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78614 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.L2cache.demand_hits 61 # Number of cache demand hits +system.ruby.l1_cntrl5.L2cache.demand_misses 78536 # Number of cache demand misses +system.ruby.l1_cntrl5.L2cache.demand_accesses 78597 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 14 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78489 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78503 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.L2cache.demand_hits 82 # Number of cache demand hits +system.ruby.l1_cntrl6.L2cache.demand_misses 78407 # Number of cache demand misses +system.ruby.l1_cntrl6.L2cache.demand_accesses 78489 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 15 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78561 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78576 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.L2cache.demand_hits 76 # Number of cache demand hits +system.ruby.l1_cntrl7.L2cache.demand_misses 78485 # Number of cache demand misses +system.ruby.l1_cntrl7.L2cache.demand_accesses 78561 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 99219 # number of read accesses completed -system.cpu0.num_writes 55551 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99783 # number of read accesses completed -system.cpu1.num_writes 55285 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98991 # number of read accesses completed -system.cpu2.num_writes 55373 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99031 # number of read accesses completed -system.cpu3.num_writes 55449 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98792 # number of read accesses completed -system.cpu4.num_writes 55139 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99529 # number of read accesses completed -system.cpu5.num_writes 55264 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 55596 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98769 # number of read accesses completed -system.cpu7.num_writes 55429 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers0.throttle0.link_utilization 19.712173 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 126 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78654 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 547231 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 74259 -system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3 547799 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3 1008 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5663088 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 4377848 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 594072 -system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3 4382392 -system.ruby.network.routers0.throttle1.link_utilization 11.510746 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 78659 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 2501 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::4 545424 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 27808 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 74263 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 46285 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 78821 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 629272 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 180072 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::4 4363392 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 2002176 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 594104 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 370280 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 630568 -system.ruby.network.routers1.throttle0.link_utilization 19.657361 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::3 117 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78324 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::4 545059 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 73878 -system.ruby.network.routers1.throttle0.msg_count.Broadcast_Control::3 548111 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::3 936 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5639328 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::4 4360472 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 591024 -system.ruby.network.routers1.throttle0.msg_bytes.Broadcast_Control::3 4384888 -system.ruby.network.routers1.throttle1.link_utilization 11.475517 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 78327 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 2545 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 545683 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::5 27485 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 73881 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::5 46209 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::5 78508 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 626616 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 183240 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 4365464 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::5 1978920 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 591048 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::5 369672 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::5 628064 -system.ruby.network.routers2.throttle0.link_utilization 19.677511 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::3 123 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78442 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::4 545919 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 73986 -system.ruby.network.routers2.throttle0.msg_count.Broadcast_Control::3 547994 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::3 984 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5647824 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::4 4367352 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 591888 -system.ruby.network.routers2.throttle0.msg_bytes.Broadcast_Control::3 4383952 -system.ruby.network.routers2.throttle1.link_utilization 11.487666 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 78445 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 2553 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::4 545564 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 27579 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 73989 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 46222 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 78627 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 627560 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 183816 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4 4364512 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 1985688 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 591912 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 369776 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 629016 -system.ruby.network.routers3.throttle0.link_utilization 19.690143 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::3 103 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78534 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 546318 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 74056 -system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3 547920 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3 824 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5654448 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 4370544 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 592448 -system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3 4383360 -system.ruby.network.routers3.throttle1.link_utilization 11.499479 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::2 78537 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 2559 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::4 545464 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5 27685 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2 74059 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5 46186 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5 78718 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2 628296 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 184248 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4 4363712 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5 1993320 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2 592472 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5 369488 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5 629744 -system.ruby.network.routers4.throttle0.link_utilization 19.648489 -system.ruby.network.routers4.throttle0.msg_count.Request_Control::3 145 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78267 -system.ruby.network.routers4.throttle0.msg_count.Response_Control::4 544725 -system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 73807 -system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3 548156 -system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3 1160 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5635224 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4 4357800 -system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 590456 -system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3 4385248 -system.ruby.network.routers4.throttle1.link_utilization 11.495457 -system.ruby.network.routers4.throttle1.msg_count.Request_Control::2 78271 -system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 2504 -system.ruby.network.routers4.throttle1.msg_count.Response_Control::4 545797 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5 27786 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2 73811 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5 45834 -system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5 78454 -system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2 626168 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 180288 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4 4366376 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5 2000592 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2 590488 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5 366672 -system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5 627632 -system.ruby.network.routers5.throttle0.link_utilization 19.655041 -system.ruby.network.routers5.throttle0.msg_count.Request_Control::3 113 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78327 -system.ruby.network.routers5.throttle0.msg_count.Response_Control::4 544960 -system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 73737 -system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3 548107 -system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3 904 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5639544 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4 4359680 -system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 589896 -system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3 4384856 -system.ruby.network.routers5.throttle1.link_utilization 11.459000 -system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 78330 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 2543 -system.ruby.network.routers5.throttle1.msg_count.Response_Control::4 545677 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5 27326 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2 73739 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5 46227 -system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5 78511 -system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 626640 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 183096 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4 4365416 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5 1967472 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 589912 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 369816 -system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 628088 -system.ruby.network.routers6.throttle0.link_utilization 19.691907 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 143 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78539 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 546411 -system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 74061 -system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 547908 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 1144 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5654808 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4371288 -system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 592488 -system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4383264 -system.ruby.network.routers6.throttle1.link_utilization 11.515145 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 78540 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 2566 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::4 545485 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5 27859 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2 74064 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::5 46043 -system.ruby.network.routers6.throttle1.msg_count.Unblock_Control::5 78695 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 628320 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 184752 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::4 4363880 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Data::5 2005848 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::2 592512 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::5 368344 -system.ruby.network.routers6.throttle1.msg_bytes.Unblock_Control::5 629560 -system.ruby.network.routers7.throttle0.link_utilization 19.638807 -system.ruby.network.routers7.throttle0.msg_count.Request_Control::3 120 -system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78220 -system.ruby.network.routers7.throttle0.msg_count.Response_Control::4 544281 -system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 73709 -system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 548224 -system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 960 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5631840 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4354248 -system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 589672 -system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4385792 -system.ruby.network.routers7.throttle1.link_utilization 11.457688 -system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 78222 -system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 2534 -system.ruby.network.routers7.throttle1.msg_count.Response_Control::4 545810 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5 27338 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2 73710 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::5 46180 -system.ruby.network.routers7.throttle1.msg_count.Unblock_Control::5 78410 -system.ruby.network.routers7.throttle1.msg_bytes.Request_Control::2 625776 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 182448 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Control::4 4366480 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Data::5 1968336 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::2 589680 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::5 369440 -system.ruby.network.routers7.throttle1.msg_bytes.Unblock_Control::5 627280 -system.ruby.network.routers8.throttle0.link_utilization 44.149143 -system.ruby.network.routers8.throttle0.msg_count.Request_Control::2 627331 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Data::5 220866 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2 591516 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5 369186 -system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5 628744 -system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2 5018648 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5 15902352 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2 4732128 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5 2953488 -system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5 5029952 -system.ruby.network.routers8.throttle1.link_utilization 70.160870 -system.ruby.network.routers8.throttle1.msg_count.Request_Control::3 990 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 607002 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 591493 -system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3 626317 -system.ruby.network.routers8.throttle1.msg_bytes.Request_Control::3 7920 -system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43704144 -system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4731944 -system.ruby.network.routers8.throttle1.msg_bytes.Broadcast_Control::3 5010536 -system.ruby.network.routers9.throttle0.link_utilization 19.712173 -system.ruby.network.routers9.throttle0.msg_count.Request_Control::3 126 -system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78654 -system.ruby.network.routers9.throttle0.msg_count.Response_Control::4 547231 -system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 74259 -system.ruby.network.routers9.throttle0.msg_count.Broadcast_Control::3 547799 -system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3 1008 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5663088 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4 4377848 -system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 594072 -system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4382392 -system.ruby.network.routers9.throttle1.link_utilization 19.657361 -system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 117 -system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78324 -system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 545059 -system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 73878 -system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 548111 -system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 936 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5639328 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4 4360472 -system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 591024 -system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4384888 -system.ruby.network.routers9.throttle2.link_utilization 19.677511 -system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 123 -system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78442 -system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 545919 -system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 73986 -system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 547994 -system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 984 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5647824 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4367352 -system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 591888 -system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4383952 -system.ruby.network.routers9.throttle3.link_utilization 19.690143 -system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 103 -system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78534 -system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 546318 -system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 74056 -system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 547920 -system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 824 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5654448 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4370544 -system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 592448 -system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4383360 -system.ruby.network.routers9.throttle4.link_utilization 19.648489 -system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 145 -system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78267 -system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 544725 -system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 73807 -system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 548156 -system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 1160 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5635224 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4357800 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 590456 -system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4385248 -system.ruby.network.routers9.throttle5.link_utilization 19.655041 -system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 113 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78327 -system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 544960 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 73737 -system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 548107 -system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 904 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5639544 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4359680 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 589896 -system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4384856 -system.ruby.network.routers9.throttle6.link_utilization 19.691939 -system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 143 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78539 -system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 546411 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 74061 -system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 547908 -system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 1144 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5654808 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4371288 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 592488 -system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4383264 -system.ruby.network.routers9.throttle7.link_utilization 19.638828 -system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 120 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78221 -system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 544281 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 73709 -system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 548224 -system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 960 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5631912 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4354248 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 589672 -system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4385792 -system.ruby.network.routers9.throttle8.link_utilization 44.149143 -system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 627331 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 220866 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 591516 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 369186 -system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 628744 -system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5018648 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15902352 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4732128 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2953488 -system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5029952 +system.ruby.network.routers0.percent_links_utilized 15.728579 +system.ruby.network.routers0.msg_count.Request_Control::2 78312 +system.ruby.network.routers0.msg_count.Request_Control::3 136 +system.ruby.network.routers0.msg_count.Response_Data::4 80809 +system.ruby.network.routers0.msg_count.Response_Control::4 1091306 +system.ruby.network.routers0.msg_count.Writeback_Data::5 27751 +system.ruby.network.routers0.msg_count.Writeback_Control::2 73970 +system.ruby.network.routers0.msg_count.Writeback_Control::3 73966 +system.ruby.network.routers0.msg_count.Writeback_Control::5 46017 +system.ruby.network.routers0.msg_count.Broadcast_Control::3 548880 +system.ruby.network.routers0.msg_count.Unblock_Control::5 78505 +system.ruby.network.routers0.msg_bytes.Request_Control::2 626496 +system.ruby.network.routers0.msg_bytes.Request_Control::3 1088 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5818248 +system.ruby.network.routers0.msg_bytes.Response_Control::4 8730448 +system.ruby.network.routers0.msg_bytes.Writeback_Data::5 1998072 +system.ruby.network.routers0.msg_bytes.Writeback_Control::2 591760 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 591728 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 368136 +system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4391040 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 628040 +system.ruby.network.routers1.percent_links_utilized 15.782026 +system.ruby.network.routers1.msg_count.Request_Control::2 78779 +system.ruby.network.routers1.msg_count.Request_Control::3 148 +system.ruby.network.routers1.msg_count.Response_Data::4 81395 +system.ruby.network.routers1.msg_count.Response_Control::4 1094135 +system.ruby.network.routers1.msg_count.Writeback_Data::5 27827 +system.ruby.network.routers1.msg_count.Writeback_Control::2 74272 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+system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5036712 +system.ruby.network.msg_count.Request_Control 1887621 +system.ruby.network.msg_count.Response_Data 1884334 +system.ruby.network.msg_count.Response_Control 13110005 +system.ruby.network.msg_count.Writeback_Data 664618 +system.ruby.network.msg_count.Writeback_Control 4663647 +system.ruby.network.msg_count.Broadcast_Control 9405818 +system.ruby.network.msg_count.Unblock_Control 1888767 +system.ruby.network.msg_byte.Request_Control 15100968 +system.ruby.network.msg_byte.Response_Data 135672048 +system.ruby.network.msg_byte.Response_Control 104880040 +system.ruby.network.msg_byte.Writeback_Data 47852496 +system.ruby.network.msg_byte.Writeback_Control 37309176 +system.ruby.network.msg_byte.Broadcast_Control 75246544 +system.ruby.network.msg_byte.Unblock_Control 15110136 +system.ruby.network.routers0.throttle0.link_utilization 19.845723 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 136 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78307 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 544793 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 73966 +system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3 548880 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3 1088 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5638104 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 4358344 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 591728 +system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3 4391040 +system.ruby.network.routers0.throttle1.link_utilization 11.611436 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 78312 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 2502 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::4 546513 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+system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 27922 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 74193 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 46097 +system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 78830 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 629272 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 181224 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4 4369136 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 2010384 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 593544 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 368776 +system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 630640 +system.ruby.network.routers3.throttle0.link_utilization 19.829857 +system.ruby.network.routers3.throttle0.msg_count.Request_Control::3 132 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78220 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 544159 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 73799 +system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3 548971 +system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3 1056 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5631840 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 4353272 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 590392 +system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3 4391768 +system.ruby.network.routers3.throttle1.link_utilization 11.578083 +system.ruby.network.routers3.throttle1.msg_count.Request_Control::2 78223 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 2612 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::4 546490 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5 27301 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2 73799 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5 46306 +system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5 78412 +system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2 625784 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 188064 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4 4371920 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5 1965672 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2 590392 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5 370448 +system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5 627296 +system.ruby.network.routers4.throttle0.link_utilization 19.915438 +system.ruby.network.routers4.throttle0.msg_count.Request_Control::3 123 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78733 +system.ruby.network.routers4.throttle0.msg_count.Response_Control::4 547692 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 74240 +system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3 548464 +system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3 984 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5668776 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4 4381536 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 593920 +system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3 4387712 +system.ruby.network.routers4.throttle1.link_utilization 11.642256 +system.ruby.network.routers4.throttle1.msg_count.Request_Control::2 78735 +system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 2548 +system.ruby.network.routers4.throttle1.msg_count.Response_Control::4 546038 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5 27948 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2 74240 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5 46087 +system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5 78938 +system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2 629880 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 183456 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4 4368304 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5 2012256 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2 593920 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5 368696 +system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5 631504 +system.ruby.network.routers5.throttle0.link_utilization 19.881142 +system.ruby.network.routers5.throttle0.msg_count.Request_Control::3 138 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78533 +system.ruby.network.routers5.throttle0.msg_count.Response_Control::4 546290 +system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 73997 +system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3 548658 +system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3 1104 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5654376 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4 4370320 +system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 591976 +system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3 4389264 +system.ruby.network.routers5.throttle1.link_utilization 11.606603 +system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 78536 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 2528 +system.ruby.network.routers5.throttle1.msg_count.Response_Control::4 546267 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5 27632 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2 73998 +system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5 46175 +system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5 78722 +system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 628288 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 182016 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4 4370136 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5 1989504 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 591984 +system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 369400 +system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 629776 +system.ruby.network.routers6.throttle0.link_utilization 19.862383 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 131 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78404 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 545570 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 73995 +system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 548778 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 1048 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5645088 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4364560 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 591960 +system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4390224 +system.ruby.network.routers6.throttle1.link_utilization 11.604017 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 78407 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 2548 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::4 546361 +system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5 27600 +system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2 73996 +system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::5 46241 +system.ruby.network.routers6.throttle1.msg_count.Unblock_Control::5 78557 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 627256 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 183456 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::4 4370888 +system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Data::5 1987200 +system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::2 591968 +system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::5 369928 +system.ruby.network.routers6.throttle1.msg_bytes.Unblock_Control::5 628456 +system.ruby.network.routers7.throttle0.link_utilization 19.874720 +system.ruby.network.routers7.throttle0.msg_count.Request_Control::3 139 +system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78483 +system.ruby.network.routers7.throttle0.msg_count.Response_Control::4 546031 +system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 74059 +system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 548701 +system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 1112 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5650776 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4368248 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 592472 +system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4389608 +system.ruby.network.routers7.throttle1.link_utilization 11.604494 +system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 78484 +system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 2568 +system.ruby.network.routers7.throttle1.msg_count.Response_Control::4 546271 +system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5 27559 +system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2 74059 +system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::5 46308 +system.ruby.network.routers7.throttle1.msg_count.Unblock_Control::5 78674 +system.ruby.network.routers7.throttle1.msg_bytes.Request_Control::2 627872 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 184896 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Control::4 4370168 +system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Data::5 1984248 +system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::2 592472 +system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::5 370464 +system.ruby.network.routers7.throttle1.msg_bytes.Unblock_Control::5 629392 +system.ruby.network.routers8.throttle0.link_utilization 44.657004 +system.ruby.network.routers8.throttle0.msg_count.Request_Control::2 628133 +system.ruby.network.routers8.throttle0.msg_count.Writeback_Data::5 221539 +system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2 592525 +system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5 369502 +system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5 629589 +system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2 5025064 +system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5 15950808 +system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2 4740200 +system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5 2956016 +system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5 5036712 +system.ruby.network.routers8.throttle1.link_utilization 70.898992 +system.ruby.network.routers8.throttle1.msg_count.Request_Control::3 1073 +system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 607668 +system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 592521 +system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3 627055 +system.ruby.network.routers8.throttle1.msg_bytes.Request_Control::3 8584 +system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43752096 +system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4740168 +system.ruby.network.routers8.throttle1.msg_bytes.Broadcast_Control::3 5016440 +system.ruby.network.routers9.throttle0.link_utilization 19.845733 +system.ruby.network.routers9.throttle0.msg_count.Request_Control::3 136 +system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78307 +system.ruby.network.routers9.throttle0.msg_count.Response_Control::4 544793 +system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 73966 +system.ruby.network.routers9.throttle0.msg_count.Broadcast_Control::3 548881 +system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3 1088 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5638104 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4 4358344 +system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 591728 +system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4391048 +system.ruby.network.routers9.throttle1.link_utilization 19.924934 +system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 148 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78776 +system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 548215 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 74272 +system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 548393 +system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 1184 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5671872 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4 4385720 +system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 594176 +system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4387144 +system.ruby.network.routers9.throttle2.link_utilization 19.903717 +system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 126 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78656 +system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 547252 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 74193 +system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 548535 +system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 1008 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5663232 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4378016 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 593544 +system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4388280 +system.ruby.network.routers9.throttle3.link_utilization 19.829868 +system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 132 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78220 +system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 544159 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 73799 +system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 548972 +system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 1056 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5631840 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4353272 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 590392 +system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4391776 +system.ruby.network.routers9.throttle4.link_utilization 19.915449 +system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 123 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78733 +system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 547692 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 74240 +system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 548465 +system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 984 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5668776 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4381536 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 593920 +system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4387720 +system.ruby.network.routers9.throttle5.link_utilization 19.881153 +system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 138 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78533 +system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 546290 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 73997 +system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 548659 +system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 1104 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5654376 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4370320 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 591976 +system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4389272 +system.ruby.network.routers9.throttle6.link_utilization 19.862383 +system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 131 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78404 +system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 545570 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 73995 +system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 548778 +system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 1048 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5645088 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4364560 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 591960 +system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4390224 +system.ruby.network.routers9.throttle7.link_utilization 19.874762 +system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 139 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78483 +system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 546031 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 74059 +system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 548702 +system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 1112 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5650776 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4368248 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 592472 +system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4389616 +system.ruby.network.routers9.throttle8.link_utilization 44.657025 +system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 628134 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 221539 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 592526 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 369502 +system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 629589 +system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5025072 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15950808 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4740208 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2956016 +system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5036712 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 404465 -system.ruby.LD.latency_hist::mean 970.299534 -system.ruby.LD.latency_hist::gmean 692.486480 -system.ruby.LD.latency_hist::stdev 679.694632 -system.ruby.LD.latency_hist | 150760 37.27% 37.27% | 74841 18.50% 55.78% | 73607 18.20% 73.98% | 78428 19.39% 93.37% | 24696 6.11% 99.47% | 2062 0.51% 99.98% | 68 0.02% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 404465 +system.ruby.LD.latency_hist::samples 404426 +system.ruby.LD.latency_hist::mean 960.911900 +system.ruby.LD.latency_hist::gmean 686.068526 +system.ruby.LD.latency_hist::stdev 671.376530 +system.ruby.LD.latency_hist | 151361 37.43% 37.43% | 74618 18.45% 55.88% | 75709 18.72% 74.60% | 78644 19.45% 94.04% | 22474 5.56% 99.60% | 1576 0.39% 99.99% | 44 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 404426 system.ruby.LD.hit_latency_hist::bucket_size 128 system.ruby.LD.hit_latency_hist::max_bucket 1279 -system.ruby.LD.hit_latency_hist::samples 430 -system.ruby.LD.hit_latency_hist::mean 108.311628 -system.ruby.LD.hit_latency_hist::gmean 37.444576 -system.ruby.LD.hit_latency_hist::stdev 140.737967 -system.ruby.LD.hit_latency_hist | 301 70.00% 70.00% | 77 17.91% 87.91% | 28 6.51% 94.42% | 15 3.49% 97.91% | 5 1.16% 99.07% | 2 0.47% 99.53% | 1 0.23% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 430 +system.ruby.LD.hit_latency_hist::samples 463 +system.ruby.LD.hit_latency_hist::mean 100.805616 +system.ruby.LD.hit_latency_hist::gmean 32.902089 +system.ruby.LD.hit_latency_hist::stdev 133.872383 +system.ruby.LD.hit_latency_hist | 323 69.76% 69.76% | 89 19.22% 88.98% | 32 6.91% 95.90% | 8 1.73% 97.62% | 5 1.08% 98.70% | 3 0.65% 99.35% | 3 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 463 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 404035 -system.ruby.LD.miss_latency_hist::mean 971.216917 -system.ruby.LD.miss_latency_hist::gmean 694.639931 -system.ruby.LD.miss_latency_hist::stdev 679.458476 -system.ruby.LD.miss_latency_hist | 150339 37.21% 37.21% | 74833 18.52% 55.73% | 73606 18.22% 73.95% | 78428 19.41% 93.36% | 24696 6.11% 99.47% | 2062 0.51% 99.98% | 68 0.02% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 404035 +system.ruby.LD.miss_latency_hist::samples 403963 +system.ruby.LD.miss_latency_hist::mean 961.897706 +system.ruby.LD.miss_latency_hist::gmean 688.461131 +system.ruby.LD.miss_latency_hist::stdev 671.113774 +system.ruby.LD.miss_latency_hist | 150909 37.36% 37.36% | 74607 18.47% 55.83% | 75709 18.74% 74.57% | 78644 19.47% 94.04% | 22474 5.56% 99.60% | 1576 0.39% 99.99% | 44 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 403963 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223518 -system.ruby.ST.latency_hist::mean 970.719714 -system.ruby.ST.latency_hist::gmean 694.060578 -system.ruby.ST.latency_hist::stdev 677.980523 -system.ruby.ST.latency_hist | 83291 37.26% 37.26% | 41192 18.43% 55.69% | 40797 18.25% 73.94% | 43602 19.51% 93.45% | 13548 6.06% 99.51% | 1048 0.47% 99.98% | 38 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223518 +system.ruby.ST.latency_hist::samples 224376 +system.ruby.ST.latency_hist::mean 958.900172 +system.ruby.ST.latency_hist::gmean 685.730341 +system.ruby.ST.latency_hist::stdev 669.491597 +system.ruby.ST.latency_hist | 84132 37.50% 37.50% | 41367 18.44% 55.93% | 42120 18.77% 74.70% | 43688 19.47% 94.18% | 12162 5.42% 99.60% | 892 0.40% 99.99% | 15 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 224376 system.ruby.ST.hit_latency_hist::bucket_size 128 system.ruby.ST.hit_latency_hist::max_bucket 1279 -system.ruby.ST.hit_latency_hist::samples 244 -system.ruby.ST.hit_latency_hist::mean 122.106557 -system.ruby.ST.hit_latency_hist::gmean 40.296267 -system.ruby.ST.hit_latency_hist::stdev 171.556530 -system.ruby.ST.hit_latency_hist | 160 65.57% 65.57% | 49 20.08% 85.66% | 20 8.20% 93.85% | 7 2.87% 96.72% | 3 1.23% 97.95% | 1 0.41% 98.36% | 2 0.82% 99.18% | 0 0.00% 99.18% | 1 0.41% 99.59% | 1 0.41% 100.00% -system.ruby.ST.hit_latency_hist::total 244 +system.ruby.ST.hit_latency_hist::samples 225 +system.ruby.ST.hit_latency_hist::mean 90.933333 +system.ruby.ST.hit_latency_hist::gmean 31.648307 +system.ruby.ST.hit_latency_hist::stdev 110.860031 +system.ruby.ST.hit_latency_hist | 162 72.00% 72.00% | 42 18.67% 90.67% | 18 8.00% 98.67% | 2 0.89% 99.56% | 0 0.00% 99.56% | 1 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 225 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 223274 -system.ruby.ST.miss_latency_hist::mean 971.647102 -system.ruby.ST.miss_latency_hist::gmean 696.222826 -system.ruby.ST.miss_latency_hist::stdev 677.746286 -system.ruby.ST.miss_latency_hist | 83055 37.20% 37.20% | 41186 18.45% 55.65% | 40795 18.27% 73.92% | 43602 19.53% 93.44% | 13548 6.07% 99.51% | 1048 0.47% 99.98% | 38 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223274 +system.ruby.ST.miss_latency_hist::samples 224151 +system.ruby.ST.miss_latency_hist::mean 959.771426 +system.ruby.ST.miss_latency_hist::gmean 687.850771 +system.ruby.ST.miss_latency_hist::stdev 669.253056 +system.ruby.ST.miss_latency_hist | 83908 37.43% 37.43% | 41366 18.45% 55.89% | 42120 18.79% 74.68% | 43688 19.49% 94.17% | 12162 5.43% 99.60% | 892 0.40% 99.99% | 15 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 224151 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 123 +system.ruby.L1Cache.hit_mach_latency_hist::samples 145 system.ruby.L1Cache.hit_mach_latency_hist::mean 2 system.ruby.L1Cache.hit_mach_latency_hist::gmean 2 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 123 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 123 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 145 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 145 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 22727 -system.ruby.L1Cache.miss_mach_latency_hist::mean 917.922031 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 627.174318 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 674.707077 -system.ruby.L1Cache.miss_mach_latency_hist | 9145 40.24% 40.24% | 4043 17.79% 58.03% | 4103 18.05% 76.08% | 4239 18.65% 94.73% | 1113 4.90% 99.63% | 82 0.36% 99.99% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 22727 +system.ruby.L1Cache.miss_mach_latency_hist::samples 23221 +system.ruby.L1Cache.miss_mach_latency_hist::mean 918.506481 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 632.567536 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 669.101339 +system.ruby.L1Cache.miss_mach_latency_hist | 9304 40.07% 40.07% | 4045 17.42% 57.49% | 4386 18.89% 76.37% | 4323 18.62% 94.99% | 1085 4.67% 99.66% | 76 0.33% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 23221 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 21736 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 776.334008 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 326.213645 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 670.419505 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 9839 45.27% 45.27% | 3725 17.14% 62.40% | 4328 19.91% 82.32% | 3280 15.09% 97.41% | 536 2.47% 99.87% | 26 0.12% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 21736 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 22145 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 776.302009 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 328.435965 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 665.090173 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 10009 45.20% 45.20% | 3705 16.73% 61.93% | 4615 20.84% 82.77% | 3282 14.82% 97.59% | 507 2.29% 99.88% | 27 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 22145 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::bucket_size 128 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::max_bucket 1279 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 21736 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 50.119295 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 21.370001 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 76.768610 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 18902 86.96% 86.96% | 2171 9.99% 96.95% | 544 2.50% 99.45% | 73 0.34% 99.79% | 36 0.17% 99.95% | 9 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 21736 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 22145 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 49.022940 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 20.850081 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 75.532500 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 19287 87.09% 87.09% | 2230 10.07% 97.16% | 500 2.26% 99.42% | 82 0.37% 99.79% | 36 0.16% 99.95% | 10 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 22145 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::bucket_size 32 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples 21736 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean 82.657481 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::gmean 68.643430 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 48.070946 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3869 17.80% 17.80% | 5031 23.15% 40.95% | 5327 24.51% 65.45% | 3337 15.35% 80.81% | 2295 10.56% 91.36% | 1371 6.31% 97.67% | 466 2.14% 99.82% | 38 0.17% 99.99% | 1 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 21736 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples 22145 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean 86.190969 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::gmean 71.331937 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 49.787970 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3827 17.28% 17.28% | 4742 21.41% 38.69% | 5321 24.03% 62.72% | 3379 15.26% 77.98% | 2575 11.63% 89.61% | 1714 7.74% 97.35% | 533 2.41% 99.76% | 54 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 22145 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::bucket_size 32 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 21736 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 8.922203 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 20.770663 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 19926 91.67% 91.67% | 870 4.00% 95.68% | 588 2.71% 98.38% | 282 1.30% 99.68% | 62 0.29% 99.96% | 6 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 21736 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 22145 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 10.022533 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 22.682118 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 19996 90.30% 90.30% | 982 4.43% 94.73% | 714 3.22% 97.95% | 355 1.60% 99.56% | 88 0.40% 99.95% | 8 0.04% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 22145 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 128 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 1279 -system.ruby.L2Cache.hit_mach_latency_hist::samples 551 -system.ruby.L2Cache.hit_mach_latency_hist::mean 138.152450 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 74.393307 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 158.485922 -system.ruby.L2Cache.hit_mach_latency_hist | 338 61.34% 61.34% | 126 22.87% 84.21% | 48 8.71% 92.92% | 22 3.99% 96.91% | 8 1.45% 98.37% | 3 0.54% 98.91% | 3 0.54% 99.46% | 0 0.00% 99.46% | 2 0.36% 99.82% | 1 0.18% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 551 +system.ruby.L2Cache.hit_mach_latency_hist::samples 543 +system.ruby.L2Cache.hit_mach_latency_hist::mean 123.099448 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 68.390868 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 131.478301 +system.ruby.L2Cache.hit_mach_latency_hist | 340 62.62% 62.62% | 131 24.13% 86.74% | 50 9.21% 95.95% | 10 1.84% 97.79% | 5 0.92% 98.71% | 4 0.74% 99.45% | 3 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 543 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 604582 -system.ruby.Directory.miss_mach_latency_hist::mean 973.379207 -system.ruby.Directory.miss_mach_latency_hist::gmean 697.899337 -system.ruby.Directory.miss_mach_latency_hist::stdev 678.922764 -system.ruby.Directory.miss_mach_latency_hist | 224249 37.09% 37.09% | 111976 18.52% 55.61% | 110298 18.24% 73.86% | 117791 19.48% 93.34% | 37131 6.14% 99.48% | 3028 0.50% 99.98% | 105 0.02% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 604582 +system.ruby.Directory.miss_mach_latency_hist::samples 604893 +system.ruby.Directory.miss_mach_latency_hist::mean 962.775514 +system.ruby.Directory.miss_mach_latency_hist::gmean 690.475594 +system.ruby.Directory.miss_mach_latency_hist::stdev 670.448849 +system.ruby.Directory.miss_mach_latency_hist | 225513 37.28% 37.28% | 111928 18.50% 55.79% | 113443 18.75% 74.54% | 118009 19.51% 94.05% | 33551 5.55% 99.60% | 2392 0.40% 99.99% | 57 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 604893 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 448963 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 790.361304 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 343.581530 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 668.650065 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 200571 44.67% 44.67% | 75584 16.84% 61.51% | 92688 20.64% 82.15% | 67953 15.14% 97.29% | 11576 2.58% 99.87% | 574 0.13% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 448963 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 430767 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 785.966174 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 348.017396 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 659.442663 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 192325 44.65% 44.65% | 73086 16.97% 61.61% | 91651 21.28% 82.89% | 63254 14.68% 97.57% | 10020 2.33% 99.90% | 427 0.10% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 430767 system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 64 system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 639 -system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 448963 -system.ruby.Directory.miss_latency_hist.initial_to_forward::mean 18.043888 -system.ruby.Directory.miss_latency_hist.initial_to_forward::gmean 12.652922 -system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev 20.029649 -system.ruby.Directory.miss_latency_hist.initial_to_forward | 421009 93.77% 93.77% | 27623 6.15% 99.93% | 261 0.06% 99.98% | 54 0.01% 100.00% | 7 0.00% 100.00% | 7 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.initial_to_forward::total 448963 +system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 430767 +system.ruby.Directory.miss_latency_hist.initial_to_forward::mean 18.584000 +system.ruby.Directory.miss_latency_hist.initial_to_forward::gmean 12.855732 +system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev 20.728405 +system.ruby.Directory.miss_latency_hist.initial_to_forward | 401319 93.16% 93.16% | 29107 6.76% 99.92% | 285 0.07% 99.99% | 44 0.01% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.initial_to_forward::total 430767 system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 32 system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 319 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 448963 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 60.916207 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 52.812148 -system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 32.952264 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 109386 24.36% 24.36% | 156482 34.85% 59.22% | 113962 25.38% 84.60% | 48318 10.76% 95.36% | 17372 3.87% 99.23% | 3270 0.73% 99.96% | 172 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 448963 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 430767 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 61.207381 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 52.822325 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 33.575954 +system.ruby.Directory.miss_latency_hist.forward_to_first_response | 108043 25.08% 25.08% | 144975 33.66% 58.74% | 108992 25.30% 84.04% | 47420 11.01% 95.05% | 17597 4.09% 99.13% | 3561 0.83% 99.96% | 178 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 430767 system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 128 system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 1279 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 448963 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 141.425737 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 105.102148 -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 237351 52.87% 52.87% | 156354 34.83% 87.69% | 40339 8.98% 96.68% | 9952 2.22% 98.89% | 4722 1.05% 99.95% | 244 0.05% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 448963 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 430767 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 140.424923 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 103.684319 +system.ruby.Directory.miss_latency_hist.first_response_to_completion | 231227 53.68% 53.68% | 148723 34.53% 88.20% | 36432 8.46% 96.66% | 9650 2.24% 98.90% | 4565 1.06% 99.96% | 167 0.04% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 430767 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 78 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 100 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 78 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 78 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 100 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13125 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 912.161600 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 618.732413 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 673.071954 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 5337 40.66% 40.66% | 2281 17.38% 58.04% | 2397 18.26% 76.30% | 2468 18.80% 95.11% | 597 4.55% 99.66% | 45 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13125 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13143 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 916.963250 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 626.263580 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 671.582246 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 5258 40.01% 40.01% | 2297 17.48% 57.48% | 2504 19.05% 76.54% | 2412 18.35% 94.89% | 623 4.74% 99.63% | 49 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13143 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 352 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 131.869318 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 71.669122 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 145.398186 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 223 63.35% 63.35% | 77 21.88% 85.23% | 28 7.95% 93.18% | 15 4.26% 97.44% | 5 1.42% 98.86% | 2 0.57% 99.43% | 1 0.28% 99.72% | 0 0.00% 99.72% | 1 0.28% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 352 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 363 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 128.024793 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 71.164434 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 139.401669 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 223 61.43% 61.43% | 89 24.52% 85.95% | 32 8.82% 94.77% | 8 2.20% 96.97% | 5 1.38% 98.35% | 3 0.83% 99.17% | 3 0.83% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 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+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 690.656874 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 671.046581 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 145651 37.27% 37.27% | 72310 18.50% 55.77% | 73205 18.73% 74.50% | 76232 19.51% 94.01% | 21851 5.59% 99.60% | 1527 0.39% 99.99% | 44 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 390820 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 45 @@ -1135,377 +1139,367 @@ system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 45 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 9602 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 925.795980 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 638.900214 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 676.891520 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 3808 39.66% 39.66% | 1762 18.35% 58.01% | 1706 17.77% 75.78% | 1771 18.44% 94.22% | 516 5.37% 99.59% | 37 0.39% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 9602 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10078 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 920.519051 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 640.884134 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 665.879942 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 4046 40.15% 40.15% | 1748 17.34% 57.49% | 1882 18.67% 76.17% | 1911 18.96% 95.13% | 462 4.58% 99.71% | 27 0.27% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10078 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 128 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 199 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 149.266332 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 79.468000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 179.166771 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 115 57.79% 57.79% | 49 24.62% 82.41% | 20 10.05% 92.46% | 7 3.52% 95.98% | 3 1.51% 97.49% | 1 0.50% 97.99% | 2 1.01% 98.99% | 0 0.00% 98.99% | 1 0.50% 99.50% | 1 0.50% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 199 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 180 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 113.166667 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 63.121979 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 113.552562 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 117 65.00% 65.00% | 42 23.33% 88.33% | 18 10.00% 98.33% | 2 1.11% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 180 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213672 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 973.707561 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 698.916238 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 677.713425 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 79247 37.09% 37.09% | 39424 18.45% 55.54% | 39089 18.29% 73.83% | 41831 19.58% 93.41% | 13032 6.10% 99.51% | 1011 0.47% 99.98% | 37 0.02% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213672 -system.ruby.L1Cache_Controller.Load | 50661 12.52% 12.52% | 50602 12.50% 25.02% | 50623 12.51% 37.52% | 50689 12.52% 50.05% | 50291 12.42% 62.47% | 50786 12.55% 75.02% | 50489 12.47% 87.49% | 50629 12.51% 100.00% -system.ruby.L1Cache_Controller.Load::total 404770 -system.ruby.L1Cache_Controller.Store | 28155 12.59% 12.59% | 27873 12.46% 25.05% | 27954 12.50% 37.55% | 27997 12.52% 50.06% | 28127 12.57% 62.64% | 27687 12.38% 75.01% | 28186 12.60% 87.61% | 27704 12.39% 100.00% -system.ruby.L1Cache_Controller.Store::total 223683 -system.ruby.L1Cache_Controller.L2_Replacement | 78645 12.54% 12.54% | 78315 12.49% 25.02% | 78435 12.50% 37.53% | 78525 12.52% 50.05% | 78254 12.48% 62.52% | 78318 12.49% 75.01% | 78531 12.52% 87.53% | 78210 12.47% 100.00% -system.ruby.L1Cache_Controller.L2_Replacement::total 627233 -system.ruby.L1Cache_Controller.L1_to_L2 | 963838 12.49% 12.49% | 963397 12.49% 24.98% | 965289 12.51% 37.49% | 966306 12.52% 50.01% | 963961 12.49% 62.50% | 964279 12.50% 75.00% | 965132 12.51% 87.51% | 963900 12.49% 100.00% -system.ruby.L1Cache_Controller.L1_to_L2::total 7716102 -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 83 14.64% 14.64% | 80 14.11% 28.75% | 59 10.41% 39.15% | 75 13.23% 52.38% | 78 13.76% 66.14% | 65 11.46% 77.60% | 69 12.17% 89.77% | 58 10.23% 100.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 567 -system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 83 14.64% 14.64% | 80 14.11% 28.75% | 59 10.41% 39.15% | 75 13.23% 52.38% | 78 13.76% 66.14% | 65 11.46% 77.60% | 69 12.17% 89.77% | 58 10.23% 100.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 567 -system.ruby.L1Cache_Controller.Other_GETX | 195183 12.49% 12.49% | 195457 12.51% 24.99% | 195358 12.50% 37.49% | 195331 12.50% 49.99% | 195205 12.49% 62.48% | 195645 12.52% 75.00% | 195130 12.48% 87.48% | 195609 12.52% 100.00% -system.ruby.L1Cache_Controller.Other_GETX::total 1562918 -system.ruby.L1Cache_Controller.Other_GETS | 352616 12.50% 12.50% | 352654 12.50% 25.00% | 352636 12.50% 37.50% | 352589 12.50% 49.99% | 352951 12.51% 62.50% | 352462 12.49% 75.00% | 352778 12.50% 87.50% | 352615 12.50% 100.00% -system.ruby.L1Cache_Controller.Other_GETS::total 2821301 -system.ruby.L1Cache_Controller.Merged_GETS | 126 12.73% 12.73% | 117 11.82% 24.55% | 123 12.42% 36.97% | 103 10.40% 47.37% | 145 14.65% 62.02% | 113 11.41% 73.43% | 143 14.44% 87.88% | 120 12.12% 100.00% -system.ruby.L1Cache_Controller.Merged_GETS::total 990 -system.ruby.L1Cache_Controller.Ack | 547200 12.54% 12.54% | 545018 12.49% 25.02% | 545878 12.51% 37.53% | 546264 12.52% 50.05% | 544679 12.48% 62.53% | 544911 12.48% 75.01% | 546354 12.52% 87.53% | 544225 12.47% 100.00% -system.ruby.L1Cache_Controller.Ack::total 4364529 -system.ruby.L1Cache_Controller.Shared_Ack | 31 8.27% 8.27% | 41 10.93% 19.20% | 41 10.93% 30.13% | 54 14.40% 44.53% | 46 12.27% 56.80% | 49 13.07% 69.87% | 57 15.20% 85.07% | 56 14.93% 100.00% -system.ruby.L1Cache_Controller.Shared_Ack::total 375 -system.ruby.L1Cache_Controller.Data | 3440 12.43% 12.43% | 3377 12.20% 24.63% | 3352 12.11% 36.74% | 3580 12.93% 49.67% | 3475 12.55% 62.22% | 3501 12.65% 74.87% | 3448 12.46% 87.33% | 3508 12.67% 100.00% -system.ruby.L1Cache_Controller.Data::total 27681 -system.ruby.L1Cache_Controller.Shared_Data | 1192 12.40% 12.40% | 1173 12.20% 24.60% | 1206 12.55% 37.15% | 1220 12.69% 49.84% | 1176 12.23% 62.07% | 1276 13.27% 75.35% | 1184 12.32% 87.66% | 1186 12.34% 100.00% -system.ruby.L1Cache_Controller.Shared_Data::total 9613 -system.ruby.L1Cache_Controller.Exclusive_Data | 74022 12.55% 12.55% | 73774 12.50% 25.05% | 73884 12.52% 37.57% | 73734 12.50% 50.07% | 73616 12.48% 62.55% | 73550 12.47% 75.01% | 73907 12.53% 87.54% | 73526 12.46% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 590013 -system.ruby.L1Cache_Controller.Writeback_Ack | 74259 12.55% 12.55% | 73878 12.49% 25.04% | 73986 12.51% 37.55% | 74056 12.52% 50.07% | 73807 12.48% 62.55% | 73737 12.47% 75.02% | 74060 12.52% 87.54% | 73709 12.46% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 591492 -system.ruby.L1Cache_Controller.Writeback_Nack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 1 -system.ruby.L1Cache_Controller.All_acks | 1220 12.28% 12.28% | 1207 12.15% 24.43% | 1244 12.52% 36.95% | 1265 12.73% 49.68% | 1214 12.22% 61.90% | 1317 13.26% 75.16% | 1235 12.43% 87.59% | 1233 12.41% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 9935 -system.ruby.L1Cache_Controller.All_acks_no_sharers | 77435 12.54% 12.54% | 77117 12.49% 25.03% | 77198 12.50% 37.54% | 77268 12.52% 50.05% | 77053 12.48% 62.53% | 77010 12.47% 75.01% | 77303 12.52% 87.53% | 76986 12.47% 100.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers::total 617370 -system.ruby.L1Cache_Controller.I.Load | 50567 12.51% 12.51% | 50509 12.50% 25.02% | 50529 12.51% 37.52% | 50592 12.52% 50.04% | 50200 12.42% 62.47% | 50701 12.55% 75.01% | 50397 12.47% 87.49% | 50557 12.51% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 404052 -system.ruby.L1Cache_Controller.I.Store | 28088 12.58% 12.58% | 27817 12.46% 25.04% | 27916 12.50% 37.54% | 27943 12.52% 50.06% | 28064 12.57% 62.63% | 27628 12.37% 75.00% | 28144 12.61% 87.61% | 27663 12.39% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 223263 -system.ruby.L1Cache_Controller.I.L2_Replacement | 1147 12.07% 12.07% | 1210 12.73% 24.81% | 1229 12.93% 37.74% | 1174 12.36% 50.09% | 1173 12.34% 62.44% | 1171 12.32% 74.76% | 1198 12.61% 87.37% | 1200 12.63% 100.00% -system.ruby.L1Cache_Controller.I.L2_Replacement::total 9502 -system.ruby.L1Cache_Controller.I.L1_to_L2 | 95 11.85% 11.85% | 109 13.59% 25.44% | 82 10.22% 35.66% | 115 14.34% 50.00% | 96 11.97% 61.97% | 100 12.47% 74.44% | 106 13.22% 87.66% | 99 12.34% 100.00% -system.ruby.L1Cache_Controller.I.L1_to_L2::total 802 -system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 2 20.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 1 10.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 214073 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 961.619326 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 690.144763 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 669.356252 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 79862 37.31% 37.31% | 39618 18.51% 55.81% | 40238 18.80% 74.61% | 41777 19.52% 94.12% | 11700 5.47% 99.59% | 865 0.40% 99.99% | 13 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 214073 +system.ruby.Directory_Controller.GETX 228066 0.00% 0.00% +system.ruby.Directory_Controller.GETS 409919 0.00% 0.00% +system.ruby.Directory_Controller.PUT 606117 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 1478 0.00% 0.00% +system.ruby.Directory_Controller.UnblockS 26200 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 601910 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Clean 7982 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Dirty 1462 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 361520 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220077 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 607668 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 221538 0.00% 0.00% +system.ruby.Directory_Controller.All_Unblocks 1073 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETX 64 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETS 111 0.00% 0.00% +system.ruby.Directory_Controller.NX.PUT 10889 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 7240 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 11956 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 581636 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 9346 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 16569 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 207506 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 374265 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETX 569 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETS 1073 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 13366 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockS 8495 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 600329 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.GETX 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.PUT 10 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockS 19 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockM 550 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.GETS 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.PUT 33 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockS 42 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockM 1031 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.GETX 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.GETS 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.PUT 121 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.UnblockS 1076 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 1073 0.00% 0.00% +system.ruby.Directory_Controller.O_B.GETX 13 0.00% 0.00% +system.ruby.Directory_Controller.O_B.GETS 15 0.00% 0.00% +system.ruby.Directory_Controller.O_B.UnblockS 16568 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETX 1985 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETS 3422 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 591100 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETX 48 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETS 118 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.Memory_Data 16568 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 1246 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 2323 0.00% 0.00% +system.ruby.Directory_Controller.WB.PUT 62 0.00% 0.00% +system.ruby.Directory_Controller.WB.Unblock 1478 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Clean 7982 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Dirty 1462 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 361520 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220077 0.00% 0.00% +system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1462 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETX 44 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 61 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220076 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50385 12.45% 12.45% | 50687 12.52% 24.97% | 50468 12.47% 37.44% | 50666 12.52% 49.96% | 50623 12.51% 62.47% | 50650 12.51% 74.98% | 50545 12.49% 87.47% | 50723 12.53% 100.00% +system.ruby.L1Cache_Controller.Load::total 404747 +system.ruby.L1Cache_Controller.Store | 28072 12.50% 12.50% | 28228 12.57% 25.07% | 28321 12.61% 37.69% | 27699 12.34% 50.02% | 28273 12.59% 62.61% | 28020 12.48% 75.09% | 28027 12.48% 87.57% | 27908 12.43% 100.00% +system.ruby.L1Cache_Controller.Store::total 224548 +system.ruby.L1Cache_Controller.L2_Replacement | 78299 12.47% 12.47% | 78765 12.54% 25.01% | 78648 12.52% 37.53% | 78211 12.45% 49.98% | 78724 12.53% 62.52% | 78526 12.50% 75.02% | 78393 12.48% 87.51% | 78471 12.49% 100.00% +system.ruby.L1Cache_Controller.L2_Replacement::total 628037 +system.ruby.L1Cache_Controller.L1_to_L2 | 979507 12.50% 12.50% | 981167 12.52% 25.01% | 980052 12.50% 37.51% | 977154 12.47% 49.98% | 982076 12.53% 62.51% | 980285 12.51% 75.01% | 977927 12.48% 87.49% | 980636 12.51% 100.00% +system.ruby.L1Cache_Controller.L1_to_L2::total 7838804 +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 67 11.90% 11.90% | 65 11.55% 23.45% | 63 11.19% 34.64% | 70 12.43% 47.07% | 72 12.79% 59.86% | 62 11.01% 70.87% | 85 15.10% 85.97% | 79 14.03% 100.00% +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 563 +system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 67 11.90% 11.90% | 65 11.55% 23.45% | 63 11.19% 34.64% | 70 12.43% 47.07% | 72 12.79% 59.86% | 62 11.01% 70.87% | 85 15.10% 85.97% | 79 14.03% 100.00% +system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 563 +system.ruby.L1Cache_Controller.Other_GETX | 196134 12.50% 12.50% | 195975 12.49% 24.99% | 195874 12.48% 37.47% | 196504 12.52% 50.00% | 195940 12.49% 62.48% | 196190 12.50% 74.99% | 196188 12.50% 87.49% | 196280 12.51% 100.00% +system.ruby.L1Cache_Controller.Other_GETX::total 1569085 +system.ruby.L1Cache_Controller.Other_GETS | 352746 12.51% 12.51% | 352417 12.50% 25.00% | 352660 12.50% 37.51% | 352467 12.50% 50.01% | 352524 12.50% 62.50% | 352468 12.50% 75.00% | 352590 12.50% 87.50% | 352421 12.50% 100.00% +system.ruby.L1Cache_Controller.Other_GETS::total 2820293 +system.ruby.L1Cache_Controller.Merged_GETS | 136 12.67% 12.67% | 148 13.79% 26.47% | 126 11.74% 38.21% | 132 12.30% 50.51% | 123 11.46% 61.98% | 138 12.86% 74.84% | 131 12.21% 87.05% | 139 12.95% 100.00% +system.ruby.L1Cache_Controller.Merged_GETS::total 1073 +system.ruby.L1Cache_Controller.Ack | 544749 12.47% 12.47% | 548151 12.54% 25.01% | 547200 12.52% 37.53% | 544104 12.45% 49.99% | 547634 12.53% 62.52% | 546228 12.50% 75.02% | 545522 12.48% 87.50% | 545987 12.50% 100.00% +system.ruby.L1Cache_Controller.Ack::total 4369575 +system.ruby.L1Cache_Controller.Shared_Ack | 44 10.38% 10.38% | 64 15.09% 25.47% | 49 11.56% 37.03% | 55 12.97% 50.00% | 58 13.68% 63.68% | 62 14.62% 78.30% | 48 11.32% 89.62% | 44 10.38% 100.00% +system.ruby.L1Cache_Controller.Shared_Ack::total 424 +system.ruby.L1Cache_Controller.Data | 3431 12.51% 12.51% | 3478 12.68% 25.20% | 3487 12.72% 37.91% | 3316 12.09% 50.00% | 3463 12.63% 62.63% | 3469 12.65% 75.28% | 3357 12.24% 87.52% | 3421 12.48% 100.00% +system.ruby.L1Cache_Controller.Data::total 27422 +system.ruby.L1Cache_Controller.Shared_Data | 1205 12.51% 12.51% | 1184 12.29% 24.80% | 1195 12.41% 37.21% | 1186 12.31% 49.52% | 1199 12.45% 61.97% | 1238 12.85% 74.82% | 1198 12.44% 87.26% | 1227 12.74% 100.00% +system.ruby.L1Cache_Controller.Shared_Data::total 9632 +system.ruby.L1Cache_Controller.Exclusive_Data | 73671 12.46% 12.46% | 74114 12.54% 25.00% | 73974 12.52% 37.52% | 73718 12.47% 49.99% | 74071 12.53% 62.52% | 73826 12.49% 75.01% | 73849 12.49% 87.51% | 73835 12.49% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 591058 +system.ruby.L1Cache_Controller.Writeback_Ack | 73966 12.48% 12.48% | 74272 12.53% 25.02% | 74193 12.52% 37.54% | 73799 12.46% 49.99% | 74240 12.53% 62.52% | 73997 12.49% 75.01% | 73995 12.49% 87.50% | 74059 12.50% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 592521 +system.ruby.L1Cache_Controller.All_acks | 1242 12.43% 12.43% | 1233 12.34% 24.77% | 1238 12.39% 37.16% | 1235 12.36% 49.52% | 1246 12.47% 61.99% | 1291 12.92% 74.91% | 1239 12.40% 87.31% | 1268 12.69% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 9992 +system.ruby.L1Cache_Controller.All_acks_no_sharers | 77066 12.47% 12.47% | 77544 12.55% 25.01% | 77418 12.52% 37.54% | 76985 12.45% 49.99% | 77487 12.54% 62.53% | 77242 12.50% 75.02% | 77165 12.48% 87.51% | 77215 12.49% 100.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers::total 618122 +system.ruby.L1Cache_Controller.I.Load | 50288 12.45% 12.45% | 50598 12.53% 24.97% | 50377 12.47% 37.44% | 50572 12.52% 49.96% | 50518 12.51% 62.47% | 50570 12.52% 74.99% | 50439 12.49% 87.47% | 50607 12.53% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 403969 +system.ruby.L1Cache_Controller.I.Store | 28021 12.50% 12.50% | 28176 12.57% 25.07% | 28281 12.62% 37.69% | 27649 12.34% 50.02% | 28214 12.59% 62.61% | 27965 12.48% 75.09% | 27964 12.48% 87.56% | 27875 12.44% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 224145 +system.ruby.L1Cache_Controller.I.L2_Replacement | 1108 11.60% 11.60% | 1263 13.22% 24.81% | 1214 12.71% 37.52% | 1261 13.20% 50.72% | 1167 12.21% 62.93% | 1204 12.60% 75.53% | 1194 12.50% 88.03% | 1144 11.97% 100.00% +system.ruby.L1Cache_Controller.I.L2_Replacement::total 9555 +system.ruby.L1Cache_Controller.I.L1_to_L2 | 85 10.98% 10.98% | 100 12.92% 23.90% | 96 12.40% 36.30% | 96 12.40% 48.71% | 85 10.98% 59.69% | 104 13.44% 73.13% | 117 15.12% 88.24% | 91 11.76% 100.00% +system.ruby.L1Cache_Controller.I.L1_to_L2::total 774 +system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 1 10.00% 10.00% | 1 10.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 3 30.00% 100.00% system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total 10 -system.ruby.L1Cache_Controller.I.Other_GETX | 194128 12.49% 12.49% | 194346 12.51% 25.00% | 194236 12.50% 37.49% | 194228 12.50% 49.99% | 194087 12.49% 62.48% | 194552 12.52% 75.00% | 194037 12.49% 87.48% | 194519 12.52% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETX::total 1554133 -system.ruby.L1Cache_Controller.I.Other_GETS | 350781 12.50% 12.50% | 350787 12.50% 25.00% | 350767 12.50% 37.50% | 350672 12.50% 49.99% | 351174 12.51% 62.51% | 350517 12.49% 75.00% | 350891 12.50% 87.50% | 350707 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETS::total 2806296 -system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 2 -system.ruby.L1Cache_Controller.S.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETX | 195054 12.50% 12.50% | 194813 12.49% 24.99% | 194750 12.48% 37.47% | 195324 12.52% 49.99% | 194790 12.49% 62.48% | 195048 12.50% 74.98% | 195089 12.51% 87.49% | 195205 12.51% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETX::total 1560073 +system.ruby.L1Cache_Controller.I.Other_GETS | 350845 12.51% 12.51% | 350506 12.49% 25.00% | 350840 12.51% 37.51% | 350591 12.50% 50.01% | 350672 12.50% 62.51% | 350617 12.50% 75.00% | 350657 12.50% 87.50% | 350525 12.50% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETS::total 2805253 +system.ruby.L1Cache_Controller.S.Load | 2 22.22% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 4 44.44% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 9 +system.ruby.L1Cache_Controller.S.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Store::total 2 -system.ruby.L1Cache_Controller.S.L2_Replacement | 3235 12.34% 12.34% | 3224 12.30% 24.64% | 3217 12.27% 36.91% | 3292 12.56% 49.47% | 3270 12.47% 61.94% | 3408 13.00% 74.94% | 3268 12.47% 87.41% | 3300 12.59% 100.00% -system.ruby.L1Cache_Controller.S.L2_Replacement::total 26214 -system.ruby.L1Cache_Controller.S.L1_to_L2 | 3265 12.34% 12.34% | 3252 12.29% 24.62% | 3252 12.29% 36.91% | 3319 12.54% 49.45% | 3309 12.50% 61.95% | 3438 12.99% 74.94% | 3301 12.47% 87.41% | 3331 12.59% 100.00% -system.ruby.L1Cache_Controller.S.L1_to_L2::total 26467 -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 1 7.14% 7.14% | 2 14.29% 21.43% | 2 14.29% 35.71% | 2 14.29% 50.00% | 4 28.57% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00% -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 14 -system.ruby.L1Cache_Controller.S.Other_GETX | 32 12.31% 12.31% | 29 11.15% 23.46% | 36 13.85% 37.31% | 28 10.77% 48.08% | 34 13.08% 61.15% | 31 11.92% 73.08% | 37 14.23% 87.31% | 33 12.69% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETX::total 260 -system.ruby.L1Cache_Controller.S.Other_GETS | 44 11.73% 11.73% | 50 13.33% 25.07% | 52 13.87% 38.93% | 41 10.93% 49.87% | 43 11.47% 61.33% | 62 16.53% 77.87% | 37 9.87% 87.73% | 46 12.27% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETS::total 375 -system.ruby.L1Cache_Controller.O.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Load::total 1 -system.ruby.L1Cache_Controller.O.L2_Replacement | 872 12.65% 12.65% | 877 12.72% 25.38% | 862 12.51% 37.88% | 862 12.51% 50.39% | 846 12.28% 62.67% | 873 12.67% 75.33% | 864 12.54% 87.87% | 836 12.13% 100.00% -system.ruby.L1Cache_Controller.O.L2_Replacement::total 6892 -system.ruby.L1Cache_Controller.O.L1_to_L2 | 63 10.47% 10.47% | 75 12.46% 22.92% | 90 14.95% 37.87% | 86 14.29% 52.16% | 79 13.12% 65.28% | 72 11.96% 77.24% | 72 11.96% 89.20% | 65 10.80% 100.00% -system.ruby.L1Cache_Controller.O.L1_to_L2::total 602 -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 5 -system.ruby.L1Cache_Controller.O.Other_GETX | 7 14.58% 14.58% | 2 4.17% 18.75% | 6 12.50% 31.25% | 10 20.83% 52.08% | 7 14.58% 66.67% | 7 14.58% 81.25% | 2 4.17% 85.42% | 7 14.58% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETX::total 48 -system.ruby.L1Cache_Controller.O.Other_GETS | 3 5.08% 5.08% | 4 6.78% 11.86% | 7 11.86% 23.73% | 11 18.64% 42.37% | 9 15.25% 57.63% | 7 11.86% 69.49% | 10 16.95% 86.44% | 8 13.56% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETS::total 59 -system.ruby.L1Cache_Controller.O.Merged_GETS | 3 14.29% 14.29% | 1 4.76% 19.05% | 3 14.29% 33.33% | 4 19.05% 52.38% | 3 14.29% 66.67% | 0 0.00% 66.67% | 5 23.81% 90.48% | 2 9.52% 100.00% -system.ruby.L1Cache_Controller.O.Merged_GETS::total 21 -system.ruby.L1Cache_Controller.M.Load | 1 5.56% 5.56% | 2 11.11% 16.67% | 3 16.67% 33.33% | 4 22.22% 55.56% | 3 16.67% 72.22% | 3 16.67% 88.89% | 1 5.56% 94.44% | 1 5.56% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 18 -system.ruby.L1Cache_Controller.M.Store | 4 19.05% 19.05% | 0 0.00% 19.05% | 2 9.52% 28.57% | 4 19.05% 47.62% | 3 14.29% 61.90% | 0 0.00% 61.90% | 4 19.05% 80.95% | 4 19.05% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 21 -system.ruby.L1Cache_Controller.M.L2_Replacement | 45980 12.53% 12.53% | 45916 12.51% 25.04% | 45952 12.52% 37.55% | 45945 12.52% 50.07% | 45597 12.42% 62.49% | 45962 12.52% 75.01% | 45778 12.47% 87.49% | 45934 12.51% 100.00% -system.ruby.L1Cache_Controller.M.L2_Replacement::total 367064 -system.ruby.L1Cache_Controller.M.L1_to_L2 | 47218 12.53% 12.53% | 47164 12.52% 25.05% | 47173 12.52% 37.56% | 47162 12.52% 50.08% | 46805 12.42% 62.50% | 47183 12.52% 75.02% | 47003 12.47% 87.49% | 47135 12.51% 100.00% -system.ruby.L1Cache_Controller.M.L1_to_L2::total 376843 -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 42 13.55% 13.55% | 42 13.55% 27.10% | 30 9.68% 36.77% | 44 14.19% 50.97% | 45 14.52% 65.48% | 35 11.29% 76.77% | 39 12.58% 89.35% | 33 10.65% 100.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 310 -system.ruby.L1Cache_Controller.M.Other_GETX | 450 12.17% 12.17% | 479 12.95% 25.12% | 475 12.84% 37.97% | 473 12.79% 50.76% | 464 12.55% 63.30% | 444 12.01% 75.31% | 459 12.41% 87.72% | 454 12.28% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETX::total 3698 -system.ruby.L1Cache_Controller.M.Other_GETS | 774 12.68% 12.68% | 778 12.75% 25.43% | 761 12.47% 37.91% | 781 12.80% 50.70% | 728 11.93% 62.64% | 781 12.80% 75.43% | 749 12.27% 87.71% | 750 12.29% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETS::total 6102 -system.ruby.L1Cache_Controller.M.Merged_GETS | 66 13.02% 13.02% | 58 11.44% 24.46% | 70 13.81% 38.26% | 48 9.47% 47.73% | 79 15.58% 63.31% | 49 9.66% 72.98% | 79 15.58% 88.56% | 58 11.44% 100.00% -system.ruby.L1Cache_Controller.M.Merged_GETS::total 507 -system.ruby.L1Cache_Controller.MM.Load | 1 8.33% 8.33% | 1 8.33% 16.67% | 2 16.67% 33.33% | 2 16.67% 50.00% | 1 8.33% 58.33% | 1 8.33% 66.67% | 2 16.67% 83.33% | 2 16.67% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 12 -system.ruby.L1Cache_Controller.MM.Store | 2 20.00% 20.00% | 0 0.00% 20.00% | 1 10.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 2 20.00% 90.00% | 1 10.00% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 10 -system.ruby.L1Cache_Controller.MM.L2_Replacement | 27411 12.60% 12.60% | 27088 12.45% 25.05% | 27175 12.49% 37.54% | 27252 12.53% 50.07% | 27368 12.58% 62.65% | 26904 12.37% 75.01% | 27423 12.60% 87.62% | 26940 12.38% 100.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement::total 217561 -system.ruby.L1Cache_Controller.MM.L1_to_L2 | 28093 12.59% 12.59% | 27802 12.46% 25.05% | 27903 12.50% 37.55% | 27924 12.51% 50.07% | 28049 12.57% 62.64% | 27597 12.37% 75.01% | 28124 12.60% 87.61% | 27644 12.39% 100.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2::total 223136 -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 37 16.23% 16.23% | 35 15.35% 31.58% | 26 11.40% 42.98% | 28 12.28% 55.26% | 24 10.53% 65.79% | 29 12.72% 78.51% | 28 12.28% 90.79% | 21 9.21% 100.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 228 -system.ruby.L1Cache_Controller.MM.Other_GETX | 238 11.94% 11.94% | 259 12.99% 24.92% | 260 13.04% 37.96% | 220 11.03% 49.00% | 271 13.59% 62.59% | 241 12.09% 74.67% | 258 12.94% 87.61% | 247 12.39% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETX::total 1994 -system.ruby.L1Cache_Controller.MM.Other_GETS | 422 12.02% 12.02% | 442 12.59% 24.60% | 452 12.87% 37.47% | 444 12.64% 50.11% | 400 11.39% 61.50% | 449 12.78% 74.29% | 443 12.61% 86.90% | 460 13.10% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETS::total 3512 -system.ruby.L1Cache_Controller.MM.Merged_GETS | 40 11.98% 11.98% | 43 12.87% 24.85% | 38 11.38% 36.23% | 43 12.87% 49.10% | 47 14.07% 63.17% | 50 14.97% 78.14% | 38 11.38% 89.52% | 35 10.48% 100.00% -system.ruby.L1Cache_Controller.MM.Merged_GETS::total 334 -system.ruby.L1Cache_Controller.IR.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IR.Load::total 3 -system.ruby.L1Cache_Controller.IR.Store | 2 28.57% 28.57% | 1 14.29% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% -system.ruby.L1Cache_Controller.IR.Store::total 7 -system.ruby.L1Cache_Controller.IR.L1_to_L2 | 10 43.48% 43.48% | 0 0.00% 43.48% | 0 0.00% 43.48% | 7 30.43% 73.91% | 1 4.35% 78.26% | 0 0.00% 78.26% | 5 21.74% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IR.L1_to_L2::total 23 -system.ruby.L1Cache_Controller.SR.Load | 1 10.00% 10.00% | 2 20.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% -system.ruby.L1Cache_Controller.SR.Load::total 10 -system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% -system.ruby.L1Cache_Controller.SR.Store::total 4 -system.ruby.L1Cache_Controller.SR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SR.L1_to_L2::total 1 -system.ruby.L1Cache_Controller.OR.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.OR.Load::total 3 -system.ruby.L1Cache_Controller.OR.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.L2_Replacement | 3221 12.41% 12.41% | 3230 12.44% 24.85% | 3241 12.49% 37.34% | 3151 12.14% 49.48% | 3317 12.78% 62.26% | 3324 12.81% 75.07% | 3203 12.34% 87.41% | 3268 12.59% 100.00% +system.ruby.L1Cache_Controller.S.L2_Replacement::total 25955 +system.ruby.L1Cache_Controller.S.L1_to_L2 | 3248 12.40% 12.40% | 3268 12.48% 24.88% | 3269 12.48% 37.36% | 3185 12.16% 49.53% | 3341 12.76% 62.28% | 3367 12.86% 75.14% | 3224 12.31% 87.45% | 3286 12.55% 100.00% +system.ruby.L1Cache_Controller.S.L1_to_L2::total 26188 +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 2 7.14% 7.14% | 7 25.00% 32.14% | 2 7.14% 39.29% | 6 21.43% 60.71% | 4 14.29% 75.00% | 3 10.71% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 28 +system.ruby.L1Cache_Controller.S.Other_GETX | 28 12.07% 12.07% | 35 15.09% 27.16% | 28 12.07% 39.22% | 33 14.22% 53.45% | 23 9.91% 63.36% | 45 19.40% 82.76% | 20 8.62% 91.38% | 20 8.62% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETX::total 232 +system.ruby.L1Cache_Controller.S.Other_GETS | 62 14.62% 14.62% | 53 12.50% 27.12% | 44 10.38% 37.50% | 42 9.91% 47.41% | 54 12.74% 60.14% | 47 11.08% 71.23% | 67 15.80% 87.03% | 55 12.97% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETS::total 424 +system.ruby.L1Cache_Controller.O.L2_Replacement | 838 12.35% 12.35% | 856 12.62% 24.97% | 806 11.88% 36.86% | 859 12.66% 49.52% | 821 12.10% 61.62% | 862 12.71% 74.33% | 851 12.55% 86.88% | 890 13.12% 100.00% +system.ruby.L1Cache_Controller.O.L2_Replacement::total 6783 +system.ruby.L1Cache_Controller.O.L1_to_L2 | 81 13.92% 13.92% | 64 11.00% 24.91% | 74 12.71% 37.63% | 70 12.03% 49.66% | 59 10.14% 59.79% | 67 11.51% 71.31% | 86 14.78% 86.08% | 81 13.92% 100.00% +system.ruby.L1Cache_Controller.O.L1_to_L2::total 582 +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 1 11.11% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 9 +system.ruby.L1Cache_Controller.O.Other_GETX | 5 16.67% 16.67% | 2 6.67% 23.33% | 5 16.67% 40.00% | 6 20.00% 60.00% | 7 23.33% 83.33% | 1 3.33% 86.67% | 3 10.00% 96.67% | 1 3.33% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETX::total 30 +system.ruby.L1Cache_Controller.O.Other_GETS | 11 16.42% 16.42% | 8 11.94% 28.36% | 6 8.96% 37.31% | 10 14.93% 52.24% | 9 13.43% 65.67% | 9 13.43% 79.10% | 5 7.46% 86.57% | 9 13.43% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETS::total 67 +system.ruby.L1Cache_Controller.O.Merged_GETS | 0 0.00% 0.00% | 2 11.11% 11.11% | 3 16.67% 27.78% | 1 5.56% 33.33% | 4 22.22% 55.56% | 4 22.22% 77.78% | 1 5.56% 83.33% | 3 16.67% 100.00% +system.ruby.L1Cache_Controller.O.Merged_GETS::total 18 +system.ruby.L1Cache_Controller.M.Load | 7 21.21% 21.21% | 3 9.09% 30.30% | 7 21.21% 51.52% | 1 3.03% 54.55% | 5 15.15% 69.70% | 4 12.12% 81.82% | 2 6.06% 87.88% | 4 12.12% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 33 +system.ruby.L1Cache_Controller.M.Store | 2 13.33% 13.33% | 0 0.00% 13.33% | 1 6.67% 20.00% | 3 20.00% 40.00% | 4 26.67% 66.67% | 2 13.33% 80.00% | 3 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 15 +system.ruby.L1Cache_Controller.M.L2_Replacement | 45788 12.46% 12.46% | 46023 12.52% 24.98% | 45848 12.48% 37.46% | 46041 12.53% 49.99% | 45893 12.49% 62.48% | 45908 12.49% 74.97% | 45944 12.50% 87.48% | 46021 12.52% 100.00% +system.ruby.L1Cache_Controller.M.L2_Replacement::total 367466 +system.ruby.L1Cache_Controller.M.L1_to_L2 | 46942 12.45% 12.45% | 47247 12.53% 24.98% | 47018 12.47% 37.45% | 47302 12.54% 49.99% | 47109 12.49% 62.48% | 47115 12.49% 74.98% | 47118 12.50% 87.47% | 47240 12.53% 100.00% +system.ruby.L1Cache_Controller.M.L1_to_L2::total 377091 +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 39 12.30% 12.30% | 35 11.04% 23.34% | 34 10.73% 34.07% | 45 14.20% 48.26% | 36 11.36% 59.62% | 34 10.73% 70.35% | 43 13.56% 83.91% | 51 16.09% 100.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 317 +system.ruby.L1Cache_Controller.M.Other_GETX | 426 11.63% 11.63% | 469 12.80% 24.43% | 474 12.94% 37.36% | 499 13.62% 50.98% | 473 12.91% 63.89% | 454 12.39% 76.28% | 433 11.82% 88.10% | 436 11.90% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETX::total 3664 +system.ruby.L1Cache_Controller.M.Other_GETS | 726 12.31% 12.31% | 735 12.46% 24.77% | 709 12.02% 36.79% | 751 12.73% 49.52% | 725 12.29% 61.81% | 746 12.65% 74.45% | 739 12.53% 86.98% | 768 13.02% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETS::total 5899 +system.ruby.L1Cache_Controller.M.Merged_GETS | 78 13.59% 13.59% | 87 15.16% 28.75% | 57 9.93% 38.68% | 69 12.02% 50.70% | 61 10.63% 61.32% | 73 12.72% 74.04% | 73 12.72% 86.76% | 76 13.24% 100.00% +system.ruby.L1Cache_Controller.M.Merged_GETS::total 574 +system.ruby.L1Cache_Controller.MM.Load | 1 5.56% 5.56% | 2 11.11% 16.67% | 1 5.56% 22.22% | 6 33.33% 55.56% | 3 16.67% 72.22% | 1 5.56% 77.78% | 1 5.56% 83.33% | 3 16.67% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 18 +system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 42.86% 42.86% | 0 0.00% 42.86% | 2 28.57% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 7 +system.ruby.L1Cache_Controller.MM.L2_Replacement | 27344 12.53% 12.53% | 27393 12.55% 25.08% | 27539 12.62% 37.69% | 26899 12.32% 50.02% | 27526 12.61% 62.63% | 27228 12.47% 75.10% | 27201 12.46% 87.56% | 27148 12.44% 100.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement::total 218278 +system.ruby.L1Cache_Controller.MM.L1_to_L2 | 28016 12.51% 12.51% | 28156 12.57% 25.08% | 28260 12.62% 37.69% | 27634 12.34% 50.03% | 28206 12.59% 62.62% | 27940 12.47% 75.09% | 27939 12.47% 87.56% | 27858 12.44% 100.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2::total 224009 +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 24 12.06% 12.06% | 21 10.55% 22.61% | 24 12.06% 34.67% | 19 9.55% 44.22% | 28 14.07% 58.29% | 24 12.06% 70.35% | 37 18.59% 88.94% | 22 11.06% 100.00% +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 199 +system.ruby.L1Cache_Controller.MM.Other_GETX | 248 11.64% 11.64% | 283 13.29% 24.93% | 265 12.44% 37.37% | 277 13.00% 50.38% | 266 12.49% 62.86% | 250 11.74% 74.60% | 302 14.18% 88.78% | 239 11.22% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETX::total 2130 +system.ruby.L1Cache_Controller.MM.Other_GETS | 402 11.45% 11.45% | 475 13.53% 24.98% | 443 12.62% 37.60% | 447 12.73% 50.33% | 400 11.39% 61.72% | 455 12.96% 74.68% | 437 12.45% 87.13% | 452 12.87% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETS::total 3511 +system.ruby.L1Cache_Controller.MM.Merged_GETS | 40 11.66% 11.66% | 38 11.08% 22.74% | 45 13.12% 35.86% | 45 13.12% 48.98% | 42 12.24% 61.22% | 44 12.83% 74.05% | 42 12.24% 86.30% | 47 13.70% 100.00% +system.ruby.L1Cache_Controller.MM.Merged_GETS::total 343 +system.ruby.L1Cache_Controller.IR.Load | 1 11.11% 11.11% | 1 11.11% 22.22% | 1 11.11% 33.33% | 0 0.00% 33.33% | 2 22.22% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.IR.Load::total 9 +system.ruby.L1Cache_Controller.IR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.IR.Store::total 1 +system.ruby.L1Cache_Controller.IR.L1_to_L2 | 0 0.00% 0.00% | 10 71.43% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 1 7.14% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00% +system.ruby.L1Cache_Controller.IR.L1_to_L2::total 14 +system.ruby.L1Cache_Controller.SR.Load | 2 10.00% 10.00% | 4 20.00% 30.00% | 2 10.00% 40.00% | 4 20.00% 60.00% | 3 15.00% 75.00% | 3 15.00% 90.00% | 0 0.00% 90.00% | 2 10.00% 100.00% +system.ruby.L1Cache_Controller.SR.Load::total 20 +system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 3 37.50% 37.50% | 0 0.00% 37.50% | 2 25.00% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SR.Store::total 8 +system.ruby.L1Cache_Controller.SR.L1_to_L2 | 8 12.70% 12.70% | 13 20.63% 33.33% | 6 9.52% 42.86% | 18 28.57% 71.43% | 12 19.05% 90.48% | 6 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SR.L1_to_L2::total 63 +system.ruby.L1Cache_Controller.OR.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 28.57% 28.57% | 0 0.00% 28.57% | 2 28.57% 57.14% | 0 0.00% 57.14% | 2 28.57% 85.71% | 1 14.29% 100.00% +system.ruby.L1Cache_Controller.OR.Load::total 7 +system.ruby.L1Cache_Controller.OR.Store | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OR.Store::total 2 -system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OR.L1_to_L2::total 1 -system.ruby.L1Cache_Controller.MR.Load | 25 13.09% 13.09% | 23 12.04% 25.13% | 21 10.99% 36.13% | 29 15.18% 51.31% | 31 16.23% 67.54% | 16 8.38% 75.92% | 26 13.61% 89.53% | 20 10.47% 100.00% -system.ruby.L1Cache_Controller.MR.Load::total 191 -system.ruby.L1Cache_Controller.MR.Store | 17 14.29% 14.29% | 19 15.97% 30.25% | 9 7.56% 37.82% | 15 12.61% 50.42% | 14 11.76% 62.18% | 19 15.97% 78.15% | 13 10.92% 89.08% | 13 10.92% 100.00% -system.ruby.L1Cache_Controller.MR.Store::total 119 -system.ruby.L1Cache_Controller.MR.L1_to_L2 | 94 15.75% 15.75% | 102 17.09% 32.83% | 50 8.38% 41.21% | 86 14.41% 55.61% | 74 12.40% 68.01% | 83 13.90% 81.91% | 76 12.73% 94.64% | 32 5.36% 100.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2::total 597 -system.ruby.L1Cache_Controller.MMR.Load | 23 15.54% 15.54% | 22 14.86% 30.41% | 21 14.19% 44.59% | 20 13.51% 58.11% | 10 6.76% 64.86% | 17 11.49% 76.35% | 21 14.19% 90.54% | 14 9.46% 100.00% -system.ruby.L1Cache_Controller.MMR.Load::total 148 -system.ruby.L1Cache_Controller.MMR.Store | 14 17.50% 17.50% | 13 16.25% 33.75% | 5 6.25% 40.00% | 8 10.00% 50.00% | 14 17.50% 67.50% | 12 15.00% 82.50% | 7 8.75% 91.25% | 7 8.75% 100.00% -system.ruby.L1Cache_Controller.MMR.Store::total 80 -system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 69 17.38% 17.38% | 39 9.82% 27.20% | 42 10.58% 37.78% | 55 13.85% 51.64% | 39 9.82% 61.46% | 89 22.42% 83.88% | 28 7.05% 90.93% | 36 9.07% 100.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 397 -system.ruby.L1Cache_Controller.IM.L1_to_L2 | 274713 12.40% 12.40% | 274213 12.37% 24.77% | 276032 12.46% 37.23% | 277552 12.52% 49.75% | 280112 12.64% 62.39% | 276280 12.47% 74.86% | 283147 12.78% 87.64% | 274015 12.36% 100.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2216064 -system.ruby.L1Cache_Controller.IM.Other_GETX | 59 13.00% 13.00% | 50 11.01% 24.01% | 45 9.91% 33.92% | 57 12.56% 46.48% | 54 11.89% 58.37% | 72 15.86% 74.23% | 65 14.32% 88.55% | 52 11.45% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETX::total 454 -system.ruby.L1Cache_Controller.IM.Other_GETS | 85 9.74% 9.74% | 98 11.23% 20.96% | 117 13.40% 34.36% | 120 13.75% 48.11% | 111 12.71% 60.82% | 113 12.94% 73.77% | 106 12.14% 85.91% | 123 14.09% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETS::total 873 -system.ruby.L1Cache_Controller.IM.Ack | 143024 12.60% 12.60% | 140883 12.41% 25.01% | 141838 12.50% 37.51% | 142363 12.54% 50.05% | 142609 12.56% 62.62% | 141109 12.43% 75.05% | 142897 12.59% 87.64% | 140315 12.36% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1135038 -system.ruby.L1Cache_Controller.IM.Data | 1363 12.61% 12.61% | 1297 12.00% 24.62% | 1305 12.08% 36.70% | 1478 13.68% 50.37% | 1340 12.40% 62.78% | 1337 12.37% 75.15% | 1326 12.27% 87.42% | 1359 12.58% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 10805 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26726 12.58% 12.58% | 26520 12.48% 25.06% | 26611 12.53% 37.59% | 26464 12.46% 50.04% | 26725 12.58% 62.62% | 26292 12.37% 75.00% | 26818 12.62% 87.62% | 26305 12.38% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 212461 -system.ruby.L1Cache_Controller.SM.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 71.43% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.L1_to_L2::total 7 -system.ruby.L1Cache_Controller.SM.Ack | 7 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 7 25.00% 50.00% | 14 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 28 -system.ruby.L1Cache_Controller.SM.Data | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 3 50.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.SM.Data::total 6 -system.ruby.L1Cache_Controller.OM.L1_to_L2 | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.L1_to_L2::total 10 -system.ruby.L1Cache_Controller.OM.Ack | 7 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 7.14% 7.14% | 0 0.00% 7.14% | 7 50.00% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 6 42.86% 100.00% +system.ruby.L1Cache_Controller.OR.L1_to_L2::total 14 +system.ruby.L1Cache_Controller.MR.Load | 27 12.62% 12.62% | 21 9.81% 22.43% | 24 11.21% 33.64% | 30 14.02% 47.66% | 23 10.75% 58.41% | 22 10.28% 68.69% | 29 13.55% 82.24% | 38 17.76% 100.00% +system.ruby.L1Cache_Controller.MR.Load::total 214 +system.ruby.L1Cache_Controller.MR.Store | 12 11.65% 11.65% | 14 13.59% 25.24% | 10 9.71% 34.95% | 15 14.56% 49.51% | 13 12.62% 62.14% | 12 11.65% 73.79% | 14 13.59% 87.38% | 13 12.62% 100.00% +system.ruby.L1Cache_Controller.MR.Store::total 103 +system.ruby.L1Cache_Controller.MR.L1_to_L2 | 54 9.57% 9.57% | 59 10.46% 20.04% | 75 13.30% 33.33% | 104 18.44% 51.77% | 53 9.40% 61.17% | 57 10.11% 71.28% | 95 16.84% 88.12% | 67 11.88% 100.00% +system.ruby.L1Cache_Controller.MR.L1_to_L2::total 564 +system.ruby.L1Cache_Controller.MMR.Load | 18 14.75% 14.75% | 8 6.56% 21.31% | 19 15.57% 36.89% | 9 7.38% 44.26% | 14 11.48% 55.74% | 14 11.48% 67.21% | 25 20.49% 87.70% | 15 12.30% 100.00% +system.ruby.L1Cache_Controller.MMR.Load::total 122 +system.ruby.L1Cache_Controller.MMR.Store | 6 7.79% 7.79% | 13 16.88% 24.68% | 5 6.49% 31.17% | 10 12.99% 44.16% | 14 18.18% 62.34% | 10 12.99% 75.32% | 12 15.58% 90.91% | 7 9.09% 100.00% +system.ruby.L1Cache_Controller.MMR.Store::total 77 +system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 70 21.60% 21.60% | 45 13.89% 35.49% | 31 9.57% 45.06% | 21 6.48% 51.54% | 26 8.02% 59.57% | 33 10.19% 69.75% | 71 21.91% 91.67% | 27 8.33% 100.00% +system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 324 +system.ruby.L1Cache_Controller.IM.L1_to_L2 | 278922 12.54% 12.54% | 278884 12.54% 25.09% | 280828 12.63% 37.71% | 276004 12.41% 50.13% | 281673 12.67% 62.79% | 275479 12.39% 75.18% | 275157 12.37% 87.56% | 276670 12.44% 100.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2223617 +system.ruby.L1Cache_Controller.IM.Other_GETX | 62 11.50% 11.50% | 80 14.84% 26.35% | 63 11.69% 38.03% | 64 11.87% 49.91% | 49 9.09% 59.00% | 79 14.66% 73.65% | 68 12.62% 86.27% | 74 13.73% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETX::total 539 +system.ruby.L1Cache_Controller.IM.Other_GETS | 122 13.19% 13.19% | 114 12.32% 25.51% | 111 12.00% 37.51% | 122 13.19% 50.70% | 132 14.27% 64.97% | 114 12.32% 77.30% | 111 12.00% 89.30% | 99 10.70% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETS::total 925 +system.ruby.L1Cache_Controller.IM.Ack | 136672 12.48% 12.48% | 137498 12.56% 25.04% | 139357 12.73% 37.77% | 134236 12.26% 50.03% | 137674 12.57% 62.61% | 136413 12.46% 75.07% | 136515 12.47% 87.54% | 136466 12.46% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1094831 +system.ruby.L1Cache_Controller.IM.Data | 1385 12.77% 12.77% | 1390 12.82% 25.59% | 1413 13.03% 38.62% | 1313 12.11% 50.72% | 1321 12.18% 62.90% | 1338 12.34% 75.24% | 1325 12.22% 87.46% | 1360 12.54% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 10845 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26634 12.49% 12.49% | 26785 12.56% 25.04% | 26868 12.60% 37.64% | 26334 12.35% 49.99% | 26894 12.61% 62.60% | 26626 12.48% 75.08% | 26639 12.49% 87.57% | 26515 12.43% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 213295 +system.ruby.L1Cache_Controller.SM.L1_to_L2 | 4 7.27% 7.27% | 12 21.82% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 39 70.91% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.L1_to_L2::total 55 +system.ruby.L1Cache_Controller.SM.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Other_GETX::total 1 +system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 14 60.87% 60.87% | 0 0.00% 60.87% | 8 34.78% 95.65% | 0 0.00% 95.65% | 0 0.00% 95.65% | 1 4.35% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 23 +system.ruby.L1Cache_Controller.SM.Data | 1 11.11% 11.11% | 3 33.33% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 3 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Data::total 9 +system.ruby.L1Cache_Controller.OM.L1_to_L2 | 32 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.L1_to_L2::total 32 +system.ruby.L1Cache_Controller.OM.Ack | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OM.Ack::total 14 -system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 2 -system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1007 10.85% 10.85% | 1353 14.58% 25.42% | 1037 11.17% 36.59% | 1556 16.76% 53.36% | 1024 11.03% 64.39% | 1087 11.71% 76.10% | 1067 11.49% 87.59% | 1152 12.41% 100.00% -system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 9283 -system.ruby.L1Cache_Controller.ISM.Ack | 2517 11.99% 11.99% | 2466 11.75% 23.74% | 2543 12.12% 35.86% | 2993 14.26% 50.11% | 2755 13.13% 63.24% | 2586 12.32% 75.56% | 2564 12.22% 87.78% | 2566 12.22% 100.00% -system.ruby.L1Cache_Controller.ISM.Ack::total 20990 -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1364 12.62% 12.62% | 1297 12.00% 24.61% | 1305 12.07% 36.68% | 1479 13.68% 50.37% | 1343 12.42% 62.79% | 1337 12.37% 75.15% | 1326 12.27% 87.42% | 1360 12.58% 100.00% -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10811 -system.ruby.L1Cache_Controller.M_W.Load | 0 0.00% 0.00% | 6 22.22% 22.22% | 2 7.41% 29.63% | 3 11.11% 40.74% | 4 14.81% 55.56% | 6 22.22% 77.78% | 5 18.52% 96.30% | 1 3.70% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 27 -system.ruby.L1Cache_Controller.M_W.Store | 3 37.50% 37.50% | 0 0.00% 37.50% | 2 25.00% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 8 -system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 63122 12.28% 12.28% | 64179 12.48% 24.76% | 64634 12.57% 37.33% | 63376 12.33% 49.66% | 64257 12.50% 62.16% | 65116 12.67% 74.83% | 64478 12.54% 87.37% | 64945 12.63% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 514107 -system.ruby.L1Cache_Controller.M_W.Ack | 87604 12.42% 12.42% | 87878 12.45% 24.87% | 88420 12.53% 37.40% | 88219 12.50% 49.90% | 87686 12.43% 62.33% | 89091 12.63% 74.96% | 87950 12.46% 87.42% | 88748 12.58% 100.00% -system.ruby.L1Cache_Controller.M_W.Ack::total 705596 -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47293 12.53% 12.53% | 47254 12.52% 25.04% | 47271 12.52% 37.56% | 47269 12.52% 50.08% | 46889 12.42% 62.50% | 47258 12.52% 75.02% | 47086 12.47% 87.49% | 47220 12.51% 100.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 377540 -system.ruby.L1Cache_Controller.MM_W.Load | 1 5.88% 5.88% | 2 11.76% 17.65% | 3 17.65% 35.29% | 1 5.88% 41.18% | 3 17.65% 58.82% | 1 5.88% 64.71% | 1 5.88% 70.59% | 5 29.41% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 17 -system.ruby.L1Cache_Controller.MM_W.Store | 1 16.67% 16.67% | 3 50.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 6 -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 36722 12.63% 12.63% | 36826 12.67% 25.30% | 37113 12.76% 38.06% | 35896 12.35% 50.41% | 36377 12.51% 62.92% | 35600 12.24% 75.16% | 36168 12.44% 87.60% | 36049 12.40% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 290751 -system.ruby.L1Cache_Controller.MM_W.Ack | 50176 12.55% 12.55% | 50453 12.62% 25.18% | 50220 12.56% 37.74% | 49306 12.34% 50.07% | 50222 12.56% 62.64% | 48806 12.21% 74.85% | 50636 12.67% 87.52% | 49898 12.48% 100.00% -system.ruby.L1Cache_Controller.MM_W.Ack::total 399717 -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26729 12.58% 12.58% | 26520 12.48% 25.06% | 26613 12.53% 37.59% | 26464 12.46% 50.04% | 26726 12.58% 62.62% | 26292 12.37% 75.00% | 26820 12.62% 87.62% | 26305 12.38% 100.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 212469 -system.ruby.L1Cache_Controller.IS.L1_to_L2 | 504630 12.56% 12.56% | 503087 12.52% 25.08% | 502873 12.52% 37.60% | 504272 12.55% 50.15% | 499060 12.42% 62.57% | 502572 12.51% 75.08% | 496893 12.37% 87.45% | 504309 12.55% 100.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4017696 -system.ruby.L1Cache_Controller.IS.Other_GETX | 103 11.61% 11.61% | 108 12.18% 23.79% | 115 12.97% 36.75% | 129 14.54% 51.30% | 101 11.39% 62.68% | 113 12.74% 75.42% | 112 12.63% 88.05% | 106 11.95% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETX::total 887 -system.ruby.L1Cache_Controller.IS.Other_GETS | 192 11.83% 11.83% | 215 13.25% 25.08% | 196 12.08% 37.15% | 188 11.58% 48.74% | 193 11.89% 60.63% | 216 13.31% 73.94% | 199 12.26% 86.20% | 224 13.80% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETS::total 1623 -system.ruby.L1Cache_Controller.IS.Ack | 257105 12.56% 12.56% | 256488 12.53% 25.08% | 255973 12.50% 37.58% | 256498 12.53% 50.11% | 254407 12.42% 62.54% | 256125 12.51% 75.05% | 255415 12.47% 87.52% | 255541 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.Ack::total 2047552 -system.ruby.L1Cache_Controller.IS.Shared_Ack | 21 7.50% 7.50% | 28 10.00% 17.50% | 33 11.79% 29.29% | 46 16.43% 45.71% | 35 12.50% 58.21% | 39 13.93% 72.14% | 39 13.93% 86.07% | 39 13.93% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Ack::total 280 -system.ruby.L1Cache_Controller.IS.Data | 2076 12.31% 12.31% | 2080 12.33% 24.64% | 2047 12.13% 36.77% | 2101 12.45% 49.22% | 2132 12.64% 61.86% | 2164 12.83% 74.69% | 2122 12.58% 87.27% | 2148 12.73% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 16870 -system.ruby.L1Cache_Controller.IS.Shared_Data | 1192 12.40% 12.40% | 1173 12.20% 24.60% | 1206 12.55% 37.15% | 1220 12.69% 49.84% | 1176 12.23% 62.07% | 1276 13.27% 75.35% | 1184 12.32% 87.66% | 1186 12.34% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Data::total 9613 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47296 12.53% 12.53% | 47254 12.52% 25.04% | 47273 12.52% 37.56% | 47270 12.52% 50.08% | 46891 12.42% 62.50% | 47258 12.52% 75.02% | 47089 12.47% 87.49% | 47221 12.51% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 377552 -system.ruby.L1Cache_Controller.SS.Load | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1654 14.08% 14.08% | 1334 11.36% 25.44% | 1564 13.32% 38.75% | 1401 11.93% 50.68% | 1584 13.49% 64.17% | 1430 12.17% 76.34% | 1334 11.36% 87.70% | 1445 12.30% 100.00% +system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 11746 +system.ruby.L1Cache_Controller.ISM.Ack | 3080 13.09% 13.09% | 2971 12.63% 25.72% | 2974 12.64% 38.36% | 2882 12.25% 50.61% | 2947 12.52% 63.13% | 3048 12.95% 76.08% | 2844 12.09% 88.17% | 2783 11.83% 100.00% +system.ruby.L1Cache_Controller.ISM.Ack::total 23529 +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1386 12.77% 12.77% | 1393 12.83% 25.60% | 1413 13.02% 38.62% | 1315 12.12% 50.74% | 1321 12.17% 62.91% | 1338 12.33% 75.23% | 1328 12.24% 87.47% | 1360 12.53% 100.00% +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10854 +system.ruby.L1Cache_Controller.M_W.Load | 1 5.00% 5.00% | 2 10.00% 15.00% | 3 15.00% 30.00% | 3 15.00% 45.00% | 5 25.00% 70.00% | 4 20.00% 90.00% | 1 5.00% 95.00% | 1 5.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 20 +system.ruby.L1Cache_Controller.M_W.Store | 2 12.50% 12.50% | 1 6.25% 18.75% | 3 18.75% 37.50% | 4 25.00% 62.50% | 4 25.00% 87.50% | 1 6.25% 93.75% | 0 0.00% 93.75% | 1 6.25% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 16 +system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 74211 12.51% 12.51% | 73890 12.45% 24.96% | 73594 12.40% 37.36% | 74076 12.48% 49.84% | 74874 12.62% 62.46% | 75025 12.64% 75.10% | 73018 12.30% 87.40% | 74757 12.60% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 593445 +system.ruby.L1Cache_Controller.M_W.Ack | 97926 12.44% 12.44% | 97718 12.42% 24.86% | 98794 12.55% 37.42% | 98518 12.52% 49.94% | 99085 12.59% 62.53% | 98436 12.51% 75.04% | 97279 12.36% 87.40% | 99172 12.60% 100.00% +system.ruby.L1Cache_Controller.M_W.Ack::total 786928 +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47035 12.45% 12.45% | 47328 12.53% 24.98% | 47103 12.47% 37.45% | 47380 12.54% 49.99% | 47173 12.49% 62.48% | 47199 12.49% 74.98% | 47210 12.50% 87.47% | 47319 12.53% 100.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 377747 +system.ruby.L1Cache_Controller.MM_W.Load | 1 5.26% 5.26% | 3 15.79% 21.05% | 1 5.26% 26.32% | 3 15.79% 42.11% | 4 21.05% 63.16% | 2 10.53% 73.68% | 3 15.79% 89.47% | 2 10.53% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 19 +system.ruby.L1Cache_Controller.MM_W.Store | 3 42.86% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 7 +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 42529 12.65% 12.65% | 42714 12.70% 25.35% | 41979 12.48% 37.83% | 41933 12.47% 50.30% | 42121 12.53% 62.83% | 41515 12.35% 75.17% | 41809 12.43% 87.61% | 41681 12.39% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 336281 +system.ruby.L1Cache_Controller.MM_W.Ack | 55486 12.51% 12.51% | 55882 12.60% 25.11% | 54740 12.34% 37.45% | 55509 12.52% 49.97% | 56002 12.63% 62.60% | 55351 12.48% 75.08% | 55541 12.52% 87.60% | 54986 12.40% 100.00% +system.ruby.L1Cache_Controller.MM_W.Ack::total 443497 +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26636 12.49% 12.49% | 26786 12.56% 25.04% | 26871 12.60% 37.64% | 26338 12.35% 49.99% | 26898 12.61% 62.60% | 26627 12.48% 75.08% | 26639 12.49% 87.57% | 26516 12.43% 100.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 213311 +system.ruby.L1Cache_Controller.IS.L1_to_L2 | 498344 12.45% 12.45% | 499845 12.49% 24.94% | 498249 12.45% 37.39% | 500193 12.50% 49.89% | 497512 12.43% 62.32% | 502981 12.57% 74.89% | 502709 12.56% 87.45% | 502230 12.55% 100.00% +system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4002063 +system.ruby.L1Cache_Controller.IS.Other_GETX | 113 12.07% 12.07% | 119 12.71% 24.79% | 115 12.29% 37.07% | 109 11.65% 48.72% | 125 13.35% 62.07% | 123 13.14% 75.21% | 120 12.82% 88.03% | 112 11.97% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETX::total 936 +system.ruby.L1Cache_Controller.IS.Other_GETS | 228 14.04% 14.04% | 201 12.38% 26.42% | 192 11.82% 38.24% | 206 12.68% 50.92% | 192 11.82% 62.75% | 195 12.01% 74.75% | 229 14.10% 88.85% | 181 11.15% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETS::total 1624 +system.ruby.L1Cache_Controller.IS.Ack | 244442 12.45% 12.45% | 246481 12.56% 25.01% | 244196 12.44% 37.45% | 245842 12.52% 49.98% | 244425 12.45% 62.43% | 245791 12.52% 74.95% | 246310 12.55% 87.50% | 245330 12.50% 100.00% +system.ruby.L1Cache_Controller.IS.Ack::total 1962817 +system.ruby.L1Cache_Controller.IS.Shared_Ack | 33 10.93% 10.93% | 41 13.58% 24.50% | 32 10.60% 35.10% | 36 11.92% 47.02% | 41 13.58% 60.60% | 49 16.23% 76.82% | 35 11.59% 88.41% | 35 11.59% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Ack::total 302 +system.ruby.L1Cache_Controller.IS.Data | 2045 12.34% 12.34% | 2085 12.58% 24.93% | 2074 12.52% 37.45% | 2001 12.08% 49.52% | 2142 12.93% 62.45% | 2131 12.86% 75.31% | 2029 12.25% 87.56% | 2061 12.44% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 16568 +system.ruby.L1Cache_Controller.IS.Shared_Data | 1205 12.51% 12.51% | 1184 12.29% 24.80% | 1195 12.41% 37.21% | 1186 12.31% 49.52% | 1199 12.45% 61.97% | 1238 12.85% 74.82% | 1198 12.44% 87.26% | 1227 12.74% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Data::total 9632 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47037 12.45% 12.45% | 47329 12.53% 24.98% | 47106 12.47% 37.45% | 47384 12.54% 49.99% | 47177 12.49% 62.48% | 47200 12.49% 74.98% | 47210 12.50% 87.47% | 47320 12.53% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 377763 +system.ruby.L1Cache_Controller.SS.Load | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.SS.Load::total 1 -system.ruby.L1Cache_Controller.SS.L1_to_L2 | 4391 11.77% 11.77% | 4934 13.23% 25.00% | 4841 12.98% 37.98% | 4629 12.41% 50.38% | 4379 11.74% 62.12% | 4778 12.81% 74.93% | 4436 11.89% 86.82% | 4915 13.18% 100.00% -system.ruby.L1Cache_Controller.SS.L1_to_L2::total 37303 -system.ruby.L1Cache_Controller.SS.Ack | 6760 12.16% 12.16% | 6850 12.32% 24.48% | 6884 12.38% 36.86% | 6878 12.37% 49.24% | 6979 12.55% 61.79% | 7194 12.94% 74.73% | 6892 12.40% 87.13% | 7157 12.87% 100.00% -system.ruby.L1Cache_Controller.SS.Ack::total 55594 -system.ruby.L1Cache_Controller.SS.Shared_Ack | 10 10.53% 10.53% | 13 13.68% 24.21% | 8 8.42% 32.63% | 8 8.42% 41.05% | 11 11.58% 52.63% | 10 10.53% 63.16% | 18 18.95% 82.11% | 17 17.89% 100.00% -system.ruby.L1Cache_Controller.SS.Shared_Ack::total 95 -system.ruby.L1Cache_Controller.SS.All_acks | 1220 12.28% 12.28% | 1207 12.15% 24.43% | 1244 12.52% 36.95% | 1265 12.73% 49.68% | 1214 12.22% 61.90% | 1317 13.26% 75.16% | 1235 12.43% 87.59% | 1233 12.41% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks::total 9935 -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2048 12.38% 12.38% | 2046 12.36% 24.74% | 2009 12.14% 36.88% | 2056 12.42% 49.31% | 2094 12.65% 61.96% | 2123 12.83% 74.79% | 2071 12.52% 87.30% | 2101 12.70% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16548 -system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Load::total 1 -system.ruby.L1Cache_Controller.OI.Store | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.OI.Store::total 3 -system.ruby.L1Cache_Controller.OI.Other_GETX | 4 16.67% 16.67% | 3 12.50% 29.17% | 4 16.67% 45.83% | 3 12.50% 58.33% | 3 12.50% 70.83% | 3 12.50% 83.33% | 3 12.50% 95.83% | 1 4.17% 100.00% -system.ruby.L1Cache_Controller.OI.Other_GETX::total 24 -system.ruby.L1Cache_Controller.OI.Other_GETS | 0 0.00% 0.00% | 3 15.00% 15.00% | 3 15.00% 30.00% | 5 25.00% 55.00% | 1 5.00% 60.00% | 1 5.00% 65.00% | 1 5.00% 70.00% | 6 30.00% 100.00% -system.ruby.L1Cache_Controller.OI.Other_GETS::total 20 -system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 20.00% 20.00% | 2 10.00% 30.00% | 2 10.00% 40.00% | 3 15.00% 55.00% | 1 5.00% 60.00% | 2 10.00% 70.00% | 3 15.00% 85.00% | 3 15.00% 100.00% -system.ruby.L1Cache_Controller.OI.Merged_GETS::total 20 -system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1196 12.70% 12.70% | 1164 12.36% 25.06% | 1149 12.20% 37.26% | 1191 12.65% 49.91% | 1150 12.21% 62.12% | 1198 12.72% 74.84% | 1221 12.97% 87.81% | 1148 12.19% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9417 -system.ruby.L1Cache_Controller.MI.Load | 13 10.57% 10.57% | 20 16.26% 26.83% | 18 14.63% 41.46% | 14 11.38% 52.85% | 11 8.94% 61.79% | 25 20.33% 82.11% | 9 7.32% 89.43% | 13 10.57% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 123 -system.ruby.L1Cache_Controller.MI.Store | 5 9.80% 9.80% | 3 5.88% 15.69% | 8 15.69% 31.37% | 3 5.88% 37.25% | 12 23.53% 60.78% | 10 19.61% 80.39% | 3 5.88% 86.27% | 7 13.73% 100.00% -system.ruby.L1Cache_Controller.MI.Store::total 51 -system.ruby.L1Cache_Controller.MI.Other_GETX | 162 11.43% 11.43% | 181 12.77% 24.21% | 181 12.77% 36.98% | 182 12.84% 49.82% | 184 12.99% 62.81% | 181 12.77% 75.58% | 156 11.01% 86.59% | 190 13.41% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETX::total 1417 -system.ruby.L1Cache_Controller.MI.Other_GETS | 315 12.90% 12.90% | 277 11.35% 24.25% | 281 11.51% 35.76% | 327 13.40% 49.16% | 292 11.96% 61.12% | 316 12.95% 74.07% | 342 14.01% 88.08% | 291 11.92% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETS::total 2441 -system.ruby.L1Cache_Controller.MI.Merged_GETS | 13 12.04% 12.04% | 13 12.04% 24.07% | 10 9.26% 33.33% | 5 4.63% 37.96% | 15 13.89% 51.85% | 12 11.11% 62.96% | 18 16.67% 79.63% | 22 20.37% 100.00% -system.ruby.L1Cache_Controller.MI.Merged_GETS::total 108 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72897 12.55% 12.55% | 72530 12.49% 25.05% | 72652 12.51% 37.56% | 72680 12.52% 50.08% | 72470 12.48% 62.56% | 72355 12.46% 75.02% | 72681 12.52% 87.54% | 72370 12.46% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 580635 -system.ruby.L1Cache_Controller.II.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.II.Store::total 1 -system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Other_GETX::total 3 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 166 11.53% 11.53% | 184 12.78% 24.31% | 185 12.85% 37.15% | 185 12.85% 50.00% | 187 12.99% 62.99% | 184 12.78% 75.76% | 158 10.97% 86.74% | 191 13.26% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1440 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1 -system.ruby.L1Cache_Controller.IT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IT.Load::total 1 -system.ruby.L1Cache_Controller.IT.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IT.Store::total 2 -system.ruby.L1Cache_Controller.IT.L1_to_L2 | 10 22.73% 22.73% | 0 0.00% 22.73% | 0 0.00% 22.73% | 7 15.91% 38.64% | 15 34.09% 72.73% | 7 15.91% 88.64% | 5 11.36% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IT.L1_to_L2::total 44 -system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 2 20.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 1 10.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.L1Cache_Controller.SS.L1_to_L2 | 5041 12.61% 12.61% | 5297 13.25% 25.86% | 4845 12.12% 37.98% | 4861 12.16% 50.14% | 5186 12.97% 63.12% | 4925 12.32% 75.44% | 4836 12.10% 87.53% | 4983 12.47% 100.00% +system.ruby.L1Cache_Controller.SS.L1_to_L2::total 39974 +system.ruby.L1Cache_Controller.SS.Ack | 7136 12.32% 12.32% | 7580 13.08% 25.40% | 7139 12.32% 37.72% | 7109 12.27% 49.99% | 7501 12.95% 62.94% | 7189 12.41% 75.35% | 7032 12.14% 87.49% | 7250 12.51% 100.00% +system.ruby.L1Cache_Controller.SS.Ack::total 57936 +system.ruby.L1Cache_Controller.SS.Shared_Ack | 11 9.02% 9.02% | 23 18.85% 27.87% | 17 13.93% 41.80% | 19 15.57% 57.38% | 17 13.93% 71.31% | 13 10.66% 81.97% | 13 10.66% 92.62% | 9 7.38% 100.00% +system.ruby.L1Cache_Controller.SS.Shared_Ack::total 122 +system.ruby.L1Cache_Controller.SS.All_acks | 1242 12.43% 12.43% | 1233 12.34% 24.77% | 1238 12.39% 37.16% | 1235 12.36% 49.52% | 1246 12.47% 61.99% | 1291 12.92% 74.91% | 1239 12.40% 87.31% | 1268 12.69% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks::total 9992 +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2008 12.39% 12.39% | 2036 12.56% 24.95% | 2031 12.53% 37.48% | 1952 12.04% 49.52% | 2095 12.93% 62.45% | 2078 12.82% 75.27% | 1988 12.27% 87.54% | 2020 12.46% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16208 +system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Load::total 2 +system.ruby.L1Cache_Controller.OI.Other_GETX | 1 6.25% 6.25% | 1 6.25% 12.50% | 4 25.00% 37.50% | 2 12.50% 50.00% | 2 12.50% 62.50% | 2 12.50% 75.00% | 2 12.50% 87.50% | 2 12.50% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETX::total 16 +system.ruby.L1Cache_Controller.OI.Other_GETS | 2 7.41% 7.41% | 3 11.11% 18.52% | 5 18.52% 37.04% | 4 14.81% 51.85% | 3 11.11% 62.96% | 3 11.11% 74.07% | 2 7.41% 81.48% | 5 18.52% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETS::total 27 +system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 16.67% 16.67% | 4 16.67% 33.33% | 5 20.83% 54.17% | 3 12.50% 66.67% | 1 4.17% 70.83% | 1 4.17% 75.00% | 3 12.50% 87.50% | 3 12.50% 100.00% +system.ruby.L1Cache_Controller.OI.Merged_GETS::total 24 +system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1199 12.70% 12.70% | 1194 12.64% 25.34% | 1128 11.94% 37.28% | 1165 12.34% 49.62% | 1171 12.40% 62.02% | 1158 12.26% 74.28% | 1204 12.75% 87.03% | 1225 12.97% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9444 +system.ruby.L1Cache_Controller.MI.Load | 15 12.82% 12.82% | 22 18.80% 31.62% | 10 8.55% 40.17% | 11 9.40% 49.57% | 19 16.24% 65.81% | 10 8.55% 74.36% | 12 10.26% 84.62% | 18 15.38% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 117 +system.ruby.L1Cache_Controller.MI.Store | 13 16.46% 16.46% | 7 8.86% 25.32% | 9 11.39% 36.71% | 4 5.06% 41.77% | 8 10.13% 51.90% | 14 17.72% 69.62% | 18 22.78% 92.41% | 6 7.59% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 79 +system.ruby.L1Cache_Controller.MI.Other_GETX | 197 13.47% 13.47% | 173 11.83% 25.31% | 170 11.63% 36.94% | 190 13.00% 49.93% | 203 13.89% 63.82% | 188 12.86% 76.68% | 151 10.33% 87.00% | 190 13.00% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETX::total 1462 +system.ruby.L1Cache_Controller.MI.Other_GETS | 348 13.58% 13.58% | 322 12.56% 26.14% | 310 12.10% 38.24% | 294 11.47% 49.71% | 337 13.15% 62.86% | 282 11.00% 73.86% | 343 13.38% 87.24% | 327 12.76% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETS::total 2563 +system.ruby.L1Cache_Controller.MI.Merged_GETS | 14 12.28% 12.28% | 17 14.91% 27.19% | 16 14.04% 41.23% | 14 12.28% 53.51% | 15 13.16% 66.67% | 16 14.04% 80.70% | 12 10.53% 91.23% | 10 8.77% 100.00% +system.ruby.L1Cache_Controller.MI.Merged_GETS::total 114 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72569 12.48% 12.48% | 72904 12.54% 25.01% | 72891 12.53% 37.55% | 72442 12.46% 50.00% | 72864 12.53% 62.53% | 72649 12.49% 75.02% | 72638 12.49% 87.51% | 72642 12.49% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 581599 +system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.II.Other_GETX::total 2 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 198 13.40% 13.40% | 174 11.77% 25.17% | 174 11.77% 36.94% | 192 12.99% 49.93% | 205 13.87% 63.80% | 190 12.86% 76.66% | 153 10.35% 87.01% | 192 12.99% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1478 +system.ruby.L1Cache_Controller.IT.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% +system.ruby.L1Cache_Controller.IT.Load::total 6 +system.ruby.L1Cache_Controller.IT.L1_to_L2 | 0 0.00% 0.00% | 10 18.87% 18.87% | 0 0.00% 18.87% | 0 0.00% 18.87% | 7 13.21% 32.08% | 0 0.00% 32.08% | 34 64.15% 96.23% | 2 3.77% 100.00% +system.ruby.L1Cache_Controller.IT.L1_to_L2::total 53 +system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 1 10.00% 10.00% | 1 10.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 3 30.00% 100.00% system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total 10 -system.ruby.L1Cache_Controller.ST.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.ST.Load::total 1 -system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.Load | 1 14.29% 14.29% | 2 28.57% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.Load::total 7 +system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.ST.Store::total 3 -system.ruby.L1Cache_Controller.ST.L1_to_L2 | 9 25.71% 25.71% | 0 0.00% 25.71% | 7 20.00% 45.71% | 1 2.86% 48.57% | 8 22.86% 71.43% | 0 0.00% 71.43% | 8 22.86% 94.29% | 2 5.71% 100.00% -system.ruby.L1Cache_Controller.ST.L1_to_L2::total 35 -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 1 7.14% 7.14% | 2 14.29% 21.43% | 2 14.29% 35.71% | 2 14.29% 50.00% | 4 28.57% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00% -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 14 -system.ruby.L1Cache_Controller.OT.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OT.Store::total 1 -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 5 -system.ruby.L1Cache_Controller.MT.Load | 15 16.30% 16.30% | 8 8.70% 25.00% | 11 11.96% 36.96% | 13 14.13% 51.09% | 17 18.48% 69.57% | 8 8.70% 78.26% | 14 15.22% 93.48% | 6 6.52% 100.00% -system.ruby.L1Cache_Controller.MT.Load::total 92 -system.ruby.L1Cache_Controller.MT.Store | 10 15.38% 15.38% | 10 15.38% 30.77% | 6 9.23% 40.00% | 13 20.00% 60.00% | 6 9.23% 69.23% | 9 13.85% 83.08% | 8 12.31% 95.38% | 3 4.62% 100.00% -system.ruby.L1Cache_Controller.MT.Store::total 65 -system.ruby.L1Cache_Controller.MT.L1_to_L2 | 168 14.13% 14.13% | 216 18.17% 32.30% | 73 6.14% 38.44% | 172 14.47% 52.90% | 184 15.48% 68.38% | 141 11.86% 80.24% | 120 10.09% 90.33% | 115 9.67% 100.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1189 -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 42 13.55% 13.55% | 42 13.55% 27.10% | 30 9.68% 36.77% | 44 14.19% 50.97% | 45 14.52% 65.48% | 35 11.29% 76.77% | 39 12.58% 89.35% | 33 10.65% 100.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 310 -system.ruby.L1Cache_Controller.MMT.Load | 13 19.40% 19.40% | 7 10.45% 29.85% | 9 13.43% 43.28% | 7 10.45% 53.73% | 5 7.46% 61.19% | 8 11.94% 73.13% | 10 14.93% 88.06% | 8 11.94% 100.00% -system.ruby.L1Cache_Controller.MMT.Load::total 67 -system.ruby.L1Cache_Controller.MMT.Store | 6 17.14% 17.14% | 6 17.14% 34.29% | 3 8.57% 42.86% | 5 14.29% 57.14% | 4 11.43% 68.57% | 6 17.14% 85.71% | 3 8.57% 94.29% | 2 5.71% 100.00% -system.ruby.L1Cache_Controller.MMT.Store::total 35 -system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 149 20.03% 20.03% | 46 6.18% 26.21% | 86 11.56% 37.77% | 85 11.42% 49.19% | 91 12.23% 61.42% | 136 18.28% 79.70% | 95 12.77% 92.47% | 56 7.53% 100.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 744 -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 37 16.23% 16.23% | 35 15.35% 31.58% | 26 11.40% 42.98% | 28 12.28% 55.26% | 24 10.53% 65.79% | 29 12.72% 78.51% | 28 12.28% 90.79% | 21 9.21% 100.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 228 -system.ruby.Directory_Controller.GETX 227092 0.00% 0.00% -system.ruby.Directory_Controller.GETS 409941 0.00% 0.00% -system.ruby.Directory_Controller.PUT 604133 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 1440 0.00% 0.00% -system.ruby.Directory_Controller.UnblockS 26482 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 600822 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Clean 8072 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Dirty 1345 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 361114 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 219521 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 607003 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220866 0.00% 0.00% -system.ruby.Directory_Controller.All_Unblocks 990 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETX 86 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETS 100 0.00% 0.00% -system.ruby.Directory_Controller.NX.PUT 10824 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 7097 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 12034 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 580691 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 9322 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 16870 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 206773 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 374058 0.00% 0.00% -system.ruby.Directory_Controller.E.PUT 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETX 541 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETS 990 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 12396 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockS 8550 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 599363 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.PUT 17 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockS 31 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockM 510 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.PUT 28 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockS 41 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockM 949 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETX 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETS 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.PUT 105 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.UnblockS 991 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 990 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETX 9 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETS 21 0.00% 0.00% -system.ruby.Directory_Controller.O_B.UnblockS 16869 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETX 1892 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETS 3482 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 590133 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETX 63 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETS 87 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.Memory_Data 16870 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 1268 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 2222 0.00% 0.00% -system.ruby.Directory_Controller.WB.PUT 71 0.00% 0.00% -system.ruby.Directory_Controller.WB.Unblock 1440 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Clean 8072 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Dirty 1345 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 361114 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 219521 0.00% 0.00% -system.ruby.Directory_Controller.WB_O_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1345 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETX 38 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 71 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 219521 0.00% 0.00% +system.ruby.L1Cache_Controller.ST.L1_to_L2 | 8 8.08% 8.08% | 21 21.21% 29.29% | 6 6.06% 35.35% | 20 20.20% 55.56% | 26 26.26% 81.82% | 7 7.07% 88.89% | 11 11.11% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.L1_to_L2::total 99 +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 2 7.14% 7.14% | 7 25.00% 32.14% | 2 7.14% 39.29% | 6 21.43% 60.71% | 4 14.29% 75.00% | 3 10.71% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 28 +system.ruby.L1Cache_Controller.OT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.OT.Load::total 3 +system.ruby.L1Cache_Controller.OT.L1_to_L2 | 10 27.03% 27.03% | 0 0.00% 27.03% | 1 2.70% 29.73% | 0 0.00% 29.73% | 20 54.05% 83.78% | 0 0.00% 83.78% | 0 0.00% 83.78% | 6 16.22% 100.00% +system.ruby.L1Cache_Controller.OT.L1_to_L2::total 37 +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 1 11.11% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 9 +system.ruby.L1Cache_Controller.MT.Load | 8 7.48% 7.48% | 12 11.21% 18.69% | 12 11.21% 29.91% | 21 19.63% 49.53% | 13 12.15% 61.68% | 9 8.41% 70.09% | 14 13.08% 83.18% | 18 16.82% 100.00% +system.ruby.L1Cache_Controller.MT.Load::total 107 +system.ruby.L1Cache_Controller.MT.Store | 6 13.04% 13.04% | 4 8.70% 21.74% | 5 10.87% 32.61% | 9 19.57% 52.17% | 8 17.39% 69.57% | 6 13.04% 82.61% | 7 15.22% 97.83% | 1 2.17% 100.00% +system.ruby.L1Cache_Controller.MT.Store::total 46 +system.ruby.L1Cache_Controller.MT.L1_to_L2 | 162 14.36% 14.36% | 102 9.04% 23.40% | 101 8.95% 32.36% | 198 17.55% 49.91% | 105 9.31% 59.22% | 124 10.99% 70.21% | 181 16.05% 86.26% | 155 13.74% 100.00% +system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1128 +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 39 12.30% 12.30% | 35 11.04% 23.34% | 34 10.73% 34.07% | 45 14.20% 48.26% | 36 11.36% 59.62% | 34 10.73% 70.35% | 43 13.56% 83.91% | 51 16.09% 100.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 317 +system.ruby.L1Cache_Controller.MMT.Load | 12 18.75% 18.75% | 5 7.81% 26.56% | 7 10.94% 37.50% | 5 7.81% 45.31% | 10 15.62% 60.94% | 7 10.94% 71.88% | 10 15.62% 87.50% | 8 12.50% 100.00% +system.ruby.L1Cache_Controller.MMT.Load::total 64 +system.ruby.L1Cache_Controller.MMT.Store | 5 13.51% 13.51% | 8 21.62% 35.14% | 3 8.11% 43.24% | 2 5.41% 48.65% | 3 8.11% 56.76% | 8 21.62% 78.38% | 6 16.22% 94.59% | 2 5.41% 100.00% +system.ruby.L1Cache_Controller.MMT.Store::total 37 +system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 86 13.21% 13.21% | 96 14.75% 27.96% | 55 8.45% 36.41% | 38 5.84% 42.24% | 69 10.60% 52.84% | 110 16.90% 69.74% | 148 22.73% 92.47% | 49 7.53% 100.00% +system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 651 +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 24 12.06% 12.06% | 21 10.55% 22.61% | 24 12.06% 34.67% | 19 9.55% 44.22% | 28 14.07% 58.29% | 24 12.06% 70.35% | 37 18.59% 88.94% | 22 11.06% 100.00% +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 199 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 35e569592..6ebb8a63f 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007640 # Number of seconds simulated -sim_ticks 7640346 # Number of ticks simulated -final_tick 7640346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007583 # Number of seconds simulated +sim_ticks 7582589 # Number of ticks simulated +final_tick 7582589 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 121940 # Simulator tick rate (ticks/s) -host_mem_usage 688424 # Number of bytes of host memory used -host_seconds 62.66 # Real time elapsed on the host +host_tick_rate 210657 # Simulator tick rate (ticks/s) +host_mem_usage 700452 # Number of bytes of host memory used +host_seconds 36.00 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39630976 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39630976 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39629440 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 39629440 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 619234 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 619234 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 619210 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 619210 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 5187065612 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 5187065612 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 5186864574 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 5186864574 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 10373930186 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 10373930186 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 619241 # Number of read requests accepted -system.mem_ctrls.writeReqs 619210 # Number of write requests accepted -system.mem_ctrls.readBursts 619241 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 619210 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 38759744 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 871680 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 39127168 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39631424 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 39629440 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 13620 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 7808 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39656192 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39656192 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39654720 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 39654720 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 619628 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 619628 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 619605 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 619605 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 5229901291 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 5229901291 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 5229707162 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 5229707162 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 10459608453 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 10459608453 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 619636 # Number of read requests accepted +system.mem_ctrls.writeReqs 619605 # Number of write requests accepted +system.mem_ctrls.readBursts 619636 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 619605 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38799872 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 856832 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 39161920 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39656704 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 39654720 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 13388 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 7653 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 75930 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 75800 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 75762 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 75572 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76043 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 75649 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 75203 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 75662 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76050 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 75867 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 75889 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76027 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 75490 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 75499 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 75763 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 75663 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 76645 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 76483 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 76463 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 76307 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 76789 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 76366 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 75891 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 76418 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 76733 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 76551 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 76672 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 76745 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 76164 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 76242 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 76436 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 76362 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,53 +68,53 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 1386 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 7640332 # Total gap between requests +system.mem_ctrls.numWrRetry 1316 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 7582575 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 619241 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 619636 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 619210 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 39 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 371 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 1410 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 4295 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 10092 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 18847 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 28680 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 38557 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 46760 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 50653 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 50719 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 46401 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 41225 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 35682 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 30672 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 27887 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 25992 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 24547 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 23522 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 22441 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 20725 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 18091 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 14601 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 10683 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 6775 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 3686 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 1571 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 534 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 134 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 24 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 5 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 619605 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 32 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 346 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1534 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 4652 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 10530 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 19183 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 29616 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 40220 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 47540 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 50473 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 49842 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 45472 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 40125 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 34810 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 30290 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 27279 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 25552 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 24486 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 23585 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 22568 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 20966 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 18413 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 14793 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 10821 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 6989 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 3723 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 1662 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 594 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 130 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 20 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see @@ -147,514 +147,519 @@ system.mem_ctrls.wrQLenPdf::27 1 # Wh system.mem_ctrls.wrQLenPdf::28 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 177 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 596 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 1371 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 2500 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 4217 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 6791 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 10074 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 14120 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 17497 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 20411 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 22971 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 24800 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 25688 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 26455 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 27360 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 29089 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 30783 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 32098 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 33250 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 34420 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 35549 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 38553 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 56835 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 47905 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 21239 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 16122 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 12076 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 8373 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 4889 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 2426 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 2690 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 244065 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 319.119448 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 243.936703 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 225.750518 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 33066 13.55% 13.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 74051 30.34% 43.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 47584 19.50% 63.39% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 35781 14.66% 78.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 24395 10.00% 88.04% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 14385 5.89% 93.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7558 3.10% 97.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3779 1.55% 98.58% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 3466 1.42% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 244065 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 38211 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.849389 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 8.733627 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 11.471953 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-3 12664 33.14% 33.14% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::4-7 1717 4.49% 37.64% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-11 411 1.08% 38.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-15 217 0.57% 39.28% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-19 3256 8.52% 47.80% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-23 6962 18.22% 66.02% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-27 6191 16.20% 82.22% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::28-31 5489 14.36% 96.59% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-35 1268 3.32% 99.91% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-39 35 0.09% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-83 1 0.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 38211 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 38210 # Writes before turning the bus around for reads +system.mem_ctrls.wrQLenPdf::31 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 237 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 662 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 1409 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 2720 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 4680 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 7358 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 11234 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 14859 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 18277 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 20903 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 23502 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 25176 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 26140 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 27165 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 28236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 29242 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 30684 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 31940 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 34045 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 34472 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 35205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 37597 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 55809 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 46546 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 20844 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 15539 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 11583 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 6918 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 4170 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 2108 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 2589 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 245657 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 317.354620 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 242.734089 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 224.484514 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 33363 13.58% 13.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 75184 30.61% 44.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 48043 19.56% 63.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 35710 14.54% 78.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 24482 9.97% 88.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14306 5.82% 94.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7560 3.08% 97.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3712 1.51% 98.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 3297 1.34% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 245657 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 38245 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.851693 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 8.811529 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 11.405114 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-3 12517 32.73% 32.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::4-7 1776 4.64% 37.37% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-11 493 1.29% 38.66% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-15 184 0.48% 39.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-19 3224 8.43% 47.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-23 7216 18.87% 66.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-27 6295 16.46% 82.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::28-31 5266 13.77% 96.67% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-35 1235 3.23% 99.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-39 38 0.10% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::68-71 1 0.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 38245 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 38244 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 38210 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 38210 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 113136166 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 124642965 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3028105 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 186.81 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::16 38244 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 38244 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 111772725 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 123291437 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3031240 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 184.37 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 205.81 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 5073.04 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 5121.13 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 5187.12 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 5186.86 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 203.37 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 5116.97 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 5164.72 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 5229.97 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 5229.71 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 79.64 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 39.63 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 40.01 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 18.22 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 53.30 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 371319 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 601592 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 61.31 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 98.40 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 6.17 # Average gap between requests -system.mem_ctrls.pageHitRate 79.94 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 12 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 255060 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 7383304 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1844632440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 1024795800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7555941120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6336921600 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 498897360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 498897360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 5201932860 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 165066984 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 19918200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 4438221600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 22483039380 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 5102185944 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 2943.437268 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.968596 # Core power per rank (mW) +system.mem_ctrls.busUtil 80.33 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 39.98 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 40.35 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 18.20 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 53.15 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 370717 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 601771 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 61.15 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 98.34 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 6.12 # Average gap between requests +system.mem_ctrls.pageHitRate 79.83 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1855594440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1030885800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7559160960 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6338580480 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 494828880 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5163405192 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 16345200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 22458800952 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2964.435559 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 12 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 252980 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7323102 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 494828880 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 163720872 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4401999600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 5060549352 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.969023 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7323058 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 252980 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 99415 # number of read accesses completed +system.cpu0.num_writes 55396 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 99989 # number of read accesses completed +system.cpu1.num_writes 55766 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 55829 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99767 # number of read accesses completed +system.cpu3.num_writes 55101 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 99087 # number of read accesses completed +system.cpu4.num_writes 55181 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99334 # number of read accesses completed +system.cpu5.num_writes 55288 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 98895 # number of read accesses completed +system.cpu6.num_writes 55228 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 99279 # number of read accesses completed +system.cpu7.num_writes 55473 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 32 # delay histogram for all message system.ruby.delayHist::max_bucket 319 # delay histogram for all message -system.ruby.delayHist::samples 1259370 # delay histogram for all message -system.ruby.delayHist::mean 2.196570 # delay histogram for all message -system.ruby.delayHist::stdev 7.715497 # delay histogram for all message -system.ruby.delayHist | 1242104 98.63% 98.63% | 10923 0.87% 99.50% | 5617 0.45% 99.94% | 569 0.05% 99.99% | 127 0.01% 100.00% | 28 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1259370 # delay histogram for all message +system.ruby.delayHist::samples 1259803 # delay histogram for all message +system.ruby.delayHist::mean 2.138829 # delay histogram for all message +system.ruby.delayHist::stdev 7.497358 # delay histogram for all message +system.ruby.delayHist | 1243420 98.70% 98.70% | 10426 0.83% 99.53% | 5324 0.42% 99.95% | 510 0.04% 99.99% | 106 0.01% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1259803 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 627888 -system.ruby.outstanding_req_hist::mean 15.998458 -system.ruby.outstanding_req_hist::gmean 15.997196 -system.ruby.outstanding_req_hist::stdev 0.125735 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 24 0.00% 0.02% | 627760 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 627888 +system.ruby.outstanding_req_hist::samples 628107 +system.ruby.outstanding_req_hist::mean 15.998448 +system.ruby.outstanding_req_hist::gmean 15.997186 +system.ruby.outstanding_req_hist::stdev 0.125758 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 627972 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 628107 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 627760 -system.ruby.latency_hist::mean 1557.693635 -system.ruby.latency_hist::gmean 1534.797226 -system.ruby.latency_hist::stdev 267.213644 -system.ruby.latency_hist | 66 0.01% 0.01% | 7337 1.17% 1.18% | 304531 48.51% 49.69% | 288472 45.95% 95.64% | 27150 4.32% 99.97% | 204 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 627760 +system.ruby.latency_hist::samples 627979 +system.ruby.latency_hist::mean 1545.382761 +system.ruby.latency_hist::gmean 1522.867536 +system.ruby.latency_hist::stdev 263.957857 +system.ruby.latency_hist | 68 0.01% 0.01% | 7984 1.27% 1.28% | 316387 50.38% 51.66% | 279515 44.51% 96.17% | 23839 3.80% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 627979 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 627760 -system.ruby.miss_latency_hist::mean 1557.693635 -system.ruby.miss_latency_hist::gmean 1534.797226 -system.ruby.miss_latency_hist::stdev 267.213644 -system.ruby.miss_latency_hist | 66 0.01% 0.01% | 7337 1.17% 1.18% | 304531 48.51% 49.69% | 288472 45.95% 95.64% | 27150 4.32% 99.97% | 204 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 627760 -system.ruby.L1Cache.incomplete_times 8531 -system.ruby.Directory.incomplete_times 619225 -system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.cacheMemory.demand_misses 78662 # Number of cache demand misses -system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78662 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.cacheMemory.demand_misses 78584 # Number of cache demand misses -system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78584 # Number of cache demand accesses -system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.cacheMemory.demand_misses 78465 # Number of cache demand misses -system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78465 # Number of cache demand accesses -system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.cacheMemory.demand_misses 78643 # Number of cache demand misses -system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78643 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 627979 +system.ruby.miss_latency_hist::mean 1545.382761 +system.ruby.miss_latency_hist::gmean 1522.867536 +system.ruby.miss_latency_hist::stdev 263.957857 +system.ruby.miss_latency_hist | 68 0.01% 0.01% | 7984 1.27% 1.28% | 316387 50.38% 51.66% | 279515 44.51% 96.17% | 23839 3.80% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 627979 +system.ruby.L1Cache.incomplete_times 8356 +system.ruby.Directory.incomplete_times 619619 system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 78250 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78250 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 5.136551 -system.ruby.network.routers0.msg_count.Control::2 78250 -system.ruby.network.routers0.msg_count.Data::2 77666 -system.ruby.network.routers0.msg_count.Response_Data::4 79314 -system.ruby.network.routers0.msg_count.Writeback_Control::3 78731 -system.ruby.network.routers0.msg_bytes.Control::2 626000 -system.ruby.network.routers0.msg_bytes.Data::2 5591952 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5710608 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 629848 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 78629 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78629 # Number of cache demand accesses system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.cacheMemory.demand_misses 78453 # Number of cache demand misses -system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78453 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 5.150235 -system.ruby.network.routers1.msg_count.Control::2 78453 -system.ruby.network.routers1.msg_count.Data::2 77872 -system.ruby.network.routers1.msg_count.Response_Data::4 79526 -system.ruby.network.routers1.msg_count.Writeback_Control::3 78948 -system.ruby.network.routers1.msg_bytes.Control::2 627624 -system.ruby.network.routers1.msg_bytes.Data::2 5606784 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5725872 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 631584 +system.ruby.l1_cntrl1.cacheMemory.demand_misses 78616 # Number of cache demand misses +system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78616 # Number of cache demand accesses system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.cacheMemory.demand_misses 78358 # Number of cache demand misses -system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78358 # Number of cache demand accesses -system.ruby.network.routers2.percent_links_utilized 5.143052 -system.ruby.network.routers2.msg_count.Control::2 78358 -system.ruby.network.routers2.msg_count.Data::2 77773 -system.ruby.network.routers2.msg_count.Response_Data::4 79406 -system.ruby.network.routers2.msg_count.Writeback_Control::3 78822 -system.ruby.network.routers2.msg_bytes.Control::2 626864 -system.ruby.network.routers2.msg_bytes.Data::2 5599656 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5717232 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 630576 +system.ruby.l1_cntrl2.cacheMemory.demand_misses 78776 # Number of cache demand misses +system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78776 # Number of cache demand accesses system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.cacheMemory.demand_misses 78360 # Number of cache demand misses -system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78360 # Number of cache demand accesses -system.ruby.network.routers3.percent_links_utilized 5.142804 -system.ruby.network.routers3.msg_count.Control::2 78360 -system.ruby.network.routers3.msg_count.Data::2 77812 -system.ruby.network.routers3.msg_count.Response_Data::4 79359 -system.ruby.network.routers3.msg_count.Writeback_Control::3 78813 -system.ruby.network.routers3.msg_bytes.Control::2 626880 -system.ruby.network.routers3.msg_bytes.Data::2 5602464 -system.ruby.network.routers3.msg_bytes.Response_Data::4 5713848 -system.ruby.network.routers3.msg_bytes.Writeback_Control::3 630504 -system.ruby.network.routers4.percent_links_utilized 5.163339 -system.ruby.network.routers4.msg_count.Control::2 78660 -system.ruby.network.routers4.msg_count.Data::2 78072 -system.ruby.network.routers4.msg_count.Response_Data::4 79727 -system.ruby.network.routers4.msg_count.Writeback_Control::3 79138 -system.ruby.network.routers4.msg_bytes.Control::2 629280 -system.ruby.network.routers4.msg_bytes.Data::2 5621184 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5740344 -system.ruby.network.routers4.msg_bytes.Writeback_Control::3 633104 -system.ruby.network.routers5.percent_links_utilized 5.158644 -system.ruby.network.routers5.msg_count.Control::2 78584 -system.ruby.network.routers5.msg_count.Data::2 77942 -system.ruby.network.routers5.msg_count.Response_Data::4 79713 -system.ruby.network.routers5.msg_count.Writeback_Control::3 79074 -system.ruby.network.routers5.msg_bytes.Control::2 628672 -system.ruby.network.routers5.msg_bytes.Data::2 5611824 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5739336 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632592 -system.ruby.network.routers6.percent_links_utilized 5.151013 -system.ruby.network.routers6.msg_count.Control::2 78465 -system.ruby.network.routers6.msg_count.Data::2 77892 -system.ruby.network.routers6.msg_count.Response_Data::4 79530 -system.ruby.network.routers6.msg_count.Writeback_Control::3 78958 -system.ruby.network.routers6.msg_bytes.Control::2 627720 -system.ruby.network.routers6.msg_bytes.Data::2 5608224 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5726160 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 631664 -system.ruby.network.routers7.percent_links_utilized 5.162335 -system.ruby.network.routers7.msg_count.Control::2 78643 -system.ruby.network.routers7.msg_count.Data::2 78052 -system.ruby.network.routers7.msg_count.Response_Data::4 79716 -system.ruby.network.routers7.msg_count.Writeback_Control::3 79126 -system.ruby.network.routers7.msg_bytes.Control::2 629144 -system.ruby.network.routers7.msg_bytes.Data::2 5619744 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5739552 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 633008 -system.ruby.network.routers8.percent_links_utilized 40.705513 -system.ruby.network.routers8.msg_count.Control::2 627773 -system.ruby.network.routers8.msg_count.Data::2 623080 -system.ruby.network.routers8.msg_count.Response_Data::4 619230 -system.ruby.network.routers8.msg_count.Writeback_Control::3 631610 -system.ruby.network.routers8.msg_bytes.Control::2 5022184 -system.ruby.network.routers8.msg_bytes.Data::2 44861760 -system.ruby.network.routers8.msg_bytes.Response_Data::4 44584560 -system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5052880 -system.ruby.network.routers9.percent_links_utilized 9.101498 -system.ruby.network.routers9.msg_count.Control::2 627773 -system.ruby.network.routers9.msg_count.Data::2 623081 -system.ruby.network.routers9.msg_count.Response_Data::4 627760 -system.ruby.network.routers9.msg_count.Writeback_Control::3 631610 -system.ruby.network.routers9.msg_bytes.Control::2 5022184 -system.ruby.network.routers9.msg_bytes.Data::2 44861832 -system.ruby.network.routers9.msg_bytes.Response_Data::4 45198720 -system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5052880 -system.ruby.network.msg_count.Control 1883319 -system.ruby.network.msg_count.Data 1869242 -system.ruby.network.msg_count.Response_Data 1883281 -system.ruby.network.msg_count.Writeback_Control 1894830 -system.ruby.network.msg_byte.Control 15066552 -system.ruby.network.msg_byte.Data 134585424 -system.ruby.network.msg_byte.Response_Data 135596232 -system.ruby.network.msg_byte.Writeback_Control 15158640 +system.ruby.l1_cntrl3.cacheMemory.demand_misses 78236 # Number of cache demand misses +system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78236 # Number of cache demand accesses +system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.cacheMemory.demand_misses 78211 # Number of cache demand misses +system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78211 # Number of cache demand accesses +system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.cacheMemory.demand_misses 78653 # Number of cache demand misses +system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78653 # Number of cache demand accesses +system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.cacheMemory.demand_misses 78454 # Number of cache demand misses +system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78454 # Number of cache demand accesses +system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.cacheMemory.demand_misses 78418 # Number of cache demand misses +system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78418 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 99347 # number of read accesses completed -system.cpu0.num_writes 55561 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99174 # number of read accesses completed -system.cpu1.num_writes 55699 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100001 # number of read accesses completed -system.cpu2.num_writes 55396 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99891 # number of read accesses completed -system.cpu3.num_writes 55171 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99714 # number of read accesses completed -system.cpu4.num_writes 55703 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99497 # number of read accesses completed -system.cpu5.num_writes 55733 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99258 # number of read accesses completed -system.cpu6.num_writes 55713 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99613 # number of read accesses completed -system.cpu7.num_writes 55877 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers0.throttle0.link_utilization 5.123930 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78249 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78731 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5633928 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 629848 -system.ruby.network.routers0.throttle1.link_utilization 5.149171 -system.ruby.network.routers0.throttle1.msg_count.Control::2 78250 -system.ruby.network.routers0.throttle1.msg_count.Data::2 77666 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1065 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 626000 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5591952 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 76680 -system.ruby.network.routers1.throttle0.link_utilization 5.137189 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78450 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 78948 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5648400 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 631584 -system.ruby.network.routers1.throttle1.link_utilization 5.163281 -system.ruby.network.routers1.throttle1.msg_count.Control::2 78453 -system.ruby.network.routers1.throttle1.msg_count.Data::2 77872 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1076 -system.ruby.network.routers1.throttle1.msg_bytes.Control::2 627624 -system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5606784 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 77472 -system.ruby.network.routers2.throttle0.link_utilization 5.130867 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78357 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 78822 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5641704 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 630576 -system.ruby.network.routers2.throttle1.link_utilization 5.155238 -system.ruby.network.routers2.throttle1.msg_count.Control::2 78358 -system.ruby.network.routers2.throttle1.msg_count.Data::2 77773 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1049 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 626864 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5599656 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 75528 -system.ruby.network.routers3.throttle0.link_utilization 5.130887 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78358 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 78813 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5641776 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 630504 -system.ruby.network.routers3.throttle1.link_utilization 5.154721 -system.ruby.network.routers3.throttle1.msg_count.Control::2 78360 -system.ruby.network.routers3.throttle1.msg_count.Data::2 77812 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1001 -system.ruby.network.routers3.throttle1.msg_bytes.Control::2 626880 -system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5602464 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 72072 -system.ruby.network.routers4.throttle0.link_utilization 5.150742 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78659 -system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 79138 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5663448 -system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 633104 -system.ruby.network.routers4.throttle1.link_utilization 5.175937 -system.ruby.network.routers4.throttle1.msg_count.Control::2 78660 -system.ruby.network.routers4.throttle1.msg_count.Data::2 78072 -system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1068 -system.ruby.network.routers4.throttle1.msg_bytes.Control::2 629280 -system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5621184 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 76896 -system.ruby.network.routers5.throttle0.link_utilization 5.145729 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78581 -system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79074 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5657832 -system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632592 -system.ruby.network.routers5.throttle1.link_utilization 5.171559 -system.ruby.network.routers5.throttle1.msg_count.Control::2 78584 -system.ruby.network.routers5.throttle1.msg_count.Data::2 77942 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1132 -system.ruby.network.routers5.throttle1.msg_bytes.Control::2 628672 -system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5611824 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 81504 -system.ruby.network.routers6.throttle0.link_utilization 5.138079 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78464 -system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78958 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5649408 -system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 631664 -system.ruby.network.routers6.throttle1.link_utilization 5.163948 -system.ruby.network.routers6.throttle1.msg_count.Control::2 78465 -system.ruby.network.routers6.throttle1.msg_count.Data::2 77892 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1066 -system.ruby.network.routers6.throttle1.msg_bytes.Control::2 627720 -system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5608224 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 76752 -system.ruby.network.routers7.throttle0.link_utilization 5.149662 -system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78642 -system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 79126 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5662224 -system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 633008 -system.ruby.network.routers7.throttle1.link_utilization 5.175008 -system.ruby.network.routers7.throttle1.msg_count.Control::2 78643 -system.ruby.network.routers7.throttle1.msg_count.Data::2 78052 -system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1074 -system.ruby.network.routers7.throttle1.msg_bytes.Control::2 629144 -system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5619744 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 77328 -system.ruby.network.routers8.throttle0.link_utilization 40.806352 -system.ruby.network.routers8.throttle0.msg_count.Control::2 627773 -system.ruby.network.routers8.throttle0.msg_count.Data::2 623080 -system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5022184 -system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44861760 -system.ruby.network.routers8.throttle1.link_utilization 40.604673 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 619230 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 631610 -system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44584560 -system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5052880 -system.ruby.network.routers9.throttle0.link_utilization 5.123930 -system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78249 -system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 78731 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5633928 -system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 629848 -system.ruby.network.routers9.throttle1.link_utilization 5.137189 -system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78450 -system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 78948 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5648400 -system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 631584 -system.ruby.network.routers9.throttle2.link_utilization 5.130887 -system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78357 -system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 78822 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5641704 -system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 630576 -system.ruby.network.routers9.throttle3.link_utilization 5.130887 -system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78358 -system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 78813 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5641776 -system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 630504 -system.ruby.network.routers9.throttle4.link_utilization 5.150742 -system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78659 -system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 79138 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5663448 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 633104 -system.ruby.network.routers9.throttle5.link_utilization 5.145729 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78581 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79074 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5657832 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632592 -system.ruby.network.routers9.throttle6.link_utilization 5.138079 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78464 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78958 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5649408 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 631664 -system.ruby.network.routers9.throttle7.link_utilization 5.149662 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78642 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 79126 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5662224 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 633008 -system.ruby.network.routers9.throttle8.link_utilization 40.806378 -system.ruby.network.routers9.throttle8.msg_count.Control::2 627773 -system.ruby.network.routers9.throttle8.msg_count.Data::2 623081 -system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5022184 -system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44861832 +system.ruby.network.routers0.percent_links_utilized 5.200734 +system.ruby.network.routers0.msg_count.Control::2 78629 +system.ruby.network.routers0.msg_count.Data::2 78049 +system.ruby.network.routers0.msg_count.Response_Data::4 79691 +system.ruby.network.routers0.msg_count.Writeback_Control::3 79112 +system.ruby.network.routers0.msg_bytes.Control::2 629032 +system.ruby.network.routers0.msg_bytes.Data::2 5619528 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5737752 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 632896 +system.ruby.network.routers1.percent_links_utilized 5.199646 +system.ruby.network.routers1.msg_count.Control::2 78616 +system.ruby.network.routers1.msg_count.Data::2 78080 +system.ruby.network.routers1.msg_count.Response_Data::4 79627 +system.ruby.network.routers1.msg_count.Writeback_Control::3 79092 +system.ruby.network.routers1.msg_bytes.Control::2 628928 +system.ruby.network.routers1.msg_bytes.Data::2 5621760 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5733144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 632736 +system.ruby.network.routers2.percent_links_utilized 5.209992 +system.ruby.network.routers2.msg_count.Control::2 78776 +system.ruby.network.routers2.msg_count.Data::2 78168 +system.ruby.network.routers2.msg_count.Response_Data::4 79853 +system.ruby.network.routers2.msg_count.Writeback_Control::3 79247 +system.ruby.network.routers2.msg_bytes.Control::2 630208 +system.ruby.network.routers2.msg_bytes.Data::2 5628096 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5749416 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 633976 +system.ruby.network.routers3.percent_links_utilized 5.174657 +system.ruby.network.routers3.msg_count.Control::2 78236 +system.ruby.network.routers3.msg_count.Data::2 77624 +system.ruby.network.routers3.msg_count.Response_Data::4 79325 +system.ruby.network.routers3.msg_count.Writeback_Control::3 78715 +system.ruby.network.routers3.msg_bytes.Control::2 625888 +system.ruby.network.routers3.msg_bytes.Data::2 5588928 +system.ruby.network.routers3.msg_bytes.Response_Data::4 5711400 +system.ruby.network.routers3.msg_bytes.Writeback_Control::3 629720 +system.ruby.network.routers4.percent_links_utilized 5.172053 +system.ruby.network.routers4.msg_count.Control::2 78211 +system.ruby.network.routers4.msg_count.Data::2 77629 +system.ruby.network.routers4.msg_count.Response_Data::4 79241 +system.ruby.network.routers4.msg_count.Writeback_Control::3 78661 +system.ruby.network.routers4.msg_bytes.Control::2 625688 +system.ruby.network.routers4.msg_bytes.Data::2 5589288 +system.ruby.network.routers4.msg_bytes.Response_Data::4 5705352 +system.ruby.network.routers4.msg_bytes.Writeback_Control::3 629288 +system.ruby.network.routers5.percent_links_utilized 5.201822 +system.ruby.network.routers5.msg_count.Control::2 78653 +system.ruby.network.routers5.msg_count.Data::2 78120 +system.ruby.network.routers5.msg_count.Response_Data::4 79653 +system.ruby.network.routers5.msg_count.Writeback_Control::3 79121 +system.ruby.network.routers5.msg_bytes.Control::2 629224 +system.ruby.network.routers5.msg_bytes.Data::2 5624640 +system.ruby.network.routers5.msg_bytes.Response_Data::4 5735016 +system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632968 +system.ruby.network.routers6.percent_links_utilized 5.189062 +system.ruby.network.routers6.msg_count.Control::2 78454 +system.ruby.network.routers6.msg_count.Data::2 77910 +system.ruby.network.routers6.msg_count.Response_Data::4 79476 +system.ruby.network.routers6.msg_count.Writeback_Control::3 78933 +system.ruby.network.routers6.msg_bytes.Control::2 627632 +system.ruby.network.routers6.msg_bytes.Data::2 5609520 +system.ruby.network.routers6.msg_bytes.Response_Data::4 5722272 +system.ruby.network.routers6.msg_bytes.Writeback_Control::3 631464 +system.ruby.network.routers7.percent_links_utilized 5.188175 +system.ruby.network.routers7.msg_count.Control::2 78418 +system.ruby.network.routers7.msg_count.Data::2 77890 +system.ruby.network.routers7.msg_count.Response_Data::4 79469 +system.ruby.network.routers7.msg_count.Writeback_Control::3 78943 +system.ruby.network.routers7.msg_bytes.Control::2 627344 +system.ruby.network.routers7.msg_bytes.Data::2 5608080 +system.ruby.network.routers7.msg_bytes.Response_Data::4 5721768 +system.ruby.network.routers7.msg_bytes.Writeback_Control::3 631544 +system.ruby.network.routers8.percent_links_utilized 41.040267 +system.ruby.network.routers8.msg_count.Control::2 627993 +system.ruby.network.routers8.msg_count.Data::2 623470 +system.ruby.network.routers8.msg_count.Response_Data::4 619624 +system.ruby.network.routers8.msg_count.Writeback_Control::3 631825 +system.ruby.network.routers8.msg_bytes.Control::2 5023944 +system.ruby.network.routers8.msg_bytes.Data::2 44889840 +system.ruby.network.routers8.msg_bytes.Response_Data::4 44612928 +system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5054600 +system.ruby.network.routers9.percent_links_utilized 9.175156 +system.ruby.network.routers9.msg_count.Control::2 627993 +system.ruby.network.routers9.msg_count.Data::2 623470 +system.ruby.network.routers9.msg_count.Response_Data::4 627979 +system.ruby.network.routers9.msg_count.Writeback_Control::3 631825 +system.ruby.network.routers9.msg_bytes.Control::2 5023944 +system.ruby.network.routers9.msg_bytes.Data::2 44889840 +system.ruby.network.routers9.msg_bytes.Response_Data::4 45214488 +system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5054600 +system.ruby.network.msg_count.Control 1883979 +system.ruby.network.msg_count.Data 1870410 +system.ruby.network.msg_count.Response_Data 1883938 +system.ruby.network.msg_count.Writeback_Control 1895474 +system.ruby.network.msg_byte.Control 15071832 +system.ruby.network.msg_byte.Data 134669520 +system.ruby.network.msg_byte.Response_Data 135643536 +system.ruby.network.msg_byte.Writeback_Control 15163792 +system.ruby.network.routers0.throttle0.link_utilization 5.187964 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78628 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79112 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5661216 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 632896 +system.ruby.network.routers0.throttle1.link_utilization 5.213503 +system.ruby.network.routers0.throttle1.msg_count.Control::2 78629 +system.ruby.network.routers0.throttle1.msg_count.Data::2 78049 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1063 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 629032 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5619528 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 76536 +system.ruby.network.routers1.throttle0.link_utilization 5.186942 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78613 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 79092 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5660136 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 632736 +system.ruby.network.routers1.throttle1.link_utilization 5.212349 +system.ruby.network.routers1.throttle1.msg_count.Control::2 78616 +system.ruby.network.routers1.throttle1.msg_count.Data::2 78080 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1014 +system.ruby.network.routers1.throttle1.msg_bytes.Control::2 628928 +system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5621760 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 73008 +system.ruby.network.routers2.throttle0.link_utilization 5.197499 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78774 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79247 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5671728 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 633976 +system.ruby.network.routers2.throttle1.link_utilization 5.222484 +system.ruby.network.routers2.throttle1.msg_count.Control::2 78776 +system.ruby.network.routers2.throttle1.msg_count.Data::2 78168 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1079 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 630208 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5628096 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 77688 +system.ruby.network.routers3.throttle0.link_utilization 5.161964 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78234 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 78715 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5632848 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 629720 +system.ruby.network.routers3.throttle1.link_utilization 5.187351 +system.ruby.network.routers3.throttle1.msg_count.Control::2 78236 +system.ruby.network.routers3.throttle1.msg_count.Data::2 77624 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1091 +system.ruby.network.routers3.throttle1.msg_bytes.Control::2 625888 +system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5588928 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 78552 +system.ruby.network.routers4.throttle0.link_utilization 5.160124 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78209 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 78661 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5631048 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 629288 +system.ruby.network.routers4.throttle1.link_utilization 5.183981 +system.ruby.network.routers4.throttle1.msg_count.Control::2 78211 +system.ruby.network.routers4.throttle1.msg_count.Data::2 77629 +system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1032 +system.ruby.network.routers4.throttle1.msg_bytes.Control::2 625688 +system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5589288 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 74304 +system.ruby.network.routers5.throttle0.link_utilization 5.189448 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78652 +system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79121 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5662944 +system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632968 +system.ruby.network.routers5.throttle1.link_utilization 5.214195 +system.ruby.network.routers5.throttle1.msg_count.Control::2 78653 +system.ruby.network.routers5.throttle1.msg_count.Data::2 78120 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1001 +system.ruby.network.routers5.throttle1.msg_bytes.Control::2 629224 +system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5624640 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 72072 +system.ruby.network.routers6.throttle0.link_utilization 5.176398 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78453 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78933 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5648616 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 631464 +system.ruby.network.routers6.throttle1.link_utilization 5.201726 +system.ruby.network.routers6.throttle1.msg_count.Control::2 78454 +system.ruby.network.routers6.throttle1.msg_count.Data::2 77910 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1023 +system.ruby.network.routers6.throttle1.msg_bytes.Control::2 627632 +system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5609520 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 73656 +system.ruby.network.routers7.throttle0.link_utilization 5.174268 +system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78416 +system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 78943 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5645952 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 631544 +system.ruby.network.routers7.throttle1.link_utilization 5.202082 +system.ruby.network.routers7.throttle1.msg_count.Control::2 78418 +system.ruby.network.routers7.throttle1.msg_count.Data::2 77890 +system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1053 +system.ruby.network.routers7.throttle1.msg_bytes.Control::2 627344 +system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5608080 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 75816 +system.ruby.network.routers8.throttle0.link_utilization 41.141772 +system.ruby.network.routers8.throttle0.msg_count.Control::2 627993 +system.ruby.network.routers8.throttle0.msg_count.Data::2 623470 +system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5023944 +system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44889840 +system.ruby.network.routers8.throttle1.link_utilization 40.938761 +system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 619624 +system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 631825 +system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44612928 +system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5054600 +system.ruby.network.routers9.throttle0.link_utilization 5.187964 +system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78628 +system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 79112 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5661216 +system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 632896 +system.ruby.network.routers9.throttle1.link_utilization 5.186949 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78613 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 79093 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5660136 +system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 632744 +system.ruby.network.routers9.throttle2.link_utilization 5.197519 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78774 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 79247 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5671728 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 633976 +system.ruby.network.routers9.throttle3.link_utilization 5.161964 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78234 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 78715 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5632848 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 629720 +system.ruby.network.routers9.throttle4.link_utilization 5.160124 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78209 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 78661 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5631048 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 629288 +system.ruby.network.routers9.throttle5.link_utilization 5.189448 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78652 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79121 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5662944 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632968 +system.ruby.network.routers9.throttle6.link_utilization 5.176398 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78453 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78933 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5648616 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 631464 +system.ruby.network.routers9.throttle7.link_utilization 5.174268 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78416 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 78943 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5645952 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 631544 +system.ruby.network.routers9.throttle8.link_utilization 41.141772 +system.ruby.network.routers9.throttle8.msg_count.Control::2 627993 +system.ruby.network.routers9.throttle8.msg_count.Data::2 623470 +system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5023944 +system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44889840 system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 627760 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.272321 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 1.331534 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 602027 95.90% 95.90% | 18741 2.99% 98.89% | 5956 0.95% 99.83% | 834 0.13% 99.97% | 162 0.03% 99.99% | 34 0.01% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 627760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 627979 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.257658 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 1.293410 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 603579 96.11% 96.11% | 17844 2.84% 98.96% | 5625 0.90% 99.85% | 739 0.12% 99.97% | 162 0.03% 100.00% | 24 0.00% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 627979 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 32 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 319 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 631610 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 4.109089 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 10.468759 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 614344 97.27% 97.27% | 10923 1.73% 99.00% | 5617 0.89% 99.89% | 569 0.09% 99.98% | 127 0.02% 100.00% | 28 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 631610 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 631824 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 4.008551 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 10.168722 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 615441 97.41% 97.41% | 10426 1.65% 99.06% | 5324 0.84% 99.90% | 510 0.08% 99.98% | 106 0.02% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 631824 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 403546 -system.ruby.LD.latency_hist::mean 1557.548146 -system.ruby.LD.latency_hist::gmean 1534.608299 -system.ruby.LD.latency_hist::stdev 267.377915 -system.ruby.LD.latency_hist | 45 0.01% 0.01% | 4772 1.18% 1.19% | 195796 48.52% 49.71% | 185358 45.93% 95.64% | 17446 4.32% 99.97% | 129 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 403546 +system.ruby.LD.latency_hist::samples 404144 +system.ruby.LD.latency_hist::mean 1545.571497 +system.ruby.LD.latency_hist::gmean 1523.054184 +system.ruby.LD.latency_hist::stdev 263.999078 +system.ruby.LD.latency_hist | 46 0.01% 0.01% | 5096 1.26% 1.27% | 203787 50.42% 51.70% | 179678 44.46% 96.16% | 15429 3.82% 99.97% | 108 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 404144 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 403546 -system.ruby.LD.miss_latency_hist::mean 1557.548146 -system.ruby.LD.miss_latency_hist::gmean 1534.608299 -system.ruby.LD.miss_latency_hist::stdev 267.377915 -system.ruby.LD.miss_latency_hist | 45 0.01% 0.01% | 4772 1.18% 1.19% | 195796 48.52% 49.71% | 185358 45.93% 95.64% | 17446 4.32% 99.97% | 129 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 403546 +system.ruby.LD.miss_latency_hist::samples 404144 +system.ruby.LD.miss_latency_hist::mean 1545.571497 +system.ruby.LD.miss_latency_hist::gmean 1523.054184 +system.ruby.LD.miss_latency_hist::stdev 263.999078 +system.ruby.LD.miss_latency_hist | 46 0.01% 0.01% | 5096 1.26% 1.27% | 203787 50.42% 51.70% | 179678 44.46% 96.16% | 15429 3.82% 99.97% | 108 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 404144 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 224214 -system.ruby.ST.latency_hist::mean 1557.955489 -system.ruby.ST.latency_hist::gmean 1535.137320 -system.ruby.ST.latency_hist::stdev 266.918128 -system.ruby.ST.latency_hist | 21 0.01% 0.01% | 2565 1.14% 1.15% | 108735 48.50% 49.65% | 103114 45.99% 95.64% | 9704 4.33% 99.97% | 75 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 224214 +system.ruby.ST.latency_hist::samples 223835 +system.ruby.ST.latency_hist::mean 1545.041991 +system.ruby.ST.latency_hist::gmean 1522.530592 +system.ruby.ST.latency_hist::stdev 263.883663 +system.ruby.ST.latency_hist | 22 0.01% 0.01% | 2888 1.29% 1.30% | 112600 50.30% 51.60% | 99837 44.60% 96.21% | 8410 3.76% 99.97% | 78 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 223835 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 224214 -system.ruby.ST.miss_latency_hist::mean 1557.955489 -system.ruby.ST.miss_latency_hist::gmean 1535.137320 -system.ruby.ST.miss_latency_hist::stdev 266.918128 -system.ruby.ST.miss_latency_hist | 21 0.01% 0.01% | 2565 1.14% 1.15% | 108735 48.50% 49.65% | 103114 45.99% 95.64% | 9704 4.33% 99.97% | 75 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 224214 -system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 256 -system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 2559 -system.ruby.L1Cache.miss_mach_latency_hist::samples 8531 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1448.565233 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 1423.519365 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 270.374184 -system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 0.20% 0.20% | 336 3.94% 4.14% | 2048 24.01% 28.14% | 3165 37.10% 65.24% | 2039 23.90% 89.15% | 737 8.64% 97.78% | 163 1.91% 99.70% | 26 0.30% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 8531 +system.ruby.ST.miss_latency_hist::samples 223835 +system.ruby.ST.miss_latency_hist::mean 1545.041991 +system.ruby.ST.miss_latency_hist::gmean 1522.530592 +system.ruby.ST.miss_latency_hist::stdev 263.883663 +system.ruby.ST.miss_latency_hist | 22 0.01% 0.01% | 2888 1.29% 1.30% | 112600 50.30% 51.60% | 99837 44.60% 96.21% | 8410 3.76% 99.97% | 78 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 223835 +system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 +system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 +system.ruby.L1Cache.miss_mach_latency_hist::samples 8356 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1439.556127 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 1414.820611 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 268.620110 +system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 325 3.89% 3.89% | 5166 61.82% 65.71% | 2690 32.19% 97.91% | 173 2.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 8356 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 619229 -system.ruby.Directory.miss_mach_latency_hist::mean 1559.197076 -system.ruby.Directory.miss_mach_latency_hist::gmean 1536.389523 -system.ruby.Directory.miss_mach_latency_hist::stdev 266.858602 -system.ruby.Directory.miss_mach_latency_hist | 66 0.01% 0.01% | 6984 1.13% 1.14% | 299318 48.34% 49.48% | 285696 46.14% 95.61% | 26961 4.35% 99.97% | 204 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 619229 +system.ruby.Directory.miss_mach_latency_hist::samples 619623 +system.ruby.Directory.miss_mach_latency_hist::mean 1546.809899 +system.ruby.Directory.miss_mach_latency_hist::gmean 1524.379638 +system.ruby.Directory.miss_mach_latency_hist::stdev 263.604468 +system.ruby.Directory.miss_mach_latency_hist | 68 0.01% 0.01% | 7659 1.24% 1.25% | 311221 50.23% 51.47% | 276825 44.68% 96.15% | 23666 3.82% 99.97% | 184 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 619623 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 4 @@ -678,84 +683,84 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 8 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 6.454972 system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 4 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 256 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5413 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1445.669499 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1420.780527 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 269.907745 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 0.15% 0.15% | 212 3.92% 4.06% | 1326 24.50% 28.56% | 2026 37.43% 65.99% | 1262 23.31% 89.30% | 452 8.35% 97.65% | 110 2.03% 99.69% | 17 0.31% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5413 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5357 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1439.042561 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1414.108080 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 269.675535 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 221 4.13% 4.13% | 3291 61.43% 65.56% | 1732 32.33% 97.89% | 112 2.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5357 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 398133 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1559.069243 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1536.217141 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 267.020897 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 45 0.01% 0.01% | 4552 1.14% 1.15% | 192444 48.34% 49.49% | 183644 46.13% 95.62% | 17319 4.35% 99.97% | 129 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 398133 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 256 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 3118 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1453.592367 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1428.286665 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 271.151930 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 0.29% 0.29% | 124 3.98% 4.27% | 722 23.16% 27.42% | 1139 36.53% 63.95% | 777 24.92% 88.87% | 285 9.14% 98.01% | 53 1.70% 99.71% | 9 0.29% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 3118 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 398787 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1547.002525 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1524.573421 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 263.629488 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 46 0.01% 0.01% | 4875 1.22% 1.23% | 200496 50.28% 51.51% | 177946 44.62% 96.13% | 15317 3.84% 99.97% | 107 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 398787 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 2999 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1440.473491 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1416.094271 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 266.766826 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 104 3.47% 3.47% | 1875 62.52% 65.99% | 958 31.94% 97.93% | 61 2.03% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 2999 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221096 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1559.427267 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1536.699982 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 266.566552 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 21 0.01% 0.01% | 2432 1.10% 1.11% | 106874 48.34% 49.45% | 102052 46.16% 95.61% | 9642 4.36% 99.97% | 75 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221096 -system.ruby.L1Cache_Controller.Load | 50242 12.45% 12.45% | 50323 12.47% 24.92% | 50493 12.51% 37.43% | 50644 12.55% 49.98% | 50567 12.53% 62.51% | 50426 12.50% 75.01% | 50403 12.49% 87.50% | 50459 12.50% 100.00% -system.ruby.L1Cache_Controller.Load::total 403557 -system.ruby.L1Cache_Controller.Store | 28008 12.49% 12.49% | 28130 12.55% 25.04% | 27865 12.43% 37.46% | 27716 12.36% 49.83% | 28095 12.53% 62.36% | 28158 12.56% 74.91% | 28062 12.52% 87.43% | 28184 12.57% 100.00% -system.ruby.L1Cache_Controller.Store::total 224218 -system.ruby.L1Cache_Controller.Data | 78249 12.46% 12.46% | 78450 12.50% 24.96% | 78357 12.48% 37.44% | 78358 12.48% 49.93% | 78659 12.53% 62.46% | 78581 12.52% 74.97% | 78464 12.50% 87.47% | 78642 12.53% 100.00% -system.ruby.L1Cache_Controller.Data::total 627760 -system.ruby.L1Cache_Controller.Fwd_GETX | 1065 12.48% 12.48% | 1076 12.61% 25.10% | 1049 12.30% 37.39% | 1001 11.73% 49.13% | 1068 12.52% 61.65% | 1132 13.27% 74.92% | 1066 12.50% 87.41% | 1074 12.59% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 8531 -system.ruby.L1Cache_Controller.Replacement | 78246 12.46% 12.46% | 78449 12.50% 24.96% | 78354 12.48% 37.44% | 78356 12.48% 49.93% | 78658 12.53% 62.46% | 78580 12.52% 74.97% | 78461 12.50% 87.47% | 78639 12.53% 100.00% -system.ruby.L1Cache_Controller.Replacement::total 627743 -system.ruby.L1Cache_Controller.Writeback_Ack | 77181 12.46% 12.46% | 77373 12.50% 24.96% | 77305 12.48% 37.44% | 77355 12.49% 49.94% | 77587 12.53% 62.47% | 77448 12.51% 74.97% | 77395 12.50% 87.47% | 77565 12.53% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 619209 -system.ruby.L1Cache_Controller.Writeback_Nack | 485 12.53% 12.53% | 499 12.89% 25.43% | 468 12.09% 37.52% | 457 11.81% 49.33% | 483 12.48% 61.81% | 494 12.76% 74.57% | 497 12.84% 87.42% | 487 12.58% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 3870 -system.ruby.L1Cache_Controller.I.Load | 50242 12.45% 12.45% | 50323 12.47% 24.92% | 50493 12.51% 37.43% | 50644 12.55% 49.98% | 50567 12.53% 62.51% | 50426 12.50% 75.01% | 50403 12.49% 87.50% | 50459 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 403557 -system.ruby.L1Cache_Controller.I.Store | 28008 12.49% 12.49% | 28130 12.55% 25.04% | 27865 12.43% 37.46% | 27716 12.36% 49.83% | 28095 12.53% 62.36% | 28158 12.56% 74.91% | 28062 12.52% 87.43% | 28184 12.57% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 224218 -system.ruby.L1Cache_Controller.I.Replacement | 580 12.44% 12.44% | 577 12.38% 24.82% | 581 12.47% 37.29% | 544 11.67% 48.96% | 585 12.55% 61.51% | 638 13.69% 75.20% | 569 12.21% 87.41% | 587 12.59% 100.00% -system.ruby.L1Cache_Controller.I.Replacement::total 4661 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 485 12.53% 12.53% | 499 12.89% 25.43% | 468 12.09% 37.52% | 457 11.81% 49.33% | 483 12.48% 61.81% | 494 12.76% 74.57% | 497 12.84% 87.42% | 487 12.58% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3870 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 580 12.44% 12.44% | 577 12.38% 24.82% | 581 12.47% 37.29% | 544 11.67% 48.96% | 585 12.55% 61.51% | 638 13.69% 75.20% | 569 12.21% 87.41% | 587 12.59% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4661 -system.ruby.L1Cache_Controller.M.Replacement | 77666 12.46% 12.46% | 77872 12.50% 24.96% | 77773 12.48% 37.44% | 77812 12.49% 49.93% | 78073 12.53% 62.46% | 77942 12.51% 74.97% | 77892 12.50% 87.47% | 78052 12.53% 100.00% -system.ruby.L1Cache_Controller.M.Replacement::total 623082 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 485 12.53% 12.53% | 499 12.89% 25.43% | 468 12.09% 37.52% | 457 11.81% 49.33% | 483 12.48% 61.81% | 494 12.76% 74.57% | 497 12.84% 87.42% | 487 12.58% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3870 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77181 12.46% 12.46% | 77373 12.50% 24.96% | 77305 12.48% 37.44% | 77355 12.49% 49.94% | 77587 12.53% 62.47% | 77448 12.51% 74.97% | 77395 12.50% 87.47% | 77565 12.53% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 619209 -system.ruby.L1Cache_Controller.IS.Data | 50241 12.45% 12.45% | 50321 12.47% 24.92% | 50492 12.51% 37.43% | 50642 12.55% 49.98% | 50566 12.53% 62.51% | 50424 12.50% 75.01% | 50402 12.49% 87.50% | 50458 12.50% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 403546 -system.ruby.L1Cache_Controller.IM.Data | 28008 12.49% 12.49% | 28129 12.55% 25.04% | 27865 12.43% 37.47% | 27716 12.36% 49.83% | 28093 12.53% 62.36% | 28157 12.56% 74.91% | 28062 12.52% 87.43% | 28184 12.57% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 224214 -system.ruby.Directory_Controller.GETX 693666 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 619210 0.00% 0.00% -system.ruby.Directory_Controller.PUTX_NotOwner 3870 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 619230 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 619209 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 619241 0.00% 0.00% -system.ruby.Directory_Controller.M.GETX 8531 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 619210 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX_NotOwner 3870 0.00% 0.00% -system.ruby.Directory_Controller.IM.GETX 65555 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 619230 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 339 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 619209 0.00% 0.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 220836 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1546.462053 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1524.029766 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 263.559522 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 22 0.01% 0.01% | 2784 1.26% 1.27% | 110725 50.14% 51.41% | 98879 44.77% 96.18% | 8349 3.78% 99.97% | 77 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 220836 +system.ruby.Directory_Controller.GETX 692595 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 619605 0.00% 0.00% +system.ruby.Directory_Controller.PUTX_NotOwner 3865 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 619624 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 619604 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 619636 0.00% 0.00% +system.ruby.Directory_Controller.M.GETX 8356 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 619605 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX_NotOwner 3865 0.00% 0.00% +system.ruby.Directory_Controller.IM.GETX 64332 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 619624 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETX 271 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 619604 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50680 12.54% 12.54% | 50607 12.52% 25.06% | 50500 12.50% 37.56% | 50509 12.50% 50.05% | 50226 12.43% 62.48% | 50766 12.56% 75.04% | 50488 12.49% 87.54% | 50375 12.46% 100.00% +system.ruby.L1Cache_Controller.Load::total 404151 +system.ruby.L1Cache_Controller.Store | 27949 12.49% 12.49% | 28009 12.51% 25.00% | 28276 12.63% 37.63% | 27727 12.39% 50.02% | 27985 12.50% 62.52% | 27887 12.46% 74.98% | 27966 12.49% 87.47% | 28043 12.53% 100.00% +system.ruby.L1Cache_Controller.Store::total 223842 +system.ruby.L1Cache_Controller.Data | 78628 12.52% 12.52% | 78613 12.52% 25.04% | 78774 12.54% 37.58% | 78234 12.46% 50.04% | 78209 12.45% 62.50% | 78652 12.52% 75.02% | 78453 12.49% 87.51% | 78416 12.49% 100.00% +system.ruby.L1Cache_Controller.Data::total 627979 +system.ruby.L1Cache_Controller.Fwd_GETX | 1063 12.72% 12.72% | 1014 12.13% 24.86% | 1079 12.91% 37.77% | 1091 13.06% 50.83% | 1032 12.35% 63.18% | 1001 11.98% 75.16% | 1023 12.24% 87.40% | 1053 12.60% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 8356 +system.ruby.L1Cache_Controller.Replacement | 78625 12.52% 12.52% | 78612 12.52% 25.04% | 78772 12.54% 37.58% | 78232 12.46% 50.04% | 78207 12.45% 62.50% | 78649 12.52% 75.02% | 78450 12.49% 87.51% | 78414 12.49% 100.00% +system.ruby.L1Cache_Controller.Replacement::total 627961 +system.ruby.L1Cache_Controller.Writeback_Ack | 77562 12.52% 12.52% | 77596 12.52% 25.04% | 77693 12.54% 37.58% | 77141 12.45% 50.03% | 77175 12.46% 62.49% | 77648 12.53% 75.02% | 77427 12.50% 87.51% | 77361 12.49% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 619603 +system.ruby.L1Cache_Controller.Writeback_Nack | 487 12.60% 12.60% | 482 12.47% 25.07% | 475 12.29% 37.36% | 483 12.50% 49.86% | 454 11.75% 61.60% | 472 12.21% 73.82% | 483 12.50% 86.31% | 529 13.69% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 3865 +system.ruby.L1Cache_Controller.I.Load | 50680 12.54% 12.54% | 50607 12.52% 25.06% | 50500 12.50% 37.56% | 50509 12.50% 50.05% | 50226 12.43% 62.48% | 50766 12.56% 75.04% | 50488 12.49% 87.54% | 50375 12.46% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 404151 +system.ruby.L1Cache_Controller.I.Store | 27949 12.49% 12.49% | 28009 12.51% 25.00% | 28276 12.63% 37.63% | 27727 12.39% 50.02% | 27985 12.50% 62.52% | 27887 12.46% 74.98% | 27966 12.49% 87.47% | 28043 12.53% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 223842 +system.ruby.L1Cache_Controller.I.Replacement | 576 12.83% 12.83% | 532 11.85% 24.67% | 604 13.45% 38.12% | 608 13.54% 51.66% | 578 12.87% 64.53% | 529 11.78% 76.31% | 540 12.02% 88.33% | 524 11.67% 100.00% +system.ruby.L1Cache_Controller.I.Replacement::total 4491 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 487 12.60% 12.60% | 482 12.47% 25.07% | 475 12.29% 37.36% | 483 12.50% 49.86% | 454 11.75% 61.60% | 472 12.21% 73.82% | 483 12.50% 86.31% | 529 13.69% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3865 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 576 12.83% 12.83% | 532 11.85% 24.67% | 604 13.45% 38.12% | 608 13.54% 51.66% | 578 12.87% 64.53% | 529 11.78% 76.31% | 540 12.02% 88.33% | 524 11.67% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4491 +system.ruby.L1Cache_Controller.M.Replacement | 78049 12.52% 12.52% | 78080 12.52% 25.04% | 78168 12.54% 37.58% | 77624 12.45% 50.03% | 77629 12.45% 62.48% | 78120 12.53% 75.01% | 77910 12.50% 87.51% | 77890 12.49% 100.00% +system.ruby.L1Cache_Controller.M.Replacement::total 623470 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 487 12.60% 12.60% | 482 12.47% 25.07% | 475 12.29% 37.36% | 483 12.50% 49.86% | 454 11.75% 61.60% | 472 12.21% 73.82% | 483 12.50% 86.31% | 529 13.69% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3865 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77562 12.52% 12.52% | 77596 12.52% 25.04% | 77693 12.54% 37.58% | 77141 12.45% 50.03% | 77175 12.46% 62.49% | 77648 12.53% 75.02% | 77427 12.50% 87.51% | 77361 12.49% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 619603 +system.ruby.L1Cache_Controller.IS.Data | 50680 12.54% 12.54% | 50605 12.52% 25.06% | 50498 12.50% 37.56% | 50509 12.50% 50.05% | 50225 12.43% 62.48% | 50765 12.56% 75.04% | 50488 12.49% 87.54% | 50374 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 404144 +system.ruby.L1Cache_Controller.IM.Data | 27948 12.49% 12.49% | 28008 12.51% 25.00% | 28276 12.63% 37.63% | 27725 12.39% 50.02% | 27984 12.50% 62.52% | 27887 12.46% 74.98% | 27965 12.49% 87.47% | 28042 12.53% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 223835 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index c4d69701f..f5fe53ea2 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000323 # Nu sim_ticks 322881 # Number of ticks simulated final_tick 322881 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1612482 # Simulator tick rate (ticks/s) -host_mem_usage 434296 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 2952595 # Simulator tick rate (ticks/s) +host_mem_usage 447776 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54144 # Number of bytes read from this memory @@ -235,29 +235,34 @@ system.mem_ctrls.readRowHitRate 79.08 # Ro system.mem_ctrls.writeRowHitRate 95.59 # Row buffer hit rate for writes system.mem_ctrls.avgGap 201.77 # Average gap between requests system.mem_ctrls.pageHitRate 86.97 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 7291 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 10660 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 301549 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1171800 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 651000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 8835840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6407424 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 212765724 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 6898824 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 5055000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 185640000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 255737748 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 213389784 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 800.466211 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.915915 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1171800 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 651000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8835840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6407424 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 212765724 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 5055000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 255737748 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 800.466211 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 7291 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 10660 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 301549 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 6898824 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 185631600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 213381384 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.918891 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 308826 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 10660 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 512 # delay histogram for all message system.ruby.delayHist::max_bucket 5119 # delay histogram for all message @@ -317,6 +322,10 @@ system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 77 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 11 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.l2_cntrl0.L2cache.demand_hits 29 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 846 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 875 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 1.655176 system.ruby.network.routers0.msg_count.Control::0 876 system.ruby.network.routers0.msg_count.Request_Control::2 528 @@ -334,9 +343,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6576 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 49680 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 34056 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 272 -system.ruby.l2_cntrl0.L2cache.demand_hits 29 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 846 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 875 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 2.907186 system.ruby.network.routers1.msg_count.Control::0 1722 system.ruby.network.routers1.msg_count.Request_Control::2 528 @@ -390,7 +396,6 @@ system.ruby.network.msg_byte.Response_Data 534312 system.ruby.network.msg_byte.Response_Control 60720 system.ruby.network.msg_byte.Writeback_Data 251208 system.ruby.network.msg_byte.Writeback_Control 816 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.throttle0.link_utilization 1.412750 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 528 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 875 @@ -559,6 +564,16 @@ system.ruby.IFETCH.miss_latency_hist::gmean 799.675557 system.ruby.IFETCH.miss_latency_hist::stdev 325.423919 system.ruby.IFETCH.miss_latency_hist | 1 1.96% 1.96% | 5 9.80% 11.76% | 17 33.33% 45.10% | 17 33.33% 78.43% | 4 7.84% 86.27% | 5 9.80% 96.08% | 2 3.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 51 +system.ruby.Directory_Controller.Fetch 846 0.00% 0.00% +system.ruby.Directory_Controller.Data 752 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 846 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 752 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 89 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 846 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 752 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 89 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 846 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 752 0.00% 0.00% system.ruby.L1Cache_Controller.Load 49 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 58 0.00% 0.00% system.ruby.L1Cache_Controller.Store 841 0.00% 0.00% @@ -633,15 +648,5 @@ system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 15 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 143 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 331 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 817 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 846 0.00% 0.00% -system.ruby.Directory_Controller.Data 752 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 846 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 752 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 89 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 846 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 752 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 89 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 846 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 752 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index bbe924bff..79972c69a 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000330 # Nu sim_ticks 330331 # Number of ticks simulated final_tick 330331 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 620421 # Simulator tick rate (ticks/s) -host_mem_usage 435392 # Number of bytes of host memory used -host_seconds 0.53 # Real time elapsed on the host +host_tick_rate 797019 # Simulator tick rate (ticks/s) +host_mem_usage 449656 # Number of bytes of host memory used +host_seconds 0.41 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54784 # Number of bytes read from this memory @@ -236,29 +236,34 @@ system.mem_ctrls.readRowHitRate 78.28 # Ro system.mem_ctrls.writeRowHitRate 94.50 # Row buffer hit rate for writes system.mem_ctrls.avgGap 203.82 # Average gap between requests system.mem_ctrls.pageHitRate 86.08 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 5756 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 10920 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 310724 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1202040 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 667800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 8448960 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6189696 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 219200112 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 7067088 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 4082400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 190164000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 261150528 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 218590608 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 797.961720 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.917231 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1202040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 667800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8448960 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6189696 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 219200112 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 4082400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 261150528 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 797.961720 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5756 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 10920 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 310724 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 7067088 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 190155600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 218582208 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.920136 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 316352 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 10920 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 @@ -302,6 +307,10 @@ system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 93 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 8 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.l2_cntrl0.L2cache.demand_hits 44 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 857 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 901 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 1.492064 system.ruby.network.routers0.msg_count.Request_Control::0 901 system.ruby.network.routers0.msg_count.Response_Data::2 855 @@ -315,9 +324,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 3168 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 64296 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14304 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7184 -system.ruby.l2_cntrl0.L2cache.demand_hits 44 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 857 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 901 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 2.839803 system.ruby.network.routers1.msg_count.Request_Control::0 901 system.ruby.network.routers1.msg_count.Request_Control::1 857 @@ -375,7 +381,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 9504 system.ruby.network.msg_byte.Writeback_Data 357696 system.ruby.network.msg_byte.Writeback_Control 79544 system.ruby.network.msg_byte.Unblock_Control 42048 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.throttle0.link_utilization 1.359848 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 855 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 44 @@ -527,6 +532,31 @@ system.ruby.IFETCH.miss_latency_hist::gmean 629.917289 system.ruby.IFETCH.miss_latency_hist::stdev 289.399275 system.ruby.IFETCH.miss_latency_hist | 4 7.41% 7.41% | 8 14.81% 22.22% | 22 40.74% 62.96% | 12 22.22% 85.19% | 6 11.11% 96.30% | 2 3.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 54 +system.ruby.Directory_Controller.GETX 768 0.00% 0.00% +system.ruby.Directory_Controller.GETS 90 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 763 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 77 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 10 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 767 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 763 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 763 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 708 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 78 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 760 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 60 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 10 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 763 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 77 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 78 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Ack 1 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 10 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 10 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 767 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 768 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 2 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 763 0.00% 0.00% system.ruby.L1Cache_Controller.Load 46 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 243 0.00% 0.00% system.ruby.L1Cache_Controller.Store 1035 0.00% 0.00% @@ -610,30 +640,5 @@ system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 8 0.00% system.ruby.L2Cache_Controller.MI.L1_GETS 85 0.00% 0.00% system.ruby.L2Cache_Controller.MI.L1_GETX 1 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 763 0.00% 0.00% -system.ruby.Directory_Controller.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.GETS 90 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 763 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 77 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 10 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 767 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 763 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 763 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 708 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 78 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 760 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 60 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 10 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 763 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 77 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 10 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 10 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 767 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 768 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 2 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 763 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 6c54d9927..5f532e15e 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000238 # Nu sim_ticks 237931 # Number of ticks simulated final_tick 237931 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1532175 # Simulator tick rate (ticks/s) -host_mem_usage 434360 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 2289780 # Simulator tick rate (ticks/s) +host_mem_usage 448616 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55552 # Number of bytes read from this memory @@ -236,29 +236,34 @@ system.mem_ctrls.readRowHitRate 82.47 # Ro system.mem_ctrls.writeRowHitRate 95.96 # Row buffer hit rate for writes system.mem_ctrls.avgGap 143.45 # Average gap between requests system.mem_ctrls.pageHitRate 89.01 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 1511 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 7800 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 224543 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1028160 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 571200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 8973120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6811776 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 15256800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 15256800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 158348052 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 5047920 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1402200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 135876000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 192391308 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 156180720 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 822.747639 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.895655 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1028160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 571200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8973120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6811776 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 15256800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 158348052 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1402200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 192391308 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 822.747639 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1511 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 7800 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 224543 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 15256800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 5047920 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 135867600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 156172320 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.899720 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 226040 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 7800 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 @@ -302,6 +307,10 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 90 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 4 # Number of times a load aliased with a pending store +system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 877 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 2.062783 system.ruby.network.routers0.msg_count.Request_Control::1 915 system.ruby.network.routers0.msg_count.Response_Data::4 915 @@ -315,9 +324,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 2880 system.ruby.network.routers0.msg_bytes.Response_Control::4 24 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 74808 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 6144 -system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 877 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 1.886681 system.ruby.network.routers1.msg_count.Request_Control::1 915 system.ruby.network.routers1.msg_count.Request_Control::2 877 @@ -377,7 +383,6 @@ system.ruby.network.msg_byte.Response_Control 72 system.ruby.network.msg_byte.Writeback_Data 377352 system.ruby.network.msg_byte.Writeback_Control 1728 system.ruby.network.msg_byte.Persistent_Control 18432 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.throttle0.link_utilization 1.970739 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 894 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 40 @@ -613,6 +618,37 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 439.837439 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 188.502356 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 1 2.17% 2.17% | 5 10.87% 13.04% | 8 17.39% 30.43% | 9 19.57% 50.00% | 17 36.96% 86.96% | 3 6.52% 93.48% | 1 2.17% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 46 +system.ruby.Directory_Controller.GETX 808 0.00% 0.00% +system.ruby.Directory_Controller.GETS 105 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 192 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 192 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 1 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 792 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 72 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 788 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 778 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 81 0.00% 0.00% +system.ruby.Directory_Controller.O.Lockdown 9 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 3 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 169 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 787 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 72 0.00% 0.00% +system.ruby.Directory_Controller.L.GETX 7 0.00% 0.00% +system.ruby.Directory_Controller.L.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 191 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_All_Tokens 5 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Data 1 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 788 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETX 17 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETS 20 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Unlockdown 1 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Data 8 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 14 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 14 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 845 0.00% 0.00% system.ruby.L1Cache_Controller.Load 44 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 56 0.00% 0.00% system.ruby.L1Cache_Controller.Store 917 0.00% 0.00% @@ -690,36 +726,5 @@ system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 63 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETX 149 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 15 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 26 0.00% 0.00% -system.ruby.Directory_Controller.GETX 808 0.00% 0.00% -system.ruby.Directory_Controller.GETS 105 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 192 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 192 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 792 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 72 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 788 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 778 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 81 0.00% 0.00% -system.ruby.Directory_Controller.O.Lockdown 9 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 169 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 787 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 72 0.00% 0.00% -system.ruby.Directory_Controller.L.GETX 7 0.00% 0.00% -system.ruby.Directory_Controller.L.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 191 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_All_Tokens 5 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Data 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 788 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETX 17 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETS 20 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Unlockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Data 8 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 14 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 14 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 845 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index b61f52446..b30732380 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000180 # Nu sim_ticks 180391 # Number of ticks simulated final_tick 180391 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 754935 # Simulator tick rate (ticks/s) -host_mem_usage 435272 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 2115130 # Simulator tick rate (ticks/s) +host_mem_usage 447992 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54784 # Number of bytes read from this memory @@ -238,29 +238,34 @@ system.mem_ctrls.readRowHitRate 81.81 # Ro system.mem_ctrls.writeRowHitRate 94.85 # Row buffer hit rate for writes system.mem_ctrls.avgGap 110.69 # Average gap between requests system.mem_ctrls.pageHitRate 88.14 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 348 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 5980 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 173024 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1028160 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 571200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 8910720 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6770304 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 11696880 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 11696880 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 121998240 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 3870072 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 586800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 104208000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 151562304 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 119774952 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 845.120967 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.872687 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1028160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 571200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8910720 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6770304 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 11696880 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 121998240 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 586800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 151562304 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 845.120967 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 348 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 5980 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 173024 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 11696880 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 3870072 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 104199600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 119766552 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.877986 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 173358 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 5980 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 @@ -295,7 +300,9 @@ system.ruby.miss_latency_hist::stdev 1102.294906 system.ruby.miss_latency_hist | 91 10.67% 10.67% | 6 0.70% 11.37% | 126 14.77% 26.14% | 516 60.49% 86.64% | 112 13.13% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 853 system.ruby.Directory.incomplete_times 853 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.demand_hits 80 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 854 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 934 # Number of cache demand accesses @@ -308,6 +315,7 @@ system.ruby.l1_cntrl0.L2cache.demand_accesses 912 system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 2.513845 system.ruby.network.routers0.msg_count.Request_Control::2 858 system.ruby.network.routers0.msg_count.Response_Data::4 856 @@ -323,9 +331,6 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6792 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 616 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6816 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 2.513291 system.ruby.network.routers1.msg_count.Request_Control::2 856 system.ruby.network.routers1.msg_count.Response_Data::4 856 @@ -598,6 +603,30 @@ system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 3955.937145 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 544.674521 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 3 +system.ruby.Directory_Controller.GETX 768 0.00% 0.00% +system.ruby.Directory_Controller.GETS 88 0.00% 0.00% +system.ruby.Directory_Controller.PUT 927 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 851 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 77 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 772 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 772 0.00% 0.00% +system.ruby.Directory_Controller.GETF 3 0.00% 0.00% +system.ruby.Directory_Controller.PUTF 3 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 846 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 768 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 85 0.00% 0.00% +system.ruby.Directory_Controller.E.GETF 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 81 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 851 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 853 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 77 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 772 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 772 0.00% 0.00% +system.ruby.Directory_Controller.NO_F.PUTF 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_F_W.Memory_Data 3 0.00% 0.00% system.ruby.L1Cache_Controller.Load 44 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 65 0.00% 0.00% system.ruby.L1Cache_Controller.Store 914 0.00% 0.00% @@ -651,29 +680,5 @@ system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 47 0.00% system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 3 0.00% 0.00% system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 3 0.00% 0.00% system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 3 0.00% 0.00% -system.ruby.Directory_Controller.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.GETS 88 0.00% 0.00% -system.ruby.Directory_Controller.PUT 927 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 851 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 77 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 772 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 772 0.00% 0.00% -system.ruby.Directory_Controller.GETF 3 0.00% 0.00% -system.ruby.Directory_Controller.PUTF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 846 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 85 0.00% 0.00% -system.ruby.Directory_Controller.E.GETF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 81 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 851 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 853 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 77 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 772 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 772 0.00% 0.00% -system.ruby.Directory_Controller.NO_F.PUTF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_F_W.Memory_Data 3 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 013496257..318f529ad 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000233 # Nu sim_ticks 233251 # Number of ticks simulated final_tick 233251 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 3056189 # Simulator tick rate (ticks/s) -host_mem_usage 433064 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 4652644 # Simulator tick rate (ticks/s) +host_mem_usage 446260 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 58944 # Number of bytes read from this memory @@ -233,29 +233,34 @@ system.mem_ctrls.readRowHitRate 80.66 # Ro system.mem_ctrls.writeRowHitRate 95.51 # Row buffer hit rate for writes system.mem_ctrls.avgGap 126.67 # Average gap between requests system.mem_ctrls.pageHitRate 88.14 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 697 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 7540 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 218097 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1171800 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 651000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 9597120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 7848576 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 14748240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 14748240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 153780300 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 4879656 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 737400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 131352000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 188534436 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 150979896 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 834.023888 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.893052 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1171800 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 651000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 9597120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 7848576 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 14748240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 153780300 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 737400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 188534436 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 834.023888 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 697 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 7540 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 218097 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 14748240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 4879656 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 131343600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 150971496 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.897257 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 218514 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 7540 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 2 # delay histogram for all message system.ruby.delayHist::max_bucket 19 # delay histogram for all message @@ -297,7 +302,6 @@ system.ruby.miss_latency_hist::stdev 532.898268 system.ruby.miss_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.87% | 28 3.04% 3.91% | 584 63.41% 67.32% | 297 32.25% 99.57% | 4 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 921 system.ruby.Directory.incomplete_times 921 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 35 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 923 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 958 # Number of cache demand accesses @@ -305,6 +309,7 @@ system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 117 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 11 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 1.971696 system.ruby.network.routers0.msg_count.Control::2 921 system.ruby.network.routers0.msg_count.Data::2 919 @@ -488,6 +493,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 3875.103542 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 441.985729 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.89% 1.89% | 13 24.53% 26.42% | 19 35.85% 62.26% | 17 32.08% 94.34% | 3 5.66% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 53 +system.ruby.Directory_Controller.GETX 921 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 918 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 921 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 918 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 921 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 918 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 921 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 918 0.00% 0.00% system.ruby.L1Cache_Controller.Load 46 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00% system.ruby.L1Cache_Controller.Store 857 0.00% 0.00% @@ -504,13 +517,5 @@ system.ruby.L1Cache_Controller.M.Replacement 920 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 918 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 98 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 823 0.00% 0.00% -system.ruby.Directory_Controller.GETX 921 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 918 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 921 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 918 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 921 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 918 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 921 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 918 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 8a9cf2f50..0808c4e4e 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 8686903737 # Simulator tick rate (ticks/s) -host_mem_usage 208524 # Number of bytes of host memory used -host_seconds 11.51 # Real time elapsed on the host +host_tick_rate 8581932612 # Simulator tick rate (ticks/s) +host_mem_usage 264172 # Number of bytes of host memory used +host_seconds 11.65 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -27,46 +27,46 @@ system.physmem.readReqs 1666397 # Nu system.physmem.writeReqs 1666879 # Number of write requests accepted system.physmem.readBursts 1666397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1666879 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 106647872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1536 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 106648000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue system.physmem.bytesWritten 106676864 # Total number of bytes written to DRAM system.physmem.bytesReadSys 106649408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 106680256 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 24 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 30 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 104030 # Per bank write bursts -system.physmem.perBankRdBursts::1 103994 # Per bank write bursts +system.physmem.perBankRdBursts::1 103995 # Per bank write bursts system.physmem.perBankRdBursts::2 104918 # Per bank write bursts -system.physmem.perBankRdBursts::3 104596 # Per bank write bursts +system.physmem.perBankRdBursts::3 104597 # Per bank write bursts system.physmem.perBankRdBursts::4 103869 # Per bank write bursts system.physmem.perBankRdBursts::5 103935 # Per bank write bursts -system.physmem.perBankRdBursts::6 103649 # Per bank write bursts +system.physmem.perBankRdBursts::6 103648 # Per bank write bursts system.physmem.perBankRdBursts::7 104313 # Per bank write bursts -system.physmem.perBankRdBursts::8 103869 # Per bank write bursts +system.physmem.perBankRdBursts::8 103868 # Per bank write bursts system.physmem.perBankRdBursts::9 104354 # Per bank write bursts system.physmem.perBankRdBursts::10 103835 # Per bank write bursts system.physmem.perBankRdBursts::11 104272 # Per bank write bursts -system.physmem.perBankRdBursts::12 104076 # Per bank write bursts -system.physmem.perBankRdBursts::13 104034 # Per bank write bursts +system.physmem.perBankRdBursts::12 104077 # Per bank write bursts +system.physmem.perBankRdBursts::13 104035 # Per bank write bursts system.physmem.perBankRdBursts::14 104583 # Per bank write bursts system.physmem.perBankRdBursts::15 104046 # Per bank write bursts system.physmem.perBankWrBursts::0 104357 # Per bank write bursts -system.physmem.perBankWrBursts::1 104090 # Per bank write bursts +system.physmem.perBankWrBursts::1 104091 # Per bank write bursts system.physmem.perBankWrBursts::2 104175 # Per bank write bursts system.physmem.perBankWrBursts::3 103885 # Per bank write bursts system.physmem.perBankWrBursts::4 104730 # Per bank write bursts -system.physmem.perBankWrBursts::5 104508 # Per bank write bursts -system.physmem.perBankWrBursts::6 104083 # Per bank write bursts +system.physmem.perBankWrBursts::5 104507 # Per bank write bursts +system.physmem.perBankWrBursts::6 104082 # Per bank write bursts system.physmem.perBankWrBursts::7 104226 # Per bank write bursts -system.physmem.perBankWrBursts::8 104319 # Per bank write bursts +system.physmem.perBankWrBursts::8 104320 # Per bank write bursts system.physmem.perBankWrBursts::9 104219 # Per bank write bursts -system.physmem.perBankWrBursts::10 104229 # Per bank write bursts -system.physmem.perBankWrBursts::11 103701 # Per bank write bursts -system.physmem.perBankWrBursts::12 104102 # Per bank write bursts +system.physmem.perBankWrBursts::10 104228 # Per bank write bursts +system.physmem.perBankWrBursts::11 103702 # Per bank write bursts +system.physmem.perBankWrBursts::12 104104 # Per bank write bursts system.physmem.perBankWrBursts::13 103983 # Per bank write bursts system.physmem.perBankWrBursts::14 104296 # Per bank write bursts -system.physmem.perBankWrBursts::15 103923 # Per bank write bursts +system.physmem.perBankWrBursts::15 103921 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 99999956143 # Total gap between requests @@ -84,21 +84,21 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1666879 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 749477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 767791 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 84595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 750686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 769672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 84683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -131,33 +131,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 38121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 87361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 105787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 108512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 113649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 112259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 107672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 125741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 107991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 100241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 100173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 100040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 11292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 87757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 105663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 108535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 113878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 112245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 107898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 126067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 108001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 100239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 100135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 100039 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 100007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -180,12 +180,12 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3296263 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 64.716933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 64.192638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 23.994317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3288284 99.76% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5824 0.18% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 3296308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.716127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.192082 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 23.993116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3288370 99.76% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5783 0.18% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 32 0.00% 99.94% # Bytes accessed per row activation @@ -193,41 +193,41 @@ system.physmem.bytesPerActivate::640-767 32 0.00% 99.94% # By system.physmem.bytesPerActivate::768-895 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 1963 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3296263 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 99238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.791612 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 15.446176 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.010489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 99237 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 3296308 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 99265 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.787065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 15.442881 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 105.996031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 99264 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 99238 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 99238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.796247 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.714914 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.763911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 78818 79.42% 79.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3091 3.11% 82.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3042 3.07% 85.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1750 1.76% 87.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1374 1.38% 88.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8750 8.82% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1949 1.96% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 293 0.30% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 65 0.07% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 43 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 29 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 17 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 10 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 99265 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 99265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.791679 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.710831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.758038 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 78980 79.56% 79.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3022 3.04% 82.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3011 3.03% 85.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1773 1.79% 87.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1415 1.43% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8615 8.68% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2003 2.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 293 0.30% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 66 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 21 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 21 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 99238 # Writes before turning the bus around for reads -system.physmem.totQLat 61644213329 # Total ticks spent queuing -system.physmem.totMemAccLat 92888707079 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8331865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36993.05 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 99265 # Writes before turning the bus around for reads +system.physmem.totQLat 60762575042 # Total ticks spent queuing +system.physmem.totMemAccLat 92007106292 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8331875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36463.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55743.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 55213.93 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1066.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1066.77 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1066.49 # Average system read bandwidth in MiByte/s @@ -236,37 +236,45 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 16.67 # Data bus utilization in percentage system.physmem.busUtilRead 8.33 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 8.33 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.44 # Average write queue length when enqueuing -system.physmem.readRowHits 32184 # Number of row buffer hits during reads -system.physmem.writeRowHits 4741 # Number of row buffer hits during writes +system.physmem.readRowHits 32179 # Number of row buffer hits during reads +system.physmem.writeRowHits 4705 # Number of row buffer hits during writes system.physmem.readRowHitRate 1.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 0.28 # Row buffer hit rate for writes system.physmem.avgGap 30000.50 # Average gap between requests system.physmem.pageHitRate 1.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 5342990 # Time in different power states -system.physmem.memoryStateTime::REF 3339180000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 96654559510 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 12463083360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 12456445680 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 6800293500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 6796671750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 6499693200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 6497868000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5404598640 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5396297760 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 6531436080 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 6531436080 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 67803083460 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 67799803680 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 523052250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 525929250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 106025240490 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 106004452200 # Total energy per rank (pJ) -system.physmem.averagePower::0 1060.262279 # Core power per rank (mW) -system.physmem.averagePower::1 1060.054394 # Core power per rank (mW) +system.physmem_0.actEnergy 12463295040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6800409000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6499701000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5404592160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6531436080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67776382665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 546474000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 106022289945 # Total energy per rank (pJ) +system.physmem_0.averagePower 1060.232773 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 531628571 # Time in different power states +system.physmem_0.memoryStateTime::REF 3339180000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 96128273929 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 12456559080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 6796733625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6497875800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5396304240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6531436080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 67774932585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 547746000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 106001587410 # Total energy per rank (pJ) +system.physmem_1.averagePower 1060.025746 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 534269274 # Time in different power states +system.physmem_1.memoryStateTime::REF 3339180000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 96125633226 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.numPackets 3333276 # Number of packets generated +system.cpu.numRetries 0 # Number of retries +system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) system.membus.trans_dist::ReadReq 1666397 # Transaction distribution system.membus.trans_dist::ReadResp 1666397 # Transaction distribution system.membus.trans_dist::WriteReq 1666879 # Transaction distribution @@ -277,7 +285,7 @@ system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11427712781 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11428907481 # Layer occupancy (ticks) system.membus.respLayer0.utilization 11.4 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets @@ -331,8 +339,8 @@ system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1063154546.015704 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107915737.892311 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154535.263763 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107915844.091091 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -384,34 +392,34 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 75762.275031 # Read request-response latency -system.monitor.readLatencyHist::gmean 69897.504803 # Read request-response latency -system.monitor.readLatencyHist::stdev 42102.080811 # Read request-response latency -system.monitor.readLatencyHist::0-32767 24 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 443180 26.60% 26.60% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1020210 61.22% 87.82% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 76869 4.61% 92.43% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 59066 3.54% 95.98% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 25573 1.53% 97.51% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 9468 0.57% 98.08% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7856 0.47% 98.55% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 8007 0.48% 99.03% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7912 0.47% 99.51% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 4865 0.29% 99.80% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1179 0.07% 99.87% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 915 0.05% 99.92% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 775 0.05% 99.97% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 416 0.02% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 74 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::524288-557055 5 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::557056-589823 1 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::589824-622591 2 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 75229.617239 # Read request-response latency +system.monitor.readLatencyHist::gmean 69644.568825 # Read request-response latency +system.monitor.readLatencyHist::stdev 40693.683003 # Read request-response latency +system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 444791 26.69% 26.69% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1023501 61.42% 88.11% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 76998 4.62% 92.73% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 56964 3.42% 96.15% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 25239 1.51% 97.67% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 9180 0.55% 98.22% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7794 0.47% 98.69% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 7780 0.47% 99.15% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7547 0.45% 99.61% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 3313 0.20% 99.80% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1429 0.09% 99.89% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 850 0.05% 99.94% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 662 0.04% 99.98% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 284 0.02% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 42 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::524288-557055 1 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency system.monitor.writeLatencyHist::samples 1666879 # Write request-response latency -system.monitor.writeLatencyHist::mean 10554.999998 # Write request-response latency -system.monitor.writeLatencyHist::gmean 10497.332887 # Write request-response latency -system.monitor.writeLatencyHist::stdev 1184.671741 # Write request-response latency +system.monitor.writeLatencyHist::mean 10556.022655 # Write request-response latency +system.monitor.writeLatencyHist::gmean 10498.307841 # Write request-response latency +system.monitor.writeLatencyHist::stdev 1185.079839 # Write request-response latency system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency @@ -421,13 +429,13 @@ system.monitor.writeLatencyHist::5120-6143 0 0.00% 0.00% # system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::9216-10239 1277601 76.65% 76.65% # Write request-response latency -system.monitor.writeLatencyHist::10240-11263 91250 5.47% 82.12% # Write request-response latency -system.monitor.writeLatencyHist::11264-12287 110692 6.64% 88.76% # Write request-response latency -system.monitor.writeLatencyHist::12288-13311 90268 5.42% 94.18% # Write request-response latency -system.monitor.writeLatencyHist::13312-14335 61253 3.67% 97.85% # Write request-response latency -system.monitor.writeLatencyHist::14336-15359 31832 1.91% 99.76% # Write request-response latency -system.monitor.writeLatencyHist::15360-16383 3983 0.24% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::9216-10239 1276777 76.60% 76.60% # Write request-response latency +system.monitor.writeLatencyHist::10240-11263 91385 5.48% 82.08% # Write request-response latency +system.monitor.writeLatencyHist::11264-12287 111087 6.66% 88.74% # Write request-response latency +system.monitor.writeLatencyHist::12288-13311 90448 5.43% 94.17% # Write request-response latency +system.monitor.writeLatencyHist::13312-14335 61415 3.68% 97.85% # Write request-response latency +system.monitor.writeLatencyHist::14336-15359 31809 1.91% 99.76% # Write request-response latency +system.monitor.writeLatencyHist::15360-16383 3958 0.24% 100.00% # Write request-response latency system.monitor.writeLatencyHist::16384-17407 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency @@ -518,13 +526,13 @@ system.monitor.ittReqReq::min_value 28000 # Re system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.230000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.210000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.309291 # Outstanding read transactions -system.monitor.outstandingReadsHist::0 28 28.00% 28.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 44 44.00% 72.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 17 17.00% 89.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 6 6.00% 95.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.281532 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 27 27.00% 27.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 46 46.00% 73.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 18 18.00% 91.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 4 4.00% 95.00% # Outstanding read transactions system.monitor.outstandingReadsHist::4 1 1.00% 96.00% # Outstanding read transactions system.monitor.outstandingReadsHist::5 3 3.00% 99.00% # Outstanding read transactions system.monitor.outstandingReadsHist::6 0 0.00% 99.00% # Outstanding read transactions @@ -617,8 +625,5 @@ system.monitor.writeTransHist::17408-18431 0 0.00% 100.00% # system.monitor.writeTransHist::18432-19455 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::19456-20479 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period -system.cpu.numPackets 3333276 # Number of packets generated -system.cpu.numRetries 0 # Number of retries -system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) ---------- End Simulation Statistics ----------